Display panel, preparation method thereof and display equipment

Abstract

The embodiment of the invention discloses a display panel, a preparation method thereof and a display device, an interlayer dielectric layer covers a first active part and one side, far away from a substrate, of a first grid electrode, the interlayer dielectric layer is provided with a first contact hole and a second contact hole, the depth of the first contact hole is smaller than that of the second contact hole, and the first contact hole and the second contact hole are communicated. The first contact hole exposes the first active part, and the second contact hole exposes the shading part; the first contact hole comprises a first upper hole and a first lower hole; the second contact hole comprises a second upper hole and a second lower hole, the depth of the second upper hole is equal to that of the first upper hole, and the depth of the second lower hole is larger than that of the first lower hole. According to the embodiment of the invention, the same photomask is adopted to etch the interlayer dielectric layer to form the first contact hole exposing the first active part and the second contact hole exposing the shading part, so that the photomask is saved, and the first lower hole of the first contact hole penetrates through the part of the first active part, so that the etching degree of the first active part is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, as well as a display device. Background Art

[0002] In a conventional top-gate thin-film transistor architecture driving backplane, shallow holes and deep holes are usually required to achieve connection. The deep holes need to penetrate the buffer layer, while the shallow holes do not need to penetrate the buffer layer. For example, the shallow holes expose the active layer, and the deep holes expose the light shielding layer. In order to avoid excessive over-engraving of the active layer at the shallow holes, two photomasks are used in the art to form the shallow holes and deep holes respectively, but the use of two photomasks will increase the preparation cost. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a method for manufacturing the same, as well as a display device, which can save light masks for forming shallow holes and deep holes while reducing the risk of severe over-etching of the active layer.

[0004] An embodiment of the present application provides a display panel, comprising:

[0005] substrate;

[0006] A light shielding portion, disposed on the substrate;

[0007] A buffer layer is arranged on a side of the light shielding portion away from the substrate;

[0008] A first active portion is disposed on a side of the buffer layer away from the substrate;

[0009] A first gate is provided in a different layer from the first active portion;

[0010] an interlayer dielectric layer, covering the first active portion and a side of the first gate away from the substrate, the interlayer dielectric layer being provided with a first contact hole and a second contact hole, the first contact hole having a depth smaller than that of the second contact hole, the first contact hole penetrating the interlayer dielectric layer and exposing the first active portion, and the second contact hole penetrating the interlayer dielectric layer and the buffer layer and exposing the light shielding portion; and

[0011] Wherein, in the thickness direction of the display panel, the first contact hole includes a first upper hole and a first lower hole, the first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion, the first upper hole is connected to a side of the first lower hole away from the substrate, and an opening width of the first lower hole is smaller than an opening width of the first upper hole;

[0012] In the thickness direction of the display panel, the second contact hole includes a second upper hole and a second lower hole, the second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer, the second upper hole is connected to a side of the second lower hole away from the substrate, the opening width of the second lower hole is smaller than the opening width of the second upper hole, the depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole.

[0013] Optionally, in some embodiments of the present application, in the thickness direction of the display panel, the distance from the opening end surface of the first lower hole to the first active portion is a first distance, and the first distance is between 1 nanometer and 60 nanometers.

[0014] Optionally, in some embodiments of the present application, in the thickness direction of the display panel, the first lower hole penetrates the first active portion to a depth between 1 nanometer and 30 nanometers.

[0015] Optionally, in some embodiments of the present application, the distance from the opening of the first lower hole to the hole wall of the first upper hole is a second distance, and the second distance is between 0.1 microns and 2 microns.

[0016] Optionally, in some embodiments of the present application, the distance from the opening of the second lower hole to the hole wall of the second upper hole is a third distance, and the second distance is equal to the third distance.

[0017] Optionally, in some embodiments of the present application, the first lower hole includes a first sub-hole and a second sub-hole, the first sub-hole is connected to the first upper hole, the second sub-hole is connected to a side of the first sub-hole close to the substrate, the second sub-hole is arranged in the first active portion, and the opening width of the second sub-hole is smaller than the opening width of the first sub-hole.

[0018] Optionally, in some embodiments of the present application, the inclination angle of the hole wall of the first upper hole is greater than the inclination angle of the hole wall of the first sub-hole, and the inclination angle of the hole wall of the first sub-hole is greater than the inclination angle of the hole wall of the second sub-hole.

[0019] Optionally, in some embodiments of the present application, the display panel further includes a second active portion, a second gate, a first insulating portion, a second insulating portion and a first metal layer, the first insulating portion is arranged on a side of the first active portion away from the substrate, the second active portion, the second insulating portion and the second gate are sequentially stacked and arranged on a side of the buffer layer away from the substrate, and the interlayer dielectric layer covers the first gate, the second gate and the buffer layer;

[0020] The first metal layer is arranged on a side of the interlayer dielectric layer away from the substrate, and the first metal layer includes a first electrode, a second electrode, a third electrode and a fourth electrode, the first electrode is connected to one side of the first active part through a first contact hole, the second electrode is connected to the other side of the first active part through a first contact hole, and the other end of the second electrode is connected to the shading part through a second contact hole; the third electrode is connected to one side of the second active part through a first contact hole, and the fourth electrode is connected to the other side of the second active part through the first contact hole.

[0021] Optionally, in some embodiments of the present application, the first metal layer further includes a first peripheral routing line, the interlayer dielectric layer further includes a third contact hole exposing the second gate, the depth of the third contact hole is less than the depth of the first contact hole, and the first peripheral routing line is connected to the second gate through the third contact hole;

[0022] The third contact hole includes a third upper hole and a third lower hole, the third lower hole is connected to a side of the third upper hole close to the substrate, the opening width of the third lower hole is smaller than the opening width of the third upper hole, the third lower hole passes through a portion of the second gate, and the depth of the third lower hole is greater than the depth of the first lower hole passing through the first active portion.

[0023] Optionally, in some embodiments of the present application, the display panel further includes a second insulating layer, a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate is arranged in the same layer as the light shielding portion, the second electrode plate is arranged in the same layer as the first active portion and overlaps with the first electrode plate to form a capacitor, the second insulating layer covers the first gate, the second gate, the second electrode plate and the buffer layer, the third electrode plate is arranged on a side of the second insulating layer away from the substrate and forms a capacitor with the second electrode plate, and the interlayer dielectric layer covers the second insulating layer and the third electrode plate;

[0024] The first metal layer further includes a connecting line, the interlayer dielectric layer is further provided with a fourth contact hole exposing the third electrode plate and another second contact hole exposing the first electrode plate, the first contact hole and the second contact hole also penetrate the second insulating layer; one end of the connecting line is connected to the third electrode plate through the fourth contact hole, and the other end of the connecting line is connected to the first electrode plate through another second contact hole;

[0025] The fourth contact hole includes a fourth upper hole and a fourth lower hole, the fourth lower hole is connected to the side of the fourth upper hole close to the substrate, the opening width of the fourth lower hole is smaller than the opening width of the fourth upper hole, the fourth lower hole passes through a portion of the third electrode plate, and the depth of the fourth lower hole is greater than the depth of the first lower hole passing through the first active portion.

[0026] Accordingly, an embodiment of the present application further provides a method for preparing a display panel, which comprises the following steps:

[0027] A light shielding portion, a buffer layer, a first active portion, a first insulating portion, a first gate and an interlayer dielectric layer are sequentially formed on a substrate;

[0028] The interlayer dielectric layer is dry-etched twice using the same photomask to form a first contact hole and a second contact hole, wherein the depth of the first contact hole is less than the depth of the second contact hole, the first contact hole penetrates the interlayer dielectric layer and exposes the first active portion, the second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light shielding portion, the first contact hole comprises a first upper hole and a first lower hole, the first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion, the first upper hole is connected to a side of the first lower hole away from the substrate, and the opening width of the first lower hole is less than the opening width of the first upper hole; the second contact hole comprises a second upper hole and a second lower hole, the second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer, the second upper hole is connected to a side of the second lower hole away from the substrate, the opening width of the second lower hole is less than the opening width of the second upper hole, the depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole.

[0029] Optionally, in some embodiments of the present application, the step of performing dry etching twice on the interlayer dielectric layer using the same photomask to form the first contact hole and the second contact hole includes:

[0030] Performing a first dry etching on the interlayer dielectric layer based on a mask to form a first blind hole corresponding to the first active portion and a second blind hole corresponding to the light shielding portion, wherein the first blind hole and the second blind hole have the same depth, and a distance from the bottom of the first blind hole to the first active portion is a set distance, and the set distance is between 10 nanometers and 80 nanometers;

[0031] Based on the same mask, the interlayer dielectric layer is dry-etched for a second time to form a first contact hole and a second contact hole, wherein the distance from the opening end surface of the first lower hole to the first active portion is a first distance, and the first distance is between 1 nanometer and 60 nanometers; wherein the etching rate of the interlayer dielectric layer by the second dry etching is greater than the etching rate of the first active portion by the second dry etching.

[0032] Correspondingly, an embodiment of the present application further provides a display device, which includes a display panel as described in any one of the above embodiments.

[0033] The display panel and the display device of the embodiments of the present application use the same mask to etch the interlayer dielectric layer to form a first contact hole exposing the first active part and a second contact hole exposing the light shielding part, so as to save the mask; secondly, the depth of the first upper hole of the first contact hole and the second upper hole of the second contact hole are equal, the depth of the first lower hole of the first contact hole is less than the depth of the second lower hole of the second contact hole, and the first lower hole of the first contact hole passes through part of the first active part to reduce the degree of etching of the first active part. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0035] Figure 2 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0036] Figure 3 yes Figure 2 A magnified schematic diagram of the M1 part;

[0037] Figure 4 yes Figure 2 An enlarged schematic diagram of the M2 part;

[0038] Figure 5 is another structural schematic diagram of a display panel provided in an embodiment of the present application;

[0039] Figure 6 is another partial structural schematic diagram of a display panel provided in an embodiment of the present application;

[0040] Figure 7 yes Figure 6 An enlarged schematic diagram of the M3 part;

[0041] Figure 8 yes Figure 6 A magnified schematic diagram of the M4 part;

[0042] Fig. 9 is a schematic diagram of step B01 in the method for preparing a display panel provided in an embodiment of the present application;

[0043] Fig.10 is a schematic diagram of step B021 in the method for preparing a display panel provided in an embodiment of the present application;

[0044] Fig.11 is a schematic diagram of step B022 in the method for preparing a display panel provided in an embodiment of the present application;

[0045] Fig.12 is a schematic diagram of step B03 in the method for preparing a display panel provided in an embodiment of the present application;

[0046] Fig.13 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0048] The embodiments of the present application provide a display panel and a method for manufacturing the same, as well as a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0049] Please refer to Figures 1 to 4 An embodiment of the present application provides a display panel 100 , which includes a substrate 11 , a light shielding portion 121 , a buffer layer 13 , a first active portion 141 , a first gate 161 and an interlayer dielectric layer 17 .

[0050] The light shielding portion 121 is disposed on the substrate 11. The buffer layer 13 is disposed on a side of the light shielding portion 121 away from the substrate 11. The first active portion 141 is disposed on a side of the buffer layer 13 away from the substrate 11. The first gate 161 is disposed in a different layer from the first active portion 141. The interlayer dielectric layer 17 covers the side of the first active portion 141 and the first gate 161 away from the substrate 11.

[0051] The interlayer dielectric layer 17 is provided with a first contact hole 171 and a second contact hole 172. The depth of the first contact hole 171 is less than the depth of the second contact hole 172. The first contact hole 171 penetrates the interlayer dielectric layer 17 and exposes the first active portion 141. The second contact hole 172 penetrates the interlayer dielectric layer 17 and the buffer layer 13 and exposes the light shielding portion 121.

[0052] The first contact hole 171 includes a first upper hole 1a and a first lower hole 1b. The first lower hole 1b penetrates a portion of the interlayer dielectric layer 17 and a portion of the first active portion 141. The first upper hole 1a is connected to a side of the first lower hole 1b away from the substrate 11. The opening width k1 of the first lower hole 1b is smaller than the opening width k2 of the first upper hole 1a.

[0053] The second contact hole 172 includes a second upper hole 2a and a second lower hole 2b. The second lower hole 2b penetrates a portion of the interlayer dielectric layer 17 and the buffer layer 13. The second upper hole 2a is connected to a side of the second lower hole 2b away from the substrate 11. The opening width k3 of the second lower hole 2b is smaller than the opening width k4 of the second upper hole 2a. The depth of the second upper hole 2a is equal to the depth of the first upper hole 1a, and the depth of the second lower hole 2b is greater than the depth of the first lower hole 1b.

[0054] The display panel 100 of the embodiment of the present application uses the same mask to etch the interlayer dielectric layer 17 to form the first contact hole 171 exposing the first active portion 141 and the second contact hole 172 exposing the light shielding portion 121, so as to save masks; secondly, the depths of the first upper hole 1a of the first contact hole 171 and the second upper hole 2a of the second contact hole 172 are equal, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 passes through a portion of the first active portion 141, so as to reduce the degree to which the first active portion 141 is etched.

[0055] It can be understood that the deeper the first lower hole 1b is over-engraved into the first active portion 141, the larger the opening width k1 of the first lower hole 1b will be, which will reduce the stability and service life of the thin film transistor. When the first contact hole 171 is an output electrode via hole, the risk of leakage current of the thin film transistor device will also increase. Therefore, based on the leakage current, stability and service life of the thin film transistor, it is necessary to reduce the risk of the first lower hole 1b over-engraving the first active portion 141.

[0056] Therefore, in some embodiments of the present application, in the thickness direction of the display panel 100, the depth of the first lower hole 1b penetrating the first active portion 141 accounts for a ratio of less than or equal to 3 / 5 of the thickness of the first active portion 141, so as to reduce the degree of etching of the first active portion 141, thereby reducing the risk of leakage current and reducing the risk of device instability and short service life. In addition, the penetration depth of the first lower hole 1b is less than or equal to 3 / 5 of the thickness of the first active portion 141, which can also increase the contact area between the source and drain and the first active portion 141, improve the current control ability of the device and reduce poor contact; it can also reduce the resistance of the source and drain regions of the first active portion 141 and improve the response speed of the device.

[0057] Optionally, the penetration depth of the first lower hole 1 b is equal to 3 / 5, 2 / 5, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9 or 1 / 10 of the thickness of the first active part 141 .

[0058] Optionally, in some embodiments of the present application, the depth of the first lower hole 1b penetrating the first active portion 141 is between 1 nanometer and 30 nanometers in the thickness direction of the display panel 100. Such a setting can further reduce the risk of leakage current, device instability and short life, and can improve the current control ability and response speed of the device and reduce the risk of poor contact.

[0059] Optionally, the depth of the first lower hole 1b penetrating the first active portion 141 can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm or 30 nm, etc.

[0060] Please refer to Figure 2 and Figure 3 Optionally, in some embodiments of the present application, in the thickness direction of the display panel 100, the distance from the opening end surface of the first lower hole 1b to the first active portion 141 is a first distance D1, and the first distance D1 is between 1 nanometer and 60 nanometers.

[0061] It should be understood that when the first contact hole 171 and the second contact hole 172 are etched for the first time, a gas with a high etching rate will be selected to etch the interlayer dielectric layer 17 to shorten the preparation time. Based on the fact that the second lower hole 2b is relatively deep and the etching time and etching gas of the first lower hole 1b and the second lower hole 2b are consistent, the larger the first distance D1 is, the larger the distance between the blind hole and the first active part 141 after the first etching is, so that the first lower hole 1b formed by the second etching has a larger distance to buffer the over-etching of the first active part 141, which can reduce the degree of over-etching of the first active part 141; and the etching rate of the interlayer dielectric layer 17 in the second etching is slower, which will prolong the time to form the first contact hole 171 and the second contact hole 172.

[0062] Therefore, based on the consideration of reducing the degree of over-etching of the first active portion 141 and the time for preparing the contact hole, the first distance D1 can be selected to be between 1 nanometer and 60 nanometers, for example, it can be 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers, 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers, 30 nanometers, 32 nanometers, 34 nanometers, 36 nanometers, 38 nanometers, 40 nanometers, 42 nanometers, 44 nanometers, 46 nanometers, 48 ​​nanometers, 50 nanometers, 52 nanometers, 54 nanometers, 56 nanometers, 58 nanometers or 60 nanometers, etc.

[0063] Optionally, in some embodiments of the present application, the distance from the opening of the first lower hole 1b to the hole wall of the first upper hole 1a is a second distance D2, and the second distance D2 is between 0.1 microns and 2 microns.

[0064] It can be understood that the larger the second distance D2 is, the smaller the opening width k1 of the first lower hole 1b is, which also means that the first lower hole 1b is shallower in over-engraving the first active portion 141; and the larger the second distance D2 is, the larger the buffer area between the first upper hole 1a and the first lower hole 1b is, which can reduce the risk of subsequent fracture of the film layer covering the first contact hole 171. Secondly, the larger the second distance D2 is, the larger the layout area of ​​the first contact hole 171 is, and the aperture ratio is reduced.

[0065] Therefore, based on the considerations of reducing the degree of etching of the first active portion 141, the risk of subsequent film breakage and the aperture ratio, the second distance D2 is selected to be between 0.1 microns and 2 microns, for example, 0.1 microns, 0.2 microns, 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1 micron, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns or 2 microns.

[0066] Optionally, in some embodiments of the present application, the distance from the opening of the second lower hole 2b to the hole wall of the second upper hole 2a is a third distance D3, and the second distance D2 is equal to the third distance D3.

[0067] Since the first lower hole 1 b and the second lower hole 2 b are both etched under the same etching conditions, the third distance D3 is equal to the second distance D2 .

[0068] Optionally, in some embodiments of the present application, based on the consideration of reducing the risk of subsequent film layer breakage and the aperture rate, the third distance D3 is selected to be between 0.1 microns and 2 microns, for example, 0.1 microns, 0.2 microns, 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1 micron, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns or 2 microns.

[0069] Optionally, in some embodiments of the present application, the first lower hole 1b includes a first sub-hole b01 and a second sub-hole b02. The first sub-hole b01 is connected to the first upper hole 1a, and the second sub-hole b02 is connected to a side of the first sub-hole b01 close to the substrate 11. The second sub-hole b02 is disposed in the first active portion 141, and the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01.

[0070] It can be understood that in the process of etching the interlayer dielectric layer 17 and the first active portion 141, a gas with a relatively large etching selectivity will be selected for etching to reduce the etching of the first active portion 141 and speed up the etching of the interlayer dielectric layer 17, so that the etching gas etches the interlayer dielectric layer 17 and the buffer layer 13 at a rate greater than the etching rate of the first active portion 141, so that the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01, wherein the opening width of the first sub-hole b01 is the opening width k1 of the first lower hole 1b.

[0071] That is, the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01, so as to reduce the over-etching degree of the first lower hole 1b on the first active portion 141 and improve the stability and service life of the thin film transistor device.

[0072] Optionally, in some embodiments of the present application, the hole wall inclination angle of the first upper hole 1a is greater than the hole wall inclination angle v1 of the first sub-hole b01, and the hole wall inclination angle v2 of the first sub-hole b01 is greater than the hole wall inclination angle v3 of the second sub-hole b02.

[0073] It can be understood that in the thickness direction of the display panel 100, the inclination angle gradient of the hole wall decreases from the first upper hole 1a to the second sub-hole b02, so that the slope of the hole wall gradually becomes gentler, thereby reducing the risk of subsequent film layers (second electrodes) breaking when covering the first contact hole 171.

[0074] Optionally, in some embodiments of the present application, the depth of the first upper hole 1a is greater than the depth of the first sub-hole b01, and the depth of the first sub-hole b01 is greater than the depth of the second sub-hole b02.

[0075] It can be understood that, in the three hole areas of the first upper hole 1a, the first sub-hole b01 and the second sub-hole b02 in the first contact hole 171, the first upper hole 1a is in the upper section, the first sub-hole b01 is in the middle section, and the second sub-hole b02 is in the lower section, that is, the position of the second sub-hole b02 is in the deepest section of the first contact hole 171, and the position of the first upper hole 1a is in the shallowest section of the first contact hole 171. Therefore, the depths of the first upper hole 1a, the first sub-hole b01 and the second sub-hole b02 decrease gradually, which can reduce the proportion of the deep hole area and reduce the risk of breakage of the second electrode.

[0076] Optionally, in some embodiments of the present application, the display panel 100 further includes a second active portion 142, a second gate 162, a first insulating portion 151, a second insulating portion 152, and a first metal layer 18. The first insulating portion 151 is disposed on a side of the first active portion 141 away from the substrate 11. The second active portion 142, the second insulating portion 152, and the second gate 162 are sequentially stacked and disposed on a side of the buffer layer 13 away from the substrate 11. The interlayer dielectric layer 17 covers the first gate 161, the second gate 162, and the buffer layer 13.

[0077] The first metal layer 18 is disposed on a side of the interlayer dielectric layer 17 away from the substrate 11. The first metal layer 18 includes a first electrode 181, a second electrode 182, a third electrode 183, and a fourth electrode 184. The first electrode 181 is connected to one side of the first active portion 141 through a first contact hole 171. One end of the second electrode 182 is connected to the other side of the first active portion 141 through a first contact hole 171, and the other end of the second electrode 182 is connected to the light shielding portion 121 through a second contact hole 172. The third electrode 183 is connected to one side of the second active portion 142 through a first contact hole 171, and the fourth electrode 184 is connected to the other side of the second active portion 142 through a first contact hole 171.

[0078] The first active portion 141, the first gate 161, the first electrode 181 and the second electrode 182 constitute a first thin film transistor, which is located in the display area of ​​the display panel 100. The second active portion 142, the second gate 162, the third electrode 183 and the fourth electrode 184 constitute a second thin film transistor, which is located in the gate driving circuit area of ​​the display panel 100.

[0079] Please refer to Figure 1 and Figure 4 Optionally, in some embodiments of the present application, the first metal layer 18 further includes a first peripheral wiring 185, and the interlayer dielectric layer 17 further includes a third contact hole 173 that exposes the second gate 162. The depth of the third contact hole 173 is less than the depth of the first contact hole 171. The first peripheral wiring 185 is connected to the second gate 162 through the third contact hole 173.

[0080] The third contact hole 173 includes a third upper hole 3a and a third lower hole 3b. The third lower hole 3b is connected to the side of the third upper hole 3a close to the substrate 11. The opening width k5 of the third lower hole 3b is smaller than the opening width k6 of the third upper hole 3a. The third lower hole 3b penetrates the portion of the second gate 162, and the depth of the third lower hole 3b is greater than the depth of the first lower hole 1b penetrating the first active portion 141.

[0081] It can be understood that the third lower hole 3b passes through part of the second gate 162, and the depth of the third lower hole 3b is greater than the depth of the first lower hole 1b, which increases the contact area between the first peripheral wiring 185 and the second gate 162, improves the contact yield between the two, and secondly reduces the contact impedance between the two, thereby improving the response speed of the second thin film transistor.

[0082] Optionally, in some embodiments, the display panel 100 further includes a first electrode plate 122 and a second electrode plate 143, and the first metal layer 18 further includes a third electrode plate 186. The first electrode plate 122 and the third electrode plate 186 form capacitors with the second electrode plate 143 respectively.

[0083] The first electrode plate 122 and the light shielding portion 121 are disposed in the same layer and made of the same material. The second electrode plate 143, the first active portion 141 and the second active portion 142 are disposed in the same layer and all of them include semiconductor materials.

[0084] Optionally, in some embodiments of the present application, the thickness of the light shielding portion 121 and the first electrode plate 122 may be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers or 800 nanometers. The thickness of the two may be equal.

[0085] The materials of the light shielding portion 121 and the first electrode plate 122 can be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium. The light shielding portion 121 and the first electrode plate 122 are also single-layer or multi-layer stacked structures.

[0086] The thickness of the buffer layer 13 may be between 10 nm and 800 nm, such as 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm or 800 nm. The material of the buffer layer 13 may be at least one of silicon nitride and silicon oxide, and the buffer layer 13 may be a single film layer or a multi-film layer stacked structure.

[0087] The thickness of the first active portion 141, the second active portion 142 and the second electrode plate 143 is between 10 nanometers and 50 nanometers, such as 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers or 50 nanometers. Optionally, the thickness of the first active portion 141, the second active portion 142 and the second electrode plate 143 is equal.

[0088] The first active portion 141 , the second active portion 142 and the second electrode 143 are made of semiconductor materials, and their respective materials include at least two of indium oxide, gallium oxide, zinc oxide and titanium niobium oxide.

[0089] The thickness of each of the first insulating portion 151 and the second insulating portion 152 is between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers or 800 nanometers. The material of each of the first insulating portion 151 and the second insulating portion 152 can be at least one of silicon nitride and silicon oxide, and the first insulating portion 151 and the second insulating portion 152 are each a single film layer or a multi-film layer stacking structure. Optionally, the thickness, material and film layer structure of the first insulating portion 151 and the second insulating portion 152 are the same.

[0090] The thickness of the first gate 161 and the second gate 162 may be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers or 800 nanometers. The thickness of the two may be equal. The thickness of the first gate 161 and the second gate 162 are both greater than the thickness of the first active portion 141.

[0091] The materials of the first gate 161 and the second gate 162 can be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium, and the first gate 161 and the second gate 162 are single-layer or multi-layer stacked structures. The materials and film structures of the first gate 161 and the second gate 162 are the same.

[0092] The thickness of the interlayer dielectric layer 17 may be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers or 800 nanometers. The material of the interlayer dielectric layer 17 may be at least one of silicon nitride and silicon oxide, and the interlayer dielectric layer 17 may be a single film layer or a multi-film layer stacking structure. Optionally, the material of the interlayer dielectric layer 17 may be the same as that of the buffer layer 13.

[0093] The thickness of the first metal layer 18 is between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers or 800 nanometers. The material of the first metal layer 18 can be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium. The first metal layer 18 is a single film layer or a multi-film layer stacked structure.

[0094] Please refer to Figures 5 to 8 , Figure 5 FIG. 1 is another schematic diagram of the structure of the display panel 100 according to an embodiment of the present application. Figure 6 for Figure 5 Part of the schematic diagram, Figure 7 yes Figure 6 The enlarged schematic diagram of the M3 part, Figure 8 yes Figure 6 An enlarged schematic diagram of the M4 part.

[0095] exist Figures 5 to 8 In the present invention, parts different from those of the above-described embodiment will be described to avoid redundancy.

[0096] Please refer to Figures 5 to 8 Compared with the above embodiments, in some embodiments of the present application, the display panel 100 further includes a second insulating layer 19 .

[0097] The second insulating layer 19 covers the first gate 161 , the second gate 162 , the second electrode 143 and the buffer layer 13 . The third electrode 186 is arranged on the side of the second insulating layer 19 away from the substrate 11 and forms a capacitor with the second electrode 143 . The interlayer dielectric layer 17 covers the second insulating layer 19 and the third electrode 186 .

[0098] The first metal layer 18 also includes a connection line 187. The interlayer dielectric layer 17 is also provided with a fourth contact hole 174 exposing the third electrode 186 and another second contact hole 172 exposing the first electrode 122, and the first contact hole 171 and the second contact hole 172 also penetrate the second insulating layer 19. One end of the connection line 187 is connected to the third electrode 186 through the fourth contact hole 174, and the other end of the connection line 187 is connected to the first electrode 122 through the other second contact hole 172.

[0099] The fourth contact hole 174 includes a fourth upper hole 4a and a fourth lower hole 4b. The fourth lower hole 4b is connected to the side of the fourth upper hole 4a close to the substrate 11. The opening width k7 of the fourth lower hole 4b is smaller than the opening width k8 of the fourth upper hole 4a. The fourth lower hole 4b penetrates the portion of the third electrode plate 186, and the depth of the fourth lower hole 4b is greater than the depth of the first lower hole 1b penetrating the first active portion 141.

[0100] It can be understood that the fourth lower hole 4b passes through part of the third electrode plate 186, and the depth of the fourth lower hole 4b is greater than the depth of the first lower hole 1b, which increases the contact area between the connecting line 187 and the third electrode plate 186, improves the contact yield between the two, and secondly reduces the contact impedance between the two, thereby improving the response speed of the capacitor.

[0101] In some embodiments, the display panel 100 further includes a passivation layer 191 , a first planarization layer 192 , a second metal layer 20 , a second planarization layer 193 , a pixel definition layer 21 and an anode 22 which are sequentially disposed on a side of the first metal layer 18 away from the substrate 11 .

[0102] Optionally, the second metal layer 20 includes a second peripheral routing 201 and a third peripheral routing 202 , the second peripheral routing 201 is connected to the first peripheral routing 185 , and the third peripheral routing 202 is connected to the fourth electrode 184 .

[0103] The first peripheral routing line 185 , the second peripheral routing line 201 and the third peripheral routing line 202 are all located in the gate driving circuit area to reduce the frame width.

[0104] Optionally, the second metal layer 20 further includes a transition portion 203 and a binding pad 204. The anode 22 is connected to the transition portion 203, and the transition portion 203 is connected to the second electrode 182. The binding pad 204 is located in the binding area of ​​the display panel 100 and is configured to be bound and connected to a chip or a circuit board.

[0105] Correspondingly, an embodiment of the present application further provides a method for preparing a display panel, wherein the method is configured to prepare any one of the display panels 100 described above.

[0106] The preparation method comprises the following steps:

[0107] Step B01 , forming a light shielding portion 121 , a buffer layer 13 , a first active portion 141 , a first insulating portion 151 , a first gate 161 and an interlayer dielectric layer 17 in sequence on a substrate 11 .

[0108] Step B02, using the same photomask to perform dry etching twice on the interlayer dielectric layer 17 to form a first contact hole 171 and a second contact hole 172. The depth of the first contact hole 171 is less than the depth of the second contact hole 172. The first contact hole 171 penetrates the interlayer dielectric layer 17 and exposes the first active portion 141, and the second contact hole 172 penetrates the interlayer dielectric layer 17 and the buffer layer 13 and exposes the light shielding portion 121. The first contact hole 171 includes a first upper hole 1a and a first lower hole 1b. The first lower hole 1b penetrates a portion of the interlayer dielectric layer 17 and a portion of the first active portion 141, and the first upper hole 1a is connected to a side of the first lower hole 1b away from the substrate 11. The opening width k1 of the first lower hole 1b is less than the opening width k2 of the first upper hole 1a. The second contact hole 172 includes a second upper hole 2a and a second lower hole 2b, and the second lower hole 2b penetrates a portion of the interlayer dielectric layer 17 and the buffer layer 13, and the second upper hole 2a is connected to a side of the second lower hole 2b away from the substrate 11. The opening width k3 of the second lower hole 2b is smaller than the opening width k4 of the second upper hole 2a. The depth of the second upper hole 2a is equal to the depth of the first upper hole 1a, and the depth of the second lower hole 2b is greater than the depth of the first lower hole 1b.

[0109] The manufacturing method of the display panel 100 of the embodiment of the present application uses the same mask to etch the interlayer dielectric layer 17 to form the first contact hole 171 exposing the first active portion 141 and the second contact hole 172 exposing the light shielding portion 121, so as to save the mask. Secondly, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 passes through a part of the first active portion 141, so as to reduce the degree of etching of the first active portion 141.

[0110] The following is Figure 1 The display panel 100 of the corresponding embodiment is taken as an example to illustrate the method for manufacturing the display panel 100 .

[0111] Please refer to Fig. 9 In step B01 , a light shielding portion 121 , a buffer layer 13 , a first active portion 141 , a first insulating portion 151 , a first gate 161 and an interlayer dielectric layer 17 are sequentially formed on a substrate 11 .

[0112] The material of the buffer layer 13 and the material of the interlayer dielectric layer 17 are the same or have similar chemical properties, which is convenient for the second dry etching.

[0113] Then go to step B02.

[0114] Step B02 , using the same photomask to perform dry etching twice on the interlayer dielectric layer 17 to form a first contact hole 171 and a second contact hole 172 .

[0115] Optionally, step B02 includes:

[0116] Please refer to Fig.10 , step B021, based on a mask, the interlayer dielectric layer 17 is first dry-etched to form a first blind hole m1 corresponding to the first active portion 141 and a second blind hole m2 corresponding to the light shielding portion 121. The first blind hole m1 and the second blind hole m2 have the same depth, and the distance from the bottom of the first blind hole m1 to the first active portion 141 is a set distance Ds, and the set distance Ds is between 10 nanometers and 80 nanometers.

[0117] Optionally, the first dry etch may include SF 6 and Cl 2 , or in SF 6 and Cl 2 Add O 2 Or other etching gases.

[0118] It should be noted that the etching selectivity of the etching gas is the ratio of the etching rate of the interlayer dielectric layer 17 to the etching rate of the first active portion 141. Since the first dry etching only etches the interlayer dielectric layer 17, the etching selectivity of the first dry etching is set to be less than 4 / 1, so as to improve the etching rate and etching uniformity of the interlayer dielectric layer 17 and shorten the time for etching the interlayer dielectric layer 17.

[0119] It should be understood that the set distance Ds is a condition for switching to the second dry etching. As long as the distance from the first blind hole m1 to the first active portion 141 formed by the first dry etching satisfies the set distance Ds, the second dry etching is switched to.

[0120] The distance Ds is set between 10 nm and 80 nm to prevent the first blind hole m1 from being too close to the first active portion 141 , which would cause the subsequent second etching to over-etch the first active portion 141 and to prevent the preparation time from being too long.

[0121] Optionally, the set distance Ds can be 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers or 80 nanometers.

[0122] Then go to step B022.

[0123] Please refer to Fig.11 , step B022, based on the same mask, the interlayer dielectric layer 17 is dry-etched for a second time to form a first contact hole 171 and a second contact hole 172. The distance from the opening end surface of the first lower hole 1b to the first active portion 141 is a first distance D1, and the first distance D1 is between 1 nanometer and 60 nanometers. The etching rate of the interlayer dielectric layer 17 by the second dry etching is greater than the etching rate of the first active portion 141 by the second dry etching.

[0124] Optionally, the second dry etch may include CF 4 and O 2 , or other etching gases.

[0125] The purpose of the second dry etching is to accelerate the etching rate of the interlayer dielectric layer 17 and the buffer layer 13, and slow down the etching rate of the first active portion 141, so as to achieve the goal of etching through the buffer layer 13 while reducing the over-etching degree of the first active portion 141. Therefore, the etching selectivity ratio of the second dry etching is set to be greater than 4 / 1.

[0126] Secondly, in the second dry etching, the etching gas etches the second gate 162 at a rate greater than the etching rate of the first active portion 141 , so that the second gate 162 is etched to a greater depth than the first active portion 141 .

[0127] Optionally, the thickness of the second gate 162 is greater than the thickness of the first active portion 141 to prevent the second gate 162 from being etched through.

[0128] In addition, in some embodiments, the etching rate of the interlayer dielectric layer 17 by the first dry etching is greater than the etching rate of the interlayer dielectric layer 17 by the second dry etching, and the etching rate of the interlayer dielectric layer 17 in the second dry etching is greater than the etching rate of the first active portion 141. Therefore, in the process corresponding to the first upper hole 1a and the second upper hole 2a, relatively steep first blind holes m1 and second blind holes m2 are formed after the first rapid etching, and the second slower etching can trim the hole walls of the first blind holes m1 and second blind holes m2, making the hole walls smoother and less prone to change in the overall slope. At the same time, in the second etching, due to the slower etching speed, the slopes of the first lower holes 1b and second lower holes 2b formed are gentle, thereby reducing the risk of the second electrode 182 being broken.

[0129] Then go to step B03.

[0130] Please refer to Fig.12, step B03 , forming a patterned first metal layer 18 on the interlayer dielectric layer 17 .

[0131] It should be noted that Fig.12 The display panel 100 of the corresponding embodiment and Figure 1 The structure of the display panel 100 of the corresponding embodiment is the same, and the details can be referred to Figure 1 to Figure 2 The relevant explanation is not repeated here.

[0132] Please refer to Fig.13 Accordingly, an embodiment of the present application further provides a display device 1000, which includes the display panel 100 as described in any one of the above embodiments.

[0133] Optionally, the display panel 100 may be an electroluminescent panel, such as an organic light emitting display panel.

[0134] It should be noted that the display panel 100 of the display device 1000 of the embodiment of the present application has a structure similar to or the same as that of the display panel 100 of any of the above embodiments. Figures 1 to 12 , so I will not repeat it here.

[0135] The display device 1000 of the embodiment of the present application uses the same mask to etch the interlayer dielectric layer 17 to form a first contact hole 171 exposing the first active portion 141 and a second contact hole 172 exposing the light shielding portion 121, so as to save masks; secondly, the depths of the first upper hole 1a of the first contact hole 171 and the second upper hole 2a of the second contact hole 172 are equal, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 passes through a portion of the first active portion 141, so as to reduce the degree to which the first active portion 141 is etched.

[0136] The display device 1000 can be applied to and used in various products including, for example, televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation, and ultra mobile personal computers (UMPCs).

[0137] In addition, the display device 1000 according to some embodiments may be applied to a wearable device and may be used in a wearable device, including a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD). In addition, according to some embodiments, the display device 1000 may be applied to an instrument panel for a car, a display screen in a central dashboard or a central information display (CID) arranged on a dashboard for a car, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system arranged on the back of a front seat for rear seat passengers in a car.

[0138] The above is a detailed introduction to a display panel, a preparation method thereof, and a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; A light shielding portion, disposed on the substrate; A buffer layer is arranged on a side of the light shielding portion away from the substrate; A first active portion is disposed on a side of the buffer layer away from the substrate; A first gate is provided in a different layer from the first active portion; an interlayer dielectric layer, covering the first active portion and the first gate on a side away from the substrate, the interlayer dielectric layer being provided with a first contact hole and a second contact hole, the first contact hole having a depth smaller than that of the second contact hole, the first contact hole penetrating the interlayer dielectric layer and exposing the first active portion, and the second contact hole penetrating the interlayer dielectric layer and the buffer layer and exposing the light shielding portion; as well as The first contact hole includes a first upper hole and a first lower hole, the first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion, the first upper hole is connected to a side of the first lower hole away from the substrate, and the opening width of the first lower hole is smaller than the opening width of the first upper hole; The second contact hole includes a second upper hole and a second lower hole, the second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer, the second upper hole is connected to a side of the second lower hole away from the substrate, the opening width of the second lower hole is smaller than the opening width of the second upper hole, the depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole.

2. The display panel according to claim 1, characterized in that: In the thickness direction of the display panel, the distance from the opening end surface of the first lower hole to the first active portion is a first distance, and the first distance is between 1 nanometer and 60 nanometers.

3. The display panel according to claim 2, characterized in that: In the thickness direction of the display panel, the first lower hole penetrates the first active portion to a depth ranging from 1 nanometer to 30 nanometers.

4. The display panel according to claim 3, characterized in that: The distance from the opening of the first lower hole to the hole wall of the first upper hole is a second distance, and the second distance is between 0.1 micrometers and 2 micrometers.

5. The display panel according to claim 4, characterized in that: The distance from the opening of the second lower hole to the hole wall of the second upper hole is a third distance, and the second distance is equal to the third distance.

6. The display panel according to any one of claims 1 to 5, characterized in that: The first lower hole includes a first sub-hole and a second sub-hole, the first sub-hole is connected to the first upper hole, the second sub-hole is connected to a side of the first sub-hole close to the substrate, the second sub-hole is arranged in the first active part, and the opening width of the second sub-hole is smaller than the opening width of the first sub-hole.

7. The display panel according to claim 6, characterized in that: The inclination angle of the hole wall of the first upper hole is greater than the inclination angle of the hole wall of the first sub-hole, and the inclination angle of the hole wall of the first sub-hole is greater than the inclination angle of the hole wall of the second sub-hole.

8. The display panel according to any one of claims 1 to 5, characterized in that: The display panel further comprises a second active portion, a second gate, a first insulating portion, a second insulating portion and a first metal layer, wherein the first insulating portion is arranged on a side of the first active portion away from the substrate, the second active portion, the second insulating portion and the second gate are sequentially stacked and arranged on a side of the buffer layer away from the substrate, and the interlayer dielectric layer covers the first gate, the second gate and the buffer layer; The first metal layer is arranged on a side of the interlayer dielectric layer away from the substrate, and the first metal layer includes a first electrode, a second electrode, a third electrode and a fourth electrode, the first electrode is connected to one side of the first active part through a first contact hole, the second electrode is connected to the other side of the first active part through a first contact hole, and the other end of the second electrode is connected to the shading part through a second contact hole; the third electrode is connected to one side of the second active part through a first contact hole, and the fourth electrode is connected to the other side of the second active part through the first contact hole.

9. The display panel according to claim 8, characterized in that: The first metal layer further includes a first peripheral routing line, the interlayer dielectric layer further includes a third contact hole exposing the second gate, the depth of the third contact hole is less than the depth of the first contact hole, and the first peripheral routing line is connected to the second gate through the third contact hole; The third contact hole includes a third upper hole and a third lower hole, the third lower hole is connected to a side of the third upper hole close to the substrate, the opening width of the third lower hole is smaller than the opening width of the third upper hole, the third lower hole passes through a portion of the second gate, and the depth of the third lower hole is greater than the depth of the first lower hole passing through the first active portion.

10. The display panel according to claim 9, characterized in that: The display panel further includes a second insulating layer, a first electrode plate, a second electrode plate and a third electrode plate, wherein the first electrode plate is arranged in the same layer as the light shielding portion, the second electrode plate is arranged in the same layer as the first active portion and overlaps with the first electrode plate to form a capacitor, the second insulating layer covers the first gate, the second gate, the second electrode plate and the buffer layer, the third electrode plate is arranged on a side of the second insulating layer away from the substrate and forms a capacitor with the second electrode plate, and the interlayer dielectric layer covers the second insulating layer and the third electrode plate; The first metal layer further includes a connecting line, the interlayer dielectric layer is further provided with a fourth contact hole exposing the third electrode plate and another second contact hole exposing the first electrode plate, the first contact hole and the second contact hole also penetrate the second insulating layer; one end of the connecting line is connected to the third electrode plate through the fourth contact hole, and the other end of the connecting line is connected to the first electrode plate through another second contact hole; The fourth contact hole includes a fourth upper hole and a fourth lower hole, the fourth lower hole is connected to the side of the fourth upper hole close to the substrate, the opening width of the fourth lower hole is smaller than the opening width of the fourth upper hole, the fourth lower hole passes through a portion of the third electrode plate, and the depth of the fourth lower hole is greater than the depth of the first lower hole passing through the first active portion.

11. A method for preparing a display panel, characterized in that: The following steps are involved: A light shielding portion, a buffer layer, a first active portion, a first insulating portion, a first gate and an interlayer dielectric layer are sequentially formed on a substrate; The interlayer dielectric layer is dry-etched twice using the same photomask to form a first contact hole and a second contact hole, wherein the depth of the first contact hole is smaller than the depth of the second contact hole, the first contact hole penetrates the interlayer dielectric layer and exposes the first active portion, the second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light shielding portion, the first contact hole comprises a first upper hole and a first lower hole, the first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion, the first upper hole is connected to a side of the first lower hole away from the substrate, and the opening width of the first lower hole is smaller than the opening width of the first upper hole; The second contact hole includes a second upper hole and a second lower hole, the second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer, the second upper hole is connected to a side of the second lower hole away from the substrate, the opening width of the second lower hole is smaller than the opening width of the second upper hole, the depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole.

12. The method for preparing a display panel according to claim 11, characterized in that: The step of performing dry etching twice on the interlayer dielectric layer using the same photomask to form a first contact hole and a second contact hole comprises: Performing a first dry etching on the interlayer dielectric layer based on a mask to form a first blind hole corresponding to the first active portion and a second blind hole corresponding to the light shielding portion, wherein the first blind hole and the second blind hole have the same depth, and a distance from the bottom of the first blind hole to the first active portion is a set distance, and the set distance is between 10 nanometers and 80 nanometers; Based on the same mask, the interlayer dielectric layer is dry-etched for a second time to form a first contact hole and a second contact hole, wherein the distance from the opening end surface of the first lower hole to the first active portion is a first distance, and the first distance is between 1 nanometer and 60 nanometers; wherein the etching rate of the interlayer dielectric layer by the second dry etching is greater than the etching rate of the first active portion by the second dry etching.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-10.

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