Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate is provided with a first area and a second area which are arranged side by side in the first direction, the size of the first area in the second direction is smaller than that of the second area in the second direction, and the first direction intersects with the second direction; the array substrate comprises a plurality of first signal lines and compensation signal lines, the first signal lines extend in the second direction, and the first signal lines comprise first-class signal lines located in the first area and second-class signal lines located in the second area. The length of the first type of signal lines in the second direction is smaller than the length of the second type of signal lines in the second direction. The compensation signal line comprises a first wire extending in the second direction and a second wire extending in the first direction, and the first wire is electrically connected to the first type signal line through the second wire. Wherein the first wire and the second wire are located in a display area of the array substrate.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In order to meet market demand, the development of special-shaped folding screens has become a trend, but the display screens are prone to split-screen problems, affecting display reliability. Summary of the invention

[0003] Embodiments of the present application provide an array substrate, a display panel, and a display device, which can improve display reliability.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate having a first area and a second area arranged side by side in a first direction, the size of the first area in the second direction is smaller than the size of the second area in the second direction, and the first direction intersects the second direction;

[0005] The array substrate includes a plurality of first signal lines and compensation signal lines, wherein the first signal lines extend along a second direction, the plurality of first signal lines include a type of signal lines located in a first area and a type of second signal lines located in a second area, and the length of the first type of signal lines in the second direction is less than the length of the second type of signal lines in the second direction. The compensation signal lines include a first routing line extending along the second direction and a second routing line extending along the first direction, and the first routing line is electrically connected to the first type of signal lines through the second routing line. The first routing line and the second routing line are located in the display area of ​​the array substrate.

[0006] In some embodiments, the array substrate includes a first display area and a second display area, the first display area includes a first sub-display area located in the first area, and a second sub-display area located in the second area, and the second display area is located in the second area and on one side of the second sub-display area in the second direction;

[0007] The first type of signal lines are located in the first sub-display area, and the second type of signal lines are partially located in the second sub-display area and partially located in the second display area;

[0008] In some embodiments, the second display area and the second sub-display area are spaced apart in the second direction;

[0009] In some embodiments, the compensation signal line is located in the first display area.

[0010] In some embodiments, the first trace is located in the first sub-display area;

[0011] In some embodiments, the second trace is located in the first sub-display area;

[0012] In some embodiments, the first wiring is located at a side of the first type signal line electrically connected thereto away from the second sub-display area.

[0013] In some embodiments, the extension length of the compensation signal line is less than the extension length of the first type signal line;

[0014] In some embodiments, an extension length of the first wiring is less than or equal to a size of the second display area in the second direction.

[0015] In some embodiments, the second type of signal line includes a first sub-segment located in the second sub-display area, and a second sub-segment located in the second sub-display area;

[0016] The extension length of the compensation signal line is less than or equal to the extension length of the second sub-segment;

[0017] In some embodiments, an extension length of the first trace is less than an extension length of the second sub-segment.

[0018] In some embodiments, the extension length of the first trace is greater than the extension length of the second trace;

[0019] In some embodiments, the ordering of the plurality of first traces in the first direction is the same as the ordering of the first type of signal lines of the corresponding electrical connection arrangement in the first direction;

[0020] In some embodiments, the first routing line includes a first connection end, the first routing line is connected to the second routing line through the first connection end, and the distance between the first connection end and the second display area in the second direction tends to gradually increase in the direction from the second sub-display area to the first sub-display area.

[0021] In some embodiments, an orthographic projection of the first trace on the substrate is outside an orthographic projection of the first signal line on the substrate;

[0022] In some embodiments, the array substrate includes a first conductor layer located on one side of the substrate, and the first signal line and the first routing line are both located in the first conductor layer;

[0023] In some embodiments, the array substrate further includes a second conductor layer located between the first conductor layer and the substrate, and the second trace is located in the second conductor layer;

[0024] In some embodiments, at least a portion of the second routing lines have an orthographic projection on the substrate that overlaps with an orthographic projection of the plurality of first signal lines on the substrate;

[0025] In some embodiments, the array substrate includes a first conductor layer located on one side of the substrate, and the first conductor layer includes a first signal line and a first power line extending along the second direction;

[0026] In some embodiments, the first signal line is used to transmit a data signal;

[0027] In some embodiments, a first routing line is disposed between two first signal lines that are closest to each other.

[0028] In some embodiments, an orthographic projection of the second wiring on the substrate overlaps with an orthographic projection of the first power line on the substrate;

[0029] In some embodiments, at least two first signal lines are provided between the two first power lines closest to each other;

[0030] In some embodiments, at least a portion of the first routing line is located between adjacent first signal lines; and / or, at least a portion of the first routing line is located between adjacent first power lines and first signal lines.

[0031] In some embodiments, the first signal line and the first routing line are arranged in different layers;

[0032] In some embodiments, an orthographic projection of the first routing line on the substrate is arranged to overlap with an orthographic projection of the first signal line on the substrate;

[0033] In some embodiments, the array substrate includes a second conductor layer located on one side of the substrate, and a first conductor layer located on a side of the second conductor layer facing away from the substrate;

[0034] The first signal line is located in the first conductor layer, and the first routing line and the second routing line are both located in the second conductor layer.

[0035] In a second aspect, an embodiment of the present application provides a display panel, which includes a light-emitting structure and an array substrate as described in any of the above embodiments, wherein part of the light-emitting structure is located in the first area and part of the light-emitting structure is located in the second area.

[0036] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel in any of the aforementioned embodiments.

[0037] The embodiments of the present application provide an array substrate, a display panel, and a display device, wherein the orthographic projection of at least part of the first routing line on the substrate is located between the orthographic projections of two first signal lines on the substrate, that is, the first routing line can be integrated with multiple first signal lines at the same time within the same area, and the second routing line needs to be electrically connected to the first routing line and the first signal line, so the second routing line can usually be integrated with the first routing line and the first signal line within the same area, thereby reducing the space occupied by the compensation signal line in the peripheral edge area. Thus, while compensating the first type of signal lines to improve the uniformity of the capacitance corresponding to different first signal lines, a narrow frame effect is achieved, and the viewing experience of the display panel and display device formed subsequently is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1a and 1b is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0040] Figure 2 is a schematic structural diagram of a first signal line in an array substrate provided in an embodiment of the present application;

[0041] Figure 3 This is a schematic diagram of a wiring structure in a local area of ​​an array substrate provided in an embodiment of the present application;

[0042] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure at AA in the middle;

[0043] Figure 5 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0044] Figure 6 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0045] Figure 7 This is a schematic diagram of a wiring structure in a local area of ​​another array substrate provided in an embodiment of the present application;

[0046] Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure at BB in the middle;

[0047] Fig. 9 This is a schematic diagram of a wiring structure in a local area of ​​an array substrate provided in an embodiment of the present application;

[0048] Fig.10 This is a schematic diagram of a wiring structure in a local area of ​​an array substrate provided in an embodiment of the present application;

[0049] Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure at CC in the middle.

[0050] Marking Description:

[0051] 100, array substrate; 200, display panel; 300, display device; 310, main screen; 320, sub-screen;

[0052] 10. Substrate;

[0053] 20, first signal line; 20a, first type signal line; 20b, second type signal line; 21, first sub-segment; 22, second sub-segment; 23, first line; 24, second line; 25, third line;

[0054] 30. Compensation signal line; 31. First routing line; 32. Second routing line;

[0055] 40. a first conductor layer; 41. a first power line;

[0056] 50. second conductor layer;

[0057] A1, first area; A2, second area; A3, first display area; A31, first sub-display area; A32, second sub-display area; A4, second display area;

[0058] D1, a first connection end;

[0059] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0060] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0061] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0062] In response to market demand, the development of special-shaped folding screens has become a trend. However, due to the large missing corner area in the special-shaped folding screen, the corresponding wiring forms in different areas inside the display panel are quite different, which easily leads to split screen problems. In order to reduce the display difference, in the related technology, windings can be added in the non-display area in the peripheral area of ​​the display panel that is not used to realize the display function, and some wiring can be compensated by winding.

[0063] However, the space required for winding is usually large, which may easily lead to an increase in the size of the non-display area, or due to the limited size of the non-display area, the compensation amount corresponding to the winding may be insufficient, which not only affects the overall appearance of the product, but also reduces the image quality. In addition, during the preparation of the display panel, the corresponding peripheral edge of the display panel usually needs to be cut, and the increase in winding may easily lead to the risk of at least part of the film layer in the display panel peeling off during the cutting process, and may also increase the risk of bubble generation.

[0064] Regarding the above issues, first, please refer to Figures 1 to Figure 6 The embodiment of the present application provides an array substrate 100, the array substrate 100 has a first area A1 and a second area A2 arranged side by side in a first direction X, the size of the first area A1 in the second direction Y is smaller than the size of the second area A2 in the second direction Y, and the first direction X intersects the second direction Y;

[0065] The array substrate 100 includes a plurality of first signal lines 20 and compensation signal lines 30, wherein the first signal lines 20 extend along the second direction Y, and the plurality of first signal lines 20 include first-type signal lines 20a located in the first area A1 and second-type signal lines 20b located in the second area A2, wherein the length of the first-type signal lines 20a in the second direction Y is less than the length of the second-type signal lines 20b in the second direction Y. The compensation signal lines 30 include first routing lines 31 extending along the second direction Y, and second routing lines 32 extending along the first direction X, wherein the first routing lines 31 are electrically connected to the first-type signal lines 20a through the second routing lines 32. The first routing lines 31 and the second routing lines 32 are located in the display area of ​​the array substrate 100.

[0066] like Figure 5 and Figure 6As shown, the array substrate 100 is used to subsequently form a special-shaped display panel 200, and the special-shaped display panel 200 can have a variety of application forms. Taking the special-shaped display panel 200 used to form a folding display device 300 as an example, the folding display device 300 usually has two display areas, a main screen 310 and a sub-screen 320. The luminous surfaces corresponding to the main screen 310 and the sub-screen 320 are respectively located on both sides of the display device 300 in the thickness direction Z, and in order to avoid components such as cameras, the size of the sub-screen 320 is often smaller than that of the main screen 310. In the unfolded state, the main screen 310 in the folding display device 300 is used for viewing by the user, and in the folded state, the sub-screen 320 in the folding display device 300 is used for viewing by the user.

[0067] During the manufacturing process of the folding display device 300, the corresponding display panel 200 often needs to be made into a special shape, while the shape and size of the array substrate 100 used to form the display panel 200 are the same or similar to those of the display panel 200. Specifically, the array substrate 100 has a first area A1 and a second area A2 arranged side by side in the first direction X, and the size of the first area A1 in the second direction Y is smaller than the size of the second area A2 in the second direction Y. Among them, the partial structure of the second area A2 that exceeds the first area A1 in the second direction Y can be used to form a secondary screen later, and the partial structure of the first area A1 and the second area A2 that are correspondingly arranged in the second direction Y can be used to form a main screen, and then the partial structure of the second area A2 that exceeds the first area A1 in the second direction Y is bent to the back of the first area A1, so that the corresponding light-emitting surfaces of the main screen and the secondary screen are respectively located on both sides of the display device 300 in the thickness direction Z, meeting the needs of the folding display device 300 in different usage states.

[0068] The array substrate 100 includes a display area, which corresponds to an area in the display panel 200 formed subsequently for realizing a display effect. Furthermore, Figure 1b FIG. 1 shows a case where the display area of ​​the array substrate 100 includes a first display area A3 and a second display area A4. Figure 1a and Figure 1b It can be seen that part of the first display area A3 is located in the first area A1, the rest of the area is located in the second area A2, and the second display area A4 is completely located in the second area A2.

[0069] It should be noted that, although the embodiment of the present application provides a specific implementation method of the special-shaped display panel 200 corresponding to the array substrate 100 for subsequently forming the folding display device 300, it does not constitute a limitation on the application scenarios corresponding to the array substrate 100 and the display panel 200 provided in the embodiment of the present application. For example, the display device 300 may not be a folding display device 300, but a special-shaped display device 300, which can also be applied to the array substrate 100 and the display panel 200 provided in the embodiment of the present application, and in this case, it is not necessary to bend the part of the structure of the second area A2 that exceeds the first area A1 in the second direction Y during the preparation process.

[0070] The specific shape and size of the first area A1 and the second area A2 are not limited in the embodiment of the present application, wherein FIG. 1 shows the case where the first area A1 and the second area A2 are both rectangular structures, and the boundary between the first area A1 and the second area A2 is illustrated as a virtual straight line. However, in other embodiments, the first area A1 and the second area A2 may also be in other shapes, as long as the first area A1 and the second area A2 are arranged side by side in the first direction X, and the size of the first area A1 in the second direction Y is smaller than the size of the second area A2 in the second direction Y. Optionally, the first direction X is perpendicular to the second direction Y.

[0071] The substrate 10 is a film layer structure used to play a supporting role in the array substrate 100, and other film layers are sequentially arranged along the thickness direction Z of the substrate 10, wherein the thickness direction Z corresponding to the other film layers is usually the same as the thickness direction Z of the substrate 10, so for the convenience of representation, the embodiment of the present application shows the thickness direction Z of the substrate 10 and the thickness direction Z of other film layers in the same direction. Optionally, the substrate 10 can be a flexible substrate 10, that is, the substrate 10 includes a flexible material, which facilitates the bending process of the substrate 10 in the subsequent preparation process.

[0072] Multiple first signal lines 20 are located on one side of the substrate 10. The first signal line 20 is a routing structure in the array substrate 100 for transmitting specific potential signals. The embodiment of the present application does not limit the specific potential signal type in the first signal line 20. The first signal line 20 can be used to transmit a constant voltage signal, or the first signal line 20 can also be used to transmit a variable voltage signal.

[0073] The first signal line 20 extends along the second direction Y, and the plurality of first signal lines 20 are arranged in the first area A1 and the second area A2, which results in differences in extension lengths between different first signal lines 20. Specifically, the plurality of first signal lines 20 include a first type of signal line 20a located in the first area A1 and a second type of signal line 20b located in the second area A2. The first type of signal line 20a and the second type of signal line 20b both extend along the second direction Y, so the corresponding extension lengths of the two depend on the dimensions of the first area A1 and the second area A2 in the second direction Y, that is, the extension length of the first type of signal line 20a is often less than the extension length of the second type of signal line 20b. Furthermore, the difference in extension length will lead to corresponding differences in resistance values ​​and corresponding differences in capacitance, which can easily cause split screen problems.

[0074] In the related art, in order to reduce the split-screen problem, a winding structure is usually added to the outer edge area of ​​the array substrate 100, that is, a winding structure is added to the outer peripheral side of all the first signal lines 20, and the first type of signal line 20a is compensated with the help of the winding structure. However, this can easily affect the border size of the product, resulting in a reduction in the screen-to-body ratio, which is not conducive to the viewing experience.

[0075] In view of this, the embodiment of the present application cancels the winding structure at the peripheral edge area, and instead adds a compensation signal line 30 at the display area, and compensates the first type of signal line 20a with the help of the compensation signal line 30. Specifically, the compensation signal line 30 includes a first routing line 31 extending along the second direction Y and a second routing line 31 extending along the first direction X, and the first routing line 31 is electrically connected to the first type of signal line 20a through the second routing line 32. Among them, the first routing line 31 and the second routing line 32 can be located in the same film layer, or the two can also be located in different film layers, and the first routing line 31 and the first signal line 20 can be located in the same film layer, or the two can also be located in different film layers, and the embodiment of the present application does not limit this. As for the second routing line 32 and the first signal line 20, if the two are set in the same layer, it will cause the second routing line 32 to cross-interfere with the part of the first signal line 20 that should be relatively insulated, so the second routing line 32 needs to be set in a different layer from the first signal line 20.

[0076] Since the first wiring 31 and the first signal line 20 both extend along the second direction Y, the first wiring 31 can avoid the first signal line 20 regardless of whether they are arranged in the same layer. On this basis, the embodiment of the present application arranges the first wiring 31 and the second wiring 32 in the display area of ​​the array substrate 100, that is, the first wiring 31 and the second wiring 32 can be integrated with multiple first signal lines 20 at the same time in the same area, thereby reducing the space occupied by the compensation signal line 30 in the peripheral edge area. In this way, while compensating the first type of signal line 20a to improve the uniformity of the capacitance corresponding to different first signal lines 20, a narrow frame effect is achieved, and the viewing experience of the display panel 200 and the display device 300 formed subsequently is improved.

[0077] It should be noted that, according to different actual needs, the first trace 31 can be set in a partial area of ​​the display area within the first area A1, or can be set in a partial area of ​​the display area within the second area A2, or can be set at the junction of the first area A1 and the second area A2.

[0078] In addition, the embodiment of the present application does not limit the specific lengths of the first routing line 31 and the second routing line 32. For example, the extension length of the first routing line 31 may be greater than the extension length of the second routing line 32, or the extension length of the first routing line 31 may be less than or equal to the extension length of the second routing line 32. Moreover, the extension lengths of different first routing lines 31 may be the same or different, and the same applies to different second routing lines 32.

[0079] In some embodiments, as shown in FIG. 1 to Figure 4 As shown, the array substrate 100 includes a first display area A3 and a second display area A4, the first display area A3 includes a first sub-display area A31 located in the first area A1, and a second sub-display area A32 located in the second area A2, the second display area A4 is located in the second area A2, and is located at one side of the second sub-display area A32 in the second direction Y. The first type signal line 20a is located in the first sub-display area A31, and the second type signal line 20b is partially located in the second sub-display area A32 and partially located in the second display area A4.

[0080] The first display area A3 and the second display area A4 are both areas on the array substrate 100 for setting the light-emitting structure to realize the display function. Taking the array substrate 100 as an example, the first display area A3 may correspond to the area where the main screen is located, and the second display area A4 may correspond to the area where the secondary screen is located. Among them, the first display area A3 and the second display area A4 may have a variety of shapes, for example, at least one of the first display area A3 and the second display area A4 may be circular, square or other shapes, and the shape types corresponding to the first display area A3 and the second display area A4 may be the same, or may be different.

[0081] The first display area A3 includes a first sub-display area A31 and a second sub-display area A32, wherein the first sub-display area A31 is a partial area of ​​the first display area A3 located within the first area A1, and the second sub-display area A32 is a partial area of ​​the first display area A3 located within the second area A2. Exemplarily, the first sub-display area A31 and the second sub-display area A32 are arranged side by side in the first direction X, and the sizes of the first sub-display area A31 and the second sub-display area A32 in the second direction Y can be kept the same or similar.

[0082] The second display area A4 is completely located within the second area A2, and the second display area A4 and the second sub-display area A32 are arranged side by side in the second direction Y, wherein the second display area A4 and the second sub-display area A32 may be interconnected, or the second display area A4 and the second sub-display area A32 may also be spaced apart from each other, that is, there may be a partial non-display area between the second display area A4 and the second sub-display area A32, or there may be no other area between the two. FIG. 1 shows the case where the second display area A4 and the second sub-display area A32 are spaced apart.

[0083] Further, most of the structures of the first type signal lines 20a located in the first area A1 are located in the first sub-display area A31, so the extension length of the first type signal lines 20a depends on the size of the first sub-display area A31 in the second direction Y. Part of the structures of the second type signal lines 20b located in the second area A2 are located in the second sub-display area A32, and part are located in the second display area A4, so the extension length of the second type signal lines 20b depends on the sum of the sizes of the second sub-display area A32 and the second display area A4 in the second direction Y. In this case, the extension length of the first type signal lines 20a is often less than the extension length of the second type signal lines 20b.

[0084] Therefore, in the embodiment of the present application, a compensation signal line 30 is added and the compensation signal line 30 is electrically connected to the first type of signal line 20a, so as to achieve a compensation effect on the first type of signal line 20a, reduce the voltage drop difference corresponding to the first type of signal line 20a and the second type of signal line 20b, and improve the capacitance uniformity.

[0085] Further optionally, the compensation signal line 30 is located in the first display area A3, that is, the first wiring 31 and the second wiring 32 are both located in the first display area A3. In this design, the existence of the compensation signal line 30 will not have too much impact on the size of the peripheral edge area, which helps to improve the viewing experience of the display panel 200 and the display device 300 formed subsequently.

[0086] It should be noted that the specific positional relationship between the first wiring 31 and the second wiring 32 relative to the first sub-display area A31 and the second sub-display area A32 is not limited in the present embodiment. The first wiring 31 can be located in the first sub-display area A31, or the first wiring 31 can also be located in the second sub-display area A32, and the second wiring 32 is the same.

[0087] In some embodiments, see Figure 2 and Figure 7 , the first wiring 31 is located in the first sub-display area A31.

[0088] In the embodiment of the present application, the first wiring 31 and the first type of signal line 20a are both located in the first sub-display area A31, so that the distance between the first wiring 31 and the first type of signal line 20a in the second direction Y can be reduced, thereby facilitating the electrical connection between the first wiring 31 and the first type of signal line 20a. And this design also helps to reduce the corresponding extension length of the second wiring 32, thereby reducing the occupation of the second wiring 32 on other film layer spaces, reducing the risk of cross-interference between the second wiring 32 and the conductor structure in other film layers, and reducing the layout difficulty of the internal structure of the array substrate 100. Further optionally, the second wiring 32 is located in the first sub-display area A31.

[0089] In some embodiments, Figure 2 and Figure 7 As shown, the first wiring 31 is located at a side of the first type signal line 20a electrically connected thereto away from the second sub-display area A32.

[0090] In the embodiment of the present application, for the first wiring 31 and the first type signal line 20a which are electrically connected to each other, the first wiring 31 is located on the side of the first type signal line 20a away from the second sub-display area A32, that is, the first wiring 31 is located on the side of the first type signal line 20a away from the second type signal line 20b. This helps to increase the distance between the first wiring 31 and the second type signal line 20b in the first direction X, thereby reducing the risk of the internal signal of the second type signal line 20b interfering with the first type signal line 20a through the first wiring 31, and improving the reliability of signal transmission between the first type signal line 20a and the second type signal line 20b.

[0091] In some embodiments, the extension length of the compensation signal line 30 is less than the extension length of the first type signal line 20a. The compensation signal line 30 includes a first line 31 and a second line 32, so the extension length of the compensation signal line 30 is the sum of the extension length of the first line 31 and the extension length of the second line 32.

[0092] In combination with the above content, it can be known that the extension length of the first type signal line 20a depends on the size of the first display area A3 in the second direction Y, and the extension length of the second type signal line 20b depends on the sum of the sizes of the first display area A3 and the second display area A4 in the second direction Y. In this case, the voltage drop and capacitance difference corresponding to the first type signal line 20a and the second type signal line 20b are often caused by the partial structure of the second type signal line 20b in the second display area A4. Usually, the size of the first display area A3 in the second direction Y is larger than the size of the second display area A4 in the second direction Y. Therefore, if the compensation signal line 30 is much larger than the extension length corresponding to the partial structure of the second type signal line 20b in the second display area A4, it is also easy to cause the risk of excessive voltage drop and capacitance difference between the first type signal line 20a and the second type signal line 20b, which is not conducive to the actual display effect.

[0093] In view of this, the embodiment of the present application sets the extension length of the compensation signal line 30 to be smaller than the extension length of the first type signal line 20a, thereby reducing the difference between the sum of the extension lengths of the compensation signal line 30 and the first type signal line 20a and the second type signal line 20b, thereby reducing the voltage drop difference corresponding to the first type signal line 20a and the second type signal line 20b and improving the capacitance uniformity.

[0094] Further, in some optional embodiments, such as Figure 2 and Figure 7 As shown, the second type signal line 20 b includes a first sub-segment 21 located in the second sub-display area A32 and a second sub-segment 22 located in the second display area A4 , and the extension length of the compensation signal line 30 is less than or equal to the extension length of the second sub-segment 22 .

[0095] The second-category signal line 20b at least includes a first sub-segment 21 and a second sub-segment 22. Since the first sub-segment 21 and the first-category signal line 20a are both located in the first display area A3, the sizes of the first sub-segment 21 and the first-category signal line 20a in the second direction Y are usually kept the same or similar. The second sub-segment of the second-category signal line 20b located in the second display area A4 is the main factor causing the voltage drop and capacitance difference between the first-category signal line 20a and the second-category signal line 20b.

[0096] In view of this, by adding a compensation signal line 30 in the array substrate 100, the voltage drop and capacitance difference between different first signal lines 20 caused by the existence of the second sub-segment 22 are compensated. On this basis, the present application also controls the extension length of the compensation signal line 30 to be not greater than the length of the second sub-segment 22, so as to limit the compensation amount of the compensation signal line 30 to the first type of signal line 20a, reduce the voltage drop and capacitance difference between different first signal lines 20 caused by the excessive extension length of the compensation signal line 30, and further improve the corresponding use experience of the display panel 200 and the display device 300 formed subsequently. Optionally, the extension length of the first routing line 31 is less than the extension length of the second sub-segment 22.

[0097] Further, in some optional embodiments, the sum of the length of the first wiring 31 and the length of the second wiring 32 is equal to the length of the second type signal line 20b in the second display area A4 in the second direction Y, thereby reducing the voltage drop and capacitance difference corresponding to the first type signal line 20a and the second type signal line 20b, thereby reducing the display difference between different display areas of the display panel 200. The same length in this article means that the two are approximately the same, or the same within a certain error range.

[0098] In some embodiments, the extension length of the first trace 31 is greater than the extension length of the second trace 32 .

[0099] In the embodiment of the present application, the first wiring 31 and the first signal line 20 both extend along the second direction Y, so no matter the first wiring 31 and the first signal line 20 are arranged in the same layer or in different layers, no cross interference occurs between the first wiring 31 and the first signal line 20. Furthermore, the extension length of the compensation signal line 30 can be controlled by adjusting the extension length of the first wiring 31.

[0100] In view of this, the embodiment of the present application sets the extension length of the first routing line 31 to be greater than the extension length of the second routing line 32. On this basis, the extension lengths of different compensation signal lines 30 can be controlled by adjusting the extension lengths of different first routing lines 31, thereby achieving adjustment of the corresponding compensation amounts of different first-class signal lines 20a, which has strong flexibility and practicality.

[0101] In some embodiments, Figure 6 As shown, the arrangement of the first wirings 31 in the first direction X is the same as the arrangement of the first type signal lines 20 a correspondingly electrically connected in the first direction X.

[0102] Specifically, in conjunction with the figure, multiple first-class signal lines 20a can be arranged side by side from left to right, and the first routing lines 31 electrically connected to the multiple first-class signal lines 20a are also arranged side by side from left to right. This design can make the arrangement of the multiple first routing lines 31 the same as the arrangement of the corresponding multiple first-class signal lines 20a, thereby reducing the difficulty of electrical connection between the first-class signal lines 20a and the corresponding first routing lines 31.

[0103] In addition, this design can also reduce the maximum distance between the first type of signal line 20a and the first routing line 31 of the corresponding electrical connection setting in the first direction X, thereby reducing the difference in the extension lengths corresponding to different second routing lines 32, so that the extension length of the compensation signal line 30 can be controlled and adjusted only by adjusting the extension lengths corresponding to different first routing lines 31. Compared with the solution of adjusting the extension lengths of different second routing lines 32, this solution has lower layout difficulty and is more practical.

[0104] In some embodiments, as shown in FIG. 1 and Figure 6 As shown, the first routing line 31 includes a first connection end D1, and the first routing line 31 is connected to the second routing line 32 through the first connection end D1. In the direction from the second sub-display area A32 to the first sub-display area A31, the distance between the first connection end D1 and the second display area A4 in the second direction Y tends to gradually increase.

[0105] The first connection end D1 may be an end point of the first routing line 31 in the second direction Y, and the first routing line 31 is connected to the second routing line 32 via the first connection end D1. When the first routing line 31 and the second routing line 32 are arranged on the same layer, the first connection end D1 may be directly connected to the second routing line 32. When the first routing line 31 and the second routing line 32 are arranged on different layers, a via structure may be correspondingly provided at the first connection end D1, and the first connection end D1 may be connected to the second routing line 32 via the via structure.

[0106] In the embodiment of the present application, the arrangement of the plurality of first wirings 31 is maintained the same as the arrangement of the corresponding plurality of first-type signal lines 20a, and the plurality of first connection terminals D1 are arranged in the second direction Y according to a specific rule, so that the first wirings 31 and the second wirings 32 that are insulated from each other can be offset from each other in their orthographic projections on the substrate 10, thereby helping to improve the reliability of signal transmission within the array substrate 100.

[0107] In some embodiments, an orthographic projection of the first trace 31 on the substrate 10 is located outside an orthographic projection of the first signal line 20 on the substrate 10 .

[0108] In combination with the above content, it can be known that the first routing line 31 and the first signal line 20 both extend along the second direction Y. On this basis, the orthographic projection of the first routing line 31 on the substrate 10 can be located outside the orthographic projection of the first signal line 20 on the substrate 10. The first routing line 31 and the first signal line 20 can be located in the same film layer, or the first routing line 31 can also be located on the side of the first signal line 20 facing the substrate 10 or away from the substrate 10.

[0109] In some embodiments, please refer to FIG. Figure 6 and Figure 7 The array substrate 100 includes a first conductor layer 40 located on one side of the substrate 10 , and the first signal line 20 and the first routing line 31 are both located in the first conductor layer 40 .

[0110] In the embodiment of the present application, the first signal line 20 and the first routing line 31 are both located in the first conductor layer 40, that is, the first signal line 20 and the first routing line 31 are located in the same film layer, which can reduce the occupation of the space of other film layers by the existence of the first routing line 31, thereby facilitating the reduction of the thickness of the display panel 200 and the display device 300 formed subsequently. Further, optionally, the first signal line 20 and the first routing line 31 include the same material and are prepared and formed together in the same process, thereby simplifying the corresponding preparation process of the array substrate 100 and improving the preparation efficiency.

[0111] The specific positional relationship of the second wiring 32 relative to the first signal line 20 and the first wiring 31 is not limited in the embodiment of the present application, that is, the second wiring 32 can be located on the side of the first conductor layer 40 facing the substrate 10, or on the side of the first conductor layer 40 facing away from the substrate 10. Optionally, the array substrate 100 further includes a second conductor layer 50 located between the first conductor layer 40 and the substrate 10, and the second wiring 32 is located in the second conductor layer 50.

[0112] Further, since the second routing lines 32 and the first signal lines 20 are arranged in different film layers and have different extension directions, the orthographic projections of at least some of the second routing lines 32 on the substrate 10 are optionally arranged to overlap with the orthographic projections of the plurality of first signal lines 20 on the substrate 10. Part of the plurality of second routing lines 32 may only overlap with the orthographic projection of a single first signal line 20 on the substrate 10, or the orthographic projections of all the second routing lines 32 on the substrate 10 may also overlap with the orthographic projections of the plurality of first signal lines 20 on the substrate 10.

[0113] In some embodiments, as shown in FIG. 1, Figure 6 , Figure 7 as well as Figure 8As shown, the array substrate 100 includes a first conductor layer 40 located on one side of the substrate 10 , and the first conductor layer 40 includes a first signal line 20 and a first power line 41 extending along the second direction Y.

[0114] The first power line 41 is a conductor structure for providing a power signal. Exemplarily, the first power line 41 can be used to transmit a PVDD signal. The first power line 41 and the first signal line 20 are both located in the first conductor layer 40, that is, the first power line 41 and the first signal line 20 are conductor structures arranged in the same layer and used to transmit different signals. Optionally, the first signal line 20 is used to transmit a data signal, that is, the first signal line 20 is a data line.

[0115] The data line extends along the second direction Y and the extension length of the data line depends on the size of the array substrate 100 at its corresponding position. Furthermore, since the sizes of the first area A1 and the second area A2 in the second direction Y are not the same, the extension length of the data line located in the first area A1 is also different from the extension length of the data line located in the second area A2, which in turn causes differences in the voltage drop and capacitance corresponding to different data lines, which can easily lead to problems such as split screen.

[0116] On this basis, the embodiment of the present application adds a compensation signal line 30 in the array substrate 100, and sets the orthographic projection of the compensation signal line 30 on the substrate 10 between the orthographic projections of two data lines on the substrate 10, so that while some data lines are compensated with the help of the compensation signal line 30 to reduce the corresponding voltage drop and capacitance difference between different data lines, the compensation signal line 30 can also reduce the impact of the corresponding border size of the display panel 200 and the display device 300 formed subsequently, thereby improving the display perception.

[0117] In some embodiments, a first trace 31 is disposed between two first signal traces 20 that are closest to each other.

[0118] Combination Fig. 9 It can be seen that for a plurality of first signal lines 20, the distances between different adjacent first signal lines 20 may be different. Specifically, the first line 23, the second line 24, and the third line 25 are three first signal lines 20 that are adjacent in sequence. The first line 23 and the third line 25 are both disposed adjacent to the second line 24. However, for the second line 24, the distance between it and the first line 23 is smaller than the distance between it and the third line 25. Therefore, the first line 23 and the second line 24 are the two first signal lines 20 that are closest to each other, while the third line 25 and the second line 24 are two adjacent first signal lines 20, but not the two first signal lines 20 that are closest to each other.

[0119] On this basis, in the embodiment of the present application, a first routing line 31 is provided between the two first signal lines 20 that are closest to each other, so that the minimum distance between the first routing line 31 and the first signal line 20 can be smaller than the minimum distance between the first routing line 31 and the first power line 41, thereby reducing the mutual interference between the data signal and the PVDD signal.

[0120] The embodiment of the present application does not limit the positional relationship between the first wiring 31 and the second wiring 32 relative to the first power line 41. Optionally, the orthographic projection of the second wiring 32 on the substrate 10 overlaps with the orthographic projection of the first power line 41 on the substrate 10.

[0121] In addition, the present embodiment does not limit the layout of the first power line 41 and the first signal line 20 in the first conductor layer 40. Figure 6 As shown, at least two first signal lines 20 are arranged between the two first power lines 41 that are closest to each other, that is, two first signal lines 20 are arranged between every two first power lines 41 .

[0122] Furthermore, the first trace 31 may have various positional relationships relative to the first signal line 20 and the first power line 41. Fig. 9 , at least part of the first traces 31 are located between adjacent first signal lines 20; and / or Figure 7 As shown, at least a portion of the first trace 31 is located between the adjacent first power line 41 and the first signal line 20 .

[0123] It should be noted that the “adjacent first signal lines 20” mentioned here means that there are no other first signal lines 20 and first power lines 41 between the two first signal lines 20. Similarly, the “adjacent first power lines 41 and first signal lines 20” mentioned here means that there are no other first power lines 41 and first signal lines 20 between the first power lines 41 and the first signal lines 20.

[0124] In some embodiments, see Fig.10 and Fig.11 The first signal line 20 and the first routing line 31 are arranged in different layers.

[0125] In the embodiment of the present application, the first wiring 31 and the first signal line 20 may also be located in different film layers. In this case, the orthographic projections of the first wiring 31 and the first signal line 20 on the substrate 10 may overlap each other, or the orthographic projection of the first wiring 31 on the substrate 10 may also be located outside the orthographic projection of the first signal line 20 on the substrate 10. Optionally, the orthographic projection of the first wiring 31 on the substrate 10 overlaps with the orthographic projection of the first signal line 20 on the substrate 10.

[0126] In some optional embodiments, the array substrate 100 includes a second conductor layer 50 located on one side of the substrate 10, and a first conductor layer 40 located on a side of the second conductor layer 50 facing away from the substrate 10. The first signal line 20 is located in the first conductor layer 40, and the first routing line 31 and the second routing line 32 are both located in the second conductor layer 50.

[0127] In the embodiment of the present application, since the first routing line 31 and the first signal line 20 are arranged in different layers, the first routing line 31 and the second routing line 32 can both be arranged in the second conductor layer 50, that is, the first routing line 31 and the second routing line 32 are arranged in the same layer, so that the first routing line 31 and the second routing line 32 in the compensation signal line 30 can be formed together in the same process, thereby improving the corresponding preparation efficiency of the array substrate 100.

[0128] Second, as Figure 5 As shown, an embodiment of the present application provides a display panel 200, which includes a light-emitting structure and an array substrate in any of the aforementioned embodiments, wherein part of the light-emitting structure is located in the first area, and part of the light-emitting structure is located in the second area.

[0129] It should be noted that the display panel 200 provided in the embodiment of the present application may have various forms, for example, it may be a liquid crystal display panel 200, an organic light-emitting display panel 200, and a micro-light-emitting diode display panel 200, and the embodiment of the present application is not limited to this.

[0130] Thirdly, Figure 6 As shown, an embodiment of the present application provides a display device 300, and the display device 300 includes a display panel in any of the aforementioned implementations.

[0131] It should be noted that the display device provided in the embodiment of the present application has the beneficial effects of the display panel in any of the aforementioned embodiments. For details, please refer to the aforementioned description of the beneficial effects of the display panel and the array substrate, and the embodiment of the present application will not be repeated.

[0132] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0133] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a first area and a second area arranged side by side in a first direction, the size of the first area in the second direction is smaller than the size of the second area in the second direction, and the first direction intersects with the second direction; the array substrate comprises: Substrate, a plurality of first signal lines, located at one side of the substrate and extending along the second direction, the plurality of first signal lines comprising first-type signal lines located in the first region and second-type signal lines located in the second region, the length of the first-type signal lines in the second direction being shorter than the length of the second-type signal lines in the second direction; A compensation signal line is located on one side of the substrate and includes a first routing line extending along the second direction and a second routing line extending along the first direction, the first routing line is electrically connected to the first type of signal line through the second routing line, and the first routing line and the second routing line are located in the display area of ​​the array substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate comprises a first display area and a second display area, the first display area comprises a first sub-display area located in the first area, and a second sub-display area located in the second area, the second display area is located in the second area and is located on one side of the second sub-display area in the second direction; The first type of signal lines are located in the first sub-display area, and the second type of signal lines are partially located in the second sub-display area and partially located in the second display area; Preferably, the second display area and the second sub-display area are spaced apart in the second direction; Preferably, the compensation signal line is located in the first display area.

3. The array substrate according to claim 2, characterized in that: The first wiring is located in the first sub-display area; Preferably, the second wiring is located in the first sub-display area; Preferably, the first wiring is located on a side of the first-type signal line electrically connected thereto, away from the second sub-display area.

4. The array substrate according to claim 2, characterized in that: The extension length of the compensation signal line is less than the extension length of the first type of signal line; Preferably, the second type of signal line includes a first sub-segment located in the second sub-display area, and a second sub-segment located in the second sub-display area; The extension length of the compensation signal line is less than or equal to the extension length of the second sub-segment; Preferably, the extension length of the first routing line is less than the extension length of the second sub-segment; Preferably, the sum of the length of the first wiring and the length of the second wiring is equal to the length of the second-type signal line in the second display area in the second direction.

5. The array substrate according to claim 2, characterized in that: The extension length of the first routing line is greater than the extension length of the second routing line; Preferably, the order of the plurality of first routing lines in the first direction is the same as the order of the first type of signal lines corresponding to the electrical connection settings in the first direction; Preferably, the first routing line includes a first connecting end, the first routing line is connected to the second routing line through the first connecting end, and in the direction from the second sub-display area to the first sub-display area, the distance between the first connecting end and the second display area in the second direction tends to gradually increase.

6. The array substrate according to claim 1, characterized in that: The orthographic projection of the first routing line on the substrate is outside the orthographic projection of the first signal line on the substrate; Preferably, the array substrate comprises a first conductor layer located at one side of the substrate, and the first signal line and the first routing line are both located in the first conductor layer; Preferably, the array substrate further comprises a second conductor layer located between the first conductor layer and the substrate, and the second trace is located in the second conductor layer; Preferably, at least a portion of the second routing lines are arranged to overlap with the orthographic projections of the plurality of first signal lines on the substrate.

7. The array substrate according to claim 6, characterized in that: The array substrate comprises a first conductor layer located at one side of the substrate, the first conductor layer comprises the first signal line and the first power line extending along the second direction; Preferably, the first signal line is used to transmit a data signal; Preferably, the first routing line is provided between two of the first signal lines that are closest to each other; Preferably, the orthographic projection of the second wiring on the substrate overlaps with the orthographic projection of the first power line on the substrate; Preferably, at least two of the first signal lines are arranged between the two closest first power lines; Preferably, at least part of the first wiring is located between adjacent first signal lines; and / or at least part of the first wiring is located between adjacent first power lines and first signal lines.

8. The array substrate according to claim 1, characterized in that: The first signal line and the first routing line are arranged in different layers; Preferably, the orthographic projection of the first routing line on the substrate overlaps with the orthographic projection of the first signal line on the substrate; Preferably, the array substrate comprises a second conductor layer located on one side of the substrate, and a first conductor layer located on a side of the second conductor layer away from the substrate; The first signal line is located in the first conductor layer, and the first routing line and the second routing line are both located in the second conductor layer.

9. A display panel, characterized in that: It comprises a light emitting structure and the array substrate according to any one of claims 1 to 8, wherein part of the light emitting structure is located in the first area, and part of the light emitting structure is located in the second area.

10. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 9.

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