ESD protection devices

Abstract

This application provides an ESD protection device. The functional regions of the ESD device are fabricated within a single active region. Specifically, this application uses an internal well region (either a ring-shaped well region NW / an internal well region PW / a periphery heavily doped region N+ / an internal heavily doped region P+) within the same active region. To prevent short circuits between the anode (High) and cathode (Low) caused by metal silicides in advanced processes, a metal silicide barrier layer is used for isolation, preventing the formation of metal silicides between the anode and cathode. In the ESD protection device provided by this application, no shallow trench isolation structure is used in the path for discharging the ESD current. This means the ESD current does not need to bypass the shallow trench isolation structure as in traditional ESD devices, resulting in a shorter current path. Consequently, the on-resistance of the device is lower, and the effective ESD protection area is wider, thus fully utilizing the performance of ESD protection devices with PNP structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to an ESD protection device. Background Technology

[0002] ESD (electrostatic discharge) devices with PNP structures play an important role in the field of electrostatic protection. Due to their high holding voltage (Vh), they have virtually no risk of latch-up and are commonly used for electrostatic protection at high-voltage ports.

[0003] However, in traditional ESD devices with PNP structures, the high-voltage PNP transistors have a large on-resistance, and their limiting capability exceeds the ESD design window. Specifically, the PNP failure voltage is greater than the internal failure voltage, the effective area of ​​ESD protection is small, and the full performance of the PNP cannot be utilized. In other words, even if an ESD device with a PNP structure conducts and discharges ESD current, it cannot reach its limit performance, and internal components or circuits may fail due to static electricity. Summary of the Invention

[0004] This application provides an ESD protection device that can solve the problem of high on-resistance in traditional ESD devices with PNP structures.

[0005] This application provides an ESD protection device, including:

[0006] Substrate;

[0007] At least one internal well region of a first conductivity type, the internal well regions being spaced apart in the substrate;

[0008] Multiple internal well regions of a second conductivity type are located in the substrate at intervals and between each pair of adjacent internal well regions.

[0009] A first type of conductive ring well region, the ring well region being located in the substrate and surrounding the outermost inner well region two;

[0010] The substrate lead-out well region of the second conductivity type is located in the substrate and surrounds the annular well region;

[0011] Multiple heavily doped internal regions of a second conductivity type are located in the first internal well region, the second internal well region, and the annular well region.

[0012] The peripheral heavily doped region of the first conductivity type is located in the annular well region, and the peripheral heavily doped region is disposed around the inner heavily doped region in the annular well region and is spaced apart from the inner heavily doped region in the annular well region.

[0013] The substrate has a heavily doped region of the second conductivity type, which is located in the substrate well region.

[0014] Multiple shallow trench isolation structures, at least one of the shallow trench isolation structures is located in the annular well region and between the peripheral heavily doped region and the inner heavily doped region in the annular well region, and at least one shallow trench isolation structure is located between the peripheral heavily doped region and the substrate lead-out heavily doped region;

[0015] A metal silicide barrier layer covers the surfaces of the substrate, the annular well region, the first inner well region, and the second inner well region between all the heavily doped inner regions;

[0016] The heavy doped region in the outer periphery, the heavy doped region in the annular well region, and the heavy doped region in the first inner well region are connected to the anode of the external power supply. The heavy doped region in the second inner well region and the heavy doped region led out from the substrate are connected to the cathode of the external power supply. No shallow trench isolation structure is provided on the path of ESD current discharge in the substrate.

[0017] Optionally, in the ESD protection device, the staggered internal well region one and the internal well region two are axisymmetric structures, wherein the central axis of the axisymmetric structure is one of the internal well regions one, and the outermost periphery of the axisymmetric structure is two of the internal well regions two.

[0018] Optionally, in the ESD protection device, the substrate includes: a base and an epitaxial layer located on the base, wherein the first internal well region, the second internal well region, the annular well region and the substrate lead-out well region are all located in the epitaxial layer.

[0019] Optionally, the ESD protection device further includes: a buried layer of a first conductivity type, the buried layer being located in the substrate and the front side of the buried layer contacting the bottom surface of the inner well region one in the epitaxial layer and the bottom surface of the annular well region.

[0020] Optionally, the ESD protection device further includes: a deep well of a first conductivity type, the deep well being located at the bottom of the epitaxial layer and in contact with the bottom surface of the inner well region one in the epitaxial layer and the bottom surface of the annular well region.

[0021] Optionally, the ESD protection device further includes: a buried layer of a first conductivity type and a deep well of a first conductivity type, the deep well being located at the bottom of the epitaxial layer and in contact with the bottom surface of the inner well region one in the epitaxial layer and the bottom surface of the annular well region, the buried layer being located in the substrate and the front surface of the buried layer being in contact with the bottom surface of the deep well in the epitaxial layer.

[0022] Optionally, in the ESD protection device, the dopant ions in the substrate have a second conductivity type.

[0023] Optionally, in the ESD protection device, the first conductivity type is N-type; the second conductivity type is P-type.

[0024] The technical solution of this application has at least the following advantages:

[0025] This application provides an ESD protection device. The functional regions of the ESD device are fabricated within a single active region. Specifically, by setting an internal well region (either an inner well region NW / annular well region PW / aperture heavily doped region N+ / inner heavily doped region P+) within the same active region, a metal silicide barrier layer is used to prevent short circuits between the anode (High) and cathode (Low) caused by metal silicides in advanced processes, thus preventing the formation of metal silicides between the anode and cathode. In the ESD protection device provided by this application, no shallow trench isolation structure is used in the path for discharging the ESD current. This means the ESD current does not need to bypass the shallow trench isolation structure as in traditional ESD devices, resulting in a shorter current path. Consequently, the on-resistance of the device is lower, and the effective ESD protection area is wider, thereby fully utilizing the performance of the PNP structure ESD protection device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the ESD protection device according to Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram illustrating the working principle of the ESD protection device according to Embodiment 1 of the present invention;

[0029] Figure 3This is a schematic diagram comparing the TLP test curves of a conventional ESD protection device with a PNP structure according to Embodiment 1 of the present invention with the ESD protection device provided in this application.

[0030] Figure 4 This is a schematic diagram of the ESD protection device according to Embodiment 2 of the present invention;

[0031] Figure 5 This is a schematic diagram of the ESD protection device according to Embodiment 3 of the present invention;

[0032] Figure 6 This is a schematic diagram of the ESD protection device according to Embodiment 4 of the present invention;

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 10 - Substrate, 71 - Base layer, 72 - Epitaxial layer;

[0035] 11-Internal well region one, 12-Internal well region two, 13-Annular well region, 14-Substrate-extracted well region, 15-Buried layer, 16-Deep well;

[0036] 20 - Inner heavily doped region, 30 - Outer heavily doped region, 40 - Substrate-leaded heavily doped region, 50 - Shallow trench isolation structure, 60 - Metal silicide barrier layer. Detailed Implementation

[0037] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0040] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other. Example 1

[0041] This application provides an ESD protection device, referenced in the embodiments. Figure 1 , Figure 1 This is a schematic diagram of the ESD protection device according to Embodiment 1 of the present invention. The ESD protection device includes:

[0042] Substrate 10;

[0043] At least one internal well region 11 of a first conductivity type, the internal well regions 11 being spaced apart in the substrate 10;

[0044] Multiple internal well regions 12 of a second conductivity type are spaced apart in the substrate 10 and located between each pair of adjacent internal well regions 11.

[0045] A first conductivity type of annular well region 13, the annular well region 13 being located in the substrate 10 and surrounding the outermost inner well region 12;

[0046] The substrate lead-out well region 14 of the second conductivity type is located in the substrate 10 and surrounds the annular well region 13;

[0047] Multiple heavily doped internal regions 20 of a second conductivity type are located in the first internal well region 11, the second internal well region 12, and the annular well region 13.

[0048] The peripheral heavily doped region 30 of the first conductivity type is located in the annular well region 13. The peripheral heavily doped region 30 is arranged around the inner heavily doped region 20 in the annular well region 13 and is spaced apart from the inner heavily doped region 20 in the annular well region 13.

[0049] The substrate leads out a heavily doped region 40 of the second conductivity type, which is located in the substrate lead-out well region 14;

[0050] Multiple shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the inner heavily doped region 20 in the annular well region 13, and at least one shallow trench isolation structure 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40.

[0051] A metal silicide barrier layer 60 covers the surfaces of the substrate 10, the annular well region 13, the first inner well region 11, and the second inner well region 12 between all the inner heavily doped regions 20.

[0052] The heavy doped region 30 in the outer periphery, the heavy doped region 20 in the annular well region 13, and the heavy doped region 20 in the first inner well region 11 are connected to the anode (High) of the external power supply. The heavy doped region 20 in the second inner well region 12 and the heavy doped region 40 led out from the substrate are connected to the cathode (Low) of the external power supply. No shallow trench isolation structure is provided on the path for discharging ESD current in the substrate, that is, no shallow trench isolation structure is provided between the heavy doped region 20 connected to the anode and the heavy doped region 20 connected to the cathode.

[0053] Preferably, the first internal well region 11 and the second internal well region 12 are both strip-shaped, and the annular well region 13 and the substrate lead-out well region 14 are both annular; further, the internal heavily doped region 20 is strip-shaped, and the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40 are both annular.

[0054] In this embodiment, the inner well region 1 (NW) 11 or the ring well region (NW) 13 / the inner well region 2 (PW) 12 / the peripheral heavily doped region N+30 / the inner heavily doped region P+20 are located in the same active region, that is, the inner well region 1 (NW) 11 or the ring well region (NW) 13 / the inner well region 2 (PW) 12 / the peripheral heavily doped region N+30 / the inner heavily doped region P+20 are located in the same active region of the functional region used to fabricate the ESD device.

[0055] Preferably, the staggered arrangement of the first internal well region 11 and the second internal well region 12 is an axisymmetric structure, wherein the central axis of the symmetrical structure is the first internal well region 11, and the outermost periphery of the symmetrical structure is the two second internal well regions 12.

[0056] refer to Figure 1 In this embodiment, the ESD protection device includes an internal well region 11 and two internal well regions 12, with the two internal well regions 12 respectively disposed on both sides of the internal well region 11.

[0057] Furthermore, the conductivity type of the doped ions in the substrate 10 is the second conductivity type.

[0058] In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type. The substrate 10 can be simply referred to as Psub; the inner well region 11 and the annular well region can be simply referred to as NW; the inner well region 12 and the substrate lead-out well region 14 can be simply referred to as PW; the inner heavily doped region 20 and the substrate lead-out heavily doped region 40 can be simply referred to as P+; and the outer heavily doped region 30 can be simply referred to as N+.

[0059] Preferably, the metal silicide barrier layer (SAB) 60 can be a stack of silicon dioxide and silicon nitride, wherein silicon nitride is stacked on silicon dioxide.

[0060] refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the working principle of the ESD protection device according to Embodiment 1 of the present invention. In this application, an internal well region (NW) or a ring well region (NW) / internal well region (PW) / external heavily doped region (N+) / internal heavily doped region (P+) is set within the same active region. Specifically, the internal heavily doped region (P+) 20 - ring well region (NW) 13 - internal well region (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP transistor, and the internal heavily doped region (P+) 20 / internal well region (PW) - internal well region (NW) 11 - internal well region (PW) 12 also constitute a PNP transistor. Further, as... Figure 2 As shown, to prevent short circuits between the anode (High) and cathode (Low) caused by metal silicides in advanced processes, a metal silicide barrier layer is used for isolation, preventing the formation of metal silicides on the substrate surface between the anode and cathode. In the ESD protection device provided in this application, no shallow trench isolation structure is provided in the path for discharging ESD current. This means the ESD current does not need to bypass the shallow trench isolation structure as in traditional ESD devices, resulting in a shorter current path. Consequently, the on-resistance of the device is lower, and the effective ESD protection area is wider, thus fully utilizing the performance of ESD protection devices with PNP structures.

[0061] refer to Figure 3 , Figure 3 This is a schematic diagram comparing the TLP test curves of a conventional ESD protection device with a PNP structure according to Embodiment 1 of the present invention and the ESD protection device provided in this application. Under the same size, the on-resistance of the ESD protection device provided in this application is significantly smaller than that of the conventional ESD protection device with a PNP structure, and it can be used for a wider effective area for ESD protection and has better performance. Example 2

[0062] Embodiment 2 of this application provides an ESD protection device, referencing... Figure 4 , Figure 4 This is a schematic diagram of the ESD protection device according to Embodiment 2 of the present invention. The ESD protection device includes:

[0063] Substrate 10;

[0064] At least one internal well region 11 of a first conductivity type, the internal well regions 11 being spaced apart in the substrate 10;

[0065] Multiple internal well regions 12 of a second conductivity type are spaced apart in the substrate 10 and located between each pair of adjacent internal well regions 11.

[0066] A first conductivity type of annular well region 13, the annular well region 13 being located in the substrate 10 and surrounding the outermost inner well region 12;

[0067] The substrate lead-out well region 14 of the second conductivity type is located in the substrate 10 and surrounds the annular well region 13;

[0068] Multiple heavily doped internal regions 20 of a second conductivity type are located in the first internal well region 11, the second internal well region 12, and the annular well region 13.

[0069] The peripheral heavily doped region 30 of the first conductivity type is located in the annular well region 13. The peripheral heavily doped region 30 is arranged around the inner heavily doped region 20 in the annular well region 13 and is spaced apart from the inner heavily doped region 20 in the annular well region 13.

[0070] The substrate leads out a heavily doped region 40 of the second conductivity type, which is located in the substrate lead-out well region 14;

[0071] Multiple shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the inner heavily doped region 20 in the annular well region 13, and at least one shallow trench isolation structure 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40.

[0072] A metal silicide barrier layer 60 covers the surfaces of the substrate 10, the annular well region 13, the first inner well region 11, and the second inner well region 12 between all the inner heavily doped regions 20.

[0073] The heavy doped region 30 in the outer periphery, the heavy doped region 20 in the annular well region 13, and the heavy doped region 20 in the first inner well region 11 are connected to the anode (High) of the external power supply. The heavy doped region 20 in the second inner well region 12 and the heavy doped region 40 led out from the substrate are connected to the cathode (Low) of the external power supply. No shallow trench isolation structure is provided on the path for discharging ESD current in the substrate, that is, no shallow trench isolation structure is provided between the heavy doped region 20 connected to the anode and the heavy doped region 20 connected to the cathode.

[0074] Furthermore, the substrate 10 includes a substrate 71 and an epitaxial layer 72 located on the substrate 71, wherein the first internal well region 11, the second internal well region 12, the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72.

[0075] Preferably, the ESD protection device further includes: a buried layer 15 of a first conductivity type, the buried layer 15 being located in the substrate 71 and the front side of the buried layer 15 contacting the bottom surface of the inner well region 11 in the epitaxial layer 72 and the bottom surface of the annular well region 13, wherein the buried layer 15 serves as an isolation layer.

[0076] Preferably, the staggered arrangement of the first internal well region 11 and the second internal well region 12 is an axisymmetric structure, wherein the central axis of the symmetrical structure is the first internal well region 11, and the outermost periphery of the symmetrical structure is the two second internal well regions 12.

[0077] refer to Figure 4 In this embodiment, the ESD protection device includes an internal well region 11 and two internal well regions 12, with the two internal well regions 12 respectively disposed on both sides of the internal well region 11.

[0078] Furthermore, the doped ions in the substrate 71 and the epitaxial layer 72 are both of the second conductivity type.

[0079] In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type. The substrate 10 and base 71 can be abbreviated as Psub; the inner well region 11 and the annular well region can be abbreviated as NW; the inner well region 12 and the substrate lead-out well region 14 can be abbreviated as PW; the inner heavily doped region 20 and the substrate lead-out heavily doped region 40 can be abbreviated as P+; the outer heavily doped region 30 can be abbreviated as N+; the epitaxial layer can be abbreviated as PEPI; the buried layer 15 can be abbreviated as NBL; and the deep well can be abbreviated as DNW.

[0080] In this application, the working principle of the ESD protection device in Embodiment 2 is the same as that of the ESD protection device in Embodiment 1. In this embodiment, an internal well region 1 (NW) or a ring well region 1 (NW) / internal well region 2 (PW) / external heavily doped region 1 (N+) / internal heavily doped region 1 (P+) is set in the same active region. The internal heavily doped region (P+) 20 - ring well region (NW) 13 - internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP transistor, and the internal heavily doped region (P+) 20 / internal well region 2 (PW) - internal well region 1 (NW) 11 - internal well region 2 (PW) 12 also constitute a PNP transistor. Furthermore, to prevent metal silicides in advanced processes from causing a short circuit between the anode (High) and cathode (Low), a metal silicide barrier layer is used for isolation to prevent the formation of metal silicides on the substrate surface between the anode and cathode. In the ESD protection device provided in this embodiment, there is no shallow trench isolation structure on the path for discharging ESD current. That is, the ESD current does not need to bypass the shallow trench isolation structure like in traditional ESD devices, which makes the ESD current have a shorter current path. This results in lower on-resistance of the device and a wider effective area for ESD protection, thereby fully leveraging the performance of the PNP structure ESD protection device.

[0081] For any parts not described in this second embodiment, please refer to the first embodiment accordingly. This second embodiment will not be repeated here. Example 3

[0082] Embodiment 3 of this application provides an ESD protection device, referencing... Figure 5 , Figure 5 This is a schematic diagram of the ESD protection device according to Embodiment 3 of the present invention. The ESD protection device includes:

[0083] Substrate 10;

[0084] At least one internal well region 11 of a first conductivity type, the internal well regions 11 being spaced apart in the substrate 10;

[0085] Multiple internal well regions 12 of a second conductivity type are spaced apart in the substrate 10 and located between each pair of adjacent internal well regions 11.

[0086] A first conductivity type of annular well region 13, the annular well region 13 being located in the substrate 10 and surrounding the outermost inner well region 12;

[0087] The substrate lead-out well region 14 of the second conductivity type is located in the substrate 10 and surrounds the annular well region 13;

[0088] Multiple heavily doped internal regions 20 of a second conductivity type are located in the first internal well region 11, the second internal well region 12, and the annular well region 13.

[0089] The peripheral heavily doped region 30 of the first conductivity type is located in the annular well region 13. The peripheral heavily doped region 30 is arranged around the inner heavily doped region 20 in the annular well region 13 and is spaced apart from the inner heavily doped region 20 in the annular well region 13.

[0090] The substrate leads out a heavily doped region 40 of the second conductivity type, which is located in the substrate lead-out well region 14;

[0091] Multiple shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the inner heavily doped region 20 in the annular well region 13, and at least one shallow trench isolation structure 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40.

[0092] A metal silicide barrier layer 60 covers the surfaces of the substrate 10, the annular well region 13, the first inner well region 11, and the second inner well region 12 between all the inner heavily doped regions 20.

[0093] The heavy doped region 30 in the outer periphery, the heavy doped region 20 in the annular well region 13, and the heavy doped region 20 in the first inner well region 11 are connected to the anode (High) of the external power supply. The heavy doped region 20 in the second inner well region 12 and the heavy doped region 40 led out from the substrate are connected to the cathode (Low) of the external power supply. No shallow trench isolation structure is provided on the path for discharging ESD current in the substrate, that is, no shallow trench isolation structure is provided between the heavy doped region 20 connected to the anode and the heavy doped region 20 connected to the cathode.

[0094] Furthermore, the substrate 10 includes a substrate 71 and an epitaxial layer 72 located on the substrate 71, wherein the first internal well region 11, the second internal well region 12, the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72.

[0095] Preferably, the ESD protection device further includes: a deep well 16 of a first conductivity type, the deep well 16 being located at the bottom of the epitaxial layer 72 and in contact with the bottom surface of the inner well region 11 in the epitaxial layer 72 and the bottom surface of the annular well region 13, wherein the deep well 16 serves as an isolation device.

[0096] Preferably, the staggered arrangement of the first internal well region 11 and the second internal well region 12 is an axisymmetric structure, wherein the central axis of the symmetrical structure is the first internal well region 11, and the outermost periphery of the symmetrical structure is the two second internal well regions 12.

[0097] refer to Figure 5 In this embodiment, the ESD protection device includes an internal well region 11 and two internal well regions 12, with the two internal well regions 12 respectively disposed on both sides of the internal well region 11.

[0098] Furthermore, the doped ions in the substrate 71 and the epitaxial layer 72 are both of the second conductivity type.

[0099] In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type. The substrate 10 and base 71 can be abbreviated as Psub; the inner well region 11 and the annular well region can be abbreviated as NW; the inner well region 12 and the substrate lead-out well region 14 can be abbreviated as PW; the inner heavily doped region 20 and the substrate lead-out heavily doped region 40 can be abbreviated as P+; the outer heavily doped region 30 can be abbreviated as N+; the epitaxial layer can be abbreviated as PEPI; the buried layer 15 can be abbreviated as NBL; and the deep well can be abbreviated as DNW.

[0100] In this application, the working principle of the ESD protection device in Embodiment 3 is the same as that of the ESD protection device in Embodiment 1. In this embodiment, an internal well region 1 (NW) or a ring well region 1 (NW) / internal well region 2 (PW) / external heavily doped region 1 (N+) / internal heavily doped region 1 (P+) is set in the same active region. The internal heavily doped region (P+) 20 - ring well region (NW) 13 - internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP transistor, and the internal heavily doped region (P+) 20 / internal well region 2 (PW) - internal well region 1 (NW) 11 - internal well region 2 (PW) 12 also constitute a PNP transistor. Furthermore, to prevent metal silicides in advanced processes from causing a short circuit between the anode (High) and cathode (Low), a metal silicide barrier layer is used for isolation to prevent the formation of metal silicides on the substrate surface between the anode and cathode. In the ESD protection device provided in this embodiment, there is no shallow trench isolation structure on the path for discharging ESD current. That is, the ESD current does not need to bypass the shallow trench isolation structure like in traditional ESD devices, which makes the ESD current have a shorter current path. This results in lower on-resistance of the device and a wider effective area for ESD protection, thereby fully leveraging the performance of the PNP structure ESD protection device.

[0101] For any parts not described in this embodiment three, please refer to the corresponding embodiment one. This embodiment three will not repeat them here. Example 4

[0102] Embodiment 4 of this application provides an ESD protection device, referencing... Figure 6 , Figure 6 This is a schematic diagram of the ESD protection device according to Embodiment 4 of the present invention. The ESD protection device includes:

[0103] Substrate 10;

[0104] At least one internal well region 11 of a first conductivity type, the internal well regions 11 being spaced apart in the substrate 10;

[0105] Multiple internal well regions 12 of a second conductivity type are spaced apart in the substrate 10 and located between each pair of adjacent internal well regions 11.

[0106] A first conductivity type of annular well region 13, the annular well region 13 being located in the substrate 10 and surrounding the outermost inner well region 12;

[0107] The substrate lead-out well region 14 of the second conductivity type is located in the substrate 10 and surrounds the annular well region 13;

[0108] Multiple heavily doped internal regions 20 of a second conductivity type are located in the first internal well region 11, the second internal well region 12, and the annular well region 13.

[0109] The peripheral heavily doped region 30 of the first conductivity type is located in the annular well region 13. The peripheral heavily doped region 30 is arranged around the inner heavily doped region 20 in the annular well region 13 and is spaced apart from the inner heavily doped region 20 in the annular well region 13.

[0110] The substrate leads out a heavily doped region 40 of the second conductivity type, which is located in the substrate lead-out well region 14;

[0111] Multiple shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the inner heavily doped region 20 in the annular well region 13, and at least one shallow trench isolation structure 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40.

[0112] A metal silicide barrier layer 60 covers the surfaces of the substrate 10, the annular well region 13, the first inner well region 11, and the second inner well region 12 between all the inner heavily doped regions 20.

[0113] The heavy doped region 30 in the outer periphery, the heavy doped region 20 in the annular well region 13, and the heavy doped region 20 in the first inner well region 11 are connected to the anode (High) of the external power supply. The heavy doped region 20 in the second inner well region 12 and the heavy doped region 40 led out from the substrate are connected to the cathode (Low) of the external power supply. No shallow trench isolation structure is provided on the path for discharging ESD current in the substrate, that is, no shallow trench isolation structure is provided between the heavy doped region 20 connected to the anode and the heavy doped region 20 connected to the cathode.

[0114] Furthermore, the substrate 10 includes a substrate 71 and an epitaxial layer 72 located on the substrate 71, wherein the first internal well region 11, the second internal well region 12, the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72.

[0115] Preferably, the ESD protection device further includes: a buried layer 15 of a first conductivity type and a deep well 16 of a first conductivity type. The deep well 15 is located at the bottom of the epitaxial layer 72 and contacts the bottom surface of the inner well region 11 and the bottom surface of the annular well region 13 in the epitaxial layer 72. The buried layer 15 is located in the substrate 71 and the front surface of the buried layer 15 contacts the bottom surface of the deep well 16 in the epitaxial layer 72. Both the buried layer 15 and the deep well 16 serve as an isolation layer.

[0116] Preferably, the staggered arrangement of the first internal well region 11 and the second internal well region 12 is an axisymmetric structure, wherein the central axis of the symmetrical structure is the first internal well region 11, and the outermost periphery of the symmetrical structure is the two second internal well regions 12.

[0117] refer to Figure 6 In this embodiment, the ESD protection device includes an internal well region 11 and two internal well regions 12, with the two internal well regions 12 respectively disposed on both sides of the internal well region 11.

[0118] Furthermore, the doped ions in the substrate 71 and the epitaxial layer 72 are both of the second conductivity type.

[0119] In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type. The substrate 10 and base 71 can be abbreviated as Psub; the inner well region 11 and the annular well region can be abbreviated as NW; the inner well region 12 and the substrate lead-out well region 14 can be abbreviated as PW; the inner heavily doped region 20 and the substrate lead-out heavily doped region 40 can be abbreviated as P+; the outer heavily doped region 30 can be abbreviated as N+; the epitaxial layer can be abbreviated as PEPI; the buried layer 15 can be abbreviated as NBL; and the deep well can be abbreviated as DNW.

[0120] In this application, the working principle of the ESD protection device in Embodiment 4 is the same as that of the ESD protection device in Embodiment 1. In this embodiment, an internal well region 1 (NW) or a ring well region 1 (NW) / internal well region 2 (PW) / external heavily doped region 1 (N+) / internal heavily doped region 1 (P+) is set in the same active region. The internal heavily doped region (P+) 20 - ring well region (NW) 13 - internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP transistor, and the internal heavily doped region (P+) 20 / internal well region 2 (PW) - internal well region 1 (NW) 11 - internal well region 2 (PW) 12 also constitute a PNP transistor. Furthermore, to prevent metal silicides in advanced processes from causing a short circuit between the anode (High) and cathode (Low), a metal silicide barrier layer is used for isolation to prevent the formation of metal silicides on the substrate surface between the anode and cathode. In the ESD protection device provided in this embodiment, there is no shallow trench isolation structure on the path for discharging ESD current. That is, the ESD current does not need to bypass the shallow trench isolation structure like in traditional ESD devices, which makes the ESD current have a shorter current path. This results in lower on-resistance of the device and a wider effective area for ESD protection, thereby fully leveraging the performance of the PNP structure ESD protection device.

[0121] For any parts not described in this embodiment four, please refer to the corresponding embodiment one. This embodiment four will not be repeated here.

[0122] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. An ESD protection device, characterized in that, include: Substrate; At least one internal well region of a first conductivity type, the internal well regions being spaced apart in the substrate; Multiple internal well regions of a second conductivity type are spaced apart in the substrate and located on the periphery of the first internal well region; A ring-shaped well region of a first conductivity type, the ring-shaped well region being located in the substrate and surrounding the inner well region two; The substrate lead-out well region of the second conductivity type is located in the substrate and surrounds the annular well region; Multiple heavily doped internal regions of a second conductivity type are located in the first internal well region, the second internal well region, and the annular well region. The peripheral heavily doped region of the first conductivity type is located in the annular well region, and the peripheral heavily doped region is disposed around the inner heavily doped region in the annular well region and is spaced apart from the inner heavily doped region in the annular well region. The substrate leads out a heavily doped region of the second conductivity type, the heavily doped region being located in the substrate lead-out well region; Multiple shallow trench isolation structures, at least one of the shallow trench isolation structures is located in the annular well region and between the peripheral heavily doped region and the inner heavily doped region in the annular well region, and at least one shallow trench isolation structure is located between the peripheral heavily doped region and the substrate lead-out heavily doped region; A metal silicide barrier layer covers the surfaces of the substrate, the annular well region, the first inner well region, and the second inner well region between all the heavily doped inner regions; The heavy doped region in the outer periphery, the heavy doped region in the annular well region, and the heavy doped region in the first inner well region are connected to the anode of the external power supply. The heavy doped region in the second inner well region and the heavy doped region led out from the substrate are connected to the cathode of the external power supply. No shallow trench isolation structure is provided on the path of ESD current discharge in the substrate.

2. The ESD protection device according to claim 1, characterized in that, The staggered arrangement of the first and second internal well regions forms an axisymmetric structure, wherein the central axis of the axisymmetric structure is the first internal well region, and the outermost periphery of the axisymmetric structure consists of the two second internal well regions.

3. The ESD protection device according to claim 1, characterized in that, The substrate includes a substrate and an epitaxial layer located on the substrate, wherein the first internal well region, the second internal well region, the annular well region and the substrate lead-out well region are all located in the epitaxial layer.

4. The ESD protection device according to claim 3, characterized in that, The ESD protection device further includes: a buried layer of a first conductivity type, the buried layer being located in the substrate and the front side of the buried layer contacting the bottom surface of the inner well region one in the epitaxial layer and the bottom surface of the annular well region.

5. The ESD protection device according to claim 3, characterized in that, The ESD protection device further includes: a deep well of a first conductivity type, the deep well being located at the bottom of the epitaxial layer and in contact with the bottom surface of the inner well region one in the epitaxial layer and the bottom surface of the annular well region.

6. The ESD protection device according to claim 3, characterized in that, The ESD protection device further includes: a buried layer of a first conductivity type and a deep well of a first conductivity type, the deep well being located at the bottom of the epitaxial layer and in contact with the bottom surface of an inner well region 1 in the epitaxial layer and the bottom surface of the annular well region, the buried layer being located in the substrate and the front surface of the buried layer being in contact with the bottom surface of the deep well in the epitaxial layer.

7. The ESD protection device according to claim 1, characterized in that, The doped ions in the substrate have a conductivity type of the second conductivity type.

8. The ESD protection device according to any one of claims 1-7, characterized in that, The first conductivity type is N-type; the second conductivity type is P-type.

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