Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the substrate comprises a substrate, a gate structure arranged on the substrate, and a sacrificial sidewall arranged on both sides of the gate structure; the substrate and the gate structure are respectively formed with a metal silicide; the surface of the substrate has a gap region between the gate structure and the metal silicide; based on a stress proximity technique, the sacrificial sidewall is removed, and a stress layer is arranged on the substrate and the gate structure; the thickness of the stress layer is greater than the width of the gap region; part of the stress layer is removed to expose at least part of the surface of the metal silicide; the remaining part of the stress layer forms a gate sidewall; the gap region is covered by the gate sidewall; a first interlayer dielectric layer is arranged on the surface of the metal silicide and the gate sidewall; and the first interlayer dielectric layer is etched to prepare a contact hole corresponding to the position of the metal silicide. Thus, the problem of high contact resistance of the contact hole prepared after the SPT process is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor manufacturing process, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] SPT (Stress Proximity Technology) is a technology widely used in advanced semiconductor device manufacturing process in recent years. The technical principle is mainly as follows: after forming metal silicide at the gate and the source-drain region, the side wall is removed, and then the stress layer is deposited to more effectively transmit the stress to the channel region, thereby improving the mobility of the carriers. Subsequently, the contact hole is made at the position corresponding to the gate and the source-drain region.

[0003] However, the technical personnel found that the contact hole made after the SPT process is prone to high contact resistance problem. SUMMARY

[0004] Therefore, embodiments of the present application are devoted to providing a semiconductor structure and a manufacturing method thereof, which can reduce the high contact resistance problem of the contact hole made after the SPT process.

[0005] One embodiment of the present application provides a manufacturing method of a semiconductor structure, which comprises: providing a substrate; the substrate comprises a substrate, a gate structure arranged on the substrate, and a sacrificial side wall arranged on both sides of the gate structure; wherein the substrate and the gate structure are respectively formed with metal silicide; the surface of the substrate has a gap region between the gate structure and the metal silicide; based on the stress proximity technology, the sacrificial side wall is removed, and a stress layer is arranged on the substrate and the gate structure; wherein the thickness of the stress layer is greater than the width of the gap region; part of the stress layer is removed to expose at least part of the surface of the metal silicide; the remaining part of the stress layer forms a gate side wall; wherein the gap region is covered by the gate side wall; a first interlayer dielectric layer is arranged on the surface of the metal silicide and the gate side wall; and the first interlayer dielectric layer is etched to manufacture a contact hole at the position corresponding to the metal silicide.

[0006] Optionally, in the step of etching the first interlayer dielectric layer to manufacture a contact hole at the position corresponding to the metal silicide, the etching selectivity ratio of the first interlayer dielectric layer with respect to the gate side wall falls within the range of 6-15.

[0007] Optionally, the gate side wall is at least partially in direct contact with the metal silicide of the substrate to form a contact region; wherein the width of the contact region falls within the range of 120Å-160Å.

[0008] Optionally, in the step of etching the first interlayer dielectric layer to form the contact hole at the position of the metal silicide, the step comprises: etching a trench on the first interlayer dielectric layer based on the gate side wall and the position of the metal silicide formed on the substrate, to form a second interlayer dielectric layer; wherein the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate have a height difference; and etching the second interlayer dielectric layer to form a corresponding contact hole at the position of the metal silicide.

[0009] Optionally, the depth of the trench falls within a range of 600-1000 angstroms.

[0010] Optionally, the height difference is consistent with the height of the gate structure relative to the substrate.

[0011] Optionally, the step of etching the second interlayer dielectric layer to form a corresponding contact hole at the position of the metal silicide comprises: stacking an organic dielectric layer and a mask layer on the second interlayer dielectric layer; forming an opening defining the position of the contact hole on the organic dielectric layer and the mask layer according to the position of the metal silicide by using a photolithography and etching process; wherein the second interlayer dielectric layer is not etched during etching the organic dielectric layer; and etching the second interlayer dielectric layer along the opening to form the contact hole.

[0012] Optionally, the method for preparing the semiconductor structure further comprises: filling a metal material in the contact hole and performing planarization to form a contact structure; wherein the metal material covers the metal silicide.

[0013] Optionally, the type of the contact hole comprises: a shared contact hole; the shared contact hole is located on the metal silicide of the gate structure and the metal silicide of the substrate at the same time.

[0014] One embodiment of the present application provides a semiconductor structure prepared by using the method for preparing the semiconductor structure according to any one of the preceding embodiments.

[0015] The unexpected effect of the embodiments provided by the present application is that the stress layer on the metal silicide is removed in advance after the SPT process, so that when the contact hole is subsequently manufactured, the stress layer removal process on the metal silicide does not need to be additionally performed after the etching of the first interlayer dielectric layer is completed, so as to avoid damaging the gate side wall made of the same material, and the thickness of the stress layer is set to be greater than the width of the gap region in the SPT process, so as to avoid the exposure of the gap region after the stress layer on the metal silicide is removed. In this way, the manufactured gate side wall can completely cover the gap region, so as to avoid the problem of high contact resistance caused by the exposure of the gap region at the bottom of the contact hole. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figures 1-4 A schematic diagram of a contact hole preparation process after an SPT process in the related art.

[0017] Figure 5 A schematic diagram of a semiconductor structure preparation method provided in an embodiment of the present application.

[0018] Figure 6 A schematic diagram of a substrate in a semiconductor structure preparation method provided in an embodiment of the present application.

[0019] Figure 7 A schematic diagram of removing a sacrificial sidewall in a semiconductor structure preparation method provided in an embodiment of the present application.

[0020] Figure 8 A schematic diagram of setting a stress layer in a semiconductor structure preparation method provided in an embodiment of the present application.

[0021] Figure 9 A schematic diagram of removing part of a stress layer in a semiconductor structure preparation method provided in an embodiment of the present application.

[0022] Figure 10 A schematic diagram of setting a first interlayer dielectric layer in a semiconductor structure preparation method provided in an embodiment of the present application.

[0023] Figures 11-12 A schematic diagram of etching a trench in a first interlayer dielectric layer in a semiconductor structure preparation method provided in an embodiment of the present application.

[0024] Figure 13 A schematic diagram of setting an organic dielectric layer and a mask layer in a semiconductor structure preparation method provided in an embodiment of the present application.

[0025] Figure 14 A schematic diagram of forming an opening in a semiconductor structure preparation method provided in an embodiment of the present application.

[0026] Figure 15 A schematic diagram of etching to form a contact hole in a semiconductor structure preparation method provided in an embodiment of the present application.

[0027] Figure 16 A schematic diagram of forming a contact structure in a semiconductor structure preparation method provided in an embodiment of the present application.

[0028] Figure 17 A schematic diagram of a metal material grinding amount in the related art.

[0029] Figure 18 A schematic diagram of a metal material grinding amount in an embodiment of the present application.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS:

[0031] 10 substrate; 11 substrate; 12 metal silicide; 13 gate structure; 31 sacrificial spacer; 32 gap region; 14 stress layer; 15 gate spacer; 16 first interlayer dielectric layer; 161 second interlayer dielectric layer; 17 mask layer; 18 organic dielectric layer; 19 metal material; 21 contact region; 22 trench; 23 opening; 24 contact hole; 25 contact structure. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments of the present application.

[0033] In the present application, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features.

[0034] Unless otherwise defined, all technical and scientific terms used in the present application have the same meanings as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0035] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0036] In the description of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of the simplified description of the present application, and does not indicate that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, i.e. cannot be understood as limiting the present application.

[0037] In the description of the present application, unless otherwise explicitly defined, the terms "mounting", "connecting", "connecting", "fixing", "setting" and the like should be broadly understood. For example, "connecting" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0038] Please refer to Figures 1 to 4 . Figures 1-4 is a schematic diagram of the main steps of making a contact hole after the SPT process in the related art. As shown in Figure 1 , based on the SPT process, a stress layer 104 is deposited on the substrate 101 and the gate structure 103. In the step of making the contact hole 107, the stress layer 104 can be used as an etching stop layer. Specifically, the making of the contact hole 107 is mainly through covering the interlayer dielectric layer 106 on the stress layer 104, and according to the position of the metal silicide 102 on the gate structure 103 and the substrate 101, the photoetching and etching process is performed on the interlayer dielectric layer 106 to form Figure 2 and Figure 3 is a schematic diagram of the etching process. Since the bottom of the contact hole 107 needs to expose the metal silicide 102 to directly contact the subsequently filled metal material, after the etching process as shown in Figure 2 and Figure 3 , the stress layer 104 still covering the surface of the metal silicide 102 of the substrate 101 needs to be removed again, so as to complete the making of the contact hole 107 as shown in Figure 4 . Among them, the stress layer 104 on the side of the gate structure 103 can be used as the gate side wall 105.

[0039] However, referring to Figure 3 and Figure 4 , due to the high aspect ratio of the contact hole 107, in the process of removing the stress layer 104 covering the surface of the metal silicide 102, the stress layer 104 on the side of the gate structure 103 will also be damaged to some extent, so that when the stress layer 104 covering the surface of the metal silicide 102 is completely removed, the stress layer 104 on the side of the gate structure 103 is also almost removed, resulting in the absence of the gate side wall 105 when the contact hole 107 is made, and thus after filling the metal material in the contact hole 107, part of the metal material will directly contact the gap area 108 between the gate structure and the metal silicide, resulting in high contact resistance problem, and even easy to cause open circuit problem, affecting the electrical performance of the semiconductor structure.

[0040] To reduce the gate sidewall missing in the process of making contact hole after SPT process, so that the gap region can be completely covered, and then the metal material of the contact hole can be completely in contact with the metal silicide. An embodiment of the present application provides a method for preparing a semiconductor structure, which comprises the following steps.

[0041] However, the semiconductor structure prepared by the above preparation method still has the problem of high contact resistance. Further analysis shows that the reason is that after the original sacrificial sidewall of the gate structure is removed by the SPT process, in order to effectively transmit stress, the thickness of the deposited stress layer may be relatively thin, which leads to the exposure of part of the gap region after the stress layer on the metal silicide is removed. Especially the stress layer covering the side surface of the gate structure, if the thickness is small, after the stress layer on the metal silicide is removed, the gap region cannot be covered by the gate sidewall formed, which is easy to cause the problem of high contact resistance.

[0042] Therefore, it is necessary to provide a method for preparing a semiconductor structure, which can prevent the gap region from being covered by the gate sidewall during the process of making contact hole based on SPT process, so that the metal material filled in the contact hole later can be in complete contact with the metal silicide, avoiding the problem of high contact resistance or open circuit, and improving the electrical performance of the semiconductor structure prepared based on SPT process.

[0043] Please refer to Figures 5 to 18 An embodiment of the present application provides a method for preparing a semiconductor structure, which can comprise the following steps.

[0044] S110: providing a substrate.

[0045] In the embodiment, as shown in Figure 6 The substrate 10 can comprise a substrate 11, a gate structure 13 disposed on the substrate 11, and a sacrificial sidewall 31 located on both sides of the gate structure 13; wherein the substrate 11 and the gate structure 13 are respectively formed with a metal silicide 12; the surface of the substrate 11 has a gap region 32 located between the gate structure 13 and the metal silicide 12.

[0046] The substrate 11 can serve as the basic structure of a semiconductor structure, not only providing mechanical support but also influencing the electrical properties of the semiconductor structure, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the substrate 11 can be made of silicon (Si) or, depending on the requirements, other semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN).

[0047] The gate structure 13 can be used to influence the switching state of the MOS structure. Specifically, the gate structure 13 can be composed of a gate material and a gate oxide layer. As the gate electrode, the gate material can be polysilicon or a metal (such as aluminum, Al). The gate material can be isolated from the substrate 11 through the gate oxide layer. The gate oxide layer can specifically be silicon dioxide (SiO2). In some embodiments, the gate structure 13 may also include a work function adjustment layer. When a voltage is applied to the gate structure 13, it can attract or repel carriers in the channel region, thereby affecting the flow of carriers between the source and drain. In some embodiments, the gate structure 13 may also include oxide sidewalls located on both sides of the gate material, and sacrificial sidewalls 31 may be located on both sides of the oxide sidewalls.

[0048] The metal silicide 12 can be used as a contact connection between the metal material filling the contact hole and the substrate 11 to reduce contact resistance. Specifically, the metal silicide can be nickel silicide (NiSi), titanium silicide (TiSi2), cobalt silicide (CoSi2), etc. In some embodiments, the metal silicide 12 can be located on the gate material of the gate structure 13 to serve as a contact connection between the metal material disposed on the metal silicide 12 and the gate. The metal silicide 12 can also be located on the source / drain regions of the substrate 11 to serve as a contact connection between the metal material disposed on the metal silicide 12 and the source / drain.

[0049] The gap region 32 can be a surface region of the substrate 11 located between the gate structure 13 and the metal silicide 12. Specifically, in the fabricated semiconductor structure with contact holes, the gap region 32 needs to be covered by the gate sidewalls so that it does not come into direct contact with the metal material filling the contact holes.

[0050] S120: Based on stress proximity technology, the sacrificial sidewalls are removed, and a stress layer is formed on the substrate and gate structure; wherein the thickness of the stress layer is greater than the width of the gap region.

[0051] In this embodiment, as Figure 7 and Figure 8 As shown, by removing the sacrificial sidewall 31 and setting the stress layer 14 through deposition or other methods, stress is transferred to the channel, thereby improving the carrier mobility. It should be noted that the sacrificial sidewall 31 can be removed entirely or only partially.

[0052] In some embodiments, the stress layer 14 is used to form a stress field and transmit stress to the channel region by diffusion and mechanical coupling effect, so as to change the energy band structure of the channel region, improve the mobility of the carrier and optimize the performance of the semiconductor structure. Specifically, a suitable material can be selected as the stress layer 14 according to the type of stress to be introduced. For example, the material of the stress layer 14 can be silicon nitride or silicon carbide, or titanium nitride, aluminum nitride, etc. In some embodiments, the stress layer 14 can also be used to form a gate sidewall in subsequent processes of the SPT process.

[0053] In some embodiments, in the case that the thickness of the stress layer 14 is not uniform enough, the deposition thickness of the part of the stress layer 14 located on the side of the gate structure 13 can be made to exceed the width of the gap region 32.

[0054] S130: removing part of the stress layer to expose at least part of the surface of the metal silicide; the remaining part of the stress layer forms a gate sidewall; wherein the gap region is covered by the gate sidewall.

[0055] In the present embodiment, please refer to Figure 8 and Figure 9 The part of the stress layer 14 located on the surface of the metal silicide 12 can be removed by an etch back process to expose the metal silicide 12 and use the remaining stress layer 14 as the gate sidewall 15, that is, the fabrication of the gate sidewall 15 is performed in advance. It can be understood that in the present embodiment, the material of the gate sidewall 15 can be the same as that of the stress layer 14. In some embodiments, the removal of the part of the stress layer 14 can also be performed by other processes, which can be selected flexibly according to actual needs, and the present application does not make specific limitations in this regard.

[0056] In the present embodiment, since the deposition thickness of the stress layer 14 is greater than the width of the gap region 32, after the part of the stress layer 14 is removed by the etch back process, the gap region 32 can still be covered by the gate sidewall 15 and will not be exposed.

[0057] S140: disposing a first interlayer dielectric layer on the surface of the metal silicide and the gate sidewall.

[0058] In the present embodiment, as shown in Figure 10 the first interlayer dielectric layer 16 can be disposed on the surface of the metal silicide 12 and the gate sidewall 15 to play a role of isolation and insulation between the fabricated contact holes. Specifically, the material of the interlayer dielectric layer 16 can be silicon dioxide SiO2 or other low dielectric constant materials.

[0059] S150: etching the first interlayer dielectric layer to prepare a contact hole at the position of the metal silicide.

[0060] In the present embodiment, for the structure as shown in Figure 10 Specifically, in the fabrication process of the MOS device, the contact holes can include various types, such as the gate contact holes located on the surface of the metal silicide of the gate structure, the active area contact holes (AA CT) located on the metal silicide of the substrate as the source / drain contact, and the shared contact holes (Shared CT, SCT) located on the metal silicide of both the gate structure and the substrate as the shared contact of the gate and the source / drain. In the present embodiment, according to the type of the contact hole, the position of the contact hole to be fabricated can be determined, and then the etching can be performed according to the size (CT CD) of the contact hole.

[0061] In the present embodiment, the unexpected effect is that the stress layer 14 on the metal silicide 12 is removed in advance after the SPT process, so that when the contact hole is fabricated subsequently, the stress layer 14 removal process on the metal silicide 12 does not need to be additionally performed after the etching of the first interlayer dielectric layer 16 is completed, so as to avoid damage to the gate sidewall 15 of the same material, and the thickness of the stress layer 14 is set to be greater than the width of the gap region 32 in the SPT process, so as to avoid the exposure of the gap region 32 after the stress layer 14 on the metal silicide 12 is removed. In this way, the fabricated gate sidewall 15 can completely cover the gap region 32, so as to avoid the problem of high contact resistance caused by the exposure of the gap region 32 at the bottom of the contact hole. In particular, for the two types of contact holes, the shared contact hole and the active area contact hole, the related art will cause serious damage to the gate sidewall due to the removal of the etching stop layer before the fabrication of the shared contact hole and the active area contact hole is completed, so that the protection effect of the gate sidewall in the present embodiment is more significant when the shared contact hole and the active area contact hole are fabricated.

[0062] In some embodiments, in the step of etching the first interlayer dielectric layer to fabricate the contact hole at the position corresponding to the metal silicide, the etching selectivity ratio of the first interlayer dielectric layer with respect to the gate sidewall falls within the range of 6-15.

[0063] In some embodiments, please refer to Figure 10Since the aspect ratio of the contact hole is high, and the etching of the first interlayer dielectric layer 16 will also cause certain etching damage to the gate sidewall 15 on the side of the gate structure 13, the etching selectivity ratio of the first interlayer dielectric layer 16 relative to the gate sidewall 15 cannot be too high or too low. Controlling the etching selectivity ratio of the first interlayer dielectric layer 16 relative to the gate sidewall 15 in the range of 6-15 can not only prevent the open circuit problem caused by the by-product at the bottom of the contact hole, but also control the etching damage to the gate sidewall 15 in the process of etching the first interlayer dielectric layer 16 within a range that has less impact on electrical performance. Specifically, for example, the etching selectivity ratio of the interlayer dielectric layer 16 relative to the gate sidewall 15 can be 6, 15, or other values such as 8, 10, 12, etc.

[0064] In some embodiments, the gate sidewall at least partially directly contacts the metal silicide of the substrate to form a contact area; wherein the width of the contact area falls within the range of 120Å-160Å.

[0065] Please continue to refer to Figure 10 . As mentioned earlier, in the process of etching the first interlayer dielectric layer 16, since the selectivity ratio cannot be too high, it is inevitable that the gate sidewall 15 will be etched and damaged, therefore, in combination with Figure 8 and Figure 9 , when the stress layer 14 is set, the width of the stress layer 14 (i.e. the subsequently formed gate sidewall) on the side of the gate structure 13 can be adjusted, such as depositing the stress layer 14 with a relatively thick thickness, so that after the process of removing part of the stress layer 14 and forming the gate sidewall 15, the gate sidewall 15 can directly contact the metal silicide 12 of the substrate 11 and form an overlapping contact area 21 on the surface of the substrate 11. In this way, in the process of etching the first interlayer dielectric layer 16 as shown in Figure 10 , since the etching consumption of the gate sidewall on the contact area 21 is reserved, even if the gate sidewall 15 is etched in the width direction, the bottom of the contact hole will not be the metal silicide 12, and the metal filled in the contact hole will not directly contact the surface of the substrate without the metal silicide 12.

[0066] In some embodiments, when the etching selectivity ratio of the first interlayer dielectric layer 16 falls within the range of 6-15 as mentioned above, by controlling the width of the contact area 21 within the range of 120Å-160Å, the gate sidewall 15 can still cover the surface of the substrate between the gate structure 13 and the metal silicide 12 of the substrate 11 after etching the first interlayer dielectric layer 16, preventing the bottom of the contact hole from not being the metal silicide 12.

[0067] In some embodiments, the step of etching an interlayer dielectric layer to form a contact hole corresponding to the location of a metal silicide includes: etching trenches on the interlayer dielectric layer based on the locations of the gate sidewall and the metal silicide formed on the substrate to form a second interlayer dielectric layer; wherein there is a height difference between the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate; etching the second interlayer dielectric layer to form a corresponding contact hole at the location of the metal silicide.

[0068] In some embodiments, such as Figure 10 As shown, since the first interlayer dielectric layer 16 covers the metal silicide 12 of the gate structure 13 and the substrate 11, its thickness is uneven. The thickness of the first interlayer dielectric layer 16 directly above the surface of the metal silicide 12 of the gate structure 13 is smaller than the thickness of the first interlayer dielectric layer 16 directly above the surface of the metal silicide 12 of the substrate 11. As a result, when etching the first interlayer dielectric layer 16, the first interlayer dielectric layer 16 on the metal silicide 12 of the substrate 11 has not been completely etched before the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 has already been etched.

[0069] At this point, please refer to... Figure 2 and Figure 3 Taking related technologies as an example, the material covered by the interlayer dielectric layer 106 at the gate structure 103 will begin to be etched. When the interlayer dielectric layer 106 on the metal silicide 102 of the substrate 101 is completely etched, the metal silicide 102 of the gate structure 103 will be etched and damaged, thereby affecting the electrical performance. In some embodiments, a similar situation may occur during the etching of the first interlayer dielectric layer 16. Furthermore, referring to... Figure 10 If the stress layer 14 on the metal silicide 12 has been removed in advance, the metal silicide 12 of the gate structure 13 will be etched more severely due to the lack of protection from the stress layer 14.

[0070] In some embodiments, trenches 22 are etched on the first interlayer dielectric layer 16 at the corresponding positions of the metal silicide 12 to form a second interlayer dielectric layer 161. This allows for a height difference between the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the gate structure 13 and the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the substrate 11. This reduces the thickness difference between the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 and the first interlayer dielectric layer 16 on the metal silicide 12 of the substrate 11. Consequently, the etching processes at the corresponding positions of the metal silicide 12 of the gate structure 13 and the corresponding positions of the metal silicide 12 of the substrate 11 tend to be synchronized, reducing damage to the metal silicide 12 caused by premature etching of the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13.

[0071] In some embodiments, as shown in Figure 11 and Figure 12 , a mask layer 17 can be disposed on the first interlayer dielectric layer 16, and a photoetching process can be used to etch the first interlayer dielectric layer 16 to form the trench 22 corresponding to the position of the metal silicide 12 formed on the substrate 11 and the gate sidewall 15, and the remaining first interlayer dielectric layer 16 forms the second interlayer dielectric layer 161. The width of the trench 22 can be consistent with the interval width between the adjacent gate structures 13. The depth of the trench 22 is the height difference h between the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the gate structure 13 and the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the substrate 11.

[0072] In some embodiments, the depth of the trench 22 can fall within the range of 600 Å to 1000 Å. Controlling the height difference h within this range can make the metal silicide 12 of the gate structure 13 less or not damaged during the etching of the second interlayer dielectric layer 161, and basically does not affect the electrical performance of the semiconductor structure.

[0073] In some embodiments, the height difference is consistent with the height of the gate structure relative to the substrate. Referring to Figure 12 , in the case where the height difference h is the same as the height of the gate structure 13 relative to the substrate 11, the problem of inconsistent etching process caused by the uneven thickness of the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 and the substrate 11 can be eliminated, thereby avoiding the etching damage to the metal silicide 12 of the gate structure 13, and the effect is better.

[0074] In some embodiments, the step of etching the second interlayer dielectric layer to form a corresponding contact hole at the position of the metal silicide includes: disposing an organic dielectric layer and a mask layer on the second interlayer dielectric layer; using a photoetching and etching process to form an opening defining the position of the contact hole on the organic dielectric layer and the mask layer; wherein the second interlayer dielectric layer is not etched during the etching of the organic dielectric layer; etching the second interlayer dielectric layer along the opening position to form the contact hole.

[0075] In some embodiments, as shown in Figure 13 and Figure 14 , an organic dielectric layer 18 and a mask layer 17 are disposed on the second interlayer dielectric layer 161, and a photoetching process is used to define the position of the contact hole and etch an opening 23 on the mask layer 17 and the organic dielectric layer 18, the position of the opening 23 corresponds to the position of the contact hole, and the opening 23 can have a step surface. Further, as shown in Figure 14 and Figure 15As shown, the contact hole 24 is formed through the second interlayer dielectric layer 161 based on the position of the opening 23.

[0076] By arranging the organic dielectric layer 18 between the mask layer 17 and the second interlayer dielectric layer 161, based on the high etching selectivity of the organic dielectric layer 18 relative to the second interlayer dielectric layer 161, the existing height difference h on the second interlayer dielectric layer 161 remains unchanged during the etching of the opening 23, and thus does not affect the subsequent etching.

[0077] In some embodiments, the method for manufacturing the semiconductor structure further comprises: filling the contact hole with a metal material, and performing planarization to form a contact structure; wherein the metal material covers the metal silicide.

[0078] In some embodiments, as shown in Figure 15 and Figure 16 After filling the contact hole 24 with the metal material 19, the CMP process is used for planarization to complete the preparation of the contact structure 25. Specifically, the metal material 19 can be tungsten, or other conductive metals such as aluminum, copper, etc.

[0079] In some embodiments, since the gap region 32 is covered by the gate side wall 15, the bottom of the contact hole 24 is the metal silicide 12, and the metal material 19 can be in full contact with the metal silicide 12, thereby reducing the contact resistance.

[0080] In some embodiments, due to the existence of the height difference h, the grinding amount of the metal material 19 in the CMP process can also be reduced. Referring to Figure 17 and Figure 18 Taking the active region contact hole as an example, Figure 17 is a schematic diagram of the grinding amount of the metal material in the CMP process in the related art, and the grinding amount V1 = (H-h1)*S+S*(1-a%)*h1+a%*s*h3. Figure 18 is a schematic diagram of the grinding amount of the metal material 19 in the CMP process in the present embodiment, and the grinding amount V2=(H-h2)*S+S(1-b%)*h2+b%*S*h3. Wherein, a%, b% represent the mask opening ratio, and S represents the wafer area. Since h2>h1, b%>a%, and h3=h2, the grinding amount difference V1-V2=a%*(h2-h1)*S>0. Therefore, in the method for manufacturing the semiconductor structure provided by the present application, the grinding amount of the metal material 19 in the CMP process is less.

[0081] In some embodiments, the unexpected effect is that, by removing the stress layer 14 in advance on the metal silicide 12, and etching the trench 22 on the first interlayer dielectric layer 16 in advance during etching the first interlayer dielectric layer 16, both the problem of missing the gate side wall 15 and the etching damage to the metal silicide 12 of the gate structure 13 can be avoided, so that the electrical performance and reliability of the contact hole 24 and the contact structure 25 are greatly improved.

[0082] One embodiment of the present application further provides a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of the preceding embodiments.

[0083] It can be understood that the specific examples herein are only for better understanding of the embodiments of the present application by those skilled in the art, and do not limit the scope of the present application.

[0084] It can be understood that, in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0085] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0086] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the art of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments of the present application, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0087] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: A substrate is provided; the substrate includes a substrate, a gate structure disposed on the substrate, and sacrificial sidewalls located on both sides of the gate structure; wherein, the substrate and the gate structure are respectively formed with metal silicide; the surface of the substrate has a gap region located between the gate structure and the metal silicide; Based on stress proximity technology, the sacrificial sidewall is removed, and a stress layer is formed on the substrate and the gate structure; wherein the thickness of the stress layer is greater than the width of the gap region; A portion of the stress layer is removed to expose at least a portion of the surface of the metal silicide; the remaining portion of the stress layer forms a gate sidewall; wherein the gap region is covered by the gate sidewall; A first interlayer dielectric layer is disposed on the surfaces of the metal silicide and the gate sidewall; Corresponding to the location of the metal silicide, etching the first interlayer dielectric layer to prepare contact holes includes: etching trenches on the first interlayer dielectric layer based on the locations of the gate sidewall and the metal silicide formed on the substrate to form a second interlayer dielectric layer; wherein there is a height difference between the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate; etching the second interlayer dielectric layer to form corresponding contact holes at the locations of the metal silicides.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The gate sidewall is at least partially in direct contact with the metal silicide of the substrate to form a contact region; wherein the width of the contact region falls within the range of 120 Å to 160 Å.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, In the step of etching the first interlayer dielectric layer to form a contact hole at the location corresponding to the metal silicide, the etching selectivity of the first interlayer dielectric layer relative to the gate sidewall falls in the range of 6 to 15.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The depth of the trench falls within the range of 600 Å to 1000 Å.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The height difference corresponds to the height of the gate structure relative to the substrate.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of etching the second interlayer dielectric layer to form corresponding contact holes at the locations of the metal silicide includes: An organic dielectric layer and a mask layer are stacked on the second interlayer dielectric layer; Based on the location of the metal silicide, an opening defining the location of the contact hole is formed in the organic dielectric layer and the mask layer using photolithography and etching processes; wherein, during the etching of the organic dielectric layer, the second interlayer dielectric layer is not etched; The second interlayer dielectric layer is etched along the opening to form the contact hole.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for preparing the semiconductor structure further includes: The contact hole is filled with a metal material and planarized to form a contact structure; wherein the metal material covers the metal silicide.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, The types of contact holes include: shared contact holes; the shared contact holes are located on both the metal silicide of the gate structure and the metal silicide of the substrate.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method described in any one of claims 1 to 8.

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