Heterojunction solar cell and preparation method thereof

Abstract

The embodiment of the invention provides a heterojunction solar cell and a preparation method thereof. The heterojunction solar cell comprises a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface which are oppositely arranged; the first composite passivation layer, the first doping layer and the first antireflection film layer are located on the first surface of the silicon substrate and are sequentially stacked in the first direction; wherein the first doped layer comprises a first doped silicon layer and a first doped polycrystalline silicon layer which are sequentially stacked in the first direction; the material of the first doped silicon layer comprises one of doped amorphous silicon or doped microcrystalline silicon. The first doped layer and the first doped polycrystalline silicon layer jointly form the first doped layer, the conductivity of the first doped polycrystalline silicon layer is better, and the battery efficiency is effectively improved; the optical parasitic absorption of the first doped polycrystalline silicon layer is higher than that of the first doped silicon layer; the first doped silicon layer and the first doped polycrystalline silicon layer are stacked, so that the optical parasitic absorption of the cell is effectively reduced, and the short-circuit current and the photoelectric conversion efficiency are improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a heterojunction cell and a method for preparing the heterojunction cell. Background Art

[0002] Solar energy has become one of the most efficient renewable resources due to its clean, safe and pollution-free characteristics. Photovoltaic technology, as one of the most important applications of solar energy, can effectively change the energy consumption structure, reduce global warming and the growing trend of ecological environment deterioration. Therefore, vigorously developing photovoltaic technology has far-reaching and significant significance.

[0003] With the rapid progress and development of photovoltaic technology, the conversion efficiency of crystalline silicon solar cells has been increasing year by year. In the current photovoltaic industry, the conversion efficiency of single-crystal silicon solar cells is relatively high. At the same time, the development of high-efficiency batteries has received more and more attention, especially silicon-based heterojunction (HJT) solar cells. Due to its short manufacturing process, low preparation process temperature, high conversion efficiency, high open circuit voltage, low temperature coefficient, no light-induced degradation (LID), no electrical degradation (PID), suitable for using thin silicon wafers to make flexible battery components, and high power generation, HJT has become one of the most promising and important research directions that can compete with other energy technologies.

[0004] However, the TCO layer in heterojunction solar cells has high optical parasitic absorption and more parasitic absorption of sunlight, which affects the utilization of light and leads to a low short-circuit current of the HJT cell, thus limiting the HJT cell from fully leveraging the advantage of high opening voltage. This is a key factor affecting the competitiveness and mass production scale of HJT cells in the photovoltaic industry.

[0005] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0006] The embodiments of the present application provide a heterojunction solar cell and a method for preparing the same to solve or alleviate one or more of the technical problems mentioned above. In a first aspect, an embodiment of the present application provides a heterojunction solar cell, comprising: A silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; A first composite passivation layer, a first doping layer, and a first anti-reflection film layer are located on the first surface of the silicon substrate and are sequentially stacked along a first direction; Wherein, the first doped layer comprises: a first doped silicon layer and a first doped polysilicon layer sequentially stacked along the first direction; The material of the first doped silicon layer includes one of doped amorphous silicon and doped microcrystalline silicon.

[0007] Optionally, the first composite passivation layer includes: a first passivation layer and a second passivation layer sequentially stacked along the first direction; The material of the first passivation layer includes one or more of silicon hydroxide, amorphous silicon, microcrystalline silicon, silicon carbide or Al2O3; The material of the second passivation layer is one or more of silicon hydroxide, Al2O3, silicon oxynitride, and silicon nitride.

[0008] Optionally, the material of the second passivation layer contains silicon hydroxide.

[0009] Optionally, when the material of the first passivation layer contains silicon hydroxide, and the material of the second passivation layer contains silicon hydroxide; The hydrogen content in the second passivation layer is lower than the hydrogen content in the first passivation layer.

[0010] Optionally, a thickness ratio of the first doped silicon layer to the first doped polysilicon layer is 1:(3-5).

[0011] Optionally, the thickness of the first doped silicon layer is 15-30 nm; the thickness of the first doped polysilicon layer is 45-150 nm.

[0012] Optionally, the material of the anti-reflection film layer includes one of silicon nitride, silicon oxide or Al2O3.

[0013] Optionally, it also includes: A second composite passivation layer, a second doping layer, and a second anti-reflection film layer are located on the second surface of the silicon substrate and are sequentially stacked along a second direction; Wherein, the second doped layer comprises: a second doped silicon layer and a second doped polysilicon layer sequentially stacked along the second direction; The material of the second doped silicon layer includes one of doped amorphous silicon or doped microcrystalline silicon; The first direction and the second direction are opposite.

[0014] In a second aspect, an embodiment of the present application provides a method for preparing a heterojunction solar cell, comprising the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface disposed opposite to each other; forming the first composite passivation layer on the first surface of the silicon substrate; A first doped silicon layer, a first doped polysilicon layer and a first anti-reflection film layer are sequentially formed on the first composite passivation layer.

[0015] Optionally, during the process of forming the first doped polysilicon layer, the laser energy is 20 mJ / cm2 -800mJ / cm 2 , pulse width is 5-50ns, frequency is 1-1000Hz.

[0016] The above technical solution adopted in the embodiment of the present application may have the following advantages: The first doped layer and the first doped polysilicon layer together constitute the first doped layer. On the one hand, compared with the TCO layer in the traditional technology, the first doped polysilicon layer has better conductivity and better lateral current collection effect. At the same time, the contact resistance with the gate line is lower, which significantly reduces the series resistance and helps to improve the battery efficiency. On the other hand, since the band gap of the first doped polysilicon layer is lower than the band gap of the first doped silicon layer, its optical parasitic absorption is higher than that of the first doped silicon layer. The optical parasitic absorption of the first doped silicon layer is low, and the stacking arrangement of the first doped silicon layer and the first doped polysilicon layer can effectively reduce the optical parasitic absorption of the battery, thereby improving the short-circuit current and photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0018] Figure 1 It is a schematic diagram of the structure of the heterojunction solar cell provided in Example 1 of the present application.

[0019] Figure 2 It is a schematic diagram of the structure of a heterojunction solar cell provided in Example 2 of the present application.

[0020] Description of reference numerals: 1. Silicon substrate; 2. First passivation layer; 3. Second passivation layer; 4. First doped silicon layer; 5. First doped polysilicon layer; 6. First anti-reflection film layer; 7. Third passivation layer; 8. Fourth passivation layer; 9. Second doped silicon layer; 10. Second doped polysilicon layer; 101. Second reflective film layer; 11. First electrode; 12. Second electrode; 13. Fifth passivation layer; 14. Third doped polysilicon layer; 15. TCO layer; A1, first direction; A2, second direction. DETAILED DESCRIPTION

[0021] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application discloses the existence of the first element, component, region, layer or part.

[0023] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0026] The following provides an explanation of the terms used in this application.

[0027] CVD: It is a method of using heating, plasma excitation or light radiation to make gaseous or vaporous chemical substances react and deposit them in an atomic state on a substrate placed in an appropriate position to form the desired solid film or coating.

[0028] ALD: A method that can deposit materials layer by layer on the substrate surface in the form of a single atomic film.

[0029] PECVD: It is a method of generating plasma through microwave or radio frequency power, using high-energy electrons to activate gas molecules and promote chemical reactions, thereby achieving thin film deposition.

[0030] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0031] like Figure 1 As shown, the embodiment of the present application provides a heterojunction solar cell, comprising: A silicon substrate 1, wherein the silicon substrate 1 comprises a first surface and a second surface which are arranged opposite to each other; A first composite passivation layer, a first doping layer and a first anti-reflection film layer 6 are located on the first surface of the silicon substrate 1 and are sequentially stacked along a first direction A1; The first doped layer includes: a first doped silicon layer 4 and a first doped polysilicon layer 5 which are sequentially stacked along a first direction A1; The material of the first doped silicon layer 4 includes doped amorphous silicon or doped microcrystalline silicon.

[0032] In the present embodiment, the first doped silicon layer 4 and the first doped polysilicon layer 5 together constitute the first doped layer. On the one hand, compared with the TCO layer in the conventional technology, the first doped polysilicon layer 5 has better conductivity and better lateral current collection effect, and at the same time, has lower contact resistance with the gate line, significantly reduces the series resistance, and helps to improve the battery efficiency; on the other hand, since the band gap of the first doped polysilicon layer 5 is lower than that of the first doped silicon layer 4, its optical parasitic absorption is higher than that of the first doped silicon layer 4; the first doped silicon layer 4 has lower optical parasitic absorption, and its stacking arrangement with the first doped polysilicon layer 5 can effectively reduce the optical parasitic absorption of the battery, thereby improving the short-circuit current and photoelectric conversion efficiency; it should be noted that the first doped polysilicon layer 5 used in the embodiment of the present application is compared with the TCO layer in the conventional technology. The first doped polysilicon layer 5 is doped, and its carrier concentration is higher, the mobility is better, and the resistance is lower, so the first doped polysilicon layer 5 has better conductivity.

[0033] In addition, the first doped silicon layer 4 has fewer defects and a lower recombination rate. By combining it with the first doped polysilicon layer 5, the recombination loss of electrons and holes can be reduced and the efficiency of the battery can be improved. At the same time, the first doped polysilicon layer 5 has good thermal stability, and the first doped silicon layer 4 can be processed at a lower temperature, which can improve the stability and durability of the battery under different temperature conditions. The uncrystallized first doped silicon layer 4 has a lower light decay effect, which reduces the performance degradation during long-term use and maintains the stability of the battery performance.

[0034] In some embodiments, the first doped polysilicon layer 5 is a P-type doped polysilicon layer or an N-type doped polysilicon layer.

[0035] In an optional embodiment, the first composite passivation layer includes: a first passivation layer 2 and a second passivation layer 3 stacked in sequence along a first direction A1; the material of the first passivation layer 2 includes one or more of silicon hydroxide, amorphous silicon, microcrystalline silicon, silicon carbide or Al2O3; the material of the second passivation layer 3 includes one or more of silicon hydroxide, Al2O3, silicon oxynitride, and silicon nitride.

[0036] In this embodiment, the stacked first passivation layer 2 and the second passivation layer 3 can significantly reduce the composite loss on the surface and the interface. The first passivation layer 2 effectively reduces surface defects and surface recombination, reduces the composite loss of electrons and holes, and thus improves the open circuit voltage and photoelectric conversion efficiency of the battery. The second passivation layer 3 has poor thermal conductivity and plays a role of heat preservation during the crystallization process, preventing heat from being transferred to the first passivation layer 2, ensuring the quality of crystallization and the passivation effect of the first passivation layer 2, and improving the overall performance of the battery. In addition, the structure of the stacked first passivation layer 2 and the second passivation layer 3 can improve the stability of the battery under different environmental conditions, and can also improve the thermal stability of the battery, so that it can maintain good performance in a high temperature environment.

[0037] In an optional embodiment, the material of the second passivation layer 3 contains silicon hydroxide.

[0038] In this embodiment, the second passivation layer 3 is in contact with the first doped layer. When the material of the second passivation layer 3 is silicon hydroxide, the silicon hydroxide can not only play a passivation role, but also a heat preservation role, thereby reducing the damage of the second doped polysilicon layer 10 of the first doped layer to the heterojunction battery structure during laser processing; It should be noted that the hydrogen explosion phenomenon refers to the generation of bubbles or peeling of the thin film layer due to the release of hydrogen during the crystallization process, thereby affecting the performance and stability of the battery; silicon hydroxide can also avoid the "hydrogen explosion" phenomenon of the second doped polysilicon layer 10 in the first doped layer during the crystallization process.

[0039] In an optional embodiment, when the material of the first passivation layer 2 is silicon hydroxide-containing, and the material of the second passivation layer 3 is silicon hydroxide-containing, the hydrogen content in the second passivation layer 3 is lower than the hydrogen content in the first passivation layer 2 .

[0040] In this embodiment, the first passivation layer 2 has a higher hydrogen concentration, which can improve the separation of charge carriers, reduce recombination losses, and improve the mobility of charge carriers; the second passivation layer 3 has a lower hydrogen concentration, which can reduce hydrogen explosion in the crystallization process and improve the quality of crystallization, thereby optimizing the separation and transmission efficiency of charge carriers and improving the overall efficiency of the battery.

[0041] In an optional embodiment, the thickness ratio of the first doped silicon layer 4 to the first doped polysilicon layer 5 is 1:(3-5). For example, the thickness ratio of the first doped silicon layer 4 to the first doped polysilicon layer 5 is 1:3, 1:4, and 1:5.

[0042] In this embodiment, the first doped silicon layer 4 has a small thickness, a high optical transmittance, and low optical parasitic absorption, and can also provide surface passivation to reduce the recombination of photogenerated electrons and holes; the first doped polysilicon layer 5 has a large thickness and good electrical conductivity, which helps to more effectively collect and transport charge carriers and improve the photoelectric conversion efficiency; Therefore, when the thickness ratio of the first doped silicon layer 4 to the first doped polysilicon layer 5 is 1:(3-5), good matching of optical and electrical properties is achieved, so that optical parasitic absorption is reduced while ensuring good conductivity, thereby improving the overall battery performance.

[0043] In an optional embodiment, the thickness of the first doped silicon layer 4 is 15-30 nm (for example, 15 nm, 20 nm, 25 nm, 30 nm); the thickness of the first doped polysilicon layer 5 is 45-150 nm (for example, 45 nm, 60 nm, 85 nm, 100 nm, 130 nm, 150 nm).

[0044] In an optional embodiment, the material of the anti-reflection film layer includes one of silicon nitride, silicon oxide or Al2O3.

[0045] In this embodiment, when the material of the anti-reflection film layer is silicon nitride, it can provide excellent anti-reflection performance, a wide refractive index adjustment range, light decay resistance, chemical corrosion resistance and high temperature resistance; when the material of the anti-reflection film layer is silicon oxide, it has the advantages of excellent insulation properties, lower light decay and low cost; when the material of the anti-reflection film layer is aluminum oxide (Al2O3), it can provide excellent optical properties, outstanding chemical resistance, good stability and high hardness.

[0046] In an optional embodiment, the heterojunction solar cell further comprises: A second composite passivation layer, a second doping layer, and a second anti-reflection film layer are located on the second surface of the silicon substrate 1 and are sequentially stacked along a second direction A2; The second doped layer includes: a second doped silicon layer 9 and a second doped polysilicon layer 10 stacked in sequence along the second direction A2; The material of the second doped silicon layer 9 includes one of doped amorphous silicon or doped microcrystalline silicon; The first direction A1 is opposite to the second direction A2.

[0047] In some embodiments, the band gap of the second doped polysilicon layer 10 is lower than the band gap of the second doped silicon layer 9 .

[0048] The present application may also provide a method for preparing a heterojunction solar cell. The preparation method comprises: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; forming a first composite passivation layer on the first surface of the silicon substrate; A first doped silicon layer, a first doped polysilicon layer and a first anti-reflection film layer are sequentially formed on the first composite passivation layer.

[0049] In an optional embodiment, during the process of forming the first doped polysilicon layer, the laser energy is 20 mJ / cm 2 -800mJ / cm 2 (For example, 20mJ / cm 2 、400mJ / cm 2 、600mJ / cm 2 、800mJ / cm 2 ), the pulse width is 5-50ns (for example, 5ns, 25ns, 40ns, 50ns), and the frequency is 1-1000Hz (for example, 1Hz, 500Hz, 1000Hz).

[0050] In the embodiment of the present application, by controlling various parameters of the above-mentioned laser, the first doped polysilicon layer can be crystallized, and a first doped polysilicon layer can be formed on the first doped silicon layer.

[0051] The following will conduct performance tests on the structure or preparation method of the heterojunction solar cell provided in the embodiments of the present application and related comparative examples.

[0052] [Example 1] like Figure 1 As shown, the specific structure of the heterojunction solar cell is: A silicon substrate 1, wherein the silicon substrate 1 comprises a second surface arranged opposite to the first surface; A first composite passivation layer, a first doping layer and a first anti-reflection film layer 6 are located on the first surface of the silicon substrate 1 and are sequentially stacked along a first direction A1; A second composite passivation layer, a second doping layer, and a second anti-reflection film layer 101 are located on the second surface of the silicon substrate 1 and are sequentially stacked along a second direction A2; and a first electrode 11 located on the first surface of the silicon substrate 1 and a second electrode 12 located on the second surface; The first composite passivation layer includes: a first passivation layer 2 and a second passivation layer 3 sequentially stacked along a first direction A1; the second composite passivation layer includes: a third passivation layer 7 and a fourth passivation layer 8 sequentially stacked along a second direction A2; The first doped layer includes: a first doped silicon layer 4 and a first doped polysilicon layer 5 sequentially stacked along a first direction A1; the second doped layer includes: a second doped silicon layer 9 and a second doped polysilicon layer 10 sequentially stacked along a second direction A2; the first direction A1 and the second direction A2 are opposite.

[0053] The specific preparation method is: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: depositing a first passivation layer on the first surface of the silicon substrate by CVD or ALD; and depositing a third passivation layer on the second surface of the silicon substrate; wherein the thickness of the first passivation layer is 7 nm, and the thickness of the third passivation layer is 7 nm; Step S3: depositing a second passivation layer on the surface of the first passivation layer by CVD, and introducing a first mixed gas (SiH4, H2 and B2H6) on the surface of the second passivation layer by PECVD to sequentially form a first doped silicon layer and an initial first doped polysilicon layer; A fourth passivation layer is deposited on the surface of the third passivation layer by CVD; a second mixed gas (SiH4, H2 and PH3) is introduced into the surface of the fourth passivation layer by PECVD to sequentially form a second doped silicon layer and an initial second doped polysilicon layer; wherein the thickness of the second passivation layer is 15 nm, and the thickness of the fourth passivation layer is 17 nm; wherein the initial first doped polysilicon layer is a P-type doped polysilicon layer, and the initial second doped polysilicon layer is an N-type doped polysilicon layer; Step S4: laser treatment is performed on the initial first doped polysilicon layer and the initial second doped polysilicon layer respectively, with the laser energy density being 350 mJ / cm 2 , a pulse width of 5 ns and a frequency of 300 Hz, so that the initial first doped polysilicon layer is crystallized and transformed into the first doped polysilicon layer; the initial second doped polysilicon layer is crystallized and transformed into the second doped polysilicon layer; Step S5: using CVD or ALD to deposit a first anti-reflection film layer on the surface of the first doped polysilicon; and depositing a second anti-reflection film layer on the surface of the second doped polysilicon; wherein the thickness of the first anti-reflection film layer is 80 nm, and the thickness of the second anti-reflection film layer is 100 nm; Step S6: etching a local surface of the first anti-reflection film layer by laser, dry process or wet process to expose a portion of the first doped polysilicon layer, and fabricating a gate line for collecting carriers on the exposed surface of the first doped polysilicon layer by silk screen printing or laser transfer to form a first electrode; The local surface of the second anti-reflection film layer is etched by laser, dry process or wet process to expose part of the second doped polysilicon layer, and the gate line for collecting carriers is made on the exposed surface of the second doped polysilicon layer by silk screen printing or laser transfer to form a second electrode.

[0054] The materials of the first doped silicon layer, the second doped silicon layer, the first doped polysilicon layer and the second doped polysilicon layer are all microcrystalline silicon, the thickness of the first doped silicon layer is 30nm; the thickness of the first doped polysilicon layer is 150nm; the ratio of the thickness of the first doped silicon layer to the first doped polysilicon layer is 1:5; the thickness of the second doped silicon layer is 30nm; the thickness of the second doped polysilicon layer is 150nm; the ratio of the thickness of the second doped silicon layer to the second doped polysilicon layer is 1:5; The materials of the first passivation layer and the third passivation layer are both silicon hydroxide-containing, the materials of the second passivation layer and the fourth passivation layer are both silicon hydroxide-containing, the hydrogen content in the second passivation layer is lower than the hydrogen content in the first passivation layer; the hydrogen content in the fourth passivation layer is lower than the hydrogen content in the third passivation layer; the hydrogen content in the first passivation layer is 17%, and the hydrogen content in the second passivation layer is 5%; The materials of the first anti-reflection film layer and the second anti-reflection film layer are both silicon nitride.

[0055] [Example 2] like Figure 2 As shown, the specific structure of the heterojunction solar cell is: A silicon substrate 1, wherein the silicon substrate 1 comprises a second surface arranged opposite to the first surface; A first composite passivation layer, a first doping layer and a first anti-reflection film layer 6 are located on the first surface of the silicon substrate 1 and are sequentially stacked along a first direction A1; A fifth passivation layer 13, a third doped polysilicon layer 14 and a TCO layer 15 are located on the second surface of the silicon substrate 1 and are sequentially stacked along the second direction A2; and a first electrode 11 located on the first surface of the silicon substrate 1 and a second electrode 12 located on the second surface; The first composite passivation layer includes: a first passivation layer 2 and a second passivation layer 3 sequentially stacked along a first direction A1; The first doped layer includes: a first doped silicon layer 4 and a first doped polysilicon layer 5 which are sequentially stacked along a first direction A1; the first direction A1 is opposite to the second direction A2.

[0056] The specific preparation method is: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: depositing a first passivation layer on the first surface of the silicon substrate by CVD or ALD; and depositing a fifth passivation layer on the second surface of the silicon substrate; wherein the thickness of the first passivation layer is 7 nm, and the thickness of the fifth passivation layer is 7 nm; Step S3: depositing a second passivation layer on the surface of the first passivation layer by CVD, and introducing a first mixed gas (SiH4, H2 and B2H6) on the surface of the second passivation layer by PECVD to sequentially form a first doped silicon layer and an initial first doped polysilicon layer; By using PECVD, a third mixed gas (SiH4, H2 and PH3) is introduced into the surface of the fifth passivation layer to form an initial third doped polysilicon layer; The thickness of the second passivation layer is 15 nm, and the thickness of the fifth passivation layer is 17 nm; the initial first doped polysilicon layer is a P-type doped polysilicon layer, and the initial third doped polysilicon layer is an N-type doped polysilicon layer; Step S4: laser treatment is performed on the initial first doped polysilicon layer and the initial third doped polysilicon layer respectively, and the laser energy density is increased from 350 mJ / cm 2 , a pulse width of 5 ns and a frequency of 300 Hz, so that the initial first doped polysilicon layer is crystallized and transformed into the first doped polysilicon layer; the initial third doped polysilicon layer is crystallized and transformed into the third doped polysilicon layer; Step S5: using CVD or ALD to deposit a first anti-reflection film layer on the surface of the first doped polysilicon; and depositing a TCO layer on the surface of the third doped polysilicon; wherein the thickness of the first anti-reflection film layer is 80 nm, and the thickness of the TCO layer is 100 nm; Step S6: etching a local surface of the first anti-reflection film layer by laser, dry process or wet process to expose a portion of the first doped polysilicon layer, and fabricating a gate line for collecting carriers on the exposed surface of the first doped polysilicon layer by silk screen printing or laser transfer to form a first electrode; The local surface of the TCO layer is etched by laser, dry process or wet process to expose part of the third doped polysilicon layer, and a gate line for collecting carriers is made on the surface of the exposed third doped polysilicon layer by silk screen printing or laser transfer to form a second electrode.

[0057] The materials of the first doped silicon layer, the first doped polysilicon layer and the third doped polysilicon layer are all microcrystalline silicon, the thickness of the first doped silicon layer is 30nm; the thickness of the first doped polysilicon layer is 150nm; the ratio of the thickness of the first doped silicon layer to the first doped polysilicon layer is 1:5; the thickness of the third doped silicon layer is 25nm; The materials of the first passivation layer, the second passivation layer and the fifth passivation layer are all silicon hydroxide-containing, and the hydrogen content in the second passivation layer is lower than the hydrogen content in the first passivation layer; the hydrogen content in the first passivation layer is 17%, and the hydrogen content in the second passivation layer is 5%; The materials of the first anti-reflection film layer and the second anti-reflection film layer are both silicon nitride.

[0058] [Example 3] - [Example 6] The heterojunction solar cells of Examples 3 to 6 were prepared by referring to the preparation method of Example 1, except that: In Example 3, the thickness of the first doped silicon layer is 25nm; the thickness of the first doped polysilicon layer is 100nm; the ratio of the thickness of the first doped silicon layer to the first doped polysilicon layer is 1:4; the thickness of the second doped silicon layer is 25nm; the thickness of the second doped polysilicon layer is 100nm; the ratio of the thickness of the second doped silicon layer to the second doped polysilicon layer is 1:4.

[0059] In Example 4, the thickness of the first doped silicon layer is 30nm; the thickness of the first doped polysilicon layer is 90nm; the ratio of the thickness of the first doped silicon layer to the first doped polysilicon layer is 1:3; the thickness of the second doped silicon layer is 30nm; the thickness of the second doped polysilicon layer is 90nm; the ratio of the thickness of the second doped silicon layer to the second doped polysilicon layer is 1:3.

[0060] In Example 5, the materials of the first doped silicon layer, the second doped silicon layer, the first doped polysilicon layer, and the second doped polysilicon layer are all amorphous silicon; during the laser treatment in step 4, the laser energy density is increased from 355 mJ / cm 2 , pulse width 5ns, frequency 300Hz.

[0061] In Example 6, the material of the first passivation layer is amorphous silicon, the material of the third passivation layer is silicon carbide, the material of the second passivation layer and the fourth passivation layer are both silicon hydroxide containing hydrogen content of 5%.

[0062] [Comparative Example 1] The specific structure of heterojunction solar cells is: A silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; A first passivation layer, an N-type doped microcrystalline silicon layer and a first TCO layer are located on the first surface of the silicon substrate and are sequentially stacked in a direction away from the silicon substrate; A second passivation layer, a P-type doped microcrystalline silicon layer, and a second TCO layer are located on the second surface of the silicon substrate and are sequentially stacked in a direction away from the silicon substrate; and a first electrode located on the first surface of the silicon substrate and a second surface electrode located on the second surface; Wherein, the materials of the first passivation layer and the second passivation layer are both amorphous silicon.

[0063] The following is a performance test of the heterojunction solar cells provided in Examples 1-6 of the present application and Comparative Example 1, so as to obtain the open circuit voltage Voc, fill factor FF, short circuit current density Jsc, and photoelectric conversion efficiency PCE of the corresponding battery devices. The test results are shown in Table 1.

[0064] Table 1 Performance test results of heterojunction solar cells of Examples 1-6 and Comparative Example 1

[0065] It can be seen from Table 1 that compared with Comparative Example 1, the open circuit voltage Voc, fill factor FF, short circuit current density Jsc, and photoelectric conversion efficiency PCE of the heterojunction solar cells of Examples 1-6 of the present application are significantly improved, which indicates that the stacked first doped layer and the first doped polysilicon layer in Examples 1-6 of the present application can improve the cell's absorption and utilization of the entire spectrum of sunlight, thereby improving the cell's photoelectric conversion efficiency.

[0066] Compared with Comparative Example 1, the thickness ratio of the first doped silicon layer and the first doped polysilicon layer used in Examples 1-6 is 1:(3-5). At this thickness ratio, a good match between optical and electrical properties can be achieved, thereby reducing optical parasitic absorption while ensuring good conductivity, thereby improving the overall battery performance.

[0067] Compared with Comparative Example 1, the second passivation layer used in Examples 1-6 has a lower hydrogen concentration, which can reduce hydrogen explosion during the crystallization process and improve the quality of crystallization, thereby optimizing the separation and transmission efficiency of charge carriers and improving the overall efficiency of the battery.

[0068] To summarize, the first doped layer and the first doped polysilicon layer together constitute the first doped layer. On the one hand, compared with the TCO layer in the traditional technology, the first doped polysilicon layer has better conductivity and better lateral current collection effect. At the same time, the contact resistance with the gate line is lower, which significantly reduces the series resistance and helps to improve the battery efficiency. On the other hand, since the band gap of the first doped polysilicon layer is lower than the band gap of the first doped silicon layer, its optical parasitic absorption is higher than that of the first doped silicon layer. The optical parasitic absorption of the first doped silicon layer is low, and the stacking arrangement of the first doped silicon layer and the first doped polysilicon layer can effectively reduce the optical parasitic absorption of the battery, thereby improving the short-circuit current and photoelectric conversion efficiency.

[0069] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0070] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0071] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0072] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A heterojunction solar cell, characterized in that: include: A silicon substrate (1), the silicon substrate (1) comprising a first surface and a second surface arranged opposite to each other; A first composite passivation layer, a first doping layer and a first anti-reflection film layer (6) which are located on the first surface of the silicon substrate (1) and are stacked in sequence along a first direction (A1); The first doped layer comprises: a first doped silicon layer (4) and a first doped polysilicon layer (5) which are stacked in sequence along the first direction (A1); The material of the first doped silicon layer (4) includes one of doped amorphous silicon or doped microcrystalline silicon.

2. The heterojunction solar cell according to claim 1, characterized in that: The first composite passivation layer comprises: a first passivation layer (2) and a second passivation layer (3) which are sequentially stacked along the first direction (A1); The material of the first passivation layer (2) includes one or more of silicon hydroxide, amorphous silicon, microcrystalline silicon, silicon carbide or Al2O3; The material of the second passivation layer (3) is one or more of silicon hydroxide, Al2O3, silicon oxynitride, and silicon nitride.

3. The heterojunction solar cell according to claim 2, characterized in that: The material of the second passivation layer (3) contains silicon hydroxide.

4. The heterojunction solar cell according to claim 2, characterized in that: When the material of the first passivation layer (2) contains silicon hydroxide, and the material of the second passivation layer (3) contains silicon hydroxide; The hydrogen content in the second passivation layer (3) is lower than the hydrogen content in the first passivation layer (2).

5. The heterojunction solar cell according to claim 1, characterized in that: The ratio of the thickness of the first doped silicon layer (4) to the first doped polysilicon layer (5) is 1:(3-5).

6. The heterojunction solar cell according to claim 1, characterized in that: The thickness of the first doped silicon layer (4) is 15-30 nm; the thickness of the first doped polysilicon layer (5) is 45-150 nm.

7. The heterojunction solar cell according to claim 1, characterized in that: The material of the first anti-reflection film layer (6) includes one of silicon nitride, silicon oxide or Al2O3.

8. The heterojunction solar cell according to claim 1, characterized in that: Also includes: A second composite passivation layer, a second doping layer, and a second anti-reflection film layer are located on the second surface of the silicon substrate (1) and are stacked in sequence along a second direction (A2); The second doped layer comprises: a second doped silicon layer (9) and a second doped polysilicon layer (10) which are sequentially stacked along the second direction (A2); The material of the second doped silicon layer (9) includes one of doped amorphous silicon or doped microcrystalline silicon; The first direction (A1) and the second direction (A2) are opposite to each other.

9. A method for preparing a heterojunction solar cell, characterized in that: For preparing a heterojunction solar cell according to any one of claims 1 to 8, comprising the following steps: Providing a silicon substrate (1), wherein the silicon substrate (1) comprises a first surface and a second surface arranged opposite to each other; forming the first composite passivation layer on the first surface of the silicon substrate (1); A first doped silicon layer (4), a first doped polysilicon layer (5) and a first anti-reflection film layer (6) are sequentially formed on the first composite passivation layer.

10. The method for preparing a heterojunction solar cell according to claim 9, characterized in that: In the process of forming the first doped polysilicon layer (5), the laser energy is 20 mJ / cm 2 -800mJ / cm 2 , pulse width is 5-50ns, frequency is 1-1000Hz.

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