Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first area and a second area which are distributed at an interval, the first area is provided with a tunneling passivation structure, and the second area is provided with a second tunneling passivation structure. A passivation structure is arranged on the second area, a first electrode electrically connected with the tunneling passivation structure is further arranged on the first area, and the width W of the first area is larger than the width L of the first electrode. By setting the widths of the metal region and the electrode, the process fault tolerance rate can be improved, the electrode is ensured to be located in the metal region, and the contact passivation performance in the metal region is ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a solar cell and a preparation method thereof. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) batteries can improve the surface passivation performance of the battery, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the battery by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the battery.

[0003] The TOPCon cells of the prior art are usually single-sided TOPCon structures, with selective emitter technology used on the front side to achieve deep junctions with high boron doping concentrations in the metal region and shallow junctions with low boron doping concentrations in the non-metal region. However, the recombination in the metal region is still relatively high, which has become the main factor limiting the improvement of cell efficiency. In addition, the front boron diffusion requires a high temperature of more than 1000°C, which consumes a lot of energy. The high temperature and the borosilicate glass produced will shorten the life of the quartz tube, resulting in an increase in the cost of the entire process and equipment.

[0004] The theoretical efficiency of a single-sided TOPCon structure battery is 27.1%, and the theoretical efficiency of a double-sided TOPCon structure battery is 28.7%. Currently, a double-sided tunnel passivation contact structure is needed to further improve the efficiency. However, if a tunnel passivation contact structure is made on the front of a TOPCon battery, it is difficult to accurately control the thickness of the poly-Si layer in the non-metallic area by first depositing a thick poly-Si layer on the front, then adding a mask, and then wet etching to partially thin it. The process window is narrow, and if the tunnel passivation contact structure in the non-metallic area is not retained, the battery efficiency improvement is relatively small; if the direct laser window opening + secondary diffusion method is used, the process flow is also complicated and the process window is small and difficult to control, and high temperature is required for boron diffusion.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a solar cell and a method for preparing the same. Summary of the invention

[0006] The object of the present invention is to provide a solar cell and a method for preparing the same, so as to improve the process error tolerance and ensure the contact passivation performance in the metal region.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface arranged opposite to each other, the first surface comprises a first region and a second region distributed at intervals, a tunneling passivation structure is arranged on the first region, a passivation structure is arranged on the second region, a first electrode electrically connected to the tunneling passivation structure is also arranged on the first region, and a width W of the first region is greater than a width L of the first electrode.

[0009] In one embodiment, a difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

[0010] In one embodiment, the difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or,

[0011] A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

[0012] In one embodiment, the width of the first electrode is 5 μm to 40 μm; and / or,

[0013] The width of the first region is 45 μm to 640 μm or 45 μm to 150 μm.

[0014] In one embodiment, the tunneling passivation structure includes a first tunneling layer and a first doping layer sequentially stacked on the first region, and the passivation structure includes a blocking layer and a second doping layer sequentially stacked on the second region, and the first doping layer and the second doping layer have the same doping type.

[0015] In one embodiment, the first electrode is in contact with the first doped layer.

[0016] In one embodiment, the barrier layer and the second doping layer on the second region extend laterally into the first region and cover the first tunneling layer and the first doping layer.

[0017] In one embodiment, the first electrode is in contact with the second doped layer, or the first electrode penetrates the second doped layer and the barrier layer and is in contact with the first doped layer.

[0018] In one embodiment, the average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or,

[0019] The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 and / or,

[0020] The average doping concentration of the second doping layer is 1E20cm-3 ~5E20cm -3 .

[0021] In one embodiment, the thickness of the first doping layer is greater than the thickness of the second doping layer; and / or,

[0022] The thickness of the first doping layer is 30nm to 300nm or 100nm to 200nm; and / or,

[0023] The thickness of the second doping layer is 5 nm to 100 nm or 10 nm to 50 nm.

[0024] In one embodiment, the first doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from inside to outside; and / or,

[0025] The second doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside.

[0026] In one embodiment, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0027] The thickness of the first tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0028] The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and / or,

[0029] The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0030] In one embodiment, a second tunneling layer and a third doping layer are sequentially stacked on the second surface of the silicon substrate, the doping type of the third doping layer is opposite to that of the first doping layer, and the second electrode is in contact with the third doping layer.

[0031] In one embodiment, the average doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~3E21cm -3 and / or,

[0032] The third doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from inside to outside; and / or,

[0033] The thickness of the third doping layer is 20nm to 300nm or 60nm to 150nm; and / or,

[0034] The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0035] The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0036] In one embodiment, the silicon substrate is an N-type silicon substrate, the first doping layer and the second doping layer are P-type doped, and the third doping layer is N-type doped; and / or,

[0037] A light trapping structure is formed on the first surface and / or the second surface of the silicon substrate; and / or,

[0038] A first anti-reflection layer is stacked on the second doped layer; and / or,

[0039] A second anti-reflection layer is stacked on the third doping layer.

[0040] Another embodiment of the present invention provides a technical solution as follows:

[0041] A method for preparing a solar cell, the method comprising the following steps:

[0042] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region distributed at intervals;

[0043] Preparing a tunneling passivation structure on the first region, and preparing a passivation structure on the second region;

[0044] A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, and a width L of the first electrode is smaller than a width W of the first region.

[0045] In one embodiment, the tunnel passivation structure comprises: a first tunneling layer and a first doping layer, and the passivation structure comprises a barrier layer and a second doping layer;

[0046] The preparation of the tunneling passivation structure, the passivation structure and the first electrode includes:

[0047] Depositing a first tunneling layer and a first doping layer on the entire surface of the first surface;

[0048] forming a patterned first mask on the first doped layer in the first region;

[0049] Using an etching process and / or a texturing process to remove the first tunneling layer and the first doping layer on the second region;

[0050] Cleaning and removing the first mask on the first doping layer;

[0051] Preparing a barrier layer and a second doping layer stacked in sequence on the silicon substrate in the second region and on the first doping layer in the first region, wherein the doping type of the second doping layer is the same as the doping type of the first doping layer;

[0052] Preparing a first electrode on a first region of the first surface, the first electrode being in contact with the second doped layer or the first doped layer;

[0053] The difference between the width W of the first region and the width L of the first electrode satisfies: WL≥2X+2Y, where X is the process accuracy of forming the patterned first mask, and Y is the process accuracy of preparing the first electrode.

[0054] In one embodiment, it is characterized in that forming a patterned first mask on the first doping layer in the first region comprises:

[0055] An inorganic mask layer is prepared on the first doping layer, and patterned by a laser window opening process to remove the inorganic mask layer on the second region, with a process accuracy X greater than or equal to 15 μm; or,

[0056] An inorganic mask layer is prepared on the first doping layer, and a patterned organic mask layer is prepared on the first region by a screen printing process, with a process precision X being greater than or equal to 15 μm.

[0057] In one embodiment, the preparation of the first electrode includes:

[0058] Printing a metal layer on the first area of ​​the first surface by a screen printing process, wherein a process accuracy Y of the screen printing is greater than or equal to 5 μm;

[0059] The metal layer is sintered by a sintering process to form a first electrode in ohmic contact with the silicon substrate.

[0060] In one embodiment, a difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

[0061] In one embodiment, the difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or,

[0062] A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

[0063] In one embodiment, the width of the first electrode is 5 μm to 40 μm; and / or,

[0064] The width of the first region is 45 μm to 640 μm or 45 μm to 150 μm.

[0065] In one embodiment, the average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or,

[0066] The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 and / or,

[0067] The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 .

[0068] In one embodiment, the thickness of the first doping layer is greater than the thickness of the second doping layer; and / or,

[0069] The thickness of the first doping layer is 30nm to 300nm or 100nm to 200nm; and / or,

[0070] The thickness of the second doping layer is 5 nm to 100 nm or 10 nm to 50 nm.

[0071] In one embodiment, the preparation method further comprises:

[0072] Prepare a second tunneling layer and a third doping layer stacked in sequence on the second surface, wherein the doping type of the third doping layer is opposite to that of the first doping layer;

[0073] A second electrode in contact with the third doping layer is prepared on the second surface.

[0074] In one embodiment, the preparation of the second electrode includes:

[0075] Printing a metal layer on the second surface by screen printing;

[0076] The metal layer is sintered by a sintering process to form a second electrode in ohmic contact with the silicon substrate.

[0077] In one embodiment, the first doped layer, the second doped layer and the third doped layer all include doped amorphous silicon layers, and the preparation method further includes:

[0078] The first doped layer, the second doped layer and the third doped layer are annealed at a temperature of 900° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

[0079] In one embodiment, the preparation method further comprises:

[0080] Preparing a second mask on the second doped layer to remove silicon oxide and amorphous silicon deposited on the surface and around the edge;

[0081] Preparing a third mask on the third doped layer to remove silicon oxide and polysilicon plated on the surface and around the edge;

[0082] The second mask and the third mask are removed and cleaned.

[0083] In one embodiment, the preparation method further comprises:

[0084] The light trapping structure is prepared on the first surface and / or the second surface of the silicon substrate by a texturing process; and / or,

[0085] Prepare a first anti-reflection layer on the first surface of the silicon substrate; and / or,

[0086] A second anti-reflection layer is prepared on the second surface of the silicon substrate.

[0087] Compared with the prior art, the present invention has the following beneficial effects:

[0088] The present invention can improve the process error tolerance rate by setting the width of the metal area and the electrode, ensure that the electrode is located in the metal area, and ensure the contact passivation performance in the metal area.

[0089] The solar cell of the present invention is a double-sided TOPCon cell, which adopts a Poly-finger structure with local passivation contact, thereby ensuring contact passivation in the first area and reducing parasitic absorption in the second area, which can greatly improve the cell efficiency, and has a simple preparation process and is suitable for mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0091] Figure 1a is a schematic structural diagram of a solar cell in Example 1 of the present invention;

[0092] Figure 1b for Figure 1a A schematic diagram of the local enlarged structure at point A in the middle;

[0093] Figure 1c for Figure 1a Schematic diagram of the structure viewed from above at A in the middle;

[0094] Figures 2a to 2j is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0095] Figure 3a to 3d 4 is a process flow chart of the patterning step in Example 2 of the present invention. DETAILED DESCRIPTION

[0096] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0097] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0098] The present invention discloses a solar cell, comprising a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged opposite to each other, wherein the first surface comprises a first region and a second region distributed at intervals, wherein a tunneling passivation structure is arranged on the first region, a passivation structure is arranged on the second region, and a first electrode electrically connected to the tunneling passivation structure is also arranged on the first region, wherein a width W of the first region is greater than a width L of the first electrode.

[0099] The present invention also discloses a method for preparing a solar cell, comprising the following steps:

[0100] Provide a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region distributed at intervals;

[0101] preparing a tunnel passivation structure on the first region and preparing a passivation structure on the second region;

[0102] A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, and a width L of the first electrode is smaller than a width W of the first region.

[0103] The present invention can improve the process error tolerance rate by setting the width of the metal area and the electrode, ensure that the electrode is located in the metal area, and ensure the contact passivation performance in the metal area.

[0104] The solar cell of the present invention is a double-sided TOPCon cell, both the front and back sides of which have a tunnel passivation contact structure, thereby ensuring the passivation contact of the front / back metal regions and reducing the parasitic absorption of the front / back non-metal regions. Compared with the single-sided TOPCon cell in the prior art, the cell efficiency can be greatly improved, and the preparation process is simple, which is suitable for mass production.

[0105] The present invention is further described below in conjunction with specific embodiments.

[0106] Embodiment 1:

[0107] Ginseng Figure 1a and Figure 1b The structure diagram of the solar cell in this embodiment is shown. The solar cell is a double-sided TOPCon cell, including a silicon substrate 10. The silicon substrate includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The first surface S1 includes a first area S11 and a second area S12. The first surface S1 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first area S11 is the front metal area, and the second area S12 is the front non-metal area. Of course, in other embodiments, the first surface S1 may also be the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10, the second surface S2 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, the first area S11 is the back metal area, and the second area S12 is the back non-metal area.

[0108] In this embodiment, a first tunneling layer 11 and a first doping layer 21 are sequentially stacked on the first region S11, a barrier layer 12 and a second doping layer 22 are sequentially stacked on the second region S12, and the barrier layer 12 and the second doping layer 22 extend laterally into the first region S11 and cover the surfaces of the first tunneling layer 11 and the first doping layer 12, and a second tunneling layer 13 and a third doping layer 23 are sequentially stacked on the second surface S2.

[0109] In addition, a first electrode 41 is distributed on the first surface S1, and the first electrode 41 is located on the first region S11, and the first electrode 41 contacts the second doping layer 22 thereunder, and a second electrode 42 is distributed on the second surface S2, and the second electrode 42 contacts the third doping layer 23. The first doping layer 21 and the second doping layer 22 have the same doping type, and the first doping layer 21 and the third doping layer 23 have opposite doping types.

[0110] Preferably, in this embodiment, the thickness of the first doping layer 21 is greater than the thickness of the second doping layer 22 .

[0111] Furthermore, in this embodiment, a first anti-reflection layer 31 is stacked on the second doping layer 22 , and a second anti-reflection layer 32 is stacked on the third doping layer 23 .

[0112] The material, thickness, doping concentration, etc. of each layer in the solar cell of this embodiment are described in detail below.

[0113] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0114] Furthermore, light trapping structures are formed on both the first surface S1 and the second surface S2 of the silicon substrate 10. For example, a pyramid texture structure can be formed on the first surface S1 and the second surface S2 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5 μm to 3 μm.

[0115] In this embodiment, the first tunneling layer 11 and the second tunneling layer 13 are any one or more combinations of silicon oxide layers and silicon oxynitride layers, with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm; the barrier layer 12 is any one or more combinations of silicon oxide layers and silicon carbide layers, with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm.

[0116] In this embodiment, the first doping layer 21, the second doping layer 22 and the third doping layer 23 can all be a doped polysilicon layer or multiple doped polysilicon layers with a gradient increase in doping concentration from the inside to the outside (i.e., in a direction away from the substrate). The thickness of the first doping layer 21 is 30nm to 300nm, preferably 100nm to 200nm; the thickness of the second doping layer 22 is 5nm to 100nm, preferably 10nm to 50nm; the thickness of the third doping layer 23 is 20nm to 300nm, preferably 60nm to 150nm.

[0117] In addition, the first doping layer 21 and the second doping layer 22 are both P-type doped polysilicon layers, such as boron doped; and the third doping layer 23 is an N-type doped polysilicon layer, such as phosphorus doped.

[0118] Since the second doping layer 22 will cause serious light absorption in the non-metallic area and large current loss, the thickness of the second doping layer 22 is less than that of the first doping layer 21, so as to ensure the passivation effect of the metal area while reducing the light parasitic absorption of the non-metallic area, effectively improving the photoelectric conversion efficiency of the solar cell. In addition, the first doping layer 21 and the second doping layer 22 are both activated by annealing process. The intermediate barrier layer 12 is relatively thin and will be penetrated by the doping elements during the annealing process. Therefore, the average doping concentration of the first doping layer 21 and the second doping layer 22 is not much different. In the actual process, the average doping concentration of the first doping layer 21 will be slightly less than the average doping concentration of the second doping layer 22 or be equal to the average doping concentration of the second doping layer 22, that is, the average doping concentration of the first doping layer 21 is less than or equal to the average doping concentration of the second doping layer 22.

[0119] Furthermore, the average doping concentration of the first doping layer 21 is 5E19cm -3 ~5E20cm -3 When the first doping layer 21 is a P-type doped polysilicon layer, its doping concentration is 5E19cm -3 ~5E20cm -3 When the first doping layer 21 is a multi-layer P-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration increases gradually from the inside to the outside.

[0120] The average doping concentration of the second doping layer 22 is 1E20 cm -3 ~5E20cm -3 When the second doping layer 22 is a P-type doped polysilicon layer, its doping concentration is 5E18cm -3 ~5E20cm -3 When the second doping layer 22 is a multi-layer P-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration increases gradually from the inside to the outside.

[0121] The average doping concentration of the third doping layer 23 is 3E20 cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~3E21cm -3 When the third doping layer 23 is a P-type doped polysilicon layer, its doping concentration is 3E20cm -3 ~3E21cm -3 When the third doping layer 23 is a multi-layer P-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration increases gradually from the inside to the outside, for example, the doping concentration of the inner layer is 3E20cm -3 ~5E20cm -3 , the doping concentration of the middle layer is 5E20cm -3 ~1E21cm -3 , the doping concentration of the outer layer is 1E21cm -3 ~3E21cm -3 .

[0122] In this embodiment, the first anti-reflection layer 31 on the first surface and the second anti-reflection layer 31 on the back surface can be a combination of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness is 60 nm to 130 nm.

[0123] In this embodiment, the first electrode 41 on the first surface can contact the second doping layer 22, or penetrate the barrier layer 12 to contact the first doping layer 21, but cannot damage the bottom first tunneling layer 11, ensuring the tunneling effect of the first tunneling layer 11. The second electrode 42 on the second surface is in electrical contact with the third doping layer 23, but cannot damage the bottom second tunneling layer 13, ensuring the tunneling effect of the second tunneling layer 13.

[0124] Combination Figure 1b , Figure 1c As shown, the first electrode 41 in this embodiment is distributed directly above the first area S11, and the projection of the first electrode 41 on the first surface S1 is within the first area S11. Taking the gate line electrode as an example, the gate line electrode may include a plurality of main gate lines and a plurality of auxiliary gate lines (or fine gate lines) distributed vertically. The main gate lines are usually prepared by non-burn-through slurry. The first electrode 41 in the present invention is described by taking the auxiliary gate lines as an example. The width L of the auxiliary gate lines is 5μm to 40μm. The first area S11 includes a plurality of linear areas distributed at intervals. The width W of the first area S11 is 45μm to 640μm, preferably 45μm to 150μm.

[0125] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0126] 1. Double-sided velveting

[0127] Ginseng Figure 2a As shown, a silicon substrate 10 is provided, the silicon substrate includes a first surface S1 and a second surface S2 which are arranged opposite to each other, the first surface S1 includes a first region S11 and a second region S12, the first surface S1 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10, the first region S11 is the front metal region, and the second region S12 is the front non-metal region. Of course, in other embodiments, the first surface S1 may also be the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10, the second surface S2 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, the first region S11 is the back metal region, and the second region S12 is the back non-metal region.

[0128] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3Ω·cm to 7Ω·cm, preferably 0.5Ω·cm to 3.5Ω·cm. The first surface S1 and the second surface S2 of the silicon substrate are formed with a pyramid texture structure (not shown) by an alkali texture process, and the size of the pyramid is 0.5μm to 3μm, preferably 0.5μm to 1.5μm.

[0129] 2. Preparation of the first tunneling layer 11 and the first doping layer 21

[0130] A first tunneling layer 11 and a first doping layer 21 stacked in sequence are prepared on the first region S11. Specifically, the following steps are included:

[0131] First, Figure 2b As shown, the first tunneling layer 11 , the first doping layer 21 and the first mask 51 are deposited on the entire surface of the first surface S1 .

[0132] Exemplarily, in this embodiment, the PECVD process is used for deposition; the thickness of the first tunneling layer 11 is 0.5nm to 3nm, preferably 1.5nm to 2.5nm; the first doping layer 21 is a boron-doped amorphous silicon layer with an average doping concentration of 5E19cm -3 ~5E20cm -3 , with a thickness of 30nm to 300nm, preferably 100nm to 200nm; the first mask 51 is an inorganic mask, such as a silicon oxide mask, with a thickness of 5nm to 50nm.

[0133] Then Figure 2c As shown, a patterned first mask 51 is formed on the first doping layer 21 in the first region S11 through a patterning process.

[0134] Specifically, in this embodiment, patterning is performed by a laser windowing process, and a large-area laser windowing is performed on the second region S12 by means of laser windowing, so as to remove the first mask 51 on the second region S12.

[0135] Then participate Figure 2d As shown, the first tunneling layer 11 and the first doping layer 21 on the second region S12 are removed by using an etching process and a texturing process.

[0136] For example, in this embodiment, the second region S12 is subjected to a secondary texturing treatment using the patterned first mask 51 , and the first tunneling layer 11 and the first doping layer 21 deposited on the second region S12 are etched away.

[0137] The last Figure 2e As shown, the first mask 51 on the first doping layer is cleaned and removed.

[0138] Combination Figure 1c As shown, considering the laser process accuracy X during the laser window opening process for patterning, a certain width needs to be reserved on both sides of the first area S11. For example, if the laser process accuracy X in this embodiment is 15 μm, the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve a width of at least 30 μm.

[0139] 3. Preparation of barrier layer 12 and second doping layer 22

[0140] Ginseng Figure 2fAs shown, a barrier layer 12 , a second doping layer 22 , and a second mask 52 stacked in sequence are prepared on the second region S12 and the first doping layer 21 .

[0141] For example, in this embodiment, the PECVD process is used for deposition; the thickness of the barrier layer 12 is 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the second doping layer 22 is a boron-doped amorphous silicon layer with an average doping concentration of 1E20 cm -3 ~5E20cm -3 , with a thickness of 5nm to 100nm, preferably 10nm to 50nm; the second mask 52 is an inorganic mask, such as a silicon oxide mask, with a thickness of 5nm to 100nm.

[0142] In this embodiment, the barrier layer 12 and the second doping layer 22 are deposited on the entire surface of the first surface S1. In the actual process, the barrier layer 12 and the second doping layer 22 are not only deposited directly above the second region S12 and the first doping layer 21, but also deposited outside the side walls of the first tunneling layer 11 and the first doping layer 21.

[0143] In other embodiments, the barrier layer 12 and the second doping layer 22 may also be deposited on the second region S12 and the first doping layer 21 in different regions, which will not be described in detail herein.

[0144] 4. Backside de-plating and polishing

[0145] The single-sided chain equipment is used to remove the silicon oxide on the back and edge by hydrofluoric acid, and then the amorphous silicon on the edge is removed by alkaline solution, and the back is polished or micro-textured, and finally RCA cleaning is performed.

[0146] 5. Preparation of the second tunneling layer 13 and the third doping layer 23

[0147] Ginseng Figure 2g As shown, a second tunneling layer 13, a third doping layer 23 and a third mask 53 stacked in sequence are prepared on the second surface S2.

[0148] Exemplarily, in this embodiment, the PECVD process is used for deposition; the thickness of the second tunneling layer 13 is 0.5nm to 3nm, preferably 1.5nm to 2.5nm; the third doping layer 23 is a phosphorus-doped amorphous silicon layer with an average doping concentration of 3E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~3E21cm -3 , with a thickness of 20nm to 300nm, preferably 60nm to 150nm; the third mask 53 is an inorganic mask, such as a silicon oxide mask, with a thickness of 5nm to 50nm.

[0149] 6. Co-annealing

[0150] The first doping layer 21 , the second doping layer 22 and the third doping layer 23 are subjected to high temperature annealing treatment in a high temperature annealing furnace, and the annealing temperature is 900° C. to 980° C.

[0151] The co-annealing process can activate the doping atoms (phosphorus atoms and boron atoms) in the doping layer, convert the doped amorphous silicon layer into a doped polysilicon layer, and simultaneously form a tunnel passivation contact structure on the front and back sides.

[0152] Illustratively, in this embodiment, after the co-annealing treatment, the first doping layer 21 and the second doping layer 22 are transformed from boron-doped amorphous silicon layers to boron-doped polysilicon layers, and the third doping layer 23 is transformed from phosphorus-doped amorphous silicon layers to phosphorus-doped polysilicon layers.

[0153] 7. De-plating and cleaning

[0154] The silicon oxide on the first surface and the edge of the coating was removed by hydrofluoric acid using a single-sided chain device, and then the polysilicon on the edge was removed by alkaline solution. Figure 2h As shown, the second mask 52 on the first surface and the third mask 53 on the back surface are removed, and RCA cleaning is performed.

[0155] 8. Preparation of anti-reflection layer

[0156] Ginseng Figure 2i As shown, the first anti-reflection layer 31 is deposited on the second doping layer 22 by using a PECVD process, and the second anti-reflection layer 32 is deposited on the third doping layer 23 .

[0157] Exemplarily, the first anti-reflection layer 31 and the second anti-reflection layer 32 in this embodiment can be a silicon nitride layer, or a silicon nitride layer + a silicon oxynitride layer, or a silicon nitride layer + a silicon oxynitride layer + a silicon oxide layer, and the thickness of the anti-reflection layer is 60nm to 130nm.

[0158] 9. Preparation of metal electrodes

[0159] Ginseng Figure 2j As shown, a first electrode 41 in ohmic contact with the silicon substrate 10 is prepared on the first region S11 of the first surface S1, and a second electrode 42 in ohmic contact with the silicon substrate 10 is prepared on the second surface S2.

[0160] Specifically, in this embodiment, a screen printing process is used to print metal layers on the first area S11 in the first surface S1 and on the second surface S2, and a sintering process is used to sinter the metal layers to form a first electrode 41 and a second electrode 42 in ohmic contact with the silicon substrate 10. Finally, light injection is used to post-process the battery cell.

[0161] Combination Figure 1cAs shown, considering the printing process accuracy Y in the process of preparing electrodes by screen printing technology, a certain width needs to be reserved on both sides of the first area S11. For example, if the printing process accuracy Y in this embodiment is 5μm, the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve a width of at least 10μm.

[0162] The above steps can be used to prepare double-sided TOPCon cells, and finally the cells are tested, sorted and stored.

[0163] Taking into account the process accuracy of the laser window opening process and the screen printing process, the difference between the width W of the first region S11 and the width L of the first electrode 41 in this embodiment needs to satisfy: WL≥2X+2Y, that is, WL≥40μm. In addition, the density of the gate line will affect the efficiency of the battery. The larger the gate line spacing, the lower the current transmission efficiency. Therefore, the difference between the width W of the first region S11 and the width L of the first electrode 41 needs to be within a certain range, such as satisfying WL≤600μm in this embodiment, preferably, WL≤110μm.

[0164] Based on the above analysis, when the width L of the first electrode 41 in this embodiment is 5 μm to 40 μm, the width W of the first region S11 is 45 μm to 640 μm, preferably 45 μm to 150 μm. In other embodiments, the width W of the first region S11 is affected by the width L of the first electrode 41, the process accuracy X of forming the patterned first mask, and the process accuracy Y of preparing the first electrode, and the range of W can be adaptively adjusted according to the values ​​of L, X, and Y.

[0165] Embodiment 2:

[0166] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Embodiment 1, except for the patterning step in step 2 of the preparation method.

[0167] Specifically, in Embodiment 1, the first mask 51 is patterned by a laser windowing process, and the patterning steps in this embodiment are specifically as follows:

[0168] First, Figure 3a As shown, a first tunneling layer 11, a first doping layer 21 and a first mask 51 are deposited on the entire surface of the first surface S1, and the first mask 51 is an inorganic mask, such as a silicon oxide mask;

[0169] Then Figure 3b As shown, a patterned fourth mask 54 is prepared on the first region S11 by a screen printing process, and the fourth mask 54 is an organic mask, such as a resin mask;

[0170] Then participate Figure 3cAs shown, the second region is etched and subjected to secondary texturing treatment by a wet etching process to remove the first tunneling layer 11 and the first doping layer 21 on the second region;

[0171] The last Figure 3d As shown, the first mask 51 and the fourth mask 54 on the first doping layer are cleaned and removed.

[0172] Similarly, considering the printing process accuracy X during the patterning process of the screen printing process, a certain width needs to be reserved on both sides of the first area S11. For example, if the printing process accuracy X in this embodiment is 15 μm, then the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve at least 30 μm.

[0173] Referring to Embodiment 1, in this embodiment, the difference between the width W of the first region S11 and the width L of the first electrode 41 needs to satisfy WL≥2X+2Y, that is, WL≥40 μm, and satisfy WL≤600 μm, preferably, WL≤110 μm.

[0174] Embodiment 3:

[0175] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0176] 1. Double-sided velveting

[0177] The silicon substrate in this embodiment is an N-type silicon substrate with a resistivity of 1Ω·cm to 2Ω·cm. The first surface and the second surface of the silicon substrate are formed with a pyramid texture structure by an alkali texturing process, and the size of the pyramid is 0.5μm to 1.5μm.

[0178] 2. Preparation of the first tunneling layer and the first doping layer

[0179] A 1.5nm to 2nm tunneling silicon oxide layer is grown on the first surface using the PECVD process, and then a 10nm thick intrinsic amorphous silicon layer, a 50nm thick lightly doped P-type amorphous silicon layer, a 120nm thick heavily doped P-type amorphous silicon layer are deposited in sequence, and finally a 20nm thick silicon oxide mask layer is deposited.

[0180] Among them, the average doping concentration of the lightly doped P-type amorphous silicon layer is 5E19cm -3 ~6E19cm -3 The average doping concentration of the heavily doped P-type amorphous silicon layer is 1E20cm -3 ~3E20cm -3 .

[0181] A large-area laser window opening is performed in the second area through a laser window opening process to remove the silicon oxide mask layer deposited in the second area. Then, a secondary alkali texturing process is performed on the second area to etch away the first tunneling layer and the first doping layer. The pyramid size of the secondary alkali texturing is 0.5μm to 1.5μm. Finally, the remaining silicon oxide mask layer is cleaned and removed.

[0182] 3. Preparation of barrier layer and second doping layer

[0183] A 1.5nm to 2nm tunneling silicon oxide layer is continuously grown on the first surface using the PECVD process, and then a 5nm thick intrinsic amorphous silicon layer, a 10nm thick lightly doped P-type amorphous silicon layer, a 30nm thick heavily doped P-type amorphous silicon layer are deposited in sequence, and finally a 60nm thick silicon oxide mask layer is deposited.

[0184] Among them, the average doping concentration of the lightly doped P-type amorphous silicon layer is 1E20cm -3 ~2E20cm -3 The average doping concentration of the heavily doped P-type amorphous silicon layer is 3E20cm -3 ~5E20cm -3 .

[0185] 4. Backside de-plating and polishing

[0186] The single-sided chain equipment is used to remove the silicon oxide on the back and edge by hydrofluoric acid, and then the amorphous silicon on the edge is removed by alkaline solution, and the back is polished or micro-textured, and finally RCA cleaning is performed.

[0187] 5. Preparation of the second tunneling layer and the third doping layer

[0188] A 2nm to 2.5nm tunneling silicon oxide layer is grown on the second surface using the PECVD process, and then a 15nm thick intrinsic amorphous silicon layer, a 30nm thick lightly doped N-type amorphous silicon layer, a 70nm thick heavily doped N-type amorphous silicon layer are deposited in sequence, and finally a 20nm thick silicon oxide mask layer is deposited.

[0189] 6. Co-annealing

[0190] The first doped layer, the second doped layer and the third doped layer are subjected to high-temperature annealing treatment in a high-temperature annealing furnace at a temperature of 900°C to 980°C. The co-annealing treatment can activate the doped atoms (phosphorus atoms and boron atoms) in the doped layers, and convert the doped amorphous silicon layer into a doped polysilicon layer. At the same time, the doped atoms will diffuse into the intrinsic amorphous silicon layer, and finally convert the intrinsic amorphous silicon layer into a doped polysilicon layer, and at the same time, a tunnel passivation contact structure is formed on the front and back sides.

[0191] It should be understood that in other embodiments, the intrinsic amorphous silicon layer can be set in the middle layer, the lightly doped amorphous silicon layer can be set in the inner layer, and the heavily doped amorphous silicon layer can be set in the outer layer. In this way, after co-annealing treatment, an inner layer, a middle layer and an outer layer doped polysilicon layer structure can be formed. At this time, the average doping concentration of the middle layer doped polysilicon layer is the smallest, and the average doping concentration of the outer layer doped polysilicon layer is the largest.

[0192] 7. De-plating and cleaning

[0193] The silicon oxide on the first surface and the edge is removed by hydrofluoric acid using a single-sided chain device, and then the polysilicon on the edge is removed by an alkaline solution. Finally, the silicon oxide mask layers on the front and back sides are removed and RCA cleaning is performed.

[0194] 8. Preparation of anti-reflection layer

[0195] The PECVD process is used to deposit an anti-reflection layer of silicon nitride + silicon oxynitride + silicon oxide on the front and back sides respectively, and the thickness of the anti-reflection layer is 100nm.

[0196] 9. Preparation of metal electrodes

[0197] The metal layers are printed on the first area of ​​the first surface and on the second surface respectively by screen printing, and the metal layers are sintered by sintering process to form the first electrode and the second electrode in ohmic contact with the silicon substrate, and finally the battery cell is post-processed by light injection.

[0198] The above steps can be used to prepare double-sided TOPCon cells, and finally the cells are tested, sorted and stored.

[0199] Specifically, in this embodiment, the width of the first electrode and the second electrode is 5 μm to 40 μm, for example, 15 μm, and the width of the first region S11 is 45 μm to 150 μm, for example, 100 μm.

[0200] The double-sided TOPCon cell in the above embodiment adopts a Poly-finger structure with local passivated contacts, which ensures contact passivation in the first area and reduces parasitic absorption in the second area. Compared with the single-sided TOPCon cell in the prior art, it can greatly improve the cell efficiency, and the preparation process is simple and suitable for mass production.

[0201] By using the PECVD process to deposit the tunneling layer and the doped amorphous silicon layer twice, the thickness of the polysilicon layer can be precisely controlled, and the process for preparing the Poly-finger structure of local passivation contact is more controllable and the process is simpler.

[0202] The middle barrier layer can easily penetrate through the first doped layer below to form hole transmission; in addition, the second doped layer is relatively thin, and the electrode slurry can easily penetrate the barrier layer during sintering, without affecting carrier transmission; the first tunneling layer uses an intrinsic amorphous silicon layer as a buffer layer, which can provide a certain window for the lower tunneling layer, ensuring that the lower layer can maintain a good passivation effect after the upper tunneling layer is penetrated.

[0203] In addition, the present invention does not need to adopt a high-temperature (above 1000°C) boron diffusion process, and annealing can be performed at a temperature of 900°C to 980°C. There is also no problem of corrosion of the furnace tube by borosilicate glass (boron trioxide) in the boron diffusion process, which greatly improves the service life of the furnace tube and reduces the equipment maintenance cost.

[0204] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0205] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that: The solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface arranged opposite to each other, the first surface includes a first region and a second region distributed at intervals, a tunneling passivation structure is provided on the first region, a passivation structure is provided on the second region, a first electrode electrically connected to the tunneling passivation structure is also provided on the first region, and a width W of the first region is greater than a width L of the first electrode.

2. The solar cell according to claim 1, characterized in that A difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

3. The solar cell according to claim 1, characterized in that The difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or, A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

4. The solar cell according to claim 1, characterized in that The width of the first electrode is 5 μm to 40 μm; and / or, The width of the first region is 45 μm to 640 μm or 45 μm to 150 μm.

5. The solar cell according to claim 1, characterized in that: The tunneling passivation structure includes a first tunneling layer and a first doping layer sequentially stacked on the first region, and the passivation structure includes a barrier layer and a second doping layer sequentially stacked on the second region, and the first doping layer and the second doping layer have the same doping type.

6. The solar cell according to claim 5, characterized in that: The first electrode contacts the first doping layer.

7. The solar cell according to claim 5, characterized in that: The barrier layer and the second doping layer on the second region extend laterally into the first region and cover the first tunneling layer and the first doping layer.

8. The solar cell according to claim 7, characterized in that: The first electrode is in contact with the second doping layer, or the first electrode penetrates the second doping layer and the barrier layer and is in contact with the first doping layer.

9. The solar cell according to claim 5 or 7, characterized in that: The average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or, The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 and / or, The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 .

10. The solar cell according to claim 5 or 7, characterized in that: The thickness of the first doping layer is greater than the thickness of the second doping layer; and / or, The thickness of the first doping layer is 30nm to 300nm or 100nm to 200nm; and / or, The thickness of the second doping layer is 5 nm to 100 nm or 10 nm to 50 nm.

11. The solar cell according to claim 5 or 7, characterized in that: The first doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from inside to outside; and / or, The second doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside.

12. The solar cell according to claim 5 or 7, characterized in that: The first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the first tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and / or, The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

13. The solar cell according to claim 1, characterized in that A second tunneling layer and a third doping layer are sequentially stacked on the second surface of the silicon substrate. The doping type of the third doping layer is opposite to that of the first doping layer. The second electrode is in contact with the third doping layer.

14. The solar cell according to claim 13, characterized in that: The average doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~3E21cm -3 and / or, The third doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from inside to outside; and / or, The thickness of the third doping layer is 20nm to 300nm or 60nm to 150nm; and / or, The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

15. The solar cell according to claim 13, characterized in that: The silicon substrate is an N-type silicon substrate, the first doping layer and the second doping layer are P-type doped, and the third doping layer is N-type doped; and / or, A light trapping structure is formed on the first surface and / or the second surface of the silicon substrate; and / or, A first anti-reflection layer is stacked on the second doped layer; and / or, A second anti-reflection layer is stacked on the third doping layer.

16. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region distributed at intervals; Preparing a tunneling passivation structure on the first region, and preparing a passivation structure on the second region; A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, and a width L of the first electrode is smaller than a width W of the first region.

17. The preparation method according to claim 16, characterized in that: The tunnel passivation structure comprises: a first tunneling layer and a first doping layer, and the passivation structure comprises a barrier layer and a second doping layer; The preparation of the tunneling passivation structure, the passivation structure and the first electrode includes: Depositing a first tunneling layer and a first doping layer on the entire surface of the first surface; forming a patterned first mask on the first doped layer in the first region; Using an etching process and / or a texturing process to remove the first tunneling layer and the first doping layer on the second region; Cleaning and removing the first mask on the first doping layer; Preparing a barrier layer and a second doping layer stacked in sequence on the silicon substrate in the second region and on the first doping layer in the first region, wherein the doping type of the second doping layer is the same as the doping type of the first doping layer; Preparing a first electrode on a first region of the first surface, the first electrode being in contact with the second doped layer or the first doped layer; The difference between the width W of the first region and the width L of the first electrode satisfies: WL≥2X+2Y, where X is the process accuracy of forming the patterned first mask, and Y is the process accuracy of preparing the first electrode.

18. The preparation method according to claim 17, characterized in that: Forming a patterned first mask on the first doped layer in the first region includes: An inorganic mask layer is prepared on the first doping layer, and patterned by a laser window opening process to remove the inorganic mask layer on the second region, with a process accuracy X greater than or equal to 15 μm; or, An inorganic mask layer is prepared on the first doping layer, and a patterned organic mask layer is prepared on the first region by a screen printing process, with a process precision X being greater than or equal to 15 μm.

19. The preparation method according to claim 17, characterized in that: The preparation of the first electrode comprises: Printing a metal layer on the first area of ​​the first surface by a screen printing process, wherein a process accuracy Y of the screen printing is greater than or equal to 5 μm; The metal layer is sintered by a sintering process to form a first electrode in ohmic contact with the silicon substrate.

20. The preparation method according to claim 16, characterized in that: A difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

21. The preparation method according to claim 16, characterized in that: The difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or, A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

22. The preparation method according to claim 16, characterized in that: The width of the first electrode is 5 μm to 40 μm; and / or, The width of the first region is 45 μm to 640 μm or 45 μm to 150 μm.

23. The preparation method according to claim 17, characterized in that: The average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or, The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 and / or, The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 .

24. The preparation method according to claim 17, characterized in that: The thickness of the first doping layer is greater than the thickness of the second doping layer; and / or, The thickness of the first doping layer is 30nm to 300nm or 100nm to 200nm; and / or, The thickness of the second doping layer is 5 nm to 100 nm or 10 nm to 50 nm.

25. The preparation method according to claim 17, characterized in that: The preparation method further comprises: Prepare a second tunneling layer and a third doping layer stacked in sequence on the second surface, wherein the doping type of the third doping layer is opposite to that of the first doping layer; A second electrode in contact with the third doping layer is prepared on the second surface.

26. The preparation method according to claim 25, characterized in that: The preparation of the second electrode comprises: Printing a metal layer on the second surface by screen printing; The metal layer is sintered by a sintering process to form a second electrode in ohmic contact with the silicon substrate.

27. The preparation method according to claim 25, characterized in that: The first doped layer, the second doped layer and the third doped layer all include doped amorphous silicon layers, and the preparation method further includes: The first doped layer, the second doped layer and the third doped layer are annealed at a temperature of 900° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

28. The preparation method according to claim 27, characterized in that: The preparation method further comprises: Preparing a second mask on the second doped layer to remove silicon oxide and amorphous silicon deposited on the surface and around the edge; Preparing a third mask on the third doped layer to remove silicon oxide and polysilicon plated on the surface and around the edge; The second mask and the third mask are removed and cleaned.

29. The preparation method according to claim 16, characterized in that: The preparation method further comprises: The light trapping structure is prepared on the first surface and / or the second surface of the silicon substrate by a texturing process; and / or, Prepare a first anti-reflection layer on the first surface of the silicon substrate; and / or, A second anti-reflection layer is prepared on the second surface of the silicon substrate.

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