Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate; the first doped semiconductor layer is arranged on the first surface of the semiconductor substrate; the passivation layer is located on the side, away from the semiconductor substrate, of the first doped semiconductor layer, and the passivation layer is provided with a plurality of open holes exposing the first doped semiconductor layer; the first grid line extends in the first direction and is arranged on the passivation layer, and the first grid line penetrates through the open hole and is electrically connected with the first doped semiconductor layer; the plurality of holes comprise a first hole closest to the first edge, the distance between the edge of the first hole and the first edge is d1, and the d1 is larger than or equal to 150 micrometers and larger than or equal to 1000 micrometers. Therefore, the first doped semiconductor layer can be prevented from being damaged and blackened, the passivation effect of the first doped semiconductor layer is improved, carriers collected in the edge area of the first doped semiconductor layer can be timely led out through the first grid line, and the photoelectric conversion efficiency of the whole solar cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] During the manufacturing process, the passivation layer of the solar cell generally needs to be grooved to expose the doped semiconductor layer, so that the electrode paste can directly contact the doped semiconductor layer through the grooved area, thereby achieving electrical connection to form a grid line structure. However, in the EL or PL test of the cell, we found that the passivation effect of the edge area of ​​the cell was poor. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module to reduce the damage and blackening of the doped semiconductor layer in the edge area of ​​the cell and improve the passivation effect of the edge area of ​​the cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] A first doped semiconductor layer, disposed on a first surface of the semiconductor substrate;

[0009] a passivation layer, the passivation layer being located on a side of the first doped semiconductor layer away from the semiconductor substrate, the passivation layer having a plurality of openings exposing the first doped semiconductor layer;

[0010] A first gate line extending along a first direction and disposed on the passivation layer, wherein the first gate line passes through the opening and is electrically connected to the first doped semiconductor layer;

[0011] Wherein, along the first direction, the semiconductor substrate includes a first edge and a second edge arranged opposite to each other, the plurality of openings include a first opening closest to the first edge, and the distance between the edges of the first opening and the first edge is d1, 1000 μm ≥ d1 ≥ 150 μm.

[0012] By adopting the above technical solution, along the first direction, the distance between the first opening and the first edge of the semiconductor substrate is greater than or equal to 150 μm, that is, a sufficient distance is reserved between the first opening and the first edge of the semiconductor substrate, and it is also ensured that all the openings along the first direction are sufficiently far away from the edge of the semiconductor substrate, thereby avoiding opening the passivation layer in the edge region where the first doped semiconductor layer is thinner, preventing the opening from causing the first doped semiconductor layer to be damaged and blackened, thereby improving the passivation effect of the edge region where the first doped semiconductor layer is thinner; and, the distance between the first opening and the first edge of the semiconductor substrate is less than or equal to 1000 μm, preventing the distance between the first opening and the first edge of the semiconductor substrate from being too large, thereby avoiding the situation where the carriers collected in the edge region of the first doped semiconductor layer cannot be timely guided out through the first gate line. As can be seen from the above, in the present application, making d1 within a reasonable range of 150 μm to 1000 μm can not only prevent the first doped semiconductor layer from being damaged and blackened, improve the passivation effect of the first doped semiconductor layer, but also ensure that the carriers collected in the edge region of the first doped semiconductor layer are timely guided out through the first gate line, thereby improving the photoelectric conversion efficiency of the entire solar cell.

[0013] In one implementation, along the first direction, a distance between an edge of the first opening and an edge of the first doped semiconductor layer is d2;

[0014] The first doped semiconductor layer and the semiconductor substrate have the same doping type, d1-d2≤20 μm; or, the first doped semiconductor layer and the semiconductor substrate have opposite doping types, 50 μm≤d2≤550 μm.

[0015] In an implementation manner, along the first direction, a distance between an edge of the first opening and an edge of the first gate line is d3, and 50 μm≤d3≤500 μm.

[0016] In one implementation, the opening closest to the edge of the first doped semiconductor layer along a second direction is a second opening, and the second direction intersects with the first direction;

[0017] Along the second direction, a distance between an edge of the second opening and an edge of the first doped semiconductor layer is S, and 50 μm≤S≤550 μm.

[0018] In one implementation, the passivation layer has a heat-affected zone surrounding the opening, and the width of the heat-affected zone is W; 1 μm≤W≤5 μm, or S>W.

[0019] In one implementation, the heat affected zone includes a plurality of holes, the holes are filled with a conductive material, and the conductive material is electrically connected to the first doped semiconductor layer.

[0020] In an implementation manner, a seed layer is further disposed between the first gate line and the doped semiconductor layer, the seed layer fills the plurality of openings, and the first gate line covers the seed layer and a side of the conductive material facing away from the semiconductor substrate.

[0021] In one implementation, the orthographic projections of the heat-affected zones surrounding two adjacent openings on the first surface do not overlap.

[0022] In one implementation, the orthographic projections of the plurality of openings on the first surface are located inside the orthographic projection of the first grid line on the first surface; or, part or all of the orthographic projections of the first openings on the first surface are located outside the orthographic projection of the first grid line on the first surface.

[0023] In one implementation, the plurality of openings are arranged in at least one row along the first direction.

[0024] In one implementation, the first doped semiconductor layer is in the shape of a strip extending along a first direction, and a plurality of the first doped semiconductor layers are arranged at intervals along a second direction; or, the entire first doped semiconductor layer is disposed on the first surface.

[0025] In one implementation, the solar cell further includes a second doped semiconductor layer, the conductivity type of the second doped semiconductor layer being opposite to that of the first doped semiconductor layer;

[0026] The second doped semiconductor layer covers at least a portion of the second surface of the semiconductor substrate; or, the second doped semiconductor layer covers at least a portion of the first surface of the semiconductor substrate, and the first doped semiconductor layer and the second doped semiconductor layer are arranged at intervals along the second direction.

[0027] In one implementation, the first doped semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first doped semiconductor layer close to the semiconductor substrate;

[0028] The second doped semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on a side of the second doped semiconductor layer close to the semiconductor substrate.

[0029] A photovoltaic assembly comprises the solar cell described in any one of the above.

[0030] Compared with the prior art, the beneficial effects of the photovoltaic module provided in the present application are the same as the beneficial effects of the above-mentioned solar cells, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0032] Figure 1 A top view of a solar cell provided in an embodiment of the present application;

[0033] Figure 2 for Figure 1 A partial cross-sectional view along the middle line A1-A2;

[0034] Figure 3 A partial cross-sectional view of another solar cell is provided for an embodiment of the present application;

[0035] Figure 4 A partial cross-sectional view of another solar cell is provided for an embodiment of the present application;

[0036] Figure 5 A partial cross-sectional view of a solar cell along its thickness direction is provided for an embodiment of the present application;

[0037] Figure 6 A local SEM image of a solar cell is provided for the embodiment of the present application;

[0038] Figure 7 A top view of another solar cell provided in an embodiment of the present application.

[0039] Reference numerals:

[0040] 1-semiconductor substrate, 1a-first edge, 2-first doped semiconductor layer, 3-first opening, 4-first gate line, 4a-seed layer, 5-heat affected zone, 6-first interface layer, 7-passivation layer, 8-conductive material, 9-second doped semiconductor layer. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0042] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0044] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0045] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] In the process of manufacturing solar cells, the passivation layer 7 of the solar cell generally needs to be grooved to expose the doped semiconductor layer, so that the electrode paste can directly contact the doped semiconductor layer through the grooved area, thereby achieving electrical connection to form a grid line structure. However, in the EL or PL test of the cell, we found that the passivation effect of the edge area of ​​the cell is poor.

[0047] In view of the above situation, the applicant has found through research that since the edge of the doped semiconductor layer is thin, opening holes in the passivation layer 7 outside the thinner doped semiconductor layer will cause the doped semiconductor layer to be damaged and blackened, reducing the passivation effect and further affecting the photoelectric conversion efficiency of the entire solar cell.

[0048] In order to reduce the damage and blackening of the doped semiconductor layer at the edge of the cell and improve the passivation effect of the edge of the cell, the present application provides a solar cell, which includes a semiconductor substrate 1, a first doped semiconductor layer 2, a passivation layer 7 and a first gate line 4.

[0049] The semiconductor substrate 1 has a first surface and a second surface opposite to each other, that is, the two surfaces opposite to each other along the thickness direction of the semiconductor substrate 1 are the first surface and the second surface respectively. The first surface may correspond to the backlight side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell; or the first surface may correspond to the light-facing side of the solar cell, and the second surface may correspond to the backlight side of the solar cell.

[0050] The first doped semiconductor layer 2 is disposed on the first surface of the semiconductor substrate 1. Specifically, the first doped semiconductor layer 2 may be disposed entirely on the first surface, or may be disposed partially on the first surface, for example Figure 1 As shown, the first doped semiconductor layer 2 is arranged on the first surface in a strip shape. In addition, the first doped semiconductor layer 2 can be additionally formed on the semiconductor substrate 1 by deposition technology, or formed in the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0051] The passivation layer 7 is located on the side of the first doped semiconductor layer 2 away from the semiconductor substrate 1, and the passivation layer 7 has a plurality of openings exposing the first doped semiconductor layer 2. The passivation layer 7 can passivate the surface of the doped semiconductor layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the solar cell. The material of the passivation layer 7 may include one or more of silicon nitride, silicon oxynitride, and silicon oxide. In addition, the passivation layer 7 may be a single-layer structure or a multi-layer structure. As for the thickness of the passivation layer 7, it only needs to meet the passivation effect and ensure the contact performance between the gate line and the doped semiconductor layer.

[0052] The first gate line 4 extends along the first direction, that is, the length of the first gate line 4 is arranged along the first direction. The first gate line 4 is arranged on the passivation layer 7, that is, the first gate line 4 is arranged on the side of the passivation layer 7 away from the semiconductor substrate 1, and the first gate line 4 is partially passed through the opening and electrically connected to the first doped semiconductor layer 2, so as to use the first gate line 4 to derive the carriers collected by the first doped semiconductor layer 2. The first gate line 4 is formed by a non-burn-through type slurry, and the non-burn-through type slurry can include one or more of low-temperature silver paste, copper paste, and aluminum paste. The first gate line 4 can be formed by screen printing, electroplating, sputtering or evaporation, etc., corresponding to the opening area. The non-burn-through type slurry refers to a slurry that cannot directly penetrate the passivation layer 7 by sintering to achieve contact with the first doped semiconductor layer 2. Generally speaking, the first gate line 4 formed by the non-burn-through type slurry finally retains an adhesive material, such as an organic component.

[0053] Along the first direction, the semiconductor substrate 1 includes a first edge 1a and a second edge that are arranged opposite to each other, that is, the first edge 1a and the second edge are arranged along the first direction, and the first edge 1a and the second edge both intersect with the first direction. Among the multiple openings of the passivation layer 7, the opening closest to the first edge 1a is the first opening 3. Figure 2As shown, the distance between the edge of the first opening 3 and the first edge 1 a is d1, and 1000 μm ≥ d1 ≥ 150 μm.

[0054] By adopting the above technical solution, along the first direction, the distance between the first opening 3 and the first edge 1a of the semiconductor substrate 1 is greater than or equal to 150μm, that is, sufficient distance is reserved between the first opening 3 and the first edge 1a of the semiconductor substrate 1, and it is also ensured that sufficient distance is reserved between all the openings along the first direction and the edge of the semiconductor substrate 1, thereby avoiding opening holes in the passivation layer 7 in the thinner edge area of ​​the first doped semiconductor layer 2, preventing the opening from causing the first doped semiconductor layer 2 to be damaged and blackened, thereby improving the passivation effect of the thinner edge area of ​​the first doped semiconductor layer 2; and, the distance between the first opening 3 and the first edge 1a of the semiconductor substrate 1 is less than or equal to 1000μm, preventing the distance between the first opening 3 and the first edge 1a of the semiconductor substrate 1 from being too large, thereby avoiding the situation where the carriers collected in the edge area of ​​the first doped semiconductor layer 2 cannot be promptly exported through the first gate line 4. As can be seen from the above, in the present application, making d1 within a reasonable range of 150μm to 1000μm can not only prevent the first doped semiconductor layer 2 from being damaged and blackened, thereby improving the passivation effect of the first doped semiconductor layer 2, but also ensure that the carriers collected in the edge area of ​​the first doped semiconductor layer 2 are promptly exported through the first gate line 4, thereby improving the photoelectric conversion efficiency of the entire solar cell.

[0055] Illustratively, d1 may be 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1000 μm, etc.

[0056] In some embodiments, Figure 2 As shown, along the first direction, the distance between the edge of the first opening 3 and the edge of the first doped semiconductor layer 2 is d2, wherein d1-d2≤20 μm; or, 50 μm≤d2≤550 μm.

[0057] In some embodiments, the first doped semiconductor layer 2 has the same doping type as the semiconductor substrate 1, so there is no need to worry about the first doped semiconductor layer 2 and the semiconductor substrate 1 being recombined. Therefore, in the process of depositing the first doped semiconductor layer 2, the distance between the two side edges of the first doped semiconductor layer 2 opposite to each other along the first direction and the edge of the semiconductor substrate 1 can be made smaller or overlapped. Specifically, d1-d2≤20μm, so that the area of ​​the first doped semiconductor layer 2 is larger, thereby improving the carrier collection efficiency of the first doped semiconductor layer 2. Exemplarily, d1-d2 can be 20μm, 18μm, 15μm, 12μm, 10μm, 8μm, 6μm, 5μm, 3μm, 1μm or 0, etc.

[0058] In other embodiments, the doping types of the first doped semiconductor layer 2 and the semiconductor substrate 1 are opposite. At this time, if the distance between the edge of the first doped semiconductor layer 2 and the edge of the semiconductor substrate 1 is small or overlapped, it is easy to cause the first doped semiconductor layer 2 and the semiconductor substrate 1 to have a recombination loss. Therefore, in the process of depositing the first doped semiconductor layer 2, a certain distance is provided between the edges of the first doped semiconductor layer 2 on both sides opposite to each other along the first direction and the edge of the semiconductor substrate 1 to prevent the first doped semiconductor layer 2 from recombination with the side of the semiconductor substrate 1, resulting in leakage. Based on this, 50μm≤d2≤550μm, along the first direction, ensure that the distance d2 between the first opening 3 and the edge of the first doped semiconductor layer 2 is within a reasonable range, which not only reduces the recombination loss and the risk of leakage, but also prevents the first doped semiconductor layer 2 from being damaged and blackened, thereby improving the passivation effect of the first doped semiconductor layer 2. It can be understood that in this technical solution, the solar cell can be a back contact cell, the first doped semiconductor layer 2 and the second doped semiconductor layer 9 are both located on the first surface, and the first doped semiconductor layer 2 and the second doped semiconductor layer 9 are arranged at intervals along the second direction.

[0059] For example, d2 can be 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm , 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm or 550μm, etc.

[0060] In some embodiments, Figure 2As shown, along the first direction, the distance between the edge of the first opening 3 and the edge of the first grid line 4 is d3. If d3 is too large, the distance of the first grid line 4 beyond the first opening 3 is too large, resulting in waste of the raw materials of the first grid line 4; if d3 is too small, the deviation in the laser opening process and the deviation caused by printing the first grid line 4 may cause the first grid line 4 to fail to cover the first opening 3, thereby affecting the carrier extraction efficiency. In view of the above situation, in this application, 50μm≤d3≤500μm is used to prevent the waste of the raw materials of the first grid line 4, and at the same time prevent the processing deviation from causing the first grid line 4 to fail to cover the first opening 3, thereby ensuring the carrier extraction efficiency.

[0061] For example, d3 can be 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm , 280μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm or 500μm, etc.

[0062] In other embodiments, Figure 2 and Figure 4 As shown, the opening closest to the edge of the first doped semiconductor layer 2 along the second direction is the second opening. The second direction intersects with the first direction, and the optional first direction and second direction are perpendicular to each other. Along the second direction, the distance between the edge of the second opening and the edge of the first doped semiconductor layer 2 is S. If S is too small, it may cause the first gate line 4 to exceed the first doped semiconductor layer 2 and cause leakage. If S is too large, it may affect the extraction efficiency of the carriers collected at the edge of the first doped semiconductor layer 2. Based on this, in this technical solution, 50μm≤S≤550μm is used to ensure the extraction efficiency of the edge carriers of the first doped semiconductor layer 2 while reducing the risk of leakage.

[0063] For example, S can be 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm or 550μm, etc.

[0064] In some embodiments, Figure 2 and Figure 3As shown, the passivation layer 7 has a heat-affected zone 5 surrounding the opening. Specifically, in the process of slotting the passivation layer 7 using a laser process, the area near the edge of the opening is not removed, but it is affected by the heat of the laser and is called the heat-affected zone 5. The heat-affected zone 5 is formed around the opening. The shape of the opening can be circular, elliptical, rectangular or other shapes, and the surrounding shape of the heat-affected zone 5 also changes with the shape of the opening, and its annular shape can be a circular ring, an elliptical ring or a rectangular ring, etc.

[0065] In some embodiments, the width of the heat affected zone 5 is W, 1 μm ≤ W ≤ 5 μm, so as to avoid the heat affected zone 5 being too wide and reducing the passivation effect. For example, W can be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0066] In addition, in order to prevent the heat-affected zone 5 from reaching the edge of the first doped semiconductor layer 2 and affecting the collection of carriers, S>W in this technical solution, while also preventing the heat-affected zone 5 from covering the edge of the first doped semiconductor layer 2, thereby ensuring the passivation effect of the edge of the first doped semiconductor layer 2.

[0067] In some embodiments, Figure 5 and Figure 6 As shown, during the laser hole opening process, the laser energy at the edge position is appropriately increased, for example, greater than 200 J / cm 2 , the passivation layer material of the heat-affected zone 5 will be opened to form a plurality of holes. The purpose of such a setting is that if no holes are formed in the heat-affected zone 5, the thermal damage of the first doped semiconductor layer 2 corresponding to the position of the heat-affected zone cannot be repaired, and in this embodiment, the hole is filled with a conductive material 8, and the conductive material 8 is electrically connected to the first doped semiconductor layer 2. In such a setting, the first gate line 4 can be electrically connected to the first doped semiconductor layer 2 through the conductive material 8 while passing through the opening to be electrically connected to the first doped semiconductor layer 2, and the first doped semiconductor layer 2 at the position corresponding to the hole is also a heat concentration area with greater damage (holes are easily generated in the heat concentration area), and the conductive material 8 can repair the damage at this position. The conductive material 8 is distributed in the heat-affected zone 5 in a granular form, and the granular conductive material 8 at the position farthest from the center of the opening defines the width W of the heat-affected zone 5.

[0068] The conductive material 8 may be one or more materials selected from titanium, copper, silver, aluminum, tungsten, nickel and the like, and is preferably formed by electroplating or chemical plating.

[0069] In some embodiments, Figure 5As shown, a seed layer 4a is further provided between the first grid line 4 and the doped semiconductor layer, the seed layer 4a is filled in a plurality of openings, and the first grid line 4 covers the seed layer 4a and the side of the conductive material 8 away from the semiconductor substrate 1. In this technical solution, the seed layer 4a can achieve a good electrical connection effect between the first grid line 4 and the first doped semiconductor layer 2, and can prevent the metal elements in the first grid line 4 thereon from diffusing into the semiconductor substrate 1, which can reduce recombination. At the same time, the first grid line 4 has more options, and some metals (such as base metal materials, copper or aluminum, etc.) with mature technology and low price can be selected to replace silver, which can reduce the cost of the electrode, and then reduce the cost of the solar cell.

[0070] In some embodiments, Figure 2 and Figure 3 As shown, the orthographic projections of the heat-affected zones 5 surrounding two adjacent openings on the first surface do not overlap, that is, the heat-affected zones 5 of the two adjacent openings are not arranged to overlap. This arrangement can prevent the heat-affected zones 5 of the two adjacent openings from having too much influence on the first doped semiconductor layer 2, thereby affecting the collection of carriers.

[0071] In some embodiments, Figure 2 As shown, the orthographic projections of the plurality of openings on the first surface are located inside the orthographic projections of the first grid lines 4 on the first surface, that is, the plurality of openings are all covered by the first grid lines 4, thereby improving the conductive efficiency of the first grid lines 4.

[0072] In another embodiment, Figure 3 As shown, part or all of the orthographic projection of the first opening 3 on the first surface is located outside the orthographic projection of the first grid line 4 on the first surface. In other words, the first grid line 4 can cover part of the opening closest to the first edge 1a, or the first grid line 4 does not cover the opening closest to the first edge 1a. With this technical solution, the extension distance of the first grid line 4 along the first direction can be adjusted according to actual conditions, without being restricted by the position of the first opening 3, thereby reducing the processing difficulty of the first grid line 4 and improving the processing efficiency.

[0073] In some embodiments, the plurality of openings are arranged in at least one row along the first direction. Figure 3 As shown, the plurality of openings may be distributed in a row and arranged sequentially along the first direction. Figure 4 As shown, the plurality of openings may be distributed in multiple rows and each row of openings may be arranged sequentially along the first direction. For example, the plurality of openings may also be distributed in two rows, three rows or more rows. In this way, the plurality of openings are distributed more evenly, and the positions where the first gate line 4 is electrically connected to the first doped semiconductor layer 2 are distributed more evenly, which is beneficial for the first gate line 4 to timely conduct the current at each position of the first doped semiconductor layer 2 to avoid local overheating.

[0074] In the actual application process, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0075] Exemplarily, the semiconductor substrate 1 may be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0076] In some embodiments, the first doped semiconductor layer 2 may be partially or entirely disposed on the first surface. In the case where the first doped semiconductor layer 2 is partially disposed on the first surface, the first doped semiconductor layer 2 may be distributed in a strip shape, and the strip-shaped first doped semiconductor layer 2 extends along the first direction, and a plurality of first doped semiconductor layers 2 are arranged at intervals along the second direction.

[0077] The solar cell further includes a second doped semiconductor layer 9, which has a conductivity type opposite to that of the first doped semiconductor layer 2, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. A second gate line is arranged on a side of the second doped semiconductor layer 9 away from the semiconductor substrate 1, so as to conduct the carriers collected by the second doped semiconductor layer 9 by means of the second gate line.

[0078] The solar cell may be a back contact cell or a bifacial cell. When the solar cell is a back contact cell, the back contact cell may be a TBC (Tunnel Oxide Passivated Contact Back Contact) or a HPBC (Hybrid Passivated Back Contact), etc.; when the solar cell is a bifacial solar cell, the bifacial solar cell may be a PREC (Passivated Emitter Rear Cell) solar cell or a TOPCon (Tunnel Oxide Passivated Contact) solar cell, etc. Of course, the solar cell may also be a single-sided hybrid cell or a bifacial hybrid cell.

[0079] In the case where the solar cell is a bifacial cell, the second doped semiconductor layer covers at least a portion of the second surface of the semiconductor substrate 1. Figure 7As shown, in the case where the solar cell is a back contact cell, the second doped semiconductor layer 9 covers at least a portion of the first surface of the semiconductor substrate 1, and the first doped semiconductor layer 2 and the second doped semiconductor layer 9 are arranged at intervals along the second direction. Specifically, the second doped semiconductor layer 9 and the first doped semiconductor layer 2 can be arranged alternately at intervals in a strip shape, or can be arranged alternately at intervals in an interdigitated shape.

[0080] Specifically, the first doped semiconductor layer 2 includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer 2 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. Of course, the first doped semiconductor layer 2 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped semiconductor layer 9 also includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0081] In some embodiments, a first interface layer 6 is provided between the first doped semiconductor layer 2 and the semiconductor substrate 1, and a second interface layer is provided between the second doped semiconductor layer 9 and the semiconductor substrate 1. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the area where the semiconductor layer is formed on the surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 6 can be set according to the material of the first doped semiconductor layer 2 and actual needs, and the material and thickness of the second interface layer can be set according to the material of the second doped semiconductor layer 9 and actual needs, and are not specifically limited here.

[0082] For example, the first doped semiconductor layer 2 may be a doped polysilicon layer, and the first interface layer 6 may be a tunneling oxide layer. The second doped semiconductor layer 9 may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0083] Of course, when the first doped semiconductor layer 2 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 6 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon. When the second doped semiconductor layer 9 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon.

[0084] The materials of the first doped semiconductor layer 2 and the second doped semiconductor layer 9 may be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. In terms of conductivity type, the first doped semiconductor layer 2 may be an n-type doped layer, and the second doped semiconductor layer 9 may be a p-type doped layer; or, the first doped semiconductor layer 2 may be a p-type doped layer, and the second doped semiconductor layer 9 may be an n-type doped layer.

[0085] The embodiment of the present application also provides a photovoltaic module, which includes the solar cell provided by any of the above embodiments. Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above solar cell, which will not be described in detail here.

[0086] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0087] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A first doped semiconductor layer, disposed on a first surface of the semiconductor substrate; a passivation layer, the passivation layer being located on a side of the first doped semiconductor layer away from the semiconductor substrate, the passivation layer having a plurality of openings exposing the first doped semiconductor layer; A first gate line extending along a first direction and disposed on the passivation layer, wherein the first gate line passes through the opening and is electrically connected to the first doped semiconductor layer; Wherein, along the first direction, the semiconductor substrate includes a first edge and a second edge arranged opposite to each other, the plurality of openings include a first opening closest to the first edge, and the distance between the edges of the first opening and the first edge is d1, 1000 μm ≥ d1 ≥ 150 μm.

2. The solar cell according to claim 1, characterized in that Along the first direction, the distance between the edge of the first opening and the edge of the first doped semiconductor layer is d2; The first doped semiconductor layer and the semiconductor substrate have the same doping type, d1-d2≤20 μm; or, the first doped semiconductor layer and the semiconductor substrate have opposite doping types, 50 μm≤d2≤550 μm.

3. The solar cell according to claim 1, characterized in that Along the first direction, a distance between an edge of the first opening and an edge of the first gate line is d3, and 50 μm≤d3≤500 μm.

4. The solar cell according to claim 1, characterized in that The opening closest to the edge of the first doped semiconductor layer along a second direction is a second opening, and the second direction intersects with the first direction; Along the second direction, a distance between an edge of the second opening and an edge of the first doped semiconductor layer is S, and 50 μm≤S≤550 μm.

5. The solar cell according to claim 4, characterized in that: The passivation layer has a heat-affected zone surrounding the opening, and the width of the heat-affected zone is W; 1 μm≤W≤5 μm, or S>W.

6. The solar cell according to claim 5, characterized in that: The heat affected zone includes a plurality of holes, the holes are filled with a conductive material, and the conductive material is electrically connected to the first doped semiconductor layer.

7. The solar cell according to claim 6, characterized in that: A seed layer is further arranged between the first gate line and the doped semiconductor layer. The seed layer fills the plurality of openings. The first gate line covers the seed layer and a side of the conductive material facing away from the semiconductor substrate.

8. The solar cell according to claim 5, characterized in that: The orthographic projections of the heat-affected zones surrounding two adjacent openings on the first surface do not overlap.

9. The solar cell according to claim 1, characterized in that: The orthographic projections of the plurality of openings on the first surface are located inside the orthographic projection of the first grid line on the first surface; or part or all of the orthographic projections of the first openings on the first surface are located outside the orthographic projection of the first grid line on the first surface.

10. The solar cell according to any one of claims 1 to 9, characterized in that: The plurality of openings are arranged in at least one row along the first direction.

11. The solar cell according to any one of claims 1 to 9, characterized in that: The first doped semiconductor layer is in a strip shape extending along the first direction, and a plurality of the first doped semiconductor layers are arranged at intervals along the second direction; or, the first doped semiconductor layer is entirely disposed on the first surface.

12. The solar cell according to any one of claims 1 to 9, characterized in that: The solar cell further comprises a second doped semiconductor layer, the conductivity type of the second doped semiconductor layer being opposite to that of the first doped semiconductor layer; The second doped semiconductor layer covers at least a portion of the second surface of the semiconductor substrate; Alternatively, the second doped semiconductor layer covers at least a portion of the first surface of the semiconductor substrate, and the first doped semiconductor layer and the second doped semiconductor layer are arranged at intervals along the second direction.

13. The solar cell according to claim 12, characterized in that: The first doped semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first doped semiconductor layer close to the semiconductor substrate; The second doped semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on a side of the second doped semiconductor layer close to the semiconductor substrate.

14. A photovoltaic module, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 13.

Images