Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and the solar cell comprises a silicon substrate which is provided with a light receiving surface and a backlight surface which are oppositely disposed, and the light receiving surface is provided with a first region and a second region; the first tunneling layer is arranged in the first region; the first doping layer is located on the side, away from the silicon substrate, of the first tunneling layer, and the doping type of the first doping layer is consistent with that of the silicon substrate; the second tunneling layer is positioned on the backlight surface; the second doping layer is located on the surface of the side, away from the silicon substrate, of the second tunneling layer, and the doping type of the second doping layer is opposite to that of the silicon substrate; the first electrode is in contact with the first doping layer; and the second electrode is in contact with the second doping layer. The passivation contact structures are adopted on the two sides, compared with a structure with a boron diffusion layer on the front side in a traditional TOPCon battery, the passivation effect on the two sides is good, metal contact of a grid line area can be improved, and J0 under metal is reduced.

Description

Technical Field

[0001] The present invention relates to the photovoltaic field, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Currently, TOPCon batteries have become mainstream products. Their structure determines that silver paste is used for both the front and back electrodes, and high-temperature sintering at 850℃ to 900℃ is required. The cost is high, and the high-temperature sintering process will cause damage and deformation of the silicon substrate, resulting in a high warping rate, which is not conducive to the development of thin-film production.

[0003] In view of this, it is necessary to provide an improved solar cell and a preparation method thereof to solve the above technical problems. Summary of the invention

[0004] The present invention provides a solar cell and a preparation method thereof, which reduces damage to the battery and lowers the battery cost by optimizing the battery structure and the preparation process.

[0005] In order to achieve one of the above-mentioned invention objects, the present invention adopts the following technical solution:

[0006] A solar cell comprises: a silicon substrate, the silicon substrate having a light-receiving surface and a light-receiving surface arranged opposite to each other, the light-receiving surface having a first area and a second area; a first tunneling layer, the first tunneling layer being arranged in the first area; a first doping layer, the first doping layer being located on a side of the first tunneling layer away from the silicon substrate; a second tunneling layer, the second tunneling layer being located on the light-receiving surface; a second doping layer, the second doping layer being located on a side of the second tunneling layer away from the silicon substrate; a first electrode, the first electrode being in contact with the first doping layer; and a second electrode, the second electrode being in contact with the second doping layer.

[0007] In one embodiment, the first area is a non-textured area, and the second area is a texturized area; and / or the first area is a gate line area, and the second area is a non-gate line area.

[0008] In one embodiment, the solar cell further includes a first passivation layer located on the side where the light receiving surface is located, the first passivation layer contacts the first doped layer in the first region, and the first passivation layer is an aluminum oxide layer; and / or the solar cell further includes a second passivation layer located on the side of the second doped layer away from the second tunneling layer, and the second passivation layer is an aluminum oxide layer.

[0009] In one embodiment, the solar cell further includes a first passivation / anti-reflection layer located on the side where the light-receiving surface of the solar cell is located, the first passivation / anti-reflection layer contacts the first doped layer in the first region, the first passivation / anti-reflection layer contacts the silicon substrate in the second region, the first passivation / anti-reflection layer has a first groove located in the first region, and the first electrode is located in the first groove; and / or, the solar cell further includes a second passivation / anti-reflection layer located on a surface of the second doped layer on a side away from the second tunneling layer, the second passivation / anti-reflection layer has a second groove, and the second electrode is located in the second groove.

[0010] In one embodiment, the first passivation / antireflection layer has a first groove, the width of the first groove is 1 / 4 to 1 / 15 of the width of the first zone; and / or the width of the first zone is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

[0011] In one embodiment, the first passivation / anti-reflection layer has a first groove, the first doped layer has a first groove corresponding to the first groove, and the first electrode is located in the first groove and the first groove; and / or, the second passivation / anti-reflection layer has a second groove, the second doped layer has a second groove corresponding to the second groove, and the second electrode is located in the second groove and the second groove.

[0012] In one embodiment, the depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm; and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the first doped layer outside the first groove; and / or the thickness of the first doped layer at the location of the first groove is 30nm-150nm; and / or the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped layer outside the second groove, and / or the thickness of the second doped layer at the second groove is 30nm-395nm.

[0013] In one embodiment, the first electrode is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating; and / or the second electrode is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating.

[0014] In one embodiment, the silicon substrate is an N-type silicon wafer, and the first doped layer is an N-type doped polysilicon layer with a doping concentration of 1E20 cm -3 ~1E21cm -3, and / or the thickness is 35nm to 200nm; and / or the second doped layer is a P-type doped polysilicon layer with a doping concentration of 1E19cm -3 ~1E20cm -3 , and / or a thickness of 80nm to 400nm.

[0015] A method for preparing a solar cell comprises the following steps: providing a silicon substrate, the silicon substrate having a light-receiving surface and a light-receiving surface arranged opposite to each other, the light-receiving surface having a first region and a second region; forming a first tunneling layer on the light-receiving surface of the silicon substrate; forming a first doped amorphous silicon layer on a side of the first tunneling layer away from the silicon substrate; forming a second tunneling layer on a light-receiving surface of the silicon substrate; forming a second doped amorphous silicon layer on a side of the second tunneling layer away from the silicon substrate; annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polycrystalline silicon layer, and the second doped amorphous silicon layer is transformed into a second doped polycrystalline silicon layer; removing the first doped polycrystalline silicon layer located in the second region; forming a first electrode in contact with the first doped polycrystalline silicon layer in the first region, and forming a second electrode in contact with the second doped polycrystalline silicon layer on the light-receiving surface.

[0016] In one embodiment, the light-receiving surface and the backlight surface of the silicon substrate are both light surface structures; or the silicon substrate is polished before forming the first tunneling layer and the second tunneling layer.

[0017] In one embodiment, the second tunneling layer is first formed on the backlight surface, the second doped amorphous silicon layer is formed on the side of the second tunneling layer away from the silicon substrate, and the second mask layer is formed on the side of the second doped amorphous silicon layer away from the second tunneling layer; after removing the film layer coated on the light-receiving surface, the first tunneling layer is formed on the light-receiving surface, the first doped amorphous silicon layer is formed on the side of the first tunneling layer away from the silicon substrate, and the first mask layer is formed on the side of the first doped amorphous silicon layer away from the first tunneling layer; annealing is performed, and the first doped amorphous silicon layer is transformed into a first doped polycrystalline silicon layer, and the second doped amorphous silicon layer is transformed into a second doped polycrystalline silicon layer; after annealing, the first mask layer located in the second area is removed to expose the first doped polycrystalline silicon layer; the film layer coated on the backlight surface and the first doped polycrystalline silicon layer located in the second area are removed, and a velvet structure is formed in the second area; the first electrode in contact with the first doped polycrystalline silicon layer is formed in the first area, and the second electrode in contact with the second doped polycrystalline silicon layer is formed on the backlight surface.

[0018] In one embodiment, the method for preparing the solar cell further includes the following steps: before preparing the first electrode, forming a first passivation / anti-reflection layer on the side where the light receiving surface is located, the first passivation / anti-reflection layer contacts the first doped layer in the first region, the first passivation / anti-reflection layer contacts the silicon substrate in the second region, and a first groove is formed in the first passivation / anti-reflection layer in the first region by a laser grooving process; the first electrode is formed in the first groove; and / or before preparing the second electrode, forming a second passivation / anti-reflection layer on a side of the second doped polysilicon layer away from the second tunneling layer, and a second groove is formed in the gate line region of the second passivation / anti-reflection layer by a laser grooving process; the second electrode is formed in the second groove.

[0019] In one embodiment, the width of the first slot is 1 / 4 to 1 / 15 of the width of the first zone; and / or,

[0020] The width of the first region is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

[0021] In one embodiment, before forming the first electrode, a first passivation / anti-reflection layer is formed, a first groove is formed in the first passivation / anti-reflection layer by a laser grooving process, and a first groove corresponding to the first groove is formed on the first doped polysilicon layer; the depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness d2 of the first doped polysilicon layer outside the first groove; and / or the thickness of the first doped polysilicon layer at the first groove is 30nm-150nm; and / or, before forming the second electrode, a second passivation / anti-reflection layer is formed, a second groove is formed in the second passivation / anti-reflection layer using a laser grooving process, and a second groove corresponding to the second groove is formed on the second doped polysilicon layer, the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped polysilicon layer outside the location of the second groove, and / or the thickness of the second doped polysilicon layer at the location of the second groove is 30nm-395nm.

[0022] The beneficial effects of the present invention are as follows: the solar cell and its preparation method of the present invention adopt a passivation contact structure on both sides, which has a good passivation effect on both sides compared with the structure of the light-receiving surface of the traditional TOPCon cell as a boron diffusion layer, and can improve the metal contact of the gate line area, so that the J0 under the metal is reduced. In addition, the first doping layer is consistent with the doping type of the silicon substrate, and the second doping layer is opposite to the doping type of the silicon substrate. The doping layer opposite to the doping type of the silicon substrate is arranged on the backlight side of the silicon substrate, that is, the PN junction is arranged on the backlight side of the silicon substrate, which ensures that the area for generating the photovoltaic effect is maximized and the efficiency of the cell is ensured; and the doping layer consistent with the doping type of the silicon substrate is located on the light-receiving surface, and is arranged as a discontinuous structure, for example, the first doped polysilicon layer is only located in the first area, which does not affect the light absorption of the second area, thereby improving the efficiency of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of a solar cell in one embodiment of the present invention, omitting part of the first electrode and the second electrode;

[0024] Figure 2 is a schematic structural diagram of a solar cell in another embodiment of the present invention, in which part of the first electrode and the second electrode are omitted;

[0025] Figure 3 for Figure 2 A partial enlarged view of the middle A;

[0026] Figure 4 for Figure 2 A partial enlarged view of point B in the middle;

[0027] Figure 5 is a flow chart of a method for preparing a solar cell in one embodiment of the present invention;

[0028] Figure 6 The present invention is a flow chart of a method for preparing a solar cell in one embodiment of the present invention.

[0029] Among them, 100-solar cell, 1-silicon substrate, s1-light receiving surface, s2-backlight surface, 11-first region, 12-second region, 2-first tunneling layer, 3-first doping layer, 4-first passivation layer, 5-first anti-reflection layer, 6-second tunneling layer, 7-second doping layer, 8-second passivation layer, 9-second anti-reflection layer, 101-first electrode, 102-second electrode. DETAILED DESCRIPTION

[0030] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0031] In the various drawings of the present invention, for the convenience of illustration, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, they are only used to illustrate the basic structure of the subject matter of the present invention.

[0032] like Figures 1 to 4 As shown, a solar cell 100 according to an embodiment of the present invention comprises a silicon substrate 1, wherein the silicon substrate 1 has a light-receiving surface s1 and a light-receiving surface s2 arranged opposite to each other, the light-receiving surface s1 comprises a first region 11 and a second region 12; a first tunneling layer 2 located in the first region, a first doping layer 3 located on a side of the first tunneling layer 2 away from the silicon substrate 1, and a first electrode in contact with the first doping layer 3, wherein the first tunneling layer 2 and the first doping layer 3 constitute a first passivation contact structure; a second tunneling layer 6 located on the light-receiving surface s2, a second doping layer 7 located on a side of the second tunneling layer 6 away from the silicon substrate 1, and a second electrode 102 in contact with the second doping layer 6, wherein the second tunneling layer 6 and the second doping layer 7 constitute a second passivation contact structure.

[0033] The present invention mainly optimizes the structure of the entire battery, improves the efficiency of the battery, and can also simplify the process steps and process difficulty of the battery. The solar cell 100 has a passivation contact structure on both sides. Compared with the structure of the traditional TOPCon battery in which the light-receiving surface is a boron diffusion layer, the double-sided passivation effect is good, and the metal contact in the gate line area can be improved to reduce the J0 under the metal.

[0034] The silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.5 Ω·cm to 7 Ω·cm.

[0035] In one embodiment, the first region 11 is a gate line region, and the second region 12 is a non-gate line region.

[0036] like Figures 1 to 4As shown, in one embodiment, the first area 11 is a non-textured area, that is, the first area 11 is a smooth surface structure, which is convenient for the subsequent preparation of the first passivation contact structure and the first electrode 101. The surface roughness of the smooth surface structure is small, and the reflectivity is between 45% and 55%. On the one hand, it is conducive to forming a good first tunneling layer 2 and a first doping layer 3 in the first area 11, improving the passivation effect of the gate line area, and thus improving the open circuit voltage; it can also improve the metal contact in the gate line area, so that the J0 under the metal is reduced, thereby improving the battery efficiency. On the other hand, it is conducive to the formation of the first electrode 101; for example, grooving in the first area 11 provides a guarantee for forming the first electrode 101 by electroplating and / or chemical plating, reducing the recombination of the first area 11, and improving the battery efficiency.

[0037] The second area 12 is a textured area, that is, the second area 12 has a textured structure, which reduces the reflectivity of the light receiving surface s1, improves light absorption, and further improves battery efficiency.

[0038] In addition, the inventors found that: when a passivation contact structure is used on both sides, the passivation effect can be significantly improved; however, the doping layer of the light-receiving surface s1 will affect the absorption of light due to parasitic absorption. In some embodiments of the present invention, the first doping layer 3 is consistent with the doping type of the silicon substrate 1, and the second doping layer 7 is opposite to the doping type of the silicon substrate 1. In this design, the doping layer with the opposite doping type to the silicon substrate 1 is arranged on the backlight surface s2 of the silicon substrate 1, that is, the PN junction is arranged on the backlight surface s2 of the silicon substrate 1, which ensures that the area for generating the photovoltaic effect is maximized and the efficiency of the battery is ensured; and the doping layer consistent with the doping type of the silicon substrate 1 is located on the light-receiving surface s1, and it is set to a discontinuous structure, for example, the first doping layer 3 is only located in the first area 11, which does not affect the light absorption of the second area 12, thereby improving the battery efficiency. The specific structure is described as follows.

[0039] The first passivation contact structure is a discontinuous structure, that is, it does not cover the entire light-receiving surface s1. The first passivation contact structure is only located in the first area 11, and the first area 11 is passivated to prevent the first electrode 101 from directly contacting the silicon substrate 1, reduce the metal recombination of the first area 11, and improve the battery efficiency; at the same time, it does not affect the light absorption of the second area 12, which can improve the battery efficiency.

[0040] The first tunneling layer 2 is selected from a silicon oxide layer or a silicon oxynitride layer, and has a thickness of 1 nm to 3 nm, and can be 1.5 nm, 2 nm, or 2.5 nm. The first tunneling layer 2 utilizes the quantum tunneling effect to allow electrons to pass smoothly and prevent the recombination of holes.

[0041] The first doping layer 3 is an N-type doping layer, specifically an N-type doped polysilicon layer (n-poly Si), such as a phosphorus-doped polysilicon layer or an arsenic-doped polysilicon layer. The doping concentration of the first doping layer 3 is 1E20 cm -3 ~1E21cm -3 , and / or the thickness of the first doping layer 3 is 35nm to 200nm, preferably 80nm to 100nm.

[0042] In other embodiments, the solar cell further includes a first passivation / anti-reflection layer located on the side where the light-receiving surface s1 is located, so as to play a role of passivation and / or reduce reflection. The first passivation / anti-reflection layer is located in the first region, contacts the first doped layer 3 in the first region 11, and the first electrode 101 contacts the first doped layer 3 through the first passivation / anti-reflection layer. Alternatively, the first passivation / anti-reflection layer is located in the first region 11 and the second region 12, contacts the first doped layer 3 in the first region 11, and contacts the silicon substrate 1 in the second region 12, and the first electrode 101 contacts the first doped layer 3 through the first passivation / anti-reflection layer.

[0043] In one embodiment, the first passivation / anti-reflection layer includes a first passivation layer 4, the first passivation layer 4 is only located in the first region 11, or the first passivation layer 4 is located in the first region 11 and the second region 12, and the first electrode 101 contacts the first doping layer 3 through the first passivation layer 4.

[0044] The first passivation layer 4 contacts the first doped layer 3 in the first area 11 and contacts the silicon substrate 1 in the second area 12 to passivate the non-gate line area 12 of the silicon substrate 1 and the first doped layer 3 to reduce interface recombination.

[0045] In a specific embodiment, the first passivation layer 4 can be selected from an aluminum oxide layer (Al2O3), and the thickness of the first passivation layer 4 is 3nm to 5nm.

[0046] The second region 12 of the light-receiving surface s1 has no first passivation contact structure, and the silicon substrate 1 is exposed outward. The passivation effect of the light-receiving surface s1 can be improved by utilizing the superior interface passivation effect of aluminum oxide, and can be formed by ALD process, so its thickness can be precisely controlled, further ensuring a good passivation effect.

[0047] In another embodiment, Figures 1 to 4As shown, the first passivation / anti-reflection layer includes a first passivation layer 4 and a first anti-reflection layer 5 located on a surface of the first passivation layer 4 away from the silicon substrate 1. The first passivation layer 4 and the first anti-reflection layer 5 are only located in the first area 11, or the first passivation layer 4 and the first anti-reflection layer 5 are located in the first area 11 and the second area 12, and the first electrode 101 passes through the first anti-reflection layer 5 and the first passivation layer 4 to contact the first doping layer 3.

[0048] The first passivation layer 4 is configured as described above and will not be described in detail herein.

[0049] The first anti-reflection layer 5 is selected from silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), silicon oxide (SiO x ), the thickness of the first anti-reflection layer 5 is 70nm-90nm, which can further reduce the reflectivity of the side where the light receiving surface s1 is located and improve the utilization rate of light.

[0050] In another embodiment, the first passivation / anti-reflection layer includes a first anti-reflection layer 5, and the first electrode 101 passes through the first anti-reflection layer 5 and contacts the first doped layer 3. The first anti-reflection layer 5 is only located in the first area 11, or the first anti-reflection layer 5 contacts the first doped layer 3 in the first area 11, and the first anti-reflection layer 5 contacts the silicon substrate 1 in the second area 12, and the material and thickness of the first anti-reflection layer 5 are as described above.

[0051] The first passivation / anti-reflection layer has a first groove 51, the first electrode 101 is located in the first groove 51, and the first electrode 101 is in direct contact with the first doping layer 3. Compared with the prior art, the first region 11 of the present invention is a planar structure, which is convenient for groove opening and has little groove opening damage. Figures 1 to 4 As shown, in the embodiment with the first passivation layer 4 and the first anti-reflection layer 5 , the first groove 51 is formed on the first passivation layer 4 and the first anti-reflection layer 5 .

[0052] The width w1 of the first groove 51 is smaller than the width w3 of the first region 11 , so that the first groove 51 is completely located in the first region 11 and the first electrode 101 is in contact with the first doping layer 3 .

[0053] In one embodiment, the width w1 of the first groove 51 is 1 / 4 to 1 / 15 of the width w3 of the first region 11. On the one hand, the first region 11 will not be too wide to avoid affecting light absorption. On the other hand, this ratio design reduces the alignment requirements of the groove process to a certain extent. Even if there is an error in the groove, it can prevent the first groove 51 from extending to the second region 12 and prevent the first electrode 101 from exceeding the first region 11.

[0054] Since the parasitic absorption of the doped polysilicon layer material itself causes current loss, it is necessary to reduce the width w3 of the first region 11. The limit is that the width w3 of the first region 11 is consistent with the width of the first electrode 101, so that the best efficiency can be achieved. However, the first electrode 101 needs to be printed on the first passivation contact structure, so the width w3 of the first region 11 cannot be reduced infinitely, otherwise the accuracy of the subsequent process cannot be guaranteed; retaining a certain width of the first passivation contact structure can ensure that the first electrode 101 falls 100% on the first passivation contact structure during preparation.

[0055] In one embodiment, the width w3 of the first region 11 is 50 μm to 150 μm, and / or the width of the first electrode 101 is 10 μm to 15 μm.

[0056] Please refer to Figures 2 to 4 As shown, in one embodiment, the first doping layer 3 has a first groove 31 corresponding to the first groove 51, and the first electrode 101 is located in the first groove 51 and the first groove 31, and contacts the first doping layer 3. By providing the first groove 31, the contact area between the first electrode 101 and the first doping layer 3 is increased, and the bonding strength between the first electrode 101 and the first doping layer 3 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0057] In one embodiment, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d2 of the first doping layer 3 outside the location of the first groove 31, and / or the thickness (d2-d1) of the first doping layer 3 at the location of the first groove 31 is 30nm-150nm, that is, after the first groove 31 is formed, the thickness of the first doping layer 3 retained is 30nm-150nm.

[0058] The present invention optimizes at least one characteristic parameter of the depth d1 of the first groove 31, the ratio of the depth d1 of the first groove 31 to the thickness d2 of the first doping layer 3, and the thickness (d2-d1) of the first doping layer 3 at the first groove 31, thereby ensuring the depth of the first electrode 101 extending into the first doping layer 3 and optimizing the contact area between the first electrode 101 and the first doping layer 3; and avoiding damage to the first doping layer 3 when forming the first groove 51 and the first groove 31, and preventing the doped elements in the first doping layer 3 from penetrating the first tunneling layer 2 under the heat / energy of the groove, thereby destroying the passivation effect of the gate line area.

[0059] In one embodiment, the first electrode 101 is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating.

[0060] In one embodiment, the first electrode 101 is a composite metal electrode, including a metal transition layer in contact with the first doping layer 3 and a metal main layer located on the surface of the metal transition layer.

[0061] The metal transition layer is selected from metals that can form an alloy with silicon under low-temperature annealing conditions. The temperature of the low-temperature annealing is 300° C. to 400° C. to avoid problems such as battery cell warping caused by high-temperature sintering.

[0062] The metal transition layer is selected from a combination of at least one or more of a Ni layer, a Ti layer, and a Co layer. In an optional embodiment, the metal transition layer is a Ni layer, which can be formed by electroplating or chemical plating, and annealed at 300° C. to 400° C. to form a Ni-Si alloy, thereby reducing contact resistance.

[0063] The metal main body layer is the main body of the first electrode 101, and is preferably a metal with good conductivity, low cost, and certain anti-oxidation and anti-corrosion properties. In one embodiment, the metal main body layer is a Cu layer.

[0064] In addition, the metal transition layer serves as a bridge for the metal electrode to bond with silicon, and its thickness is less than that of the metal main layer. In one embodiment, the thickness of the metal transition layer is 100nm to 500nm, and the thickness of the metal main layer is 3μm to 12μm.

[0065] Please refer to Figures 1 to 4 As shown, the second passivation contact structure covers the entire backlight surface s2 of the entire silicon substrate 1. The entire surface absorbs light and generates photogenerated carriers, passivating the entire backlight surface s2 of the silicon substrate 1 to prevent the second electrode 102 from directly contacting the silicon substrate 1, reducing the metal recombination of the gate line area of ​​the backlight surface s2, and improving the battery efficiency.

[0066] The second tunneling layer 6 is selected from a silicon oxide layer or a silicon oxynitride layer, and has a thickness of 1 nm to 3 nm, and can be 1.5 nm, 2 nm, or 2.5 nm.

[0067] The second doping layer 7 is a P-type doping layer, specifically a P-type doped polysilicon layer (p-poly Si), such as a boron-doped polysilicon layer or a gallium-doped polysilicon layer. The thickness of the second doping layer 7 is 80nm to 400nm, preferably 200nm to 300nm; and / or the doping concentration of the second doping layer 7 is 1E19cm -3 ~1E20cm -3 .

[0068] In other embodiments, the solar cell further includes a second passivation / anti-reflection layer located on a side of the second doped layer 7 away from the second tunneling layer 6. The second electrode 102 contacts the second doped layer 7 through the second passivation / anti-reflection layer.

[0069] In one embodiment, the second passivation / anti-reflection layer includes a second passivation layer 8 , and the second electrode 102 passes through the second passivation layer 8 and contacts the second doping layer 7 .

[0070] The second passivation layer 8 is an aluminum oxide layer. On the one hand, aluminum oxide can form a good field passivation effect on the P-type doped polysilicon layer, and on the other hand, the thickness of the aluminum oxide layer is precisely controllable. In an optional embodiment, the thickness of the second passivation layer 8 is 3nm to 5nm.

[0071] Preferably, the second passivation layer 8 is made of the same material and has the same thickness as the first passivation layer 4 and can be formed by synchronous deposition.

[0072] In other embodiments, the second passivation / anti-reflection layer includes a second passivation layer 8 and a second anti-reflection layer 9 located on a side of the second passivation layer 8 away from the second doped layer 7, and the second electrode 102 passes through the second anti-reflection layer 9 and the second passivation layer 8 and contacts the second doped layer 7.

[0073] The second passivation layer 8 is as described above.

[0074] The second anti-reflection layer 9 is selected from one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the second anti-reflection layer 9 is 70nm to 90nm, which further reduces the reflectivity of the backlight surface s2 and improves the utilization rate of light.

[0075] Preferably, the second anti-reflection layer 9 is made of the same material and has the same thickness as the first anti-reflection layer 5 and can be formed by synchronous deposition.

[0076] In another embodiment, the second passivation / anti-reflection layer includes a second anti-reflection layer 9, which is located on a surface of the second doped layer 7 away from the second tunneling layer 6, and the material and thickness of the second doped layer 7 are as described above. The second electrode 102 passes through the second anti-reflection layer 9 and contacts the second doped layer 7.

[0077] The second passivation / anti-reflection layer 9 has a second groove 91, the second electrode 102 is located in the second groove 91, and the second electrode 102 is in direct contact with the second doping layer 7, and high-temperature sintering is not required to allow the slurry to penetrate the second anti-reflection layer 9 and the second passivation layer 8. In the embodiment having the second passivation layer 8 and the second anti-reflection layer 9, the second groove 91 is formed on the second passivation layer 8 and the second anti-reflection layer 9.

[0078] The width w2 of the second slot 91 is 10 μm to 15 μm, which meets the width requirement of the second electrode 102 . The second electrode 102 can also be formed in the second slot 91 by electroplating and / or chemical plating.

[0079] In one embodiment, the second doping layer 7 has a second groove 71 corresponding to the second groove 91. The second electrode 102 is located in the second groove 91 and the second groove 71, and contacts the second doping layer 7. By providing the second groove 71, the bonding strength between the second electrode 102 and the second doping layer 7 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0080] In one embodiment, the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d4 of the second doping layer 7 outside the second groove 71, and / or the thickness (d4-d3) of the second doping layer 7 at the second groove 71 is 30nm-395nm, that is, after the second groove 71 is formed, the thickness of the remaining second doping layer 7 is 30nm-395nm.

[0081] The present invention optimizes at least one of the above characteristic parameters: the depth d3 of the second groove 71, the ratio of the depth d3 of the second groove 71 to the thickness d4 of the first doping layer 3, and the thickness (d4-d3) of the second doping layer 7 at the first groove 31. This ensures the depth of the second electrode 102 extending into the second doping layer 7 and optimizes the contact area between the second electrode 102 and the second doping layer 7; it also avoids damage to the second doping layer 7 when forming the second groove 91 and the second groove 71, and under the heat / energy of the groove, the doping elements in the second doping layer 7 penetrate the second tunneling layer 6 and destroy the passivation effect of the gate line area.

[0082] The second electrode 102 is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating. In the present invention, the structure, material and process of the second electrode 102 are the same as those of the first electrode 101, and will not be described in detail herein.

[0083] In one embodiment, the second electrode 102 is a nickel-copper composite electrode, including a Ni layer in contact with the second doping layer 7 and a copper layer located on the surface of the Ni layer.

[0084] In summary, the solar cell 100 of the present invention adopts a passivation contact structure on both sides. Compared with the structure of the light-receiving surface s1 of the traditional TOPCon cell as a boron diffusion layer, the double-sided passivation effect is good, and the metal contact in the gate line area can be improved to reduce J0 under the metal. In addition, the second doping layer 7 with the opposite doping type to the silicon substrate 1 is arranged on the backlight surface s2 of the silicon substrate 1, that is, the PN junction is arranged on the backlight surface s2 of the silicon substrate 1, which ensures that the area for generating the photovoltaic effect is maximized and the efficiency of the cell is ensured. The first doping layer 3 with the same doping type as the silicon substrate 1 is located on the light-receiving surface s1, and it is set to a discontinuous structure. The first doping layer 3 is only arranged in the first area 11, which does not affect the light absorption of the second area 12, thereby improving the cell efficiency.

[0085] Please refer to Figure 2 As shown, the present invention also provides a method for preparing a solar cell, which improves production efficiency and reduces production costs on the basis of improving cell efficiency.

[0086] The method for preparing the solar cell comprises the following steps:

[0087] A silicon substrate 1 is provided, wherein the silicon substrate 1 has a light-receiving surface s1 and a backlight surface s2 which are arranged opposite to each other, and the light-receiving surface s1 has a first area 11 and a second area 12;

[0088] Forming a first tunneling layer 2 on the light-receiving surface s1 of the silicon substrate 1;

[0089] forming a first doped amorphous silicon layer on a side of the first tunneling layer 2 away from the silicon substrate 1;

[0090] Forming a second tunneling layer 6 on the backlight surface s2 of the silicon substrate 1;

[0091] forming a second doped amorphous silicon layer on a side of the second tunneling layer 6 away from the silicon substrate 1;

[0092] Annealing to transform the first doped amorphous silicon layer into a first doped polysilicon layer as the first doped layer 3; and transform the second doped amorphous silicon layer into a second doped polysilicon layer as the second doped layer 7;

[0093] removing the first doped polysilicon layer located in the second region 12;

[0094] A first electrode 101 contacting the first doped polysilicon layer is formed in the first region 11 , and a second electrode 102 contacting the second doped polysilicon layer is formed on the backlight surface s2 .

[0095] In the method, the silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.5 Ω·cm to 7 Ω·cm.

[0096] In this method, the light-receiving surface s1 and the backlight surface s2 of the silicon substrate 1 are both smooth structures, that is, a double-sided polished silicon wafer is used as the silicon substrate 1, which is convenient for the subsequent grooving process and can reduce the damage of the grooving.

[0097] Alternatively, before depositing the first tunneling layer 2 and the second tunneling layer 6, the silicon substrate 1 is polished, preferably both sides are polished to ensure that both sides have a planar structure.

[0098] In the present invention, the polishing solution is 0.2mol / L to 0.5mol / L sodium hydroxide (NaOH), 0.2mol / L to 0.5mol / L potassium hydroxide (KOH), and 0.4mol / L to 0.8mol / L tetramethylammonium hydroxide (TMAH), and the polishing time is 100s to 300s.

[0099] Alternatively, the reflectivity of the light-receiving surface s1 and the backlight surface s2 of the silicon substrate 1 is between 45% and 55%, and there is no abnormal appearance.

[0100] Please refer to Figure 5 and Figure 6As shown, in one embodiment, the second tunneling layer 6 is first formed on the backlight surface s2 of the silicon substrate 1, the second doped amorphous silicon layer is formed on the side of the first tunneling layer 6 away from the silicon substrate, and the second mask layer is formed on the side of the second doped amorphous silicon layer away from the second tunneling layer 6; after removing the film layer coated around the light-receiving surface s1, the first tunneling layer 2 is formed on the light-receiving surface s1 of the silicon substrate 1, the first doped amorphous silicon layer is formed on the side of the first tunneling layer 2 away from the silicon substrate 1, and the first mask layer is formed on the side of the first doped amorphous silicon layer away from the first tunneling layer 2; annealing is performed to transform the first doped amorphous silicon layer The first doped polysilicon layer is formed on the first mask layer of the second area 12, and the second doped amorphous silicon layer is transformed into a second doped polysilicon layer; after annealing, a groove is formed on the first mask layer of the second area 12 to expose the first doped polysilicon layer; the film layer coated on the backlight surface s2 and the first doped polysilicon layer located in the second area 12 are removed, and a velvet structure is formed in the second area 12, at this time, under the protection of the first mask layer, the first passivation contact structure of the first area 11 is not destroyed; the first electrode 101 in contact with the first doped polysilicon layer is formed in the first area 11, and the second electrode 102 in contact with the second doped polysilicon layer is formed on the backlight surface s2.

[0101] A PECVD process is adopted to deposit a silicon oxide layer or a silicon oxynitride layer as the second tunneling layer 6 on the backlight surface s2 of the polished silicon substrate 1 , with a thickness of 1 nm to 3 nm.

[0102] A PECVD process is used, trimethylboron (TMB), borane (B2H6), boron trifluoride (BF3), or metal gallium (Ga) is used as a doping source of a P-type structure, and a P-type amorphous silicon layer doped with B or Ga is deposited as the second doped amorphous silicon layer; the thickness of the P-type amorphous silicon layer is 80nm to 400nm, preferably 200nm to 300nm; the doping concentration is 1E19cm -3 ~1E20cm -3 .

[0103] After forming the P-type amorphous silicon layer, nitrous oxide (N2O) and silane (SiH4) are introduced to form a silicon oxide layer as the second mask layer to protect the film structure of the backlight surface s2 when "removing the film layer coated on the light-receiving surface s1".

[0104] “Removing the film layer coated on the light-receiving surface s1” includes: using a hydrofluoric acid (HF) solution to remove the mask layer deposited on the light-receiving surface s1; and then using an alkaline solution to remove the doped amorphous silicon layer coated on the light-receiving surface s1, and under the protection of the second mask layer, the structure of the backlight surface s2 is not destroyed. In this article, the concentration of the HF solution used for de-coating is 0.01mol / L to 0.03mol / L, and the alkaline solution is 0.2mol / L to 0.5mol / L NaOH solution or 0.2mol / L to 0.5mol / L KOH solution.

[0105] In one embodiment, a chain machine and HF solution are used to remove the mask layer deposited on the light-receiving surface s1; and a tank machine and polishing alkali solution are used to remove the doped amorphous silicon layer plated on the light-receiving surface s1.

[0106] A PECVD process is adopted to deposit a silicon oxide layer or a silicon oxynitride layer as the first tunneling layer 2 on the polished light-receiving surface s1, with a thickness of 1 nm to 3 nm.

[0107] A PECVD process is used, using phosphine (PH3) or arsine (AsH3) as an N-type doping source, to deposit an amorphous silicon layer doped with phosphorus or arsenic as the first doped amorphous silicon layer, with a thickness of 35nm to 200nm, preferably 80nm to 100nm; 8 doping concentration is 1E20cm -3 ~1E21cm -3 .

[0108] The first mask layer is formed by a PECVD process, wherein the first mask layer is selected from SiO x layer, or SiN x layer, or SiO x N y Layer, with a thickness of 70nm to 90nm, acts as a mask in subsequent processes.

[0109] The annealing temperature of the present invention is 880° C. to 940° C., which simultaneously meets the doping annealing requirements of the first doped amorphous silicon layer and the second doped amorphous silicon layer. The two-step annealing is integrated into one step, which can reduce the fixed asset investment.

[0110] In this step, the N-type doped amorphous silicon layer on the light-receiving surface s1 is transformed into an N-type doped polysilicon layer; the P-type amorphous silicon layer on the backlight surface s2 is transformed into a P-type doped polysilicon layer to form a back junction with the silicon substrate 1 .

[0111] After annealing, a groove is formed on the first mask layer in the second area 12, that is, the first mask layer in the second area 12 is removed to expose the first doped polysilicon layer; the first mask layer in the first area 11 is retained to protect the first doped polysilicon layer in subsequent processes.

[0112] The width w3 of the remaining first region 11 is 50 μm to 150 μm. If it is too narrow, the accuracy of the subsequent process cannot be guaranteed. If it is too wide, it will have a greater impact on the light absorption of the light receiving surface s1.

[0113] In one embodiment, a laser grooving process is used to remove the first mask layer located in the second area 12. In the present invention, the laser grooving process used is selected from green picosecond laser or ultraviolet picosecond laser, and the laser damage is small.

[0114] Specifically, the power of the ultraviolet picosecond laser is 8W to 20W, the spot diameter is 100μm to 150μm, the frequency is 500kHz to 600kHz, and the scanning speed is 45000m / s to 60000m / s.

[0115] The power of green picosecond laser is 20W~50W, the spot diameter is 100μm~150μm, the frequency is 500kHz~600kHz, and the scanning speed is 45000m / s~60000m / s.

[0116] “Removing the film layer coated on the backlight surface s2 and the first doped polysilicon layer located in the second area 12” includes: using HF solution to remove the mask layer coated on the backlight surface s2, using potassium hydroxide solution to remove the N-type doped polysilicon layer coated on the backlight surface s2 and the N-type doped polysilicon layer in the second area 12, and at the same time forming a velvet structure in the second area 12, and the first area 11 retains the first doped polysilicon layer due to the blocking of the first mask layer.

[0117] In one embodiment, a chain machine and HF solution are used to remove the mask layer plated on the backlight surface s2, and a slot machine and texturing alkali solution are used to remove the doped polysilicon layer plated on the back side and the second doped polysilicon layer located in the second area 12, and a texturing structure is formed in the second area 12.

[0118] In some embodiments, before preparing the first electrode 101, a first passivation / anti-reflection layer is formed on the side where the light-receiving surface s1 is located, the first passivation / anti-reflection layer is in contact with the first doped layer 3 in the first region 11, and the first passivation / anti-reflection layer is in contact with the silicon substrate 1 in the second region 12. Then, a first groove 51 is formed on the first passivation / anti-reflection layer in the first region 11; and the first electrode 101 is formed in the first groove 51.

[0119] In some implementations, the first passivation layer 4 is formed as the first passivation / anti-reflection layer. The first passivation layer 4 is in contact with the first doping layer 3 in the first region 11 , and the first passivation layer 4 is in contact with the silicon substrate 1 in the second region 12 .

[0120] The first passivation layer 4 is selected from an aluminum oxide layer. The thickness of the first passivation layer 4 is 3nm-5nm. If it is too thin, the film layer may be uneven and the passivation effect is poor; if it is too thick, material is wasted and it is not conducive to the incidence of light.

[0121] In one embodiment, a tubular Thermal-ALD process is used in a single-chip manner to deposit an aluminum oxide layer on the light-receiving surface s1 as the first passivation layer 4 , thereby forming a good chemical passivation effect on the light-receiving surface s1 .

[0122] In some implementations, a first passivation layer 4 is formed on the side where the light receiving surface s1 is located, and a first anti-reflection layer 5 is formed on the side of the first passivation layer 4 away from the silicon substrate 1 as the first passivation / anti-reflection layer.

[0123] The formation of the first passivation layer 4 is as described above and will not be repeated here. The present invention adopts a PECVD process to prepare the first anti-reflection layer 5, and the first anti-reflection layer 5 is selected from a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the first anti-reflection layer 5 is 70nm to 90nm, which reduces the reflectivity while ensuring the transmittance of light.

[0124] In some embodiments, the first anti-reflection layer 5 is formed on the side of the light-receiving surface s1 as the first passivation / anti-reflection layer. The first anti-reflection layer 5 contacts the first doped layer 3 in the first region 11 and contacts the silicon substrate 1 in the second region 12 .

[0125] In some embodiments, the solar cell manufacturing method further includes: before preparing the second electrode 102, forming a second passivation / anti-reflection layer on the surface of the second doping layer 7 away from the second tunneling layer 6. Then, forming a second groove 91 in the gate line region of the second passivation / anti-reflection layer; and forming the second electrode 102 at the second groove 91.

[0126] In one embodiment, the second passivation layer 8 is formed on a surface of the second doping layer 7 away from the second tunneling layer 6 as the second passivation / anti-reflection layer.

[0127] The film material, thickness and preparation process of the second passivation layer 8 can refer to the first passivation layer 4. The first passivation layer 4 and the second passivation layer 8 can be formed in steps to adapt to the differentiated design of the passivation layers on both sides in terms of materials, thickness, etc. For example, the thickness of the first passivation layer 4 is less than the thickness of the second passivation layer 8 to ensure the light transmittance of the film layer on the light receiving surface s1; they can also be formed simultaneously to simplify the process steps.

[0128] In one embodiment, a tubular Thermal-ALD process is adopted in a single-chip manner to deposit an aluminum oxide layer on the light-receiving surface s1 as the first passivation layer 4, thereby forming a good chemical passivation effect on the light-receiving surface s1; at the same time, an aluminum oxide layer is deposited on the backlight surface s2 as the second passivation layer 8, thereby forming a good field passivation effect on the backlight surface s2.

[0129] In some embodiments, a second passivation layer 8 is formed on the surface of the second doped layer 7 away from the second tunneling layer 6, and a second anti-reflection layer 9 is formed on the side of the second passivation layer 8 away from the second doped layer 7, and the second passivation layer 8 and the second anti-reflection layer 9 constitute the second passivation / anti-reflection layer. Then, a second groove 91 is formed in the gate line region of the second passivation layer 8 and the second anti-reflection layer 9; and the second electrode 102 is formed at the second groove 91.

[0130] The second passivation layer 8 is formed as described above, and will not be described in detail here. The film material, thickness and preparation process of the second anti-reflection layer 9 can refer to the first anti-reflection layer 5 .

[0131] The materials and / or thicknesses of the first anti-reflection layer 5 and the second anti-reflection layer 9 may be the same or different. The first anti-reflection layer 5 and the second anti-reflection layer 9 may be formed in steps to adapt to the differentiated design of the anti-reflection layers on both sides in terms of materials, thicknesses, etc. For example, the thickness of the first anti-reflection layer 5 is less than the thickness of the second anti-reflection layer 9 to ensure the light transmittance of the film layer on the light-receiving surface s1; they may also be formed simultaneously to simplify the process steps.

[0132] In one embodiment, a PECVD process is used to deposit a stacked film of one or more of silicon nitride, silicon oxynitride, and silicon oxide on the light-receiving surface s1 of the silicon substrate 1 as the first anti-reflection layer 5; at the same time, a second anti-reflection layer 9 is deposited on the backlight surface s2 of the silicon substrate 1.

[0133] In some embodiments, a second anti-reflection layer 9 is formed as the second passivation / anti-reflection layer on the surface of the second doped layer 7 away from the second tunneling layer 6. Then, a second groove 91 is formed in the gate line region of the second anti-reflection layer 9; and the second electrode 102 is formed at the second groove 91.

[0134] In the present invention, a laser grooving process is used to form the first groove 51 and the second groove 91. The width w1 of the first groove 51 is narrower than the first region 11, ensuring that the first electrode 101 is in contact with the first doped polysilicon layer. Preferably, the width w1 of the first groove 51 is 1 / 4 to 1 / 15 of the width of the gate line region, so that even if there is an error, the first groove 51 can be completely located in the gate line region.

[0135] In one embodiment, the width w1 of the first slot 51 is 10 μm-15 μm.

[0136] Compared with the velvet structure, the first area 11 is a planar structure, laser grooving is simple, and the damage caused is relatively light. In this way, in the subsequent electroplating and chemical plating processes, the bonding force of metals such as Ni and Cu attached to Si is strong, which can reduce the contact resistance.

[0137] The width w2 of the second groove 91 is 10 μm to 15 μm, which meets the width requirement of the second electrode 102 . The second electrode 102 can also be formed in the second groove 91 by electroplating and / or chemical plating.

[0138] The inventors found that when the laser grooving process forms the first groove 31 and the second groove 91, laser damage will be caused to the first doped polysilicon layer and the second doped polysilicon layer inside. Under the laser energy, the first doped polysilicon layer and the second doped polysilicon layer react with the surrounding atmosphere to form a laser damaged layer, for example, react with oxygen in the air to form a silicon oxide layer. The laser damaged layer is not conductive, which will affect the formation of electrodes by the electroplating process, and will also affect the bonding of the electrode to silicon. Furthermore, the method for preparing the solar cell also includes the following steps: before forming the first electrode 101 and the second electrode 102, the damaged layer is removed to reduce the contact resistance between the electrode and the doped polysilicon layer.

[0139] In the present invention, a cleaning liquid is used to remove the laser damaged layer in the first slot 51 and the second slot 91. The cleaning liquid is selected from a 0.01 mol / L to 0.05 mol / L HF solution, and the cleaning time is 20 s to 100 s.

[0140] The forming of the first electrode 101 and the second electrode 102 by electroplating and / or chemical plating includes: forming a metal transition layer by electroplating or chemical plating; annealing to form an alloy between the metal transition layer and silicon; and forming a metal main layer by electroplating or chemical plating.

[0141] The metal transition layer can enhance the bonding between the first electrode 101, the second electrode 102 and silicon, and in particular, can form an alloy with the silicon substrate 1 after annealing, with stronger bonding. The metal transition layer can also improve the conductivity of the inner wall of the first slot 51 and the second slot 91, which is conducive to forming a good metal main layer in the subsequent electroplating process.

[0142] The metal transition layer is selected from metals that can form alloys with silicon under low temperature annealing conditions. The low temperature annealing temperature is 300° C. to 400° C., which avoids the problem of cell warping caused by high temperature, and the low temperature annealing cost is low.

[0143] The metal transition layer is at least one of a Ni layer, a Ti layer, and a Co layer. In one embodiment, the metal transition layer is a Ni layer, which can be formed by electroplating or chemical plating, and annealed at 300° C. to 400° C. to form a Ni-Si alloy.

[0144] The metal main body layer is the main body of the first electrode 101 and the second electrode 102, and is preferably a metal with good electrical conductivity, low cost, and certain anti-oxidation and anti-corrosion properties.

[0145] The metal main layer is a Cu layer. In one embodiment, the metal main layer is a Cu layer.

[0146] In addition, the metal transition layer serves as a bridge for combining the metal electrode and silicon, and its thickness is less than that of the metal main layer. The thickness of the metal transition layer is 100nm to 500nm, and the thickness of the metal main layer is 3μm to 12μm.

[0147] In addition, based on any of the above-mentioned preparation methods, the preparation method of the solar cell further includes: forming a first groove 31 corresponding to the first groove 51 on the first doped polysilicon layer. The first electrode 101 is located in the first groove 31 and the first groove 51, and contacts the first doped layer 3. By providing the first groove 31, the contact area between the first electrode 101 and the first doped layer 3 is increased, and the bonding strength between the first electrode 101 and the first doped layer 3 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0148] In one embodiment, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d2 of the first doped polysilicon layer outside the first groove 31, that is, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 accounts for no more than 20% of the thickness of the first doped polysilicon layer; and / or the thickness (d2-d1) of the first doped layer 3 at the first groove 31 is 30nm-150nm, that is, after the first groove 31 is formed, the thickness of the first doped layer 3 retained is 30nm-150nm.

[0149] Such a configuration not only ensures the depth of the first electrode 101 extending into the first doping layer 3 and optimizes the contact area between the first electrode 101 and the first doping layer 3, but also avoids damage to the first doping layer 3 when forming the first groove 51 and the first groove 31, and avoids the doping elements in the first doping layer 3 penetrating the first tunneling layer 2 under the heat / energy of the groove, thereby destroying the passivation effect of the gate line area.

[0150] In the present invention, the first groove 31 and the first slot 51 are formed by a laser slotting process, which is described above and will not be described in detail herein. Specifically, the first groove 31 is formed when the first slot 51 is formed, that is, in the same process step, the first slot 51 and the first groove 31 are formed successively by a laser slotting process.

[0151] The first passivation / anti-reflection layer is provided with a first groove 51. When the first doped polysilicon layer is provided with the first groove 31, the washing liquid is used to remove the laser damaged layer in the first groove 51 and the first groove 31, and then the first electrode 101 is formed by electroplating and / or chemical plating process.

[0152] In addition, based on any of the above-mentioned preparation methods, the preparation method of the solar cell further includes: forming a second groove 71 corresponding to the second groove 91 on the second doped polysilicon layer. The second electrode 102 is located in the second groove 91 and the second groove 71, and contacts the second doped layer 7. By providing the second groove 71, the bonding strength between the second electrode 102 and the second doped layer 7 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0153] In one embodiment, the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d4 of the second doping layer 7 outside the second groove 71, and / or the thickness (d4-d3) of the second doping layer 7 at the second groove 71 is 30nm-395nm, that is, after the second groove 71 is formed, the thickness of the remaining second doping layer 7 is 30nm-395nm.

[0154] Such a configuration not only ensures the depth of the second electrode 102 extending into the second doping layer 7 and optimizes the contact area between the second electrode 102 and the second doping layer 7, but also avoids damage to the second doping layer 7 when forming the second groove 91 and the second groove 71, and under the heat / energy of the groove, the doping elements in the second doping layer 7 penetrate the second tunneling layer 6 and destroy the passivation effect of the gate line area.

[0155] In the present invention, the second groove 71 and the second slot 91 are formed by a laser slotting process, which is described above and will not be described in detail herein. Specifically, the second groove 71 is formed when the second slot 91 is formed, that is, in the same process step, the second slot 91 and the second groove 71 are formed successively by a laser slotting process.

[0156] When a second groove 91 is provided on the second passivation / anti-reflection layer and a second groove 71 is provided on the second doped polysilicon layer, the washing liquid is used to remove the laser damaged layer in the second groove 91 and the second groove 71, and then the second electrode 102 is formed by electroplating and / or chemical plating process.

[0157] In another embodiment, the present invention may also prepare the first passivation contact structure and the second passivation contact structure separately.

[0158] In the method for preparing the solar cell, the method for preparing the first passivation contact structure comprises the following steps:

[0159] forming a first tunneling layer 2 on the entire light-receiving surface s1 of the silicon substrate 1, forming the first doped amorphous silicon layer on a side of the first tunneling layer 2 away from the silicon substrate 1, and forming a first mask layer on a side of the first doped amorphous silicon layer away from the first tunneling layer 2;

[0160] Annealing to transform the first doped amorphous silicon layer into a first doped polycrystalline silicon layer as the first doped layer 3;

[0161] Grooving the first mask layer in the second area 12 to expose the first doped polysilicon layer of the silicon substrate 1, removing the first doped polysilicon layer in the second area 12 with an alkaline solution, and forming a velvet structure in the second area 12;

[0162] The first passivation layer 4 is formed on the side where the light receiving surface s1 is located, and the first anti-reflection layer 5 is formed on the side of the first passivation layer 4 away from the silicon substrate 1, the first passivation layer 4 is in contact with the first doping layer 3 in the first area 11, and the first passivation layer 4 is in contact with the silicon substrate 1 in the second area 12;

[0163] The first groove 51 is formed in the gate line region of the first passivation layer 4 and the first anti-reflection layer 5 to expose the first doping layer 3 , and the first electrode 101 is formed in the first groove 51 by electroplating and / or chemical plating.

[0164] In this method, each step may adopt the above-mentioned process steps, which will not be described in detail here.

[0165] In the method for preparing the solar cell, the method for preparing the second passivation contact structure comprises the following steps:

[0166] forming a second tunneling layer 6 on the backlight surface s2 of the silicon substrate 1, and forming the second doped amorphous silicon layer on a side of the second tunneling layer 6 away from the silicon substrate 1;

[0167] Annealing, so that the second doped amorphous silicon layer is transformed into a second doped polycrystalline silicon layer as the second doped layer 7;

[0168] forming a second passivation layer 8 on a side of the second doped layer 7 away from the second tunneling layer 7 , and forming a second anti-reflection layer 9 on a side of the second passivation layer 8 away from the second doped layer 7 ;

[0169] Laser grooves are formed in the gate line regions of the second passivation layer 8 and the second anti-reflection layer 9 to form the second grooves 91, exposing the second doped layer 7;

[0170] The second electrode 102 is formed in the second groove 91 by electroplating and / or chemical plating.

[0171] In this method, each step may adopt the above-mentioned process steps, which will not be described in detail here.

[0172] In addition, the characteristic parameters of the solar cell 100 of the present invention are applicable to the corresponding structures in the method for preparing the solar cell; the characteristic parameters of the method for preparing the solar cell are applicable to the corresponding characteristics of the solar cell 100. The solar cell 100 can be prepared by the method for preparing the solar cell, or by other preparation methods.

[0173] The method for preparing the solar cell of the present invention will be described in detail below with specific implementations.

[0174] Example 1

[0175] Polishing: Conventional silicon wafer polishing process, both sides of the silicon wafer form a polished surface with a reflectivity of 45% to 55%, with no abnormal appearance; the polishing solution is 0.3 mol / L sodium hydroxide (NaOH) solution, and the polishing time is 200s.

[0176] A 2 nm silicon oxide layer is deposited on the backlight surface s2 of the silicon substrate 1 as the second tunneling layer 6 by using the PECVD process.

[0177] The PECVD process is used to form a P-type doped amorphous silicon layer as the second doped amorphous silicon layer using borane (B2H6) as a doping source of a P-type structure, with a thickness of 250nm and a doping concentration of 1E19cm -3 ~1E20cm -3 .

[0178] After the PECVD equipment deposits the P-type doped amorphous silicon layer, laughing gas (N2O) and silane (SiH4) are introduced to generate SiO x , as the second mask layer.

[0179] Remove the film layer plated on the light-receiving surface s1: use a chain machine to add a 0.01 mol / L HF solution to remove the mask layer plated on the light-receiving surface s1; use a slot machine to add a 0.4 mol / L NaOH solution to remove the P-type doped amorphous silicon layer plated on the light-receiving surface s1.

[0180] A 2 nm thick silicon oxide layer is deposited on the light receiving surface s1 of the silicon substrate 1 by using a PECVD process as the first tunneling layer 2 .

[0181] The PECVD method is used to form an N-type doped amorphous silicon layer using PH3 as an N-type doping source as the first doped amorphous silicon layer, with a thickness of 90nm and a doping concentration of 1E20cm -3 ~1E21cm -3 .

[0182] After the PECVD equipment deposits the N-type doped amorphous silicon layer, laughing gas (N2O) and silane (SiH4) are introduced to generate SiO x , as the first mask layer.

[0183] Annealing: the annealing temperature is 910° C., so that the first doped amorphous silicon layer is transformed into the first doped polysilicon layer, and the second doped amorphous silicon layer is transformed into the second doped polysilicon layer.

[0184] In the second region 12 , green light picosecond or ultraviolet picosecond laser grooving is performed to expose the first doped polysilicon layer in the second region 12 . The width w3 of the first region 11 is 100 μm.

[0185] The film layer plated on the backlight surface s2 is removed, and the second area 12 is textured: a chain machine is used to add 0.02mol / L HF solution to remove the mask layer plated on the backlight surface s2; a slot machine is used to add 0.3mol / L NaOH solution to remove the doped polysilicon layer plated on the backlight surface s2, and a velvet structure is formed in the second area 12. The first area 11 retains the structure of the polished surface due to the blocking of the retained first mask layer.

[0186] Preparation of double-sided passivation layer: Using ALD process, Al2O3 film layer is plated on both sides as the first passivation layer 4 and the second passivation layer 8, with a thickness of 4nm, which has a field passivation effect on the p-poly Si layer of the backlight surface s2 and a good chemical passivation effect on the n-poly Si layer of the light-receiving surface s1.

[0187] Preparation of double-sided anti-reflection layer: SiNx film is deposited on both sides by PECVD process as the first anti-reflection layer 5 on the side where the light-receiving surface s1 is located and the second anti-reflection layer 9 on the side where the backlight surface s2 is located, so as to reduce the reflectivity.

[0188] Grooving the light-receiving surface s1: using a laser grooving process, forming the first groove 51 on the first anti-reflection layer 5 and the first passivation layer 3 of the first region 11, the width w1 of the first groove 51 is 13 μm, so as to form the first electrode 101 by subsequent electroplating or chemical plating.

[0189] Grooving on the backlight surface s2: using a laser grooving process, laser grooving is performed on the second anti-reflection layer 9 and the second passivation layer 8 in the gate line area of ​​the backlight surface s2 to form the second groove 91, and the width w2 of the second groove 91 is 12μm, so that the second electrode 102 can be formed by subsequent electroplating or chemical plating.

[0190] An HF solution with a concentration of 0.01 to 0.05 mol / L is used to remove surface dust and the laser damaged layer formed by laser grooving, improve the bonding between the metal electrode and silicon, and increase the open circuit voltage (Voc) and short circuit current (Jsc).

[0191] Electroplating / chemical Ni plating, using relevant processes in the prior art to form a uniform and dense nickel plating layer in the first groove 51 and the second groove 91.

[0192] Annealing: The temperature is preferably 300°C to 400°C to form a Ni-Si alloy.

[0193] Electroplating / chemical plating of Cu: using the related process in the prior art to grow Cu in the first slot 51 and the second slot 91 to form a Ni-Cu composite metal electrode.

[0194] Testing and sorting: Testing and sorting of battery cells and storage.

[0195] Example 2

[0196] The difference between Example 2 and Example 1 is only that:

[0197] Grooving the light-receiving surface s1: using a laser grooving process, the first groove 51 is formed on the first anti-reflection layer 5 and the first passivation layer 3 of the first region 11, and a first groove 31 corresponding to the first groove 51 is formed on the first doped polysilicon layer, and the width w1 of the first groove 51 and the first groove 31 is 13 μm, so that the first electrode 101 can be formed by subsequent electroplating or chemical plating.

[0198] Grooving on the backlight surface s2: using a laser grooving process, laser grooving is performed on the second anti-reflection layer 9 and the second passivation layer 8 in the gate line area of ​​the backlight surface s2 to form the second groove 91, and a second groove 71 corresponding to the second groove 91 is formed on the second doped polysilicon layer 7, and the width w2 of the second groove 91 and the second groove 71 is 12μm, so that the second electrode 102 can be formed by subsequent electroplating or chemical plating.

[0199] An HF solution with a concentration of 0.01 to 0.05 mol / L is used to remove surface dust and the laser damaged layer formed by laser grooving, improve the bonding between the metal electrode and silicon, and increase the open circuit voltage (Voc) and short circuit current (Jsc).

[0200] Electroplating / chemical Ni plating, using relevant processes in the prior art to form a uniform and dense nickel plating layer in the first slot 51 and the first groove 31 , the second slot 91 and the second groove 71 .

[0201] Annealing: The temperature is preferably 300°C to 400°C to form a Ni-Si alloy.

[0202] Electroplating / chemical plating of Cu: using the relevant process in the prior art to grow Cu on the nickel plating layer to form a Ni-Cu composite metal electrode.

[0203] In summary, the solar cell 100 and its preparation method of the present invention adopt a passivation contact structure on both sides. Compared with the structure of the light-receiving surface s1 of the traditional TOPCon cell as a boron diffusion layer, the double-sided passivation effect is good, and the metal contact of the gate line area can be improved, so that the J0 under the metal is reduced. In addition, the first doping layer 3 is consistent with the doping type of the silicon substrate 1, and the second doping layer 7 is opposite to the doping type of the silicon substrate 1. The doping layer with the opposite doping type to the silicon substrate 1 is set on the backlight surface s2 of the silicon substrate 1, that is, the PN junction is set on the backlight surface s2 of the silicon substrate 1, which ensures that the area for generating the photovoltaic effect is maximized and the efficiency of the cell is ensured; and the doping layer consistent with the doping type of the silicon substrate 1 is located on the light-receiving surface s1, and it is set as a discontinuous structure, for example, the first doping layer 3 is only located in the first area 11, which does not affect the light absorption of the second area 12, thereby improving the cell efficiency.

[0204] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0205] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate has a light-receiving surface and a backlight surface that are arranged opposite to each other, and the light-receiving surface has a first area and a second area; A first tunneling layer, wherein the first tunneling layer is disposed in the first region; a first doping layer, wherein the first doping layer is located on a side of the first tunneling layer away from the silicon substrate; A second tunneling layer, wherein the second tunneling layer is located on the backlight surface; a second doped layer, wherein the second doped layer is located on a surface of the second tunneling layer that is away from the silicon substrate; a first electrode, the first electrode being in contact with the first doping layer; A second electrode is in contact with the second doping layer.

2. The solar cell according to claim 1, characterized in that: The first area is a non-textured area, and the second area is a texturized area; and / or the first area is a gate line area, and the second area is a non-gate line area.

3. The solar cell according to claim 1, characterized in that: It also includes a first passivation layer located on the side where the light receiving surface is located, the first passivation layer is in contact with the first doped layer in the first region, and the first passivation layer is an aluminum oxide layer; and / or The solar cell further includes a second passivation layer located on a side of the second doping layer away from the second tunneling layer, and the second passivation layer is an aluminum oxide layer.

4. The solar cell according to claim 1, characterized in that: The solar cell further comprises a first passivation / anti-reflection layer located on the side where the light-receiving surface is located, wherein the first passivation / anti-reflection layer contacts the first doping layer in the first region, and the first passivation / anti-reflection layer contacts the silicon substrate in the second region, and the first passivation / anti-reflection layer has a first groove located in the first region, and the first electrode is located in the first groove; And / or, the solar cell further includes a second passivation / anti-reflection layer located on a surface of the second doping layer away from the second tunneling layer, the second passivation / anti-reflection layer has a second groove, and the second electrode is located in the second groove.

5. The solar cell according to claim 4, characterized in that: The first passivation / anti-reflection layer has a first groove, the width of the first groove is 1 / 4 to 1 / 15 of the width of the first zone; and / or the width of the first zone is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

6. The solar cell according to claim 4, characterized in that: The first passivation / anti-reflection layer has a first groove, the first doping layer has a first groove corresponding to the first groove, and the first electrode is located in the first groove and the first groove; And / or, the second passivation / anti-reflection layer has a second groove, the second doping layer has a second groove corresponding to the second groove, and the second electrode is located in the second groove and the second groove.

7. The solar cell according to claim 6, characterized in that: The depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm; and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the first doped layer outside the location of the first groove; and / or the thickness of the first doped layer at the location of the first groove is 30nm-150nm; And / or, the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped layer outside the second groove, and / or the thickness of the second doped layer at the second groove is 30nm-395nm.

8. The solar cell according to claim 1, characterized in that: The first electrode is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating; and / or The second electrode is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating.

9. The solar cell according to any one of claims 1 to 8, characterized in that: The silicon substrate is an N-type silicon wafer, and the first doping layer is an N-type doped polysilicon layer with a doping concentration of 1E20cm -3 ~1E21cm -3 , and / or a thickness of 35nm to 200nm; And / or, the second doped layer is a P-type doped polysilicon layer with a doping concentration of 1E19cm -3 ~1E20cm -3 , and / or a thickness of 80nm to 400nm.

10. A method for preparing a solar cell, characterized in that: The steps include: Providing a silicon substrate, wherein the silicon substrate has a light-receiving surface and a backlight surface that are oppositely arranged, and the light-receiving surface has a first area and a second area; forming a first tunneling layer on the light-receiving surface of the silicon substrate; forming a first doped amorphous silicon layer on a side of the first tunneling layer away from the silicon substrate; forming a second tunneling layer on the backlight surface of the silicon substrate; forming a second doped amorphous silicon layer on a side of the second tunneling layer away from the silicon substrate; Annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polysilicon layer, and the second doped amorphous silicon layer is transformed into a second doped polysilicon layer; removing the first doped polysilicon layer located in the second region; A first electrode contacting the first doped polysilicon layer is formed in the first region, and a second electrode contacting the second doped polysilicon layer is formed on the backlight surface.

11. The method for preparing a solar cell according to claim 10, characterized in that: The light-receiving surface and the backlight surface of the silicon substrate are both light surface structures; or Before forming the first tunneling layer and the second tunneling layer, the silicon substrate is polished.

12. The method for preparing a solar cell according to claim 10, characterized in that: Firstly, forming the second tunneling layer on the backlight surface, forming the second doped amorphous silicon layer on the side of the second tunneling layer away from the silicon substrate, and forming a second mask layer on the side of the second doped amorphous silicon layer away from the second tunneling layer; After removing the film layer coated on the light-receiving surface, forming the first tunneling layer on the light-receiving surface, forming the first doped amorphous silicon layer on a side of the first tunneling layer away from the silicon substrate, and forming a first mask layer on a side of the first doped amorphous silicon layer away from the first tunneling layer; Annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polysilicon layer, and the second doped amorphous silicon layer is transformed into a second doped polysilicon layer; After annealing, removing the first mask layer located in the second region to expose the first doped polysilicon layer; Removing the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area, and forming a velvet structure in the second area; The first electrode is formed in the first region and in contact with the first doped polysilicon layer, and the second electrode is formed in contact with the second doped polysilicon layer on the backlight surface.

13. The method for preparing a solar cell according to claim 10, characterized in that: The method for preparing the solar cell further comprises the following steps: Before preparing the first electrode, a first passivation / anti-reflection layer is formed on the side where the light-receiving surface is located, the first passivation / anti-reflection layer is in contact with the first doped layer in the first region, the first passivation / anti-reflection layer is in contact with the silicon substrate in the second region, and a first groove is formed in the first passivation / anti-reflection layer in the first region by a laser grooving process; the first electrode is formed in the first groove; and / or Before preparing the second electrode, a second passivation / anti-reflection layer is formed on a side of the second doped polysilicon layer away from the second tunneling layer, and a second groove is formed in the gate line area of ​​the second passivation / anti-reflection layer using a laser grooving process; the second electrode is formed in the second groove.

14. The method for preparing a solar cell according to claim 13, characterized in that: The width of the first slot is 1 / 4 to 1 / 15 of the width of the first zone; and / or, The width of the first region is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

15. The method for preparing a solar cell according to claim 13, characterized in that: Before forming the first electrode, a first passivation / anti-reflection layer is formed, a first groove is formed in the first passivation / anti-reflection layer by a laser grooving process, and a first groove corresponding to the first groove is formed on the first doped polysilicon layer; the depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness d2 of the first doped polysilicon layer outside the first groove; and / or the thickness of the first doped polysilicon layer at the first groove is 30nm-150nm; And / or, before forming the second electrode, a second passivation / anti-reflection layer is formed, a second groove is formed in the second passivation / anti-reflection layer using a laser grooving process, and a second groove corresponding to the second groove is formed on the second doped polysilicon layer, the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped polysilicon layer outside the location of the second groove, and / or the thickness of the second doped polysilicon layer at the location of the second groove is 30nm-395nm.

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