Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a barrier layer disposed on a substrate, a buffer layer, a first active layer of a first thin film transistor, a first insulating layer, a first conductive layer including a first gate electrode overlapping the first active layer, a second insulating layer, a second conductive layer including a back gate electrode overlapping a second active layer of a second thin film transistor, the semiconductor device includes a barrier layer, a buffer layer, a first insulating layer, a second insulating layer, a third insulating layer, a second active layer, a fourth insulating layer, a valley portion penetrating the barrier layer, the buffer layer, and at least a portion of the first insulating layer to the fourth insulating layer and not overlapping the first active layer and the second active layer, a third conductive layer including a second gate electrode overlapping the second active layer, the light emitting device includes a substrate, a valley portion, a first insulating layer, a second insulating layer, a fifth insulating layer, and a light emitting element, in which the fifth insulating layer includes a first inorganic layer disposed directly on an inner sidewall of the valley portion, and a second inorganic layer including a material different from that of the first inorganic layer and disposed on the first inorganic layer.

Description

Technical Field

[0001] The present invention relates to a display device and a manufacturing method thereof. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigators, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, an organic light emitting display device, etc. In these flat panel display devices, the light emitting display device includes a light emitting element that can make each pixel of the display panel self-luminous, thereby being able to display an image even if there is no backlight unit providing light in the display panel.

[0003] The display device may further include pixels emitting predetermined light, scan wiring for driving the pixels, data wiring, power wiring, a scan driving unit outputting a scan signal to the scan wiring, and a display driving unit outputting a data voltage to the data wiring. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a display device and a manufacturing method thereof which can prevent circuit elements from being damaged due to impact applied from the outside and prevent the circuit elements from being degraded.

[0005] The technical problems of the present invention are not limited to the technical problems mentioned above, and those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0006] A display device according to an embodiment for solving the above technical problems includes: a barrier layer arranged on a substrate; a buffer layer arranged on the barrier layer; a first active layer of a first thin film transistor arranged on the buffer layer; a first insulating layer arranged on the first active layer; a first conductive layer arranged on the first insulating layer and including a first gate electrode overlapping the first active layer; a second insulating layer arranged on the first conductive layer; a second conductive layer arranged on the second insulating layer and including a back gate electrode overlapping the second active layer of the second thin film transistor; a third insulating layer arranged on the second conductive layer; the second active layer arranged on the third insulating layer; a fourth insulating layer arranged on the second active layer; a valley portion penetrating the barrier layer; a first active layer of a first thin film transistor arranged on the buffer layer; a first insulating layer arranged on the first active layer; a first conductive layer arranged on the first insulating layer and including a first gate electrode overlapping the first active layer; a second conductive layer arranged on the second insulating layer and including a back gate electrode overlapping the second active layer of the second thin film transistor; a third insulating layer arranged on the second conductive layer; a second active layer arranged on the third insulating layer; a fourth insulating layer arranged on the second active layer; a valley portion penetrating the barrier layer; a first active layer of a first thin film transistor arranged on the buffer layer; a first insulating layer arranged on the first active layer; a first conductive layer of a first thin film transistor arranged on the buffer layer; a first conductive layer of a first thin film transistor arranged on the buffer layer; a first conductive layer of a first thin film transistor arranged on the buffer layer; a first conductive layer of a first thin film transistor arranged on the buffer layer; a first conductive layer of a second ... layer, the buffer layer and at least a portion of the first insulating layer to the fourth insulating layer, and not overlapping with the first active layer and the second active layer; a third conductive layer, arranged on the fourth insulating layer, and including a second gate electrode overlapping with the second active layer; a fifth insulating layer, arranged on the third conductive layer and the fourth insulating layer, and covering the inner side wall of the valley; and a light emitting element, arranged on the fifth insulating layer, and electrically connected to the first thin film transistor and the second thin film transistor, respectively, wherein the fifth insulating layer includes a first inorganic layer and a second inorganic layer, the first inorganic layer is directly arranged on the inner side wall of the valley, and the second inorganic layer contains a material different from the first inorganic layer and is arranged on the first inorganic layer.

[0007] The first inorganic layer may include silicon oxide, and the second inorganic layer may include silicon nitride.

[0008] The valley portion may be formed to recess a portion of an upper surface of the barrier layer or the buffer layer, and the first inorganic layer may be in direct contact with a portion of an upper surface of the barrier layer or the buffer layer.

[0009] A thickness of a portion of the barrier layer that forms a bottom surface of the valley may be smaller than a thickness of a portion that does not overlap with the valley.

[0010] The first inorganic layer may be in direct contact with the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer at inner side walls of the valley portion, respectively.

[0011] The valley portion may be formed to penetrate the barrier layer to expose an upper surface of the substrate, and the first inorganic layer may be in direct contact with the substrate.

[0012] The display device may further include a filling layer filling the inside of the valley and disposed on the second inorganic layer, wherein the filling layer may include an organic insulating substance.

[0013] The display device may further include: a wiring electrically connected to at least one of the first thin film transistor and the second thin film transistor, wherein at least one of the wirings may be arranged to overlap the valley portion on the filling layer.

[0014] The valley portion may include a first valley portion and a second valley portion overlapping the first valley portion and penetrating the fifth insulating layer, wherein the second valley portion may be arranged inside the first valley portion.

[0015] The depth of the second valley portion may be smaller than the depth of the first valley portion, and the width of the second valley portion may be smaller than the width of the first valley portion.

[0016] The display device may further include: a cover layer disposed on the second inorganic layer on the valley portion and disposed on an inner side wall of the second valley portion; and a filling layer disposed on the cover layer and filling the inside of the valley portion.

[0017] The maximum widths of the cover layer and the filling layer may be the same as each other.

[0018] The interval distance between the valley portion and the second active layer may be 3 μm or less.

[0019] The substrate may include a plurality of unit pixel regions where the first thin film transistor and the second thin film transistor are arranged, and the valley may be arranged at a boundary between adjacent unit pixel regions.

[0020] A manufacturing method of a display device according to an embodiment for solving the above-mentioned technical problem includes the following steps: forming a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second semiconductor layer, a third insulating layer, a second conductive layer and a fourth insulating layer on a substrate, and forming a gate contact hole penetrating the third insulating layer and a valley penetrating the second insulating layer to the fourth insulating layer; forming a fifth insulating layer including a first inorganic layer covering the inner side wall of the valley and a second inorganic layer arranged on the first inorganic layer; and forming a plurality of contact holes penetrating at least a portion of the second insulating layer, the third insulating layer and the fourth insulating layer, and forming a plurality of bridging electrodes arranged on the fourth insulating layer and connected to at least one of the first semiconductor layer and the second semiconductor layer through the contact holes, wherein the first inorganic layer and the second inorganic layer contain different materials from each other.

[0021] The first inorganic layer may include silicon oxide, and the second inorganic layer may include silicon nitride.

[0022] In the manufacturing method of the display device, a buffer layer arranged between the substrate and the first semiconductor layer and a barrier layer arranged between the buffer layer and the substrate may also be formed, wherein the valley may be formed to penetrate the barrier layer or the buffer layer and to recess a portion of the upper surface of the barrier layer or the buffer layer, and the first inorganic layer may be in direct contact with a portion of the upper surface of the barrier layer or the buffer layer.

[0023] In the manufacturing method of the display device, a buffer layer arranged between the substrate and the first semiconductor layer and a barrier layer arranged between the buffer layer and the substrate may also be formed, wherein the valley may be formed to pass through the buffer layer and the barrier layer, and the first inorganic layer may be in direct contact with a portion of the upper surface of the substrate.

[0024] In the step of forming the plurality of contact holes, a portion of the first inorganic layer and the second inorganic layer may be penetrated inside the valley portion, wherein the valley portion may include a first valley portion and a second valley portion penetrating the first inorganic layer and the second inorganic layer.

[0025] The method for manufacturing a display device may further include forming a cover layer disposed on an inner side wall of the second valley portion and the second inorganic layer, and a filling layer filling the inside of the valley portion.

[0026] Details of other embodiments are included in the detailed description and drawings.

[0027] The display device according to an embodiment may include a valley portion, and the area where the pixel circuit is arranged is arranged around the valley portion. The inner side wall of the valley portion may be covered by an insulating layer arranged thereon, and the gas generated by the organic insulating material may be prevented from moving to adjacent circuit elements. Thus, the display device can prevent damage to the circuit elements caused by external impact and degradation of the circuit elements caused by the gas.

[0028] Furthermore, the display device can form the valley portion without adding a mask process, thereby having an advantage in the manufacturing process.

[0029] Furthermore, in the case where the display device has a flexible characteristic, cracks that may be formed in a plurality of insulating layers disposed thereon when the substrate is folded can be prevented by the valley portion.

[0030] The effects according to the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a perspective view of a display device according to an embodiment.

[0032] Figure 2 It is shown Figure 1 A plan view of a display device.

[0033] Figure 3 is along Figure 2 Cross-sectional view taken along line A-A'.

[0034] Figure 4 is a plan view showing a display panel according to an embodiment.

[0035] Figure 5 is a pixel circuit diagram of a sub-pixel according to an embodiment.

[0036] Figure 6 is a pixel circuit diagram of a sub-pixel according to another embodiment.

[0037] Figure 7 is a plan view showing an arrangement of a plurality of pixels arranged in a display area of ​​a display device according to an embodiment.

[0038] Figure 8 It is shown that the arrangement Figure 7 A plan view of a pixel circuit in a unit pixel area.

[0039] Fig. 9 is along Figure 8 Cross-sectional view taken along line IX-IX'.

[0040] Fig.10 is magnified and shows Fig. 9 Figure 4 shows the valley portion of the graph.

[0041] Figures 11 to 17 FIG. 1 is a diagram sequentially showing a part of a manufacturing process of a display device according to an embodiment.

[0042] Fig.18 is a plan view showing an arrangement of a plurality of pixels and valleys arranged in a display area of ​​a display device according to another embodiment.

[0043] Fig.19 is a cross-sectional view showing a portion of a display device according to another embodiment.

[0044] Fig. 20 is a cross-sectional view showing a portion of a display device according to still another embodiment.

[0045] Fig.21 is a cross-sectional view showing a portion of a display device according to still another embodiment.

[0046] Figure 22 to Figure 26 is shown in order Fig.21 FIG. 1 is a diagram of a portion of a manufacturing process of a display device.

[0047] Description of Reference Numerals

[0048] 10: Display device

[0049] 100: Display panel 200: Driving unit

[0050] 300: Circuit board

[0051] 110: Substrate

[0052] TFT1, TFT2: Thin Film Transistor

[0053] VA: Tanibe DETAILED DESCRIPTION

[0054] The advantages and features of the present invention and the methods for achieving the advantages and features will become clear with reference to the accompanying drawings and the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. The present embodiments are provided only to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0055] When an element or layer is mentioned as being "on" another element or layer, it includes all cases where it is directly above the other element or layer or where other layers or other elements are sandwiched in between. Similarly, when "below", "left" and "right" are mentioned, it includes all cases where it is directly adjacent to another element or layer or where other layers or other elements are sandwiched in between. Throughout the specification, the same reference numerals represent the same constituent elements.

[0056] Although the terms "first", "second" and the like are used to describe various components, these components are obviously not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical concept of the present invention, the first component mentioned below can obviously also be the second component.

[0057] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device according to an embodiment.

[0059] Reference Figure 1The display device 10 is a device for displaying moving images or still images, and can be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMP: portable multimedia player), navigators, ultra-portable PCs (UMPC: UltraMobile PC), but also as a display screen for a variety of products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT: internet of things) devices.

[0060] The display device 10 may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano LED). Hereinafter, an embodiment in which the display device 10 is an organic light-emitting display device is described, but the type of the display device 10 is not limited thereto.

[0061] In one embodiment, the display device 10 may be formed flat. For example, the display device 10 may be formed substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a predetermined thickness (or height) in the third direction DR3. In another embodiment, the display device 10 may include a curved surface portion in at least a portion including an edge region, etc. In addition, the display device 10 may be flexibly formed to be able to be folded, bent, curved, folded, or rolled.

[0062] In one embodiment, based on the image display surface of the display device 10, the first direction DR1 may be a longitudinal direction, a column direction, or a vertical direction, and the second direction DR2, as a direction crossing the first direction DR1, may be a transverse direction, a row direction, or a horizontal direction as an example. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0063] The display device 10 may include a display panel 100 , a driving part 200 , and a circuit board 300 .

[0064] The display panel 100 may include a main area MA including a display area DA displaying an image and a sub area SBA located at one side of the main area MA.

[0065] The main area MA may include a display area DA and a non-display area NA around the display area DA. The display area DA may be located at the center of the main area MA and may occupy most of the main area MA. The non-display area NA may be located at the edge of the main area MA and may contact the sub-area SBA.

[0066] The display area DA is used as a pixel (as an example, Figure 4 The area where the pixels PX are arranged may be an area where an image is displayed by the pixels PX. In one embodiment, a sensing pattern (as an example, a touch electrode) for sensing a touch input or the like may also be provided in the display area DA, and the display area DA may include a sensing area for sensing a touch input by the sensing pattern.

[0067] In one embodiment, the display area DA may include a long side in the first direction DR1 and a short side in the second direction DR2, and may be formed as a plane having a substantially rectangular shape. The corner portion where the long side and the short side of the display area DA intersect may be formed smoothly or at a right angle. The shape of the display area DA may be varied according to the embodiment. For example, the display area DA may also be formed as a polygon other than a quadrilateral, a circle, an ellipse, etc.

[0068] The non-display area NA may be located in close proximity to the periphery of the display area DA. The non-display area NA may surround the display area DA. A built-in circuit may be arranged in the non-display area NA. For example, a built-in circuit including a scan drive circuit and the like may be arranged in the non-display area NA located on one side (as an example, the left side or the right side) or both sides of the display area DA.

[0069] The sub-region SBA may be located at one side of the main region MA. For example, the sub-region SBA may be a region protruding from one side of the main region MA toward the first direction DR1. As an example, the sub-region SBA may protrude from the lower end of the main region MA in the first direction DR1. In one embodiment, the sub-region SBA may have a narrower width than the main region MA. For example, with the second direction DR2 as a reference, the sub-region SBA may have a narrower width than the main region MA.

[0070] Wiring and pads may be arranged in the sub-area SBA. For example, wiring and pads connected to pixels and / or built-in circuits located in the main area MA, the driving unit 200 and / or the circuit board 300 located in the sub-area SBA may be arranged in the sub-area SBA. When describing the embodiments, "connection" may include the meaning of electrical connection and / or physical connection.

[0071] In one embodiment, a driving unit 200 (as an example, a display driving circuit) may be mounted in the sub-area SBA. A circuit board 300 may be arranged on a portion of the sub-area SBA.

[0072] The driving unit 200 may include a data driving circuit for driving pixels. In one embodiment, the driving unit 200 may be formed as an integrated circuit chip (IC) and arranged in the sub-area SBA. In another embodiment, the driving unit 200 may be arranged on a circuit board 300 on the sub-area SBA, or may be arranged on another circuit board connected to the display panel 100 through the circuit board 300.

[0073] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad located at a portion of the sub-area SBA (as an example, the lower edge), and may supply or transmit a power supply voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (as an example, digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB: Flexible Printed Circuit Board), a rigid printed circuit board (RPCB: Rigid Printed Circuit Board), or a flexible film such as a chip on film (COF: Chip on Film), but is not limited thereto.

[0074] Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 is along Figure 2 Cross-sectional view taken along line A-A'.

[0075] Figure 1 The display device 10 is shown in a state where it is unfolded and not bent. Figure 2 and Figure 3 A state in which the display device 10 is bent in the sub-area SBA is illustrated. Figure 1 The sub-area SBA is shown to be developed in parallel with the main area MA. Figure 2 and Figure 3 A state in which a part of the sub-area SBA is bent is shown.

[0076] Reference Figure 2 and Figure 3, the display panel 100 includes a substrate 110 including a main area MA and a sub-area SBA, and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 sequentially arranged on the substrate 110. The circuit layer 120 may also be located in the main area MA and the sub-area SBA on the substrate 110. The light emitting element layer 130 and the encapsulation layer 140 may be located on a portion of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130 and the encapsulation layer 140 may be located in the main area MA.

[0077] In one embodiment, the display device 10 may further include additional elements arranged on the display panel 100. For example, the display device 10 may further include at least one of a sensor layer (as an example, a touch sensor layer), a polarizing layer, a color filter layer, and a protective layer (as an example, a window) arranged on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, the color filter layer, and / or the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and attached to the display panel 100 using an adhesive layer or the like as a medium.

[0078] The substrate 110 may include insulating materials such as polymer resin. For example, the substrate 110 may be formed using polyimide or other insulating materials. The substrate 110 may be a flexible substrate that is bendable, foldable, rollable, etc. Alternatively, the substrate 110 may include insulating materials such as glass.

[0079] The circuit layer 120 may include pixel circuits and wiring. For example, the circuit layer 120 may include circuit elements (as an example, pixel transistors and capacitors) constituting the pixel circuit of each pixel and wiring connected to the pixel. In one embodiment, the circuit layer 120 may also include circuit elements constituting built-in circuits such as scan drive circuits and wiring connected to the built-in circuits.

[0080] The light emitting element layer 130 may include a light emitting element arranged in a light emitting area of ​​a pixel. For example, each pixel may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each pixel may be located in a pixel area including a light emitting area where a light emitting element is arranged and a pixel circuit area where a pixel circuit is arranged. The light emitting area and the pixel circuit area of ​​each pixel may overlap each other, but are not limited thereto.

[0081] In describing the embodiment, the circuit layer 120 and the light emitting element layer 130 are separated and described, but the embodiment is not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may also be integrated.

[0082] The encapsulation layer 140 may cover the light emitting element layer 130, and may extend to the non-display area NA and contact the circuit layer 120. In one embodiment, the encapsulation layer 140 may have a multilayer structure including at least two inorganic encapsulation films overlapping each other and at least one organic encapsulation film interposed between the inorganic encapsulation films.

[0083] In an embodiment, the display panel 100 may be bent at the bending area BA. The bending area BA may be a part of the sub area SBA and may be spaced apart from the main area MA.

[0084] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a portion of the sub-area SBA, thereby reducing or minimizing the frame area recognized as the non-display area NA by the user.

[0085] Figure 4 is a plan view showing a display panel according to an embodiment. Figure 4 A state in which the display panel 100 is unfolded without being bent is shown.

[0086] Reference Figure 4 The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NA, and the sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0087] The display area DA may be an area where a plurality of pixels PX are arranged. The pixels PX and wirings (or a portion of the wirings) connected to the pixels PX may be arranged in the display area DA.

[0088] The pixels PX may be provided in the circuit layer 120 and the light emitting element layer 130 of the display panel 100. As an example, each pixel PX may include a pixel circuit including circuit elements arranged in the circuit layer 120 (as an example, Figure 5 or Figure 6 The pixel circuit PCA) and the light emitting element (as an example, Figure 5 or Figure 6 light-emitting element EL).

[0089] The pixel PX may include at least two color sub-pixels SPX that emit light of different colors from each other. For example, the pixel PX may include a first color sub-pixel SPX1 that emits light of a first color (as an example, red light), a second color sub-pixel SPX2 that emits light of a second color (as an example, green light), and a third color sub-pixel SPX3 that emits light of a third color (as an example, blue light).

[0090] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel PX. For example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel PX. Each unit pixel PX may emit light of multiple colors including white light by mixing the light emitted from the sub-pixels SPX1, SPX2, and SPX3 constituting it. In one embodiment, the first color sub-pixel SPX1 and the third color sub-pixel SPX3 may be arranged alternately with each other in the first direction DR1 and / or the second direction DR2, and the second color sub-pixel SPX2 may be arranged continuously and / or sequentially in the first direction DR1. The type, shape, and / or arrangement structure of the sub-pixels SPX1, SPX2, and SPX3 may be varied according to the embodiment. In addition, the type, number, ratio, and / or arrangement structure of the sub-pixels SPX1, SPX2, and SPX3 constituting each unit pixel PX may also be varied according to the embodiment.

[0091] An encapsulation layer 140 may be disposed on the pixel PX. For example, the encapsulation layer 140 may be provided at least in the display area DA to cover the pixel PX, and a portion of the encapsulation layer 140 may extend to the non-display area NA.

[0092] The wiring may be provided in the circuit layer 120 and may be located in the display area DA and the non-display area NA. In addition, the wiring may also be located in the sub-area SBA. For example, the wiring may extend from the sub-area SBA through the non-display area NA to the display area DA.

[0093] The non-display area NA may be located at the periphery of the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA located at the outer contour of the display area DA.

[0094] The non-display area NA may include a dam area DAMA separated from the display area DA, a first non-display area NA1 between the display area DA and the dam area DAMA, and a second non-display area NA2 outside the dam area DAMA. The dam area DAMA may be an area where a dam surrounding the display area DA is arranged. The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "joining area") where inorganic encapsulation films of the encapsulation layer 140 are joined to each other.

[0095] The sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA sequentially arranged on one side of the main area MA. Wiring (or part of the wiring), a bank, and a pad PD may be arranged in the sub-area SBA. At least a part of the wiring may extend to the main area MA and be connected to the pixel PX.

[0096] The bank area BNKA may be an area where a bank including at least one organic film is arranged. In one embodiment, the bank area BNKA may include a bending area BA. For example, the bank area BNKA may include a bending area BA separated from the main area MA and a first edge area BEA1 and a second edge area BEA2 located on both sides of the bending area BA in the first direction DR1. The bank may be provided in the bending area BA and its peripheral area (as an example, the first edge area BEA1 and the second edge area BEA2 of the bank area BNKA) and cover the wiring passing through the bending area BA. The display panel 100 may be bent at the bending area BA so that a portion of the sub-area SBA is located on the rear surface of the main area MA.

[0097] The driving circuit mounting area ICA may be an area where the driving part 200 is arranged. Pads for connecting at least a portion of wiring with the driving part 200 may be arranged in the driving circuit mounting area ICA. For example, input pads for connecting the driving part 200 with specific pads (as an example, data input pads) of the pad area PA and output pads for connecting the driving part 200 with the pixels PX may be arranged in the driving circuit mounting area ICA.

[0098] In some embodiments, the driving unit 200 may not be disposed on the display panel 100. In this case, the display panel 100 may not include the driving circuit mounting area ICA, and only wiring may be disposed in the area between the bank area BNKA and the pad area PA.

[0099] The pad area PA may be an area where a pad PD for connecting the display panel 100 and / or the driving part 200 with the circuit board 300, etc. is arranged. The circuit board 300 may be arranged or bonded on the pad area PA.

[0100] In the pad area PA, a plurality of pads PD including power pads and signal pads connected to the pixels PX, the driving unit 200, and / or the built-in circuit, etc. may be arranged. A power supply voltage for driving the pixels PX, the driving unit 200, and / or the built-in circuit, etc. may be supplied to the power pads. A driving signal and / or image data for driving the pixels PX, the driving unit 200, and / or the built-in circuit, etc. may be supplied to the signal pads. The type, position, arrangement order, and / or number of the pads PD, etc. may be variously changed according to the embodiment.

[0101] Figure 5is a pixel circuit diagram of a sub-pixel according to an embodiment. Figure 6 is a pixel circuit diagram of a sub-pixel according to another embodiment.

[0102] Figure 5 and Figure 6 The embodiments different from each other regarding the pixel circuit PCA and the wiring connected to the pixel circuit PCA are shown. The configuration of the pixel circuit PCA and the type and number of wiring connected to the pixel circuit PCA can be variously changed according to the embodiment.

[0103] exist Figure 5 In the embodiment, each pixel circuit PCA includes a first transistor T1 to a seventh transistor T7. In one embodiment, Figure 5 The scan wiring SL connected to the sub-pixel SPX may include a first scan wiring SL1, a second scan wiring SL2, a third scan wiring SL3, and a fourth scan wiring SL4. Figure 5 The power wiring PL connected to the sub-pixel SPX may include a first pixel power wiring VDL, a second pixel power wiring VSL, a first initialization power wiring VIL, and a second initialization power wiring VAIL. Figure 5 The sub-pixel SPX can also be connected to the light emission control wiring ECL.

[0104] exist Figure 6 In the embodiment, each pixel circuit PCA includes a first transistor T1 to an eighth transistor T8. In one embodiment, Figure 6 The scan wiring SL connected to the sub-pixel SPX may include a first scan wiring SL1, a second scan wiring SL2, a third scan wiring SL3, and a fifth scan wiring SL5. Figure 6 The power wiring PL connected to the sub-pixel SPX may include a first pixel power wiring VDL, a second pixel power wiring VSL, a first initialization power wiring VIL, a second initialization power wiring VAIL, and a bias power wiring VOBL. Figure 6 The sub-pixel SPX can also be connected to the light emission control wiring ECL.

[0105] Reference Figure 5 The sub-pixel SPX may include a light-emitting unit EMU including at least one light-emitting element EL and a pixel circuit PCA (also referred to as a “pixel driving unit”) connected to the light-emitting unit EMU.

[0106] The light emitting element EL may be connected between the second pixel power supply wiring VSL to which the second pixel power supply voltage ELVSS is applied and the pixel circuit PCA. In one embodiment, the second pixel power supply voltage ELVSS may be a low potential pixel driving voltage. The light emitting element EL, as a light source of the pixel PX, may receive a driving current supplied from the pixel circuit PCA to emit light.

[0107] The light emitting element EL may be an organic light emitting diode, but is not limited thereto. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0108] The pixel circuit PCA can control the light emission time point and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel circuit PCA may include at least one pixel transistor T and a capacitor Cst. In an embodiment, the pixel circuit PCA may include a pixel transistor T including a first transistor T1 to a seventh transistor T7.

[0109] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power wiring VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (as an example, a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of a sub-pixel SPX.

[0110] The second transistor T2 may include a gate electrode connected to the first scan wiring SL1, a first electrode connected to the data wiring DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by the first scan signal supplied to the first scan wiring SL1, thereby electrically connecting the first electrode of the first transistor T1 to the data wiring DL. If the second transistor T2 is turned on, the voltage of the data signal supplied to the data wiring DL may be applied to the first electrode of the first transistor T1.

[0111] The third transistor T3 may include a gate electrode connected to the second scan wiring SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by a second scan signal supplied to the second scan wiring SL2, thereby electrically connecting the gate electrode of the first transistor T1 to the second electrode. If the third transistor T3 is turned on, the first transistor T1 may be driven as a diode.

[0112] The fourth transistor T4 may include a gate electrode connected to the third scan wiring SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power wiring VIL. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan wiring SL3, thereby electrically connecting the gate electrode of the first transistor T1 to the first initialization power wiring VIL. If the fourth transistor T4 is turned on, the first initialization voltage VINT (as an example, a gate initialization voltage) of the first initialization power wiring VIL may be applied to the gate electrode of the first transistor T1.

[0113] The fifth transistor T5 may include a gate electrode connected to the light emission control wiring ECL, a first electrode connected to the first pixel power wiring VDL, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 may be turned on by the light emission control signal supplied to the light emission control wiring ECL, thereby electrically connecting the first electrode of the first transistor T1 to the first pixel power wiring VDL to which the first pixel power voltage ELVDD is applied. If the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In one embodiment, the first pixel power voltage ELVDD may be a high potential pixel driving voltage.

[0114] The sixth transistor T6 may include a gate electrode connected to the light emission control wiring ECL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by the light emission control signal supplied to the light emission control wiring ECL, thereby electrically connecting the first transistor T1 to the light emitting element EL. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current of a magnitude corresponding to the voltage of the gate electrode of the first transistor T1 may flow through the light emitting element EL.

[0115] The seventh transistor T7 may include a gate electrode connected to the fourth scan wiring SL4, a first electrode connected to the anode electrode of the light emitting element EL, and a second electrode connected to the second initialization power wiring VAIL. The seventh transistor T7 may be turned on by the fourth scan signal supplied to the fourth scan wiring SL4, thereby electrically connecting the anode electrode of the light emitting element EL to the second initialization power wiring VAIL. The fourth scan signal may be the same signal as the first scan signal or a different signal. If the seventh transistor T7 is turned on, the second initialization voltage VAINT (as an example, the anode initialization voltage) of the second initialization power wiring VAIL may be applied to the anode electrode of the light emitting element EL.

[0116] The capacitor Cst may be connected between the gate electrode of the first transistor T1 and the first pixel power wiring VDL. The capacitor Cst may be charged to a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1.

[0117] The active layer (as an example, a semiconductor pattern including a channel region) of each of the pixel transistors T (as an example, the first transistor T1 to the seventh transistor T7) may include a semiconductor material selected from polycrystalline silicon, amorphous silicon, and an oxide semiconductor. In one embodiment, a portion and another portion of the pixel transistors T may be formed by transistors of different conductivity types. In addition, a portion and another portion of the pixel transistors T may include semiconductor materials of different types from each other.

[0118] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed by P-type transistors (as an example, P-type MOSFETs) including respective active layers formed using polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed by N-type transistors (as an example, N-type MOSFETs) including respective active layers formed using oxide semiconductors. In one embodiment, transistors including respective active layers formed using polysilicon and transistors including respective active layers formed using oxide semiconductors may be arranged on different layers from each other in the circuit layer 120.

[0119] Combination Figure 5 Reference Figure 6 , the pixel circuit PCA may further include an eighth transistor T8. The eighth transistor T8 may include a gate electrode connected to the fifth scan wiring SL5, a first electrode connected to the bias power wiring VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fifth scan signal supplied to the fifth scan wiring SL5, thereby electrically connecting the first electrode of the first transistor T1 to the bias power wiring VOBL. If the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power wiring VOBL may be applied to the first electrode of the first transistor T1. In one embodiment, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. As the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0120] exist Figure 6 In the embodiment of FIG. 1 , the gate electrode of the seventh transistor T7 may be connected to the fifth scan wiring SL5. Thus, the seventh transistor T7 may be turned on by the fifth scan signal supplied to the fifth scan wiring SL5, thereby connecting the anode electrode of the light emitting element EL to the second initialization power wiring VAIL.

[0121] Figure 7 is a plan view showing an arrangement of a plurality of pixels arranged in a display area of ​​a display device according to an embodiment. Figure 8 It is shown that the arrangement Figure 7 A plan view of a pixel circuit in a unit pixel area.

[0122] Reference Figure 7 and Figure 8 The display device 10 may include a plurality of pixel circuits (PXC: PXC1, PXC2, PXC3, PXC4) arranged in the display area DA. The plurality of pixel circuits PXC may be electrically connected to the light emitting elements EL included in the respective sub-pixels SPX1, SPX2, SPX3, respectively. The plurality of circuit elements included in the pixel circuits PXC may be applied with electrical signals for light emission of the light emitting elements EL.

[0123] A plurality of pixel circuits PXC may be arranged in the first direction DR1 and the second direction DR2. For example, two pixel circuits PXC adjacent to each other in the second direction DR2 may constitute a unit pixel region (UPX: UPX1, UPX2, UPX3, UPX4), and may be arranged in the first direction DR1 and the second direction DR2. The first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 may constitute a first unit pixel region UPX1. The third pixel circuit PXC3 and the fourth pixel circuit PXC4 adjacent to each other in the second direction DR2 may constitute a second unit pixel region UPX2. The first unit pixel region UPX1 and the second unit pixel region UPX2 may be arranged with each other in the first direction DR1. Each of the third unit pixel region UPX3 and the fourth unit pixel region UPX4 may also include two pixel circuits adjacent to each other in the second direction DR2, and they may be arranged with each other in the first direction DR1. The first unit pixel region UPX1 and the second unit pixel region UPX2 may be arranged with the third unit pixel region UPX3 and the fourth unit pixel region UPX4 in the second direction DR2, respectively.

[0124] The plurality of wirings, conductive patterns, and semiconductor layers constituting the pixel circuit may repeat the same pattern based on one unit pixel region UPX, rather than repeating the same pattern based on the pixel circuit. For example, the arrangement structure of the wirings, conductive patterns, and semiconductor layers of the first unit pixel region UPX1 may have the same arrangement structure in the second unit pixel region UPX2, the third unit pixel region UPX3, and the fourth unit pixel region UPX4. The first pixel circuit PXC1 and the second pixel circuit PXC2 may respectively have a structure in which the arrangement of the conductive patterns and the semiconductor layers is symmetrical to each other, and the patterns of the conductive patterns and semiconductor layers constituting the two pixel circuits PXC1 and PXC2 may be repeatedly arranged in the entire display area DA.

[0125] According to an embodiment, the display device 10 may include a valley VA arranged to surround a unit pixel region UPX. The valley VA may surround one unit pixel region UPX, and may surround a plurality of unit pixel regions UPX in the entire display area DA. The valley VA may be arranged at the boundary of a plurality of unit pixel regions UPX arranged along the first direction DR1 and the second direction DR2. The valley VA may be arranged to extend along the first direction DR1 and the second direction DR2, and two pixel circuits PXC may be arranged in the region intersecting and surrounding the valley VA. A plurality of unit pixel regions UPX may be arranged to be separated from each other across the valley VA, and may be isolated in the region surrounded by the valley VA.

[0126] The valley VA may be formed to penetrate a plurality of conductive layers constituting the pixel circuit PXC and an interlayer insulating layer arranged between semiconductor layers. The valley VA may prevent an external impact applied to the display device 10 from being transmitted to the elements of the pixel circuit. In addition, since the display device 10 includes a valley VA surrounding an area where the pixel circuit PXC is arranged, cracks that may be formed in a plurality of insulating layers when the display device 10 including the flexible substrate 110 is folded may be prevented. However, this is not limited to this. In some embodiments, the valley VA may also be formed as a pattern that does not completely surround the unit pixel area UPX but extends in one direction and is separated from other valleys VA.

[0127] Fig. 9 is along Figure 8 Cross-sectional view taken along line IX-IX′. Fig.10 is magnified and shows Fig. 9 Figure 4 shows the valley portion of the graph.

[0128] Fig. 9 A cross section of a portion of the display area DA corresponding to a region where one unit pixel region UPX is arranged is schematically shown. Fig. 9A cross section spanning a portion of the first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 is shown. Fig.10 Further zooming in shows Fig. 9 The valley of VA.

[0129] Reference Fig. 9 The display panel 100 may include a substrate 110, a circuit layer 120, a light emitting element layer 130 and an encapsulation layer 140 disposed on the substrate 110. The circuit layer 120, the light emitting element layer 130 and the encapsulation layer 140 may be sequentially disposed or stacked on the substrate 110 along the third direction DR3.

[0130] The substrate 110 may be formed of a material having flexible properties such as bending, folding, and rolling. The substrate 110 may be formed of an insulating material such as a polymer resin. As an example, the substrate 110 may be formed of polyimide.

[0131] The circuit layer 120 may include a pixel circuit PXC and wiring. For example, the circuit layer 120 may include circuit elements constituting the pixel circuit PXC of each sub-pixel SPX (as an example, a pixel transistor T and a capacitor Cst) and wiring electrically connected to the sub-pixel SPX (as an example, various power wirings including a power wiring PL, a scan wiring SL, a light emission control wiring ECL, and a data wiring DL, and signal wiring).

[0132] Fig. 9 The first thin film transistor TFT1 (also referred to as "first pixel transistor"), the second thin film transistor TFT2 (also referred to as "second pixel transistor"), and the capacitor Cst included in the pixel circuit PXC of each sub-pixel SPX in the elements that can be provided in the circuit layer 120 are illustrated. The first thin film transistor TFT1 can represent a first type transistor (as an example, a P-type transistor) containing a first semiconductor material (as an example, polysilicon) in the pixel transistor T constituting each pixel circuit PXC. For example, the first thin film transistor TFT1 can be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and / or the eighth transistor T8. Fig. 9 In the embodiment, as the first thin film transistor TFT1, a transistor (as an example, a first connection electrode CNE1 and a second connection electrode CNE2) connected to the light emitting element EL through at least one connection electrode (as an example, a first connection electrode CNE1 and a second connection electrode CNE2) among the first type transistors is exemplified. Figure 5 or Figure 6The second thin film transistor TFT2 may represent a second type transistor (as an example, an N-type transistor) containing a second semiconductor material (as an example, an oxide semiconductor) in the pixel transistor T. For example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0133] The cross section of the subpixel SPX may be variously changed according to the type and / or structure of each subpixel SPX and the display panel 100 including the subpixel SPX. For example, the positions and formation order of the first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may vary according to the embodiment.

[0134] The circuit layer 120 may include a semiconductor layer for forming circuit elements, wirings, and the like, a conductive layer, and an insulating film disposed between and / or around the conductive layer and the semiconductor layer. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (as an example, a polycrystalline silicon semiconductor layer), a first insulating layer 123 (as an example, a first gate insulating film), a first conductive layer CDL1 (as an example, a first gate conductive layer), a second insulating layer 124 (as an example, a second gate insulating layer), a second conductive layer CDL2 (as an example, a second gate conductive layer), a third insulating layer 125 (as an example, a first interlayer insulating layer), a second semiconductor layer SCL2 (as an example, an oxide semiconductor layer), a fourth insulating layer 126 (as an example, a third gate insulating layer), a third conductive layer CDL3 (as an example, a third gate conductive layer), a fifth insulating layer 127 (as an example, a second interlayer insulating layer), a fourth conductive layer CDL4 (as an example, a first source-drain conductive layer), and a sixth insulating layer 128 (as an example, a first through-hole layer or a first planarization film). In one embodiment, the circuit layer 120 may further include a fifth conductive layer CDL5 (as an example, a second source-drain conductive layer) and a seventh insulating layer 129 (as an example, a second via layer or a second planarization layer) sequentially arranged on the sixth insulating layer 128. In one embodiment, the circuit layer 120 may further include a lower conductive layer BCDL arranged between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 arranged between the substrate 110 and the lower conductive layer BCDL, and a buffer layer 122 arranged between the lower conductive layer BCDL and the first semiconductor layer SCL1.

[0135] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed on the circuit layer 120 and the light emitting element layer 130 from the moisture penetrating through the moisture permeable substrate 110. The barrier layer 121 may include at least one inorganic film containing an inorganic insulating substance (as an example, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating substances). The substance of the barrier layer 121 may be variously changed according to the embodiment.

[0136] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML and / or at least one wiring (or a portion of the at least one wiring) overlapping with an active layer (as an example, the first active layer ACT1 and / or the second active layer ACT2) of at least one pixel transistor T. Fig. 9 , the lower metal layer BML is arranged to overlap only the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst, but the present invention is not limited thereto. For example, the lower metal layer BML may be patterned into an appropriate size and / or shape as required and arranged in a portion of the pixel circuit PXC, or may be arranged in the entire pixel circuit PXC. As an example, the lower metal layer BML may also be arranged in a manner similar to that of the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst. Figure 5 and Figure 6 The first transistor T1 disclosed in the disclosure is only arranged in a part of the pixel area in an overlapping manner. In one embodiment, the lower metal layer BML can also be used as a light shielding pattern and / or a back gate electrode of at least one pixel transistor T, etc.

[0137] The buffer layer 122 may be disposed on the lower conductive layer BCDL so as to cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic film including an inorganic insulating substance.

[0138] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be arranged on one surface of the substrate 110 including the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In one embodiment, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0139] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and / or the eighth transistor T8.

[0140] The first active layer ACT1 may be provided on the first semiconductor layer SCL1 and include a first semiconductor material (as an example, polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping ions or impurities into the semiconductor used to form the first active layer ACT1. In one embodiment, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In one embodiment, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0141] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0142] The first conductive layer CDL1 may be arranged on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be arranged to overlap a portion of the first active layer ACT1 (as an example, the first channel region CH1). In an embodiment, the first conductive layer CDL1 may further include at least one wiring (or a portion of the at least one wiring), a conductive pattern (as an example, a bridge pattern) and / or a capacitor electrode. As an example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of the capacitor Cst.

[0143] In one embodiment, the first capacitor electrode CAE1 may be formed integrally with the gate electrode of at least one first thin film transistor TFT1. Figure 5 and Figure 6The gate electrode of the first transistor T1 illustrated in FIG. 1 is formed as one body. As an example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed of one conductive pattern, and the second capacitor electrode CAE2 may be arranged to overlap the conductive pattern.

[0144] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0145] The second conductive layer CDL2 may be arranged on the second insulating layer 124. The second conductive layer CDL2 may include an electrode of the capacitor Cst, and as an example, may include a second capacitor electrode CAE2. In one embodiment, the second conductive layer CDL2 may also include at least one electrode, a wiring (or a portion of the at least one wiring) and / or a conductive pattern (as an example, a bridge pattern). For example, the second conductive layer CDL2 may also include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0146] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0147] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include a second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4.

[0148] The second active layer ACT2 may be provided on the second semiconductor layer SCL2 and include a second semiconductor material (as an example, an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn) and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn) and oxygen (O)).

[0149] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CH2, and the second drain region D2 may be arranged on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be regions that have conductivity by doping ions or impurities into the semiconductor used to form the second active layer ACT2. In one embodiment, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In one embodiment, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0150] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0151] In one embodiment, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be an inorganic insulating film containing an inorganic insulating material (as an example, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). And each may have a single-layer or multi-layer structure. At least two insulating layers of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may contain the same material, or may contain different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be varied according to the embodiment.

[0152] The third conductive layer CDL3 may be arranged on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be arranged to overlap a portion of the second active layer ACT2 (as an example, the second channel region CH2). In an embodiment, the third conductive layer CDL3 may further include at least one wiring (or a portion of the at least one wiring), a conductive pattern (as an example, a bridge pattern) and / or a capacitor electrode.

[0153] In one embodiment, each electrode, conductive pattern and / or wiring provided in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CLD3 may include a conductive substance (as an example, at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, their alloys or other conductive substances), and may have a single-layer or multi-layer structure. For example, each electrode, conductive pattern and / or wiring provided in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CLD3 may include molybdenum (Mo) or other metal substances. At least two conductive layers of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CLD3 may include the same substance, or may include different substances. The materials of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CLD3 are not limited and may be variously changed according to embodiments.

[0154] The valley VA may be formed to penetrate at least a portion of the plurality of insulating layers arranged on the substrate 110. For example, the valley VA may penetrate at least a portion of the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126. The valley VA may penetrate at least a portion of the plurality of insulating layers overlapping the first thin film transistor TFT1 and the second thin film transistor TFT2. The valley VA may have a maximum depth when it is formed to penetrate all of the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126. Fig. 9 , an embodiment is illustrated in which the valley VA is formed to penetrate all of the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 and only penetrate a portion of the barrier layer 121. Accordingly, the bottom surface of the valley VA can become a portion of the upper surface of the barrier layer 121 that is recessed due to the valley VA. The upper surface of the barrier layer 121 is exposed due to the formation of the valley VA, so that the thickness of the exposed portion can be thinner. For example, the thickness H2 of the portion of the barrier layer 121 that becomes the bottom surface of the valley VA can be less than the thickness H1 of the portion that does not overlap with the valley VA.

[0155] However, the present invention is not limited thereto. The valley VA may also be formed to completely penetrate the barrier layer 121 , thereby exposing a portion of the upper surface of the substrate 110 . In this case, the bottom surface of the valley VA may become the upper surface of the substrate 110 .

[0156] The valley VA may be formed not to penetrate the semiconductor layers SCL1, SCL2 and the conductive layers CDL1, CDL2, CDL3 disposed between the barrier layer 121 and the fourth insulating layer 126. Among the valleys VA, the depth of the valleys VA formed at the portions overlapping the semiconductor layers SCL1, SCL2 and the conductive layers CDL1, CDL2, CDL3 may be smaller. Fig. 9 As the portion of the valley VA that does not overlap with the semiconductor layers SCL1, SCL2 and the conductive layers CDL1, CDL2, CDL3, a portion of the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 are exemplified. However, the valley VA may overlap with at least one of the semiconductor layers SCL1, SCL2 and the conductive layers CDL1, CDL2, CDL3 depending on the position, in which case the depth thereof may be smaller.

[0157] The valley VA can protect the circuit elements from external impact applied to the display device 10. The valley VA can be formed by a process of etching the lower insulating layer before forming the fourth conductive layer CDL4. The process of forming the valley VA can be performed together with the process of etching the insulating layer to connect the existing third conductive layer CDL3 and the conductive layer or semiconductor layer below it. The display device 10 has the following advantages in the manufacturing process: in the process of forming the through hole of the conductive layer, the valley VA can be formed in the display area DA without adding an additional mask.

[0158] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3. In addition, the fifth insulating layer 127 may cover the inner sidewall of the valley VA.

[0159] According to an embodiment, the fifth insulating layer 127 may include a first inorganic layer IL1 and a second inorganic layer IL2 disposed on the first inorganic layer IL1. The first inorganic layer IL1 may be directly disposed on the fourth insulating layer 126, the third conductive layer CDL3, and the inner sidewall of the valley VA. The first inorganic layer IL1 may also be in direct contact with the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, and the third insulating layer 125 at the inner sidewall of the valley VA. The first inorganic layer IL1 may be in direct contact with a portion of the upper surface of the barrier layer 121 forming the bottom surface of the valley VA.

[0160] The first inorganic layer IL1 and the second inorganic layer IL2 may include insulating materials, respectively, and may include materials different from each other. In one embodiment, the first inorganic layer IL1 may include silicon oxide (SiO x ), and the second inorganic layer IL2 may include silicon nitride (SiN x). The fifth insulating layer 127 may cover the inner sidewall of the valley VA, thereby preventing the gas generated when forming the sixth insulating layer 128 described later from deteriorating the adjacent circuit elements. In particular, the second thin film transistor TFT2 may include a second active layer ACT2 including an oxide semiconductor, the sixth insulating layer 128 may include an organic insulating substance, and the fifth insulating layer 127 may prevent the gas generated in the sixth insulating layer 128 from moving to the second active layer ACT2. The fifth insulating layer 127 includes a plurality of layers, and the second inorganic layer IL2 disposed on the upper portion includes silicon nitride (SiN x ), thereby effectively preventing the gas generated in the manufacturing process from moving toward the second active layer ACT2.

[0161] The fifth insulating layer 127 covers the inner sidewall of the valley VA, so that the first inorganic layer IL1 and the second inorganic layer IL2 can be arranged at the same height as at least the second semiconductor layer SCL2 in the valley VA. For example, the first inorganic layer IL1 and the second inorganic layer IL2 can overlap the second semiconductor layer SCL2 in a direction parallel to the upper surface of the substrate 110. The first inorganic layer IL1 and the second inorganic layer IL2 are arranged between the second semiconductor layer SCL2 and the organic insulating substance arranged in the valley VA, so that gas can be prevented from moving from the organic insulating substance to the second semiconductor layer SCL2, and the second semiconductor layer SCL2 can be prevented from being degraded.

[0162] According to an embodiment, the shortest spacing distance DC between the second active layer ACT2 including an oxide semiconductor and the fifth insulating layer 127 arranged in the valley VA may be 3 μm or less. In the case where the valley VA is formed in a region within 10 μm from the second semiconductor layer SCL2, the gas generated by the organic substance filling the valley VA may cause degradation of the second semiconductor layer SCL2. In order to prevent this, the inner side wall of the valley VA generated in the region within 3 μm from the second semiconductor layer SCL2 may be covered by the fifth insulating layer 127, and the shortest spacing distance between the second active layer ACT2 and the fifth insulating layer 127 may be 3 μm or less.

[0163] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided on the fourth conductive layer CDL4 and connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be provided on the fourth conductive layer CDL4 and may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridge electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In an embodiment, the fourth conductive layer CDL4 may further include at least one wiring (or a portion of the at least one wiring) and / or a conductive pattern (as an example, a bridge pattern). As an example, the fourth conductive layer CDL4 may include a portion of a power wiring PL (as an example, a first pixel power wiring VDL and / or a second pixel power wiring VSL) provided inside and / or outside the display area DA.

[0164] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4. In addition, the sixth insulating layer 128 may fill the inside of the valley VA and may be directly disposed on the second inorganic layer IL2 of the fifth insulating layer 127.

[0165] The fifth conductive layer CDL5 may be arranged on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be provided on the fifth conductive layer CDL5 and connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) penetrating the sixth insulating layer 128. In one embodiment, the fifth conductive layer CDL5 may further include at least one wiring (or a portion of the at least one wiring) and / or a conductive pattern (as an example, a bridge pattern). As an example, the fifth conductive layer CDL5 may include a portion of a power wiring PL (as an example, a first pixel power wiring VDL and / or a second pixel power wiring VSL) provided inside and / or outside the display area DA.

[0166] In one embodiment, the respective electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may contain a conductive substance (as an example, at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals in addition thereto, their alloys or other conductive substances in addition thereto), and may have a single-layer or multi-layer structure. For example, the respective electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed into a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may contain the same substance as each other, or may contain different substances from each other. The substance of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be variously changed according to the embodiment.

[0167] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0168] In one embodiment, for the flattening of the circuit layer 120, the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating film containing an organic insulating substance (as an example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or other organic insulating substances other than these), and may have a single-layer or multi-layer structure, respectively. The sixth insulating layer 128 and the seventh insulating layer 129 may contain the same substance as each other, or may contain different substances from each other. The substance of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be variously changed according to the embodiment.

[0169] The light emitting element layer 130 may include a pixel definition film 131 that divides the light emitting area EA of the pixel PX and each light emitting element EL located in each light emitting area EA. In one embodiment, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel definition film 131 .

[0170] Each light emitting element EL may include a first electrode ET1 (as an example, an anode electrode) connected to at least one pixel transistor T (as an example, a first thin film transistor TFT1) included in a corresponding sub-pixel SPX through a first connection electrode CNE1 and / or a second connection electrode CNE2, etc., and a light emitting layer EML and a second electrode ET2 (as an example, a cathode electrode) sequentially arranged on the first electrode ET1. In an embodiment, the light emitting element EL may further include a first intermediate layer (as an example, a hole layer including a hole transport layer) sandwiched between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (as an example, an electron layer including an electron transport layer) sandwiched between the light emitting layer EML and the second electrode ET2.

[0171] The first electrode ET1 of the light emitting element EL may include a conductive substance and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 corresponding to each light emitting area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) penetrating the seventh insulating layer 129.

[0172] In one embodiment, the first electrode ET1 may include a metal material with high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO: Induim-Tin-Oxide), indium zinc oxide (IZO: Induim-Zinc-Oxide), zinc oxide (ZnO: Zinc Oxide), indium oxide (In 2 O 3 : Induim Oxide) and a multilayer structure of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (as an example, ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.).

[0173] The light-emitting layer EML of the light-emitting element EL may contain a polymer substance or a low-molecular substance. In one embodiment, the light-emitting layer EML may be arranged according to each sub-pixel SPX, and the light-emitting layer EML of each sub-pixel SPX may emit visible light of a color corresponding to the corresponding sub-pixel SPX. In another embodiment, the light-emitting layer EML may be a common layer shared by sub-pixels SPX of different colors from each other, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light to be emitted from each sub-pixel SPX may be arranged in the light-emitting area EA of at least a portion of the sub-pixels SPX.

[0174] The second electrode ET2 of the light emitting element EL may include a conductive material and may be connected to the second pixel power supply wiring VSL. In one embodiment, the second electrode ET2 may be a common layer formed in the entire display area DA in the form of covering the light emitting layer EML and the pixel definition film 131. In one embodiment, the second electrode ET2 may be composed of a transparent metal material (transparent conductive material (TCO)) such as ITO and IZO that can transmit light, or may be composed of a semi-transmissive metal material (semi-transmissive conductive material) such as magnesium (Mg), silver (Ag) or an alloy of magnesium (Mg) and silver (Ag). In the case where the second electrode ET2 is composed of a semi-transmissive metal material, it is expected that the light output efficiency will be improved by using the micro cavity effect.

[0175] The pixel definition film 131 may have an opening corresponding to each light emitting area EA and may surround the light emitting area EA. For example, the pixel definition film 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL and may include an opening exposing the remaining portion of the first electrode ET1. The area where the exposed first electrode ET1 overlaps with the light emitting layer EML (or the area including it) may be defined as the light emitting area EA of each pixel PX.

[0176] In one embodiment, the pixel definition film 131 may include at least one organic film including an organic insulating material. For example, the pixel definition film 131 may include polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB) resin or other organic insulating materials.

[0177] The spacer 132 may be arranged on a portion of the pixel definition film 131. The spacer 132 may include at least one organic film containing an organic insulating substance. The spacer 132 may contain the same substance as the pixel definition film 131, or may contain a substance different from the pixel definition film 131. In one embodiment, the pixel definition film 131 and the spacer 132 may be formed sequentially by respective mask processes. In another embodiment, the pixel definition film 131 and the spacer 132 may be formed simultaneously using a halftone mask. In this case, the pixel definition film 131 and the spacer 132 may also be regarded as an insulating film that is integrated with each other. The organic insulating substance constituting the spacer 132 is not particularly limited, and it may be varied according to the embodiment.

[0178] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may block the penetration of oxygen or moisture to the light emitting element layer 130, and may mitigate electrical or physical impacts to the circuit layer 120 and the light emitting element layer 130.

[0179] In one embodiment, the encapsulation layer 140 may include a first inorganic encapsulation film 141, an organic encapsulation film 142, and a second inorganic encapsulation film 143 sequentially arranged on the light emitting element layer 130. The first inorganic encapsulation film 141 and the second inorganic encapsulation film 143 may include inorganic substances, and the organic encapsulation film 142 may include organic substances.

[0180] The display device 10 according to an embodiment may include a valley VA surrounding a region where a plurality of pixel circuits PXC are arranged and a fifth insulating layer 127 covering the inner sidewall of the valley VA. The valley VA of the display device 10 can prevent the circuit elements from being damaged by an impact applied from the outside of the display device 10. In addition, in the case where the display device 10 has a flexible characteristic, cracks (Crack) that may be formed in a plurality of insulating layers arranged thereon when the substrate 110 is folded can be prevented by the valley VA. Further, the display device 10 includes the fifth insulating layer 127 arranged on the inner sidewall of the valley VA, so that the degradation of the oxide semiconductor caused by the gas generated by the organic substance filling the valley VA can be prevented.

[0181] Hereinafter, a manufacturing process of the display device 10 will be described with reference to other drawings.

[0182] Figures 11 to 17 FIG. 1 is a diagram sequentially showing a part of a manufacturing process of a display device according to an embodiment.

[0183] First, refer to Fig.11, a barrier layer 121, a lower conductive layer BCDL, a buffer layer 122, a first semiconductor layer SCL1, a first insulating layer 123, a first conductive layer CDL1, a second insulating layer 124, a second conductive layer CDL2, a third insulating layer 125, a second semiconductor layer SCL2, and a fourth insulating layer 126 are formed on the substrate 110. The lower conductive layer BCDL, the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer CDL1, and the second conductive layer CDL2 may be formed by depositing materials forming them and then patterning the deposited layers according to a specific shape. The barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be formed by depositing materials forming corresponding layers on the entire upper surface of the substrate 110. Their formation processes may be processes commonly used in the technical field of the present invention.

[0184] Reference Fig.12 In the etching process of exposing a portion of the second conductive layer CDL2, a gate contact hole GCT penetrating the third insulating layer 125 and the fourth insulating layer 126 and a valley VA penetrating at least a portion of the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125 and the fourth insulating layer 126 are formed. This process can be formed by a process of etching multiple insulating layers. The process of forming the gate contact hole GCT can be an etching process for forming a path for electrically connecting a portion of the third conductive layer CDL3 arranged on the fourth insulating layer 126 to the second conductive layer CDL2 arranged thereunder. In the process of forming the gate contact hole GCT, the valley VA can be formed simultaneously without adding a separate mask. The valley VA can penetrate the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125 and the fourth insulating layer 126, and only penetrate a portion of the barrier layer 121, so that the bottom surface of the valley VA can become the upper surface of the barrier layer 121. Thus, the local thickness of the barrier layer 121 may become different.

[0185] Then, refer to Fig.13 , a third conductive layer CDL3 is formed on the fourth insulating layer 126. A portion of the third conductive layer CDL3 (eg, the second gate electrode G2) may contact the back gate electrode BG of the second conductive layer CDL2 through the gate contact hole GCT.

[0186] Next, refer to Fig.14 and Fig.15, a first inorganic layer IL1 and a second inorganic layer IL2 are sequentially formed on the fourth insulating layer 126 and the third conductive layer CDL3 to form a fifth insulating layer 127. The first inorganic layer IL1 may be directly disposed on the fourth insulating layer 126 and the third conductive layer CDL3, and may be in direct contact with the inner sidewall of the valley VA. The first inorganic layer IL1 may be in direct contact with the barrier layer 121 at the bottom surface of the valley VA. The second inorganic layer IL2 may be disposed on the first inorganic layer IL1. The second active layer ACT2 around the valley VA may be separated from the space inside the valley VA by the second inorganic layer IL2.

[0187] In one embodiment, the first inorganic layer IL1 and the second inorganic layer IL2 may include different insulating materials (for example, the first inorganic layer IL1 includes silicon oxide, and the second inorganic layer IL2 includes silicon nitride), so that they can be formed in separate deposition processes. x ) and is disposed on the upper portion of the first inorganic layer IL1, which can effectively prevent moisture permeation caused by external air.

[0188] Next, refer to Fig.16 and Fig.17 , contact holes CT1, CT2, CT3 are formed penetrating at least a portion of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127, and a fourth conductive layer CDL4 is formed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a plurality of bridge electrodes BE1, BE2 and a connection electrode CNE1, which may function as source electrodes or drain electrodes of the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0189] Next, although not shown in the drawings, a sixth insulating layer 128, a second connection electrode CNE2, a seventh insulating layer 129, a light emitting element layer 130, and an encapsulation layer 140 are formed on the fourth conductive layer CDL4. The sixth insulating layer 128 may include an organic insulating substance, and the sixth insulating layer 128 may fill the inside of the valley VA. However, the gas generated in the formation process of the sixth insulating layer 128 may be blocked from moisture permeation by the inorganic layers IL1 and IL2 of the fifth insulating layer 127, and the second active layer ACT2 and the second thin film transistor TFT2 around the valley VA may be prevented from being degraded.

[0190] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0191] Fig.18 is a plan view showing an arrangement of a plurality of pixels and valleys arranged in a display area of ​​a display device according to another embodiment.

[0192] Reference Fig.18 In a display device 10_1 according to another embodiment, the valley VA may have a shape extending in the second direction DR2 and may be arranged in a linear pattern spaced apart from each other in the first direction DR1. The valley VA may be arranged only between the unit pixel regions UPX1, UPX2, UPX3, and UPX4 adjacent to each other in the first direction DR1, and not between the unit pixel regions UPX1, UPX2, UPX3, and UPX4 adjacent to each other in the second direction DR2. The valley VA is formed by passing through a plurality of insulating layers, and therefore, when formed by extending in the first direction DR1, it may partially overlap with the wiring extending in the second direction DR2. In this case, the wiring may be damaged in the process of forming the valley VA, and therefore, on the premise of ensuring the impact resistance characteristics of the display device 10_1, the valley VA may also be arranged only partially.

[0193] For example, Fig.18 As shown, in the display device 10_1, the valley VA may extend along the second direction DR2 at the boundary of the unit pixel regions UPX1, UPX2, UPX3, UPX4, rather than extending along the first direction DR1. Accordingly, at the boundary of the unit pixel regions UPX1, UPX2, UPX3, UPX4 adjacent to each other in the second direction DR2, a plurality of wirings may be arranged without spatial restriction.

[0194] Fig.19 is a cross-sectional view showing a portion of a display device according to another embodiment.

[0195] Reference Fig.19 In the display device 10_2 according to another embodiment, the valley VA_2 may be formed to completely penetrate the barrier layer 121. The valley VA_2 may completely penetrate the barrier layer 121, and the bottom surface of the valley VA_2 may become the upper surface of the substrate 110. Thus, the first inorganic layer IL1 of the fifth insulating layer 127 may be in direct contact with the upper surface of the substrate 110, and may be in contact with the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 at the inner side surface of the valley VA_2. The valley VA_2 may be formed together in the process of forming the gate contact hole GCT, and the barrier layer 121 may be completely penetrated according to the conditions of the etching process.

[0196] Fig. 20 is a cross-sectional view showing a portion of a display device according to still another embodiment.

[0197] Reference Fig. 20According to another embodiment, the display device 10_3 may further include a filling layer FIL_3 filling the inside of the valley VA_3 and arranged on the second inorganic layer IL2 of the fifth insulating layer 127. The filling layer FIL_3 may include an organic insulating substance to fill the inside of the valley VA_3. The filling layer FIL_3 may fill the step formed by the valley VA_3, and a wiring SDV arranged on the fourth conductive layer CDL4 and electrically connected to at least one of the first thin film transistor TFT1 and the second thin film transistor TFT2 may also be arranged on the filling layer FIL_3.

[0198] As the valley VA_3 is arranged in the display area DA, a large step difference may be formed between the periphery of the valley VA_3 and the inside of the valley VA_3. As described above, as the valley VA_3 extends along the first direction DR1 and / or the second direction DR2, a portion of the wiring SDV extending in one direction in the display area DA may also cross the valley VA_3. A portion of the wiring SDV may be arranged to overlap the valley VA_3 on the filling layer FIL_3. The filling layer FIL_3 may be arranged to fill the inside of the valley VA_3, and even if the wiring SDV extending in one direction crosses the valley VA_3, the wiring SDV may be prevented from being disconnected due to the step difference.

[0199] The filling layer FIL_3 may include an organic insulating material and be formed along the valley VA_3, thereby actually flattening the step difference generated by the valley VA_3. The valley VA_3 may be arranged to extend along the first direction DR1 and / or the second direction DR2 at the boundary of the unit pixel regions UPX1, UPX2, UPX3, and UPX4, and the filling layer FIL_3 may also overlap with the valley VA_3 and extend along the first direction DR1 and / or the second direction DR2 at the boundary of the unit pixel regions UPX1, UPX2, UPX3, and UPX4. The filling layer FIL_3 may fill the inside of the valley VA_3, thereby flattening the plane on which the fourth conductive layer CDL4 is formed.

[0200] In addition, since the inner sidewall of the valley portion VA_3 is covered by the first inorganic layer IL1 and the second inorganic layer IL2 , even if the filling layer FIL_3 includes an organic insulating material, the gas generated during the manufacturing process can be blocked from moisture transmission by the second inorganic layer IL2 .

[0201] Fig.21 is a cross-sectional view showing a portion of a display device according to still another embodiment.

[0202] Reference Fig.21In a display device 10_4 according to yet another embodiment, the valley VA_4 may include a first valley VA1 and a second valley VA2 formed inside the first valley VA1 to penetrate the fifth insulating layer 127. If the first valley VA1 is formed to penetrate the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126, the second valley VA2 may be formed to penetrate the fifth insulating layer 127. The second valley VA2 may be formed to penetrate the fifth insulating layer 127 after forming the fifth insulating layer 127 covering the inner sidewall of the first valley VA1. The first valley VA1 and the second valley VA2 may be formed to overlap each other in the thickness direction, and their widths and depths may be different from each other. The second valley VA2 is substantially arranged inside the first valley VA1, so the width and depth of the second valley VA2 may be smaller than the width and depth of the first valley VA1.

[0203] For example, in an embodiment where the first valley VA1 is formed to penetrate the barrier layer 121, the second valley VA2 may penetrate the fifth insulating layer 127 to expose the upper surface of the substrate 110. The bottom surface of the second valley VA2 may become a part of the upper surface of the substrate 110. In an embodiment where the first valley VA1 is formed to penetrate only a part of the barrier layer 121, the second valley VA2 may penetrate the fifth insulating layer 127 and the barrier layer 121 to expose the upper surface of the substrate 110. The valley VA_4 includes a double valley VA1, VA2 structure, so that the impact resistance is more excellent, and when the display device 10_4 has a foldable feature, it can make a greater contribution to the flexibility of the display device 10_4.

[0204] According to an embodiment, the display device 10_4 may further include: a cover layer CPL_4, which is arranged on the second inorganic layer IL2 and arranged on the inner side wall of the valley VA_4; and a filling layer FIL_4, which fills the inside of the valley VA_4. Similar to the second inorganic layer IL2 of the fifth insulating layer 127, the cover layer CPL_4 may be arranged on the inner side wall of the valley VA_4 to prevent moisture penetration of external air. For example, the cover layer CPL_4 may be arranged on the inner side wall of the second valley VA2 and on the bottom surface of the second valley VA2. The cover layer CPL_4 may be in direct contact with the first inorganic layer IL1 and the second inorganic layer IL2 of the fifth insulating layer 127 on the upper surface of the substrate 110 and the inner side wall of the second valley VA2. In addition, the cover layer CPL_4 may be arranged on the second inorganic layer IL2 on the inner side wall of the first valley VA1. Gas generated in the formation process of the filling layer FIL_4 disposed inside the valley VA_4 may be blocked from moisture permeation toward the second active layer ACT2 by the second inorganic layer IL2 and the capping layer CPL_4 .

[0205] In some embodiments, the cover layer CPL_4 may include silicon nitride similar to the second inorganic layer IL2 . However, it is not limited thereto. The cover layer CPL_4 may also be formed of a metal wiring.

[0206] The filling layer FIL_4 may be arranged inside the valley portion VA_4 to fill the step difference generated by the valley portion VA_4. Thus, a wiring SDV may be arranged on the filling layer FIL_4. Fig. 20 The same instructions are performed.

[0207] According to an embodiment, the maximum width of the filling layer FIL_4 may be the same as the maximum width of the covering layer CPL_4. The filling layer FIL_4 and the covering layer CPL_4 may be formed by patterning according to the shape of the valley VA_4 after depositing the materials forming them. If the same mask is used in the patterning process of the filling layer FIL_4 and the covering layer CPL_4, two layers may be further arranged on the second inorganic layer IL2 even if only one mask is added. The display device 10_4 may minimize the increase of the mask, so that only one mask is used to form the covering layer CPL_4 and the filling layer FIL_4, respectively, and their maximum widths (for example, the width measured around the upper end of the valley VA_4) may be the same as each other.

[0208] Figure 22 to Figure 26 is shown in order Fig.21 FIG. 1 is a diagram of a portion of a manufacturing process of a display device.

[0209] First, refer to Fig. 22 , as referenced Figures 11 to 15 As described above, a barrier layer 121, a buffer layer 122, a lower conductive layer BCDL, a plurality of conductive layers CDL1, CDL2, CDL3, a plurality of insulating layers 123, 124, 125, 126, 127, a plurality of semiconductor layers SCL1, SCL2 and a first valley VA1 are formed on the substrate 110. The description of their formation processes is the same as the above description, so the detailed description will be omitted.

[0210] The first valley VA1 may be formed together in the formation process of the gate contact hole GCT, and may be formed to penetrate the barrier layer 121, the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126. The fifth insulating layer 127 may include the first inorganic layer IL1 and the second inorganic layer IL2 to cover the inner sidewall of the first valley VA1.

[0211] Next, refer to Fig.23, forming a first contact hole CT1, a second contact hole CT2, and a third contact hole CT3 penetrating at least a portion of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127, and a second valley VA2 penetrating the first inorganic layer IL1 and the second inorganic layer IL2 of the fifth insulating layer 127 in the first valley VA1. This process can be formed by a process of etching multiple insulating layers. The process of forming the first contact hole CT1, the second contact hole CT2, and the third contact hole CT3 can be an etching process for forming a path for electrically connecting a portion of the fourth conductive layer CDL4 arranged on the fifth insulating layer 127 to the conductive layers CDL1, CDL2, CDL3 and the semiconductor layers SCL1, SCL2 thereunder. In the process of forming the first contact hole CT1, the second contact hole CT2, and the third contact hole CT3, the second valley VA2 can be formed simultaneously without adding an additional mask. The second valley VA2 can be formed to penetrate the fifth insulating layer 127 arranged in the first valley VA1. Since the second valley VA2 is formed within the first valley VA1 , the width and depth of the second valley VA2 may be smaller than those of the first valley VA1 . A bottom surface of the second valley VA2 may be an upper surface of the substrate 110 .

[0212] Next, refer to Fig.24 and Fig.25 , forming a covering layer CPL_4 arranged on the inner side wall of the valley VA_4 and a filling layer FIL_4 arranged inside the valley VA_4. The covering layer CPL_4 and the filling layer FIL_4 can be fully coated on the fifth insulating layer 127, respectively, and then patterned according to the shape of the valley VA_4. The masks used in the process of forming the covering layer CPL_4 and the filling layer FIL_4 can be the same as each other, and their widths can be the same as each other. Alternatively, the covering layer CPL_4 and the filling layer FIL_4 can be patterned simultaneously in one mask process, and their edge portions can be aligned parallel to each other.

[0213] The capping layer CPL_4 may cover the inner sidewalls and bottom surface of the second valley VA2 and may be disposed on the second inorganic layer IL2 inside the first valley VA1 . The filling layer FIL_4 may fill the inside of the valley VA_4 and planarize the upper surface of the fifth insulating layer 127 .

[0214] Next, refer to Fig.26 , a fourth conductive layer CDL4 is formed on the fifth insulating layer 127, referring to Fig.21 A sixth insulating layer 128, a second connection electrode CNE2, a seventh insulating layer 129, a light emitting element layer 130, and an encapsulation layer 140 are formed on the fourth conductive layer CDL4, thereby manufacturing the display device 10_4.

[0215] The embodiments of the present invention are described above with reference to the accompanying drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the above embodiments are exemplary in all aspects and are not restrictive.

Claims

1. A display device, comprising: a barrier layer disposed on the substrate; a buffer layer disposed on the barrier layer; A first active layer of a first thin film transistor is arranged on the buffer layer; a first insulating layer, disposed on the first active layer; a first conductive layer disposed on the first insulating layer and comprising a first gate electrode overlapping the first active layer; a second insulating layer, arranged on the first conductive layer; a second conductive layer disposed on the second insulating layer and comprising a back gate electrode overlapping the second active layer of the second thin film transistor; a third insulating layer, arranged on the second conductive layer; The second active layer is arranged on the third insulating layer; a fourth insulating layer, arranged on the second active layer; a valley portion, penetrating the barrier layer, the buffer layer, and the first insulating layer to at least a portion of the fourth insulating layer, and not overlapping the first active layer and the second active layer; a third conductive layer disposed on the fourth insulating layer and comprising a second gate electrode overlapping the second active layer; a fifth insulating layer, arranged on the third conductive layer and the fourth insulating layer, and covering the inner side wall of the valley; as well as a light emitting element, arranged on the fifth insulating layer and electrically connected to the first thin film transistor and the second thin film transistor respectively; The fifth insulating layer includes a first inorganic layer and a second inorganic layer, wherein the first inorganic layer is directly arranged on the inner side wall of the valley, and the second inorganic layer includes a material different from that of the first inorganic layer and is arranged on the first inorganic layer.

2. The display device according to claim 1, wherein: The first inorganic layer comprises silicon oxide, The second inorganic layer includes silicon nitride.

3. The display device according to claim 1, wherein: The valley portion is formed so as to recess a portion of the upper surface of the barrier layer or the buffer layer. The first inorganic layer is in direct contact with a portion of an upper surface of the barrier layer or the buffer layer.

4. The display device according to claim 3, wherein: A thickness of a portion of the barrier layer that forms a bottom surface of the valley portion is smaller than a thickness of a portion of the barrier layer that does not overlap with the valley portion.

5. The display device according to claim 3, wherein: The first inorganic layer is in direct contact with the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer at inner side walls of the valley portion, respectively.

6. The display device according to claim 1, wherein: The valley is formed to penetrate the barrier layer and expose the upper surface of the substrate. The first inorganic layer is in direct contact with the substrate.

7. The display device according to claim 1, further comprising: a filling layer filling the interior of the valley and arranged on the second inorganic layer, Wherein, the filling layer contains organic insulating material.

8. The display device according to claim 7, further comprising: a wiring electrically connected to at least one of the first thin film transistor and the second thin film transistor, At least one of the wirings is arranged to overlap the valley portion on the filling layer.

9. The display device according to claim 1, wherein: The valley portion includes a first valley portion and a second valley portion overlapping the first valley portion and penetrating the fifth insulating layer, Wherein, the second valley portion is arranged inside the first valley portion.

10. The display device according to claim 9, wherein: The depth of the second valley portion is smaller than the depth of the first valley portion, The width of the second valley portion is smaller than the width of the first valley portion.

11. The display device according to claim 9, further comprising: a covering layer disposed on the second inorganic layer on the valley portion and disposed on an inner side wall of the second valley portion; as well as The filling layer is arranged on the cover layer and fills the inside of the valley.

12. The display device according to claim 11, wherein: The maximum widths of the cover layer and the filling layer are identical to each other.

13. The display device according to claim 1, wherein: The interval distance between the valley portion and the second active layer is less than 3 μm.

14. The display device according to claim 1, wherein: The substrate includes a plurality of unit pixel regions where the first thin film transistor and the second thin film transistor are arranged, The valley portion is arranged at a boundary between adjacent unit pixel regions.

15. A method for manufacturing a display device, comprising the following steps: Forming a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second semiconductor layer, a third insulating layer, a second conductive layer and a fourth insulating layer on a substrate, and forming a gate contact hole penetrating the third insulating layer and a valley penetrating the second insulating layer to the fourth insulating layer; forming a fifth insulating layer including a first inorganic layer covering inner side walls of the valley portion and a second inorganic layer disposed on the first inorganic layer; and forming a plurality of contact holes penetrating the second insulating layer to at least a portion of the fourth insulating layer, and forming a plurality of bridge electrodes arranged on the fourth insulating layer and connected to at least one of the first semiconductor layer and the second semiconductor layer through the contact holes, in, The first inorganic layer and the second inorganic layer include materials different from each other.

16. The method for manufacturing a display device according to claim 15, wherein: The first inorganic layer comprises silicon oxide, The second inorganic layer includes silicon nitride.

17. The method for manufacturing a display device according to claim 15, wherein: A buffer layer disposed between the substrate and the first semiconductor layer and a barrier layer disposed between the buffer layer and the substrate are also formed. The valley portion is formed to penetrate the barrier layer or the buffer layer and to recess a portion of the upper surface of the barrier layer or the buffer layer. The first inorganic layer is in direct contact with a portion of an upper surface of the barrier layer or the buffer layer.

18. The method for manufacturing a display device according to claim 15, wherein: A buffer layer disposed between the substrate and the first semiconductor layer and a barrier layer disposed between the buffer layer and the substrate are also formed. wherein the valley is formed to penetrate the buffer layer and the barrier layer, The first inorganic layer is in direct contact with a portion of an upper surface of the substrate.

19. The method for manufacturing a display device according to claim 15, wherein: In the step of forming the plurality of contact holes, a portion of the first inorganic layer and a portion of the second inorganic layer penetrate through the inside of the valley portion, The valley portion includes a first valley portion and a second valley portion penetrating the first inorganic layer and the second inorganic layer.

20. The method for manufacturing a display device according to claim 19, further comprising the following steps: A capping layer disposed on the inner side wall of the second valley portion and the second inorganic layer and a filling layer filling the inside of the valley portion are formed.

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