Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel is provided with a plurality of pixel light-emitting units and a plurality of driving circuits, and each driving circuit comprises a storage capacitor and a plurality of transistors. The display panel comprises a substrate, an active layer and a first gate layer, wherein the active layer comprises a plurality of active areas; the first gate layer comprises a plurality of gates, the orthographic projection of each gate on the substrate and the orthographic projection of the corresponding active region on the substrate have an overlapping region, the gates and the active regions in the overlapping regions are constituent parts of the same transistor, and the regions, overlapped with the gates, of the active regions form channels of the transistor. Source and drain regions of the transistor are respectively formed in regions, positioned on two sides of the channel, of the active region; the transistor comprises a bypass transistor, and one source drain region of the bypass transistor is connected with the anodes of the pixel light-emitting units in two adjacent columns in the same row through an active layer. The current of the transistor can be effectively reduced, and the service life is prolonged.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, flexible OLED (Organic Light-Emitting Diode) display panels have been increasingly used. Represented by LTPS (Low Temperature Polysilicon), they have occupied most of the small and medium-sized market. In most terminal products, various sensors are integrated, such as fingerprint or infrared sensors. The application of these sensors requires a certain transmittance to ensure a sufficient signal-to-noise ratio. In related technologies, OLED display panels have a low lifespan, very tight layout design, and limited use. Summary of the invention

[0003] The present application provides a display panel and a display device that can effectively reduce transistor current and extend service life.

[0004] The embodiment of the present application provides a display panel, comprising a plurality of pixel light emitting units and a plurality of driving circuits, wherein the plurality of pixel light emitting units are arranged alternately along rows and columns and include an anode, a cathode, and a light emitting material located between the anode and the cathode, and the driving circuit includes a storage capacitor and a plurality of transistors; the display panel includes:

[0005] substrate;

[0006] an active layer, located on one side of the substrate, comprising a plurality of active regions; and

[0007] A first gate layer, located on a side of the active layer away from the substrate, includes a plurality of gates; wherein an orthographic projection of each gate on the substrate overlaps with an orthographic projection of a corresponding active region on the substrate, the gate and the active region in the overlapping region are components of the same transistor, an area of ​​the active region overlapping with the gate forms a channel of the transistor, and areas of the active region located on both sides of the channel respectively form source and drain regions of the transistor;

[0008] Wherein, the transistor comprises a bypass transistor, and a source-drain region of the bypass transistor is connected to anodes of the pixel light-emitting units in two adjacent columns in the same row through the active layer.

[0009] Optionally, the display panel also includes a second gate layer and a first source-drain electrode layer, the second gate layer is located on a side of the first gate layer away from the active layer, and the first source-drain electrode layer is located on a side of the second gate layer away from the first gate layer; the second gate layer includes a plurality of voltage control lines arranged side by side along the row, one of the voltage control lines is connected to another source-drain region of the bypass transistor through the first source-drain electrode layer, and is connected to the anodes of the pixel light-emitting units in two adjacent columns in the same row through the bypass transistor.

[0010] Optionally, the transistor includes a driving transistor and an initialization transistor, one source and drain region of the initialization transistor is connected to the voltage control line through the first source and drain electrode layer, and the other source and drain region of the initialization transistor is connected to the first gate layer through the first source and drain electrode layer, and is connected to the gates of the two driving transistors corresponding to the pixel light-emitting units in two adjacent columns in the same row.

[0011] Optionally, the second gate layer includes a plurality of driving power lines arranged side by side along a row; the transistor includes a compensation transistor, and an orthographic projection of an active area of ​​the compensation transistor on the substrate and an orthographic projection of the driving power line on the substrate have an overlapping area, and the overlapping area forms a compensation capacitor of the compensation transistor, wherein the active area of ​​the compensation transistor serves as one capacitor plate of the compensation capacitor, and the second gate layer serves as another capacitor plate of the compensation capacitor.

[0012] Optionally, one of the compensation transistors corresponding to the pixel light emitting units in two adjacent columns in the same row forms a compensation capacitor.

[0013] Optionally, the capacitance value of the compensation capacitor corresponding to each of the pixel light-emitting units is the same or different.

[0014] Optionally, the transistor includes a switching transistor, the gate of the driving transistor is connected to a source-drain region of the compensation transistor through the active region, one source-drain region of the driving transistor is connected to another source-drain region of the compensation transistor through the first source-drain electrode layer, and the other source-drain region of the driving transistor is connected to a source-drain region of the switching transistor through the first source-drain electrode layer.

[0015] Optionally, the display panel also includes a second source-drain electrode layer, located on a side of the first source-drain electrode layer away from the second gate layer; the pixel light-emitting unit is located on a side of the second source-drain electrode layer away from the first source-drain electrode layer; the second source-drain electrode layer includes a plurality of data lines and a plurality of power lines arranged side by side along a column, the plurality of data lines and the plurality of power lines are staggered, and are all connected to the active layer in turn through the first source-drain electrode layer.

[0016] Optionally, the first gate layer includes a plurality of gate lines arranged side by side along a row, and the orthographic projections of the plurality of gate lines on the substrate partially overlap with the orthographic projections of the corresponding active areas on the substrate; the transistor includes a switching transistor, a compensation transistor and an initialization transistor, and the plurality of gate lines are respectively connected to the gate of the switching transistor, the gate of the compensation transistor and the gate of the initialization transistor through the active area.

[0017] Optionally, the first gate layer includes light-emitting control signal lines arranged along rows, and the orthographic projections of the light-emitting control signal lines on the substrate partially overlap with the orthographic projections of the corresponding active areas on the substrate; the transistor includes a driving control transistor and an emission control transistor, and the light-emitting control signal lines are respectively connected to the gates of the driving control transistor and the gates of the emission control transistor through the active areas.

[0018] The present application also provides a display device, comprising a display panel as described in any one of the above embodiments.

[0019] The display panel and display device provided by the embodiments of the present application connect a source-drain region of the bypass transistor to the anodes of the pixel light-emitting units in two adjacent columns in the same row through the active layer. In this way, the pixel light-emitting units in two adjacent columns in the same row share the same bypass transistor, which can reduce the number of bypass transistors and the number of wirings, and can spare more layout space, so that there is more space to design the capacitor formed between the active layer and the first gate layer, which can increase the capacitance value of the capacitor, effectively reduce the transistor current, and extend the service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a schematic diagram of an embodiment of a display panel of the present application.

[0021] Figure 2 for Figure 1 The driving circuit of the display panel.

[0022] Figure 3 for Figure 1 A cross-sectional schematic diagram of a display panel is shown.

[0023] Figure 4Shown is a schematic structural diagram of an embodiment of a display device of the present application. DETAILED DESCRIPTION

[0024] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0025] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" includes two, which is equivalent to at least two. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0026] The present application provides a display panel and a display device. The display panel has a plurality of pixel light-emitting units and a plurality of driving circuits. The plurality of pixel light-emitting units are arranged at intervals along rows and columns, and include an anode, a cathode, and a light-emitting material located between the anode and the cathode. The driving circuit includes a storage capacitor and a plurality of transistors. The display panel includes a substrate, an active layer, and a first gate layer. The active layer is located on one side of the substrate and includes a plurality of active regions. The first gate layer is located on a side of the active layer away from the substrate and includes a plurality of gates. The positive projection of each gate on the substrate and the positive projection of the corresponding active region on the substrate have an overlapping region. The gate and the active region in the overlapping region are components of the same transistor. The region of the active region that overlaps with the gate forms a channel of the transistor. The regions of the active region located on both sides of the channel respectively form source and drain regions of the transistor. The transistor includes a bypass transistor, and a source and drain region of the bypass transistor is connected to the anodes of the pixel light-emitting units in two adjacent columns in the same row through the active layer.

[0027] The display panel and display device provided by the embodiments of the present application connect a source-drain region of the bypass transistor to the anodes of the pixel light-emitting units in two adjacent columns in the same row through the active layer. In this way, the pixel light-emitting units in two adjacent columns in the same row share the same bypass transistor, which can reduce the number of bypass transistors and the number of wirings, and can spare more layout space, so that there is more space to design the capacitor formed between the active layer and the first gate layer, which can increase the capacitance value of the capacitor, effectively reduce the transistor current, and extend the service life.

[0028] In the application scenarios of OLED display panels, there is a phenomenon of low lifespan. At present, there are two factors that affect the screen life of OLED display panels: one is the aging of EL (Electroluminescence) materials, and the other is the reduction of TFT (Thin-Film Transistor) current. Studies have found that increasing the capacitance of the capacitor formed between the active layer and the first gate layer can effectively reduce the current of the transistor and extend the service life. In the related technology, the layout design of the screen of the OLED display panel is very tight, and the capacitance formed between the active layer and the first gate layer cannot be designed to a larger value. It can only be designed using the surrounding parasitic capacitance, and the improvement of the lifespan is very limited.

[0029] Therefore, the present application provides a display panel and a display device that can effectively reduce transistor current and extend service life. The display panel and the display device of the present application are described in detail below in conjunction with the accompanying drawings. The features of the following embodiments and implementations can be combined with each other without conflict.

[0030] Figure 1 FIG. 1 is a schematic diagram of an embodiment of a display panel 10 of the present application. Figure 2 for Figure 1 The driving circuit of the display panel 10. Figure 3 for Figure 1 The cross-sectional view of the display panel 10 is shown. Figures 1 to 3As shown, the display panel 10 has a plurality of pixel light-emitting units 101 and a plurality of driving circuits 102. The driving circuits 102 correspond to the pixel light-emitting units 101 one by one. Driven by the driving circuit 102, each pixel light-emitting unit 101 emits light and displays. The driving circuit 102 includes a storage capacitor and a plurality of transistors. By way of example, in this embodiment, the driving circuit may be a 7T1C type driving circuit, indicating that it includes 7 TFT transistors (Thin Film Transistor, thin film field effect transistor) and 1 storage capacitor Cst. By way of example, the 7 TFT transistors include T1, T2, T3, T4, T5, T6 and T7. In other embodiments, the driving circuit may be the commonly used 5T2C, 6T1C, 2T1C, 3T1C, 8T1C, 8T2C, etc. without limitation.

[0031] Combination Figures 1 to 3 As shown, the display panel 10 includes a substrate 103, an active layer 104, a first gate layer 105, a second gate layer 106, a first source-drain electrode layer 107, and a second source-drain electrode layer 108. The pixel light emitting unit 101 and the driving circuit 102 can be integrated on the substrate 103 by using a common semiconductor process.

[0032] exist Figure 2 In the illustrated embodiment, the base 103 includes a substrate 109 and a buffer layer 110 stacked in sequence from bottom to top. The substrate 109 may be a flexible substrate or a rigid substrate. The material of the flexible substrate may be PI (polyimide). The material of the rigid substrate may be glass. The buffer layer 110 is an optional film layer. The material of the buffer layer 110 may be silicon oxide, silicon nitride, silicon oxynitride, or a mixed film layer thereof.

[0033] exist Figure 2 In the embodiment shown, the active layer 104 is located on one side of the substrate 103. In this embodiment, the active layer 104 is stacked on the surface of the buffer layer 110, and its material can be polycrystalline silicon commonly used in the invention. The active layer 104 includes a plurality of active regions. Each active region corresponds to a transistor (e.g. Figure 1 For example, the driving circuit of this embodiment may be a 7T1C driving circuit, which has 7 transistors (T1 to T7) and 1 capacitor (Cst). Therefore, the active layer 104 is provided with 7 active regions. Figure 1 In the illustrated embodiment, the morphology and position distribution of the seven active regions of the active layer 104 can be seen in a top view. Figure 1 There are four pixel light emitting units 101 shown in the figure, and each pixel light emitting unit 101 is correspondingly provided with four driving circuits 102, and each driving circuit 102 includes seven transistors T1-T7. Figure 2 Only some of the transistors are shown. Figure 1 In the embodiment shown, Figure 1 On the upper left side of the center is the 7 active areas of a 7T1C type drive circuit. Figure 1 In the upper right middle are the seven active areas of another 7T1C type drive circuit. Similarly, Figure 1 The seven active regions on the lower left and lower right sides are symmetrically distributed along the center line. We only need to focus on the seven active regions of the two 7T1Cs in the adjacent columns of the same row, because their structures and connection relationships are basically the same and will not be described here. Figure 2 In the embodiment shown, it can be seen that the upper and lower positions of the active layer 104 are located on the surface of the buffer layer 110, and the active layer 104 does not cover the entire substrate 103. The formation process of the active layer 104 is usually to first form a whole layer of active material layer on the substrate 109 and the buffer layer 110, and then remove the active material layer in a part of the area by local etching, and the remaining active material layer forms the active layer 104.

[0034] exist Figure 2 In the illustrated embodiment, the first gate layer 105 is located on a side of the active layer 104 away from the substrate 103. In the present embodiment, the display panel further includes a first gate insulating layer 111, which covers the active layer 104 and may be a whole layer. The first gate insulating layer 111 is disposed between the active layer 104 and the first gate layer 105 to play an isolation role and avoid signal interference between the first gate layer 105 and the active layer 104. The first gate layer 105 is stacked on the surface of the first gate insulating layer 111.

[0035] exist Figure 1 to Figure 2 In the illustrated embodiment, the first gate layer 105 includes a plurality of gates. The plurality of gates are gates of seven transistors. The orthographic projection of each gate on the substrate 103 overlaps with the orthographic projection of the corresponding active region on the substrate 103, and the gate and the active region in the overlapping region are components of the same transistor. The region of the active region that overlaps with the gate forms a channel of the transistor, and the regions of the active region on both sides of the channel form source and drain regions of the transistor respectively. Figure 2 In the embodiment shown, the source and drain regions include a source region 1041 and a drain region 1042, which are respectively located on both sides of the channel of the active region. The multiple gates and the multiple active regions thereunder constitute multiple transistors. The multiple gates provided in the first gate layer are respectively used to control the on or off state of the multiple transistors.

[0036] exist Figure 2In the illustrated embodiment, the second gate layer 106 is located on a side of the first gate layer 105 away from the active layer 104. In the present embodiment, the display panel 10 further includes a second gate insulating layer 112, which covers the first gate layer 105 and may be a whole layer. The second gate insulating layer 112 is disposed between the first gate layer 105 and the second gate layer 106 to play an isolation role and avoid signal interference between the first gate layer 105 and the second gate layer 106. The second gate layer 106 is stacked on the surface of the second gate insulating layer 112. The second gate layer 106 is used in certain device structures to enhance the performance or function of the transistor.

[0037] exist Figure 2 In the embodiment shown, the first source-drain electrode layer 107 is located on a side of the second gate layer 106 away from the first gate layer 105. In this embodiment, the display panel 10 further includes a first interlayer insulating layer 113, which covers the second gate layer 106 and can be a whole layer. The first interlayer insulating layer 113 is arranged between the second gate layer 106 and the first source-drain electrode layer 107 to play an isolation role, avoid short circuits between interlayer conductive lines, make the device have better stability and reliability, and improve the performance of the device. The first source-drain electrode layer 107 is stacked on the surface of the first interlayer insulating layer 113.

[0038] exist Figure 2 In the illustrated embodiment, the second source-drain electrode layer 108 is located on a side of the first source-drain electrode layer 107 away from the second gate layer 106. In the present embodiment, the display panel 10 further includes a second interlayer insulating layer 114, which covers the first source-drain electrode layer 107 and may be a whole layer. The second interlayer insulating layer 114 is disposed between the first source-drain electrode layer 107 and the second source-drain electrode layer 108 to play an isolation role, avoid short circuits between interlayer conductive lines, make the device have better stability and reliability, and improve the performance of the device. The second source-drain electrode layer 108 is stacked on the surface of the second interlayer insulating layer 114.

[0039] exist Figure 2 In the embodiment shown, the display panel 10 further includes a third interlayer insulating layer 115. The third interlayer insulating layer 115 covers the second source-drain electrode layer 108 and may be a whole layer. Figure 3In the illustrated embodiment, the pixel light emitting unit 101 is located on a side of the second source-drain electrode layer 108 away from the first source-drain electrode layer 107. The pixel light emitting unit 101 is stacked on the surface of the third interlayer insulating layer 115, and the third interlayer insulating layer 115 plays an isolation role to avoid short circuits between interlayer conductive lines, so that the device has better stability and reliability, and improves the performance of the device. In this embodiment, the pixel light emitting unit 101 includes an anode 116, a cathode 117, and a light emitting material 118 located between the anode 116 and the cathode 117. When a certain voltage is applied between the anode 116 and the cathode 117 of the pixel light emitting unit 101 by multiple transistors in the driving circuit 102, electrons and holes will be generated in the light emitting material 118. When these electrons and holes meet and recombine in the light emitting material, energy will be released to generate photons, so that the light emitting material 118 emits light.

[0040] exist Figure 1 and Figure 3 In the illustrated embodiment, the display panel 10 further includes a plurality of contact holes 119, which are metal through holes filled with metal material to function as a conductive connection for electrically connecting an upper layer or metal line with a lower layer or region. Figure 1 In the illustrated embodiment, the plurality of contact holes 119 include a first contact hole 119a connecting the active layer 104 and the first source-drain electrode layer 107, a second contact hole 119b connecting the first gate layer 105 and the first source-drain electrode layer 107, a third contact hole 119c connecting the second gate layer 106 and the first source-drain electrode layer 107, and a fourth contact hole 119d connecting the first source-drain electrode layer 107 and the second source-drain electrode layer 108. The first contact hole 119a is used to realize electrical connection between the active layer 104 and the first source-drain electrode layer 107. The second contact hole 119b is used to realize electrical connection between the first gate layer 105 and the first source-drain electrode layer 107. The third contact hole 119c is used to realize electrical connection between the second gate layer 106 and the first source-drain electrode layer 107. The fourth contact hole 119d is used to realize electrical connection between the first source-drain electrode layer 107 and the second source-drain electrode layer 108. Figure 2 Only a portion of the contact hole 119 is shown, but the present invention is not limited thereto.

[0041] exist Figures 1 to 3 In the illustrated embodiment, the plurality of transistors include a driving transistor T1 , a switching transistor T2 , a compensation transistor T3 , an initialization transistor T4 , a driving control transistor T5 , an emission control transistor T6 , and a bypass transistor T7 .

[0042] exist Figures 1 to 3In the embodiment shown, a source-drain region of the bypass transistor T7 is connected to the anode of the pixel light emitting unit 101 in two adjacent columns in the same row through the active layer 104. In this embodiment, a source-drain region of the bypass transistor T7 refers to one of the source region or the drain region. Sharing the same bypass transistor T7 by the pixel light emitting units in two adjacent columns in the same row can reduce the number of bypass transistors T7 and the number of wirings, free up more layout space, and have more space to design the capacitor formed between the active layer 104 and the first gate layer 105, which can increase the capacitance of the capacitor, effectively reduce the transistor current, and extend the service life.

[0043] exist Figures 1 to 3 In the embodiment shown, the second gate layer 106 includes a plurality of voltage control lines Vi arranged side by side along the row, and the voltage control lines Vi are used to input power signals to the transistor. One of the voltage control lines Vi is connected to another source-drain region of the bypass transistor T7 through the first source-drain electrode layer 107, and is connected to the anodes of the pixel light-emitting units 101 in two adjacent columns in the same row through the bypass transistor T7. In this embodiment, the other source-drain region of the bypass transistor T7 refers to the other of the source region or the drain region. Figure 1 As shown in the dotted box A in the figure, the pixel light emitting units 101 in the two adjacent columns share a bypass transistor T7, and the potential of the voltage control line Vi passes through the bypass transistor T7 and then passes through the active layer 104 to be distributed to the pixel light emitting units 101 in the two adjacent columns. In this way, the number of bypass transistors T7 and the number of wirings can be reduced, more layout space can be freed up, the layout space can be increased, the capacitance value of the capacitor can be flexibly increased, the transistor current can be effectively reduced, and the service life can be extended.

[0044] exist Figures 1 to 3 In the embodiment shown, one source and drain region of the initialization transistor T4 is connected to the voltage control line through the first source and drain electrode layer 107, and another source and drain region of the initialization transistor T4 is connected to the first gate layer 105 through the first source and drain electrode layer 107, and is connected to the gates of two driving transistors T1 corresponding to the pixel light emitting units 101 in two adjacent columns in the same row. In this embodiment, one source and drain region of the initialization transistor T4 refers to one of the source region or the drain region, and another source and drain region of the initialization transistor T4 refers to the other of the source region or the drain region. Figure 1As shown in the dotted box A in the figure, the pixel light-emitting units 101 in the two adjacent columns share an initialization transistor T4. After the potential of the voltage control line Vi passes through the initialization transistor T4, it is distributed to the pixel light-emitting units 101 in the two adjacent columns through the first source-drain electrode layer 107, and the gate of the transistor is reset. The pixel light-emitting units 101 in the two adjacent columns share a bypass transistor T7 and an initialization transistor T4, which can reduce the number of bypass transistors T7 and initialization transistors T4 and the number of wirings, and can spare more layout space, so that there is more space to design the capacitor formed between the active layer 104 and the first gate layer 105. By increasing the capacitance value of the capacitor, the transistor current is effectively reduced and the service life is extended.

[0045] exist Figures 1 to 3 In the illustrated embodiment, the second gate layer 106 includes a plurality of driving power lines VDD arranged side by side along a row. The driving power lines VDD are used to provide a driving voltage. The positive projection of the active area of ​​the compensation transistor T3 on the substrate 103 and the positive projection of the driving power line on the substrate 103 have an overlapping area, and the overlapping area forms a compensation capacitor C1 of the compensation transistor T3, wherein the active area of ​​the compensation transistor T3 serves as a capacitor plate of the compensation capacitor C1, and the second gate layer 106 serves as another capacitor plate of the compensation capacitor C1. In this embodiment, since the pixel light-emitting units 101 in the two adjacent columns on the left and right share a bypass transistor T7 and an initialization transistor T4, a bypass transistor T7 and an initialization transistor T4 of the driving circuit 102 corresponding to the pixel light-emitting units 101 in the two adjacent rows in the same column can be omitted, which can spare more layout space, and there is more sufficient space to design the compensation capacitor C1 formed between the active layer 104 and the first gate layer 105. The compensation capacitor C1 can be a capacitor formed by the node N1 connected to the source and drain regions of T3_1 and T3_2 of the compensation transistor T3 and VDD. Due to the sufficient layout space, the capacitance at the node N1 can be designed to be a larger value, which effectively reduces the transistor current and prolongs the service life. In this embodiment, by setting a plurality of power lines VDD and a plurality of voltage control lines Vi arranged side by side along the column, voltage can be provided. By using a plurality of power lines VDD and a plurality of voltage control lines Vi in combination, the problem of uneven brightness of low grayscale can be effectively improved.

[0046] In the present embodiment, one of the compensation transistors T3 corresponding to the pixel light-emitting units 101 in two adjacent columns in the same row forms a compensation capacitor C1. That is to say, a large capacitor can be formed at the node N1 between the two pixel light-emitting units 101 in the two adjacent columns on the left and right. In the present embodiment, the capacitance value of the compensation capacitor corresponding to each pixel light-emitting unit 101 is the same or different. In actual design, the life of the three sub-pixels R / G / B of the pixel light-emitting unit 101 can be comprehensively considered. If the life of a certain sub-pixel is low, the capacitance at the node N1 of the pixel light-emitting unit 101 can be designed to be larger, or the capacitance at the node N1 of each pixel light-emitting unit 101 can be designed to be the same value, which is not limited in the present application.

[0047] exist Figures 1 to 3 In the embodiment shown, the gate of the driving transistor T1 is connected to a source-drain region of the compensation transistor T3 through the active region, a source-drain region of the driving transistor T1 is connected to another source-drain region of the compensation transistor T3 through the first source-drain electrode layer 107, and another source-drain region of the driving transistor T1 is connected to a source-drain region of the switching transistor T2 through the first source-drain electrode layer 107. In this embodiment, a source-drain region of the driving transistor T1 refers to one of the source region or the drain region, and another source-drain region of the driving transistor T1 refers to the other of the source region or the drain region. A source-drain region of the switching transistor T2 refers to one of the source region or the drain region. A source-drain region of the compensation transistor T3 refers to one of the source region or the drain region, and another source-drain region of the compensation transistor T3 refers to the other of the source region or the drain region. The driving transistor T1 receives a data signal according to the switching operation through the switching transistor T2, and supplies an emission current to the pixel light-emitting unit 101.

[0048] exist Figures 1 to 3 In the illustrated embodiment, the second source-drain electrode layer 108 includes a plurality of data lines Data and a plurality of power lines VDD arranged side by side along the columns, the plurality of data lines and the plurality of power lines are staggered, and are connected to the active layer 104 in sequence through the first source-drain electrode layer 107. In this embodiment, a data line Data and a power line VDD are correspondingly arranged for each pixel light-emitting unit 101, the data line Data is used to transmit data signals, and the power line VDD is used to transmit voltage signals. The data line Data and the power line VDD jointly realize the signal transmission of the display panel 10. The data line Data and the power line VDD are arranged at intervals to avoid mutual interference. And the wiring process of the data line Data and the power line VDD is completed in the same process step.

[0049] exist Figures 1 to 3In the illustrated embodiment, the first gate layer 105 includes a plurality of gate lines arranged side by side along a row, and the orthographic projections of the plurality of gate lines on the substrate 103 partially overlap with the orthographic projections of the corresponding active areas on the substrate 103. The plurality of gate lines are connected to the gate of the switching transistor T2, the gate of the compensation transistor T3, and the gate of the initialization transistor T4 through the active area, respectively. In the present embodiment, the plurality of gate lines include a first gate line S1, which is connected to the gate of the initialization transistor T4 through the active area, and the on-off of the initialization transistor T4 is controlled by the first gate line S1. The initialization transistor T4 is turned on according to the first gate line signal from the first gate line S1, so as to transmit the initialization voltage to the gate electrode G of the driving transistor T1 for the purpose of initializing the voltage of the gate electrode G of the driving transistor T1. The plurality of gate lines include a second gate line S2, which is connected to the gate of the switching transistor T2 and the gate of the compensation transistor T3 through the active area, and the on-off of the switching transistor T2 is controlled by the first gate line S1. The switching transistor T2 is turned on according to the second gate line signal received through the second gate line S2, and performs a switching operation to transmit the data signal from the data line Data to the source electrode S of the driving transistor T1. The compensation transistor T3 is turned on according to the second gate line signal from the second gate line S2 to electrically connect the gate electrode G and the drain electrode D of the driving transistor T1, thereby placing the driving transistor T1 in a diode D1 connection state.

[0050] exist Figures 1 to 3 In the illustrated embodiment, the first gate layer 105 includes a light-emitting control signal line EM arranged along the row. The light-emitting control line EM is used to control the light-emitting duration of the light-emitting device. The positive projection of the light-emitting control signal line EM on the substrate 103 partially overlaps with the positive projection of the corresponding active area on the substrate 103. The light-emitting control signal line EM is connected to the gate of the drive control transistor T5 and the gate of the emission control transistor T6 through the active area respectively. The light-emitting control signal line EM and the plurality of gate lines are located in the same layer and are arranged at intervals in the direction of row extension, so as to avoid mutual interference of signals on the basis of reducing the number of layers. The drive control transistor T5 and the emission control transistor T6 are turned on at the same time according to the light-emitting control signal from the light-emitting control line EM, so as to allow the emission current to flow to the pixel light-emitting unit 101 based on the connection between the driving voltage VDD and the pixel light-emitting unit 101. The plurality of gate lines include a second gate line S3, which is connected to the gate of the bypass transistor T7 through the active area, and controls the on and off of the bypass transistor T7 through the first gate line S1. The bypass transistor T7 transmits the second gate line signal from the second gate line S3 to the gate of the bypass transistor T7. The second gate line signal indicates a voltage having a predetermined level for turning off the bypass transistor T7. When the bypass transistor T7 is turned off, a portion of the driving current flows as a bypass current through the bypass transistor T7.

[0051] In operation, during the initialization phase, a first gate line signal with a low level is supplied through the first gate line S1. Subsequently, the initialization transistor T4 is turned on based on the low level of the first gate line signal, and the initialization voltage from the battery line Vi is transmitted to the gate electrode G of the driving transistor T1 through the initialization transistor T4. Therefore, the driving transistor T1 is initialized due to the initialization voltage. During the data programming phase, a second gate line signal with a low level is supplied through the second gate line S2. Subsequently, the switching transistor T2 and the compensation transistor T3 are turned on based on the low level of the second gate line signal. Therefore, the driving transistor T1 is placed in a diode D1 connection state and biased in the positive direction by the turned-on compensation transistor T3. Subsequently, the compensation voltage obtained by subtracting the threshold voltage of the driving transistor T1 from the data signal supplied via the data line Data is applied to the gate electrode G of the driving transistor T1. Subsequently, the driving voltage VDD and the compensation voltage are applied to the two terminals of the storage capacitor Cst, so that the charge corresponding to the voltage difference between the corresponding terminals is stored in the storage capacitor Cst. During the emission phase, the light-emitting control signal from the light-emitting control signal line EM changes from a high level to a low level. Subsequently, during the emission phase, the drive control transistor T5 and the emission control transistor T6 are turned on based on the low level of the light emitting control signal. Subsequently, a drive current is generated based on the difference between the voltage of the gate electrode G of the drive transistor T1 and the drive voltage VDD. The emission current corresponding to the difference between the drive current and the bypass current is supplied to the pixel light emitting unit 101 through the emission control transistor T6. In this way, the transmittance and sensing performance can be effectively improved on the basis of effectively reducing the transistor current and extending the service life.

[0052] The embodiment of the present application further provides a display device 20 . Figure 4 The structure diagram of an embodiment of the display device of the present application is shown. The display device 20 can be an electronic device with a display function such as a mobile phone, a computer, or a tablet computer. The display device 20 can be Figure 4 The display device 20 provided in the embodiment of the present application only schematically shows the case where the display device 20 is a mobile phone. Figures 1 to 3 The display panel 10 provided in any of the embodiments shown can reduce the number of bypass transistors T7 and the number of wirings by sharing the same bypass transistor T7 between the pixel light-emitting units 101 in two adjacent columns in the same row of the display panel 10, free up more layout space, and have more space to design the capacitor formed between the active layer 104 and the first gate layer 105, which can increase the capacitance of the capacitor, effectively reduce the transistor current, and extend the service life. The display panel 10 of this embodiment can be an organic light-emitting diode display panel. In some other embodiments, the display panel 10 can be a high-definition screen with more data lines, which is not limited in this application.

[0053] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: A display panel having a plurality of pixel light-emitting units and a plurality of driving circuits, wherein the plurality of pixel light-emitting units are arranged in rows and columns at intervals and include an anode, a cathode and a light-emitting material between the anode and the cathode, and the driving circuit includes a storage capacitor and a plurality of transistors; the display panel includes: substrate; an active layer, located on one side of the substrate, comprising a plurality of active regions; and A first gate layer, located on a side of the active layer away from the substrate, includes a plurality of gates; wherein an orthographic projection of each gate on the substrate overlaps with an orthographic projection of a corresponding active region on the substrate, the gate and the active region in the overlapping region are components of the same transistor, an area of ​​the active region overlapping with the gate forms a channel of the transistor, and areas of the active region located on both sides of the channel respectively form source and drain regions of the transistor; Wherein, the transistor comprises a bypass transistor, and a source-drain region of the bypass transistor is connected to anodes of the pixel light-emitting units in two adjacent columns in the same row through the active layer.

2. The display panel according to claim 1, characterized in that: The display panel also includes a second gate layer and a first source-drain electrode layer, the second gate layer is located on a side of the first gate layer away from the active layer, and the first source-drain electrode layer is located on a side of the second gate layer away from the first gate layer; the second gate layer includes a plurality of voltage control lines arranged side by side along a row, one of the voltage control lines is connected to another source-drain region of the bypass transistor through the first source-drain electrode layer, and is connected to the anodes of the pixel light-emitting units in two adjacent columns in the same row through the bypass transistor.

3. The display panel according to claim 2, characterized in that: The transistor includes a driving transistor and an initialization transistor, one source and drain region of the initialization transistor is connected to the voltage control line through the first source and drain electrode layer, the other source and drain region of the initialization transistor is connected to the first gate layer through the first source and drain electrode layer, and is connected to the gates of the two driving transistors corresponding to the pixel light-emitting units in two adjacent columns in the same row.

4. The display panel according to claim 3, characterized in that: The second gate layer includes a plurality of driving power lines arranged side by side along a row; the transistor includes a compensation transistor, and an orthographic projection of an active area of ​​the compensation transistor on the substrate and an orthographic projection of the driving power line on the substrate have an overlapping area, and the overlapping area forms a compensation capacitor of the compensation transistor, wherein the active area of ​​the compensation transistor serves as one capacitor plate of the compensation capacitor, and the second gate layer serves as another capacitor plate of the compensation capacitor.

5. The display panel according to claim 4, characterized in that: One of the compensation transistors corresponding to the pixel light emitting units in two adjacent columns in the same row forms a compensation capacitor; and / or The capacitance value of the compensation capacitor corresponding to each of the pixel light-emitting units is the same or different.

6. The display panel according to claim 4, characterized in that: The transistor includes a switching transistor, the gate of the driving transistor is connected to a source-drain region of the compensation transistor through the active region, one source-drain region of the driving transistor is connected to another source-drain region of the compensation transistor through the first source-drain electrode layer, and the other source-drain region of the driving transistor is connected to a source-drain region of the switching transistor through the first source-drain electrode layer.

7. The display panel according to claim 2, characterized in that: The display panel also includes a second source-drain electrode layer, which is located on a side of the first source-drain electrode layer away from the second gate layer; the pixel light-emitting unit is located on a side of the second source-drain electrode layer away from the first source-drain electrode layer; the second source-drain electrode layer includes a plurality of data lines and a plurality of power lines arranged side by side along a column, the plurality of data lines and the plurality of power lines are staggered, and are all connected to the active layer in turn through the first source-drain electrode layer.

8. The display panel according to claim 1, characterized in that: The first gate layer includes a plurality of gate lines arranged side by side along a row, and the orthographic projections of the plurality of gate lines on the substrate partially overlap with the orthographic projections of the corresponding active areas on the substrate; the transistor includes a switching transistor, a compensation transistor and an initialization transistor, and the plurality of gate lines are respectively connected to the gate of the switching transistor, the gate of the compensation transistor and the gate of the initialization transistor through the active area.

9. The display panel according to claim 1, characterized in that: The first gate layer includes light-emitting control signal lines arranged along rows, and the orthographic projections of the light-emitting control signal lines on the substrate partially overlap with the orthographic projections of the corresponding active areas on the substrate; the transistor includes a driving control transistor and an emission control transistor, and the light-emitting control signal lines are respectively connected to the gates of the driving control transistor and the emission control transistor through the active areas.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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