Display device

Abstract

A display device includes: a substrate including a display area and a non-display area; the circuit layer is arranged on the substrate; and an element layer disposed on the circuit layer. The circuit layer comprises a light-emitting pixel driver; gate lines extending in a first direction and arranged in the display area in a second direction; a gate driving circuit including stages disposed in a portion of the non-display area, arranged in the first direction, and electrically connected to the gate lines; a data line extending in a second direction; a first auxiliary line extending in a first direction; and a second auxiliary line extending in the second direction and adjacent to the data line in the first direction. The second auxiliary line includes a gate bypass auxiliary line electrically connected between the gate line and the stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0149088, filed on November 1, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As information-oriented society develops, people have put forward more and more demands on display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element formed of an inorganic semiconductor, and a micrometer light-emitting display device including a micrometer light-emitting element.

[0006] An organic light emitting display device uses a light emitting element to display an image, each of which includes a light emitting layer made of an organic light emitting material. As described above, an organic light emitting display device uses a self-luminous element to realize image display, and therefore, compared with other display devices, can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0007] One surface of the display device may include a display area in which an image is displayed and a non-display area which is a periphery of the display area. Emission areas emitting light having corresponding brightness and color may be arranged in the display area. Summary of the invention

[0008] The display device may include gate lines extending in a first direction, data lines extending in a second direction, a gate driving circuit electrically connected to the gate lines, and a display driving circuit electrically connected to the data lines.

[0009] The gate driving circuit is a circuit that sequentially outputs signals to the gate lines arranged in the second direction, and may have a structure simpler than that of the display driving circuit. Accordingly, the gate driving circuit may be provided as part of a circuit layer together with the gate lines and the data lines.

[0010] In one example, the gate driving circuit may be disposed in a non-display region of the substrate, and may include a plurality of stages electrically connected to the gate lines.

[0011] In this case, since the gate driving circuit includes multiple stages arranged in the same direction as the arrangement direction of the gate lines, the portion of the non-display area in which the gate driving circuit is provided may be defined as the portion of the non-display area facing at least one side of the display area in the first direction.

[0012] As a result, there is a problem that there is a limit to the reduction in the width of the non-display area.

[0013] Furthermore, as the width of the display area in the first direction increases, the central portion of the display area in the first direction is further away from the gate driving circuit, thereby making it difficult to stably supply signals of the gate lines.

[0014] In view of the above situation, various aspects of the present disclosure provide a display device in which a portion of a non-display area of ​​a substrate in which a gate driving circuit is disposed may not be limited to a portion of the non-display area facing at least one side of the display area in a first direction.

[0015] According to aspects of the present disclosure, a display device is provided, comprising: a substrate, comprising a display area in which an emission area is arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate; and an element layer, arranged on the circuit layer, and comprising light-emitting elements respectively arranged in the emission area. The circuit layer comprises: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements, and arranged in parallel with each other in a first direction and a second direction intersecting the first direction; a gate line, arranged in the display area in the second direction, extending in the first direction, and used to transmit a gate signal to the light-emitting pixel driver; a gate drive circuit, comprising a plurality of stages arranged in a portion of the non-display area, arranged in the first direction and electrically connected to the gate line; a data line, extending in the second direction, and used to transmit a data signal to the light-emitting pixel driver; a first auxiliary line, extending in the first direction; and a second auxiliary line, extending in the second direction, and adjacent to the data line in the first direction. The second auxiliary line comprises a gate bypass auxiliary line electrically connected between the gate line and the plurality of stages.

[0016] The edge of the display area may include: a first side and a second side extending in the first direction and facing each other in the second direction; and a third side and a fourth side connecting the first side to the second side, facing each other in the first direction, and having a length shorter than that of the first side and the second side. The gate drive circuit may include a first central circuit portion, the first central circuit portion facing the central portion of the first side in the second direction, and including a first level among a plurality of levels arranged in the first direction. The display area may further include: a display middle area facing the first central circuit portion in the second direction; and a bypass area contacting the display middle area in the first direction. The first auxiliary line may include a first bypass auxiliary line, the first bypass auxiliary line being electrically connected to a first data line disposed in the display middle area among the data lines. The second auxiliary line may further include a second bypass auxiliary line, the second bypass auxiliary line being adjacent to a second data line disposed in the bypass area among the data lines and electrically connected to the first bypass auxiliary line, and the gate bypass auxiliary line may be disposed in the display middle area.

[0017] The display device may further include: a display driving circuit configured to supply a data signal of a data line. The circuit layer may further include: a data supply line, which is arranged in a portion of the non-display area facing the first side, is spaced apart from the first central circuit portion in the first direction, and is electrically connected between the data line and the display driving circuit. Among the data supply lines, a first data supply line that transmits a data signal of a first data line may be electrically connected to the first data line through a first bypass auxiliary line and a second bypass auxiliary line. Among the data supply lines, a second data supply line that transmits a data signal of a second data line may be directly electrically connected to the second data line. The first data line may be adjacent to one of the gate bypass auxiliary lines in the first direction.

[0018] The display driving circuit may be mounted on a portion of the non-display area of ​​the substrate facing the first side and spaced apart from the first central circuit portion in the first direction.

[0019] The display device may further include: a circuit board on which the display driving circuit is mounted; and a signal pad to which the circuit board is connected. The signal pad may be disposed in the non-display area of ​​the substrate, facing the first side, and spaced apart from the first central circuit portion in the first direction.

[0020] The display area may further include: a side area, arranged between the bypass area and the non-display area in the first direction. The data supply line may extend to the bypass area and the side area. The data line may further include a third data line arranged in the side area. Among the data supply lines, a third data supply line that transmits a data signal of the third data line may be directly electrically connected to the third data line.

[0021] Each of the light-emitting pixel drivers of the circuit layer may include: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a third node and a first power line for transmitting a first power; a second transistor electrically connected between a data line and a first node; a third transistor electrically connected between a second node and a third node; a fourth transistor electrically connected between a third node and a gate initialization voltage line for transmitting a gate initialization voltage; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between a second node and a fourth node; and a seventh transistor electrically connected between a fourth node and an anode initialization voltage line for transmitting an anode initialization voltage. The first node may be electrically connected to a first electrode of the first transistor. The second node may be electrically connected to a second electrode of the first transistor. The third node may be electrically connected to a gate electrode of the first transistor. The fourth node may be electrically connected to a corresponding one of the light-emitting elements. The gate line may include: a scan write line for transmitting a scan write signal to the light-emitting pixel driver; a scan initialization line for transmitting a scan initialization signal to the light-emitting pixel driver; an emission control line for transmitting an emission control signal to the light-emitting pixel driver; and a gate control line for transmitting a gate control signal to the light-emitting pixel driver. The second transistor and the third transistor can be turned on by scanning the write signal. The fourth transistor can be turned on by scanning the initialization signal. The fifth transistor and the sixth transistor can be turned on by the emission control signal. The seventh transistor can be turned on by the gate control signal.

[0022] The first central circuit portion may include: a scan write stage electrically connected to the scan write line; a scan initialization stage electrically connected to the scan initialization line; an emission control stage electrically connected to the emission control line; and a gate control stage electrically connected to the gate control line.

[0023] The gate drive circuit may further include: a second central circuit portion facing the central portion of the second side of the display area. The display middle area of ​​the display area may be arranged between the first central circuit portion and the second central circuit portion in the second direction. The second level of the second central circuit portion among the plurality of levels may be arranged in the first direction and electrically connected to the gate line through the gate bypass auxiliary line. Each of the first central circuit portion and the second central circuit portion may include: a scan write stage electrically connected to the scan write line; a scan initialization stage electrically connected to the scan initialization line; an emission control stage electrically connected to the emission control line; and a gate control stage electrically connected to the gate control line.

[0024] The gate driving circuit may further include a side circuit portion facing at least one of the third side and the fourth side of the display area.

[0025] Each of the first central circuit portion and the side circuit portion may include: a scan write stage electrically connected to the scan write line; a scan initialization stage electrically connected to the scan initialization line; an emission control stage electrically connected to the emission control line; and a gate control stage electrically connected to the gate control line.

[0026] Some of the scan write lines, scan initialization lines, emission control lines, and gate control lines may be electrically connected to the first central circuit portion, and others of the scan write lines, scan initialization lines, emission control lines, and gate control lines may be electrically connected to the side circuit portion.

[0027] The gate line may further include: a bias control line for transmitting a bias control signal to the light-emitting pixel driver. Each of the light-emitting pixel drivers of the circuit layer may further include an eighth transistor electrically connected between the bias power line and the first node. The eighth transistor may be turned on by the bias control signal.

[0028] The first auxiliary line may further include a power-assisted horizontal line. The second auxiliary line may further include a power-assisted vertical line.

[0029] According to aspects of the present disclosure, a display device is provided, comprising: a substrate, comprising a display area in which an emission area is arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate; and an element layer, arranged on the circuit layer, and comprising light-emitting elements respectively arranged in the emission area. The circuit layer comprises: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements, and arranged in parallel with each other in a first direction and a second direction intersecting the first direction; a gate line, arranged in the display area in the second direction, extending in the first direction, and used to transmit a gate signal to the light-emitting pixel driver; a gate driving circuit, comprising a plurality of stages arranged in a part of the non-display area, arranged in the first direction and electrically connected to the gate line; a data line, extending in the second direction, and used to transmit a data signal to the light-emitting pixel driver; a first auxiliary line, extending in the first direction; and a second auxiliary line, extending in the second direction, and adjacent to the data line in the first direction. The display area further comprises: a display middle area, facing the first central circuit part in the second direction; and a bypass area, contacting the display middle area in the first direction. The first auxiliary line comprises a first bypass auxiliary line, and the first bypass auxiliary line is electrically connected to a first data line arranged in the display middle area among the data lines. The second auxiliary lines include: a second bypass auxiliary line adjacent to a second data line disposed in a bypass region among the data lines and electrically connected to the first bypass auxiliary line; and a gate bypass auxiliary line electrically connected between the gate line and the plurality of stages.

[0030] The display device may further include: a display driving circuit configured to supply a data signal of a data line. The circuit layer further includes: a data supply line, which is arranged in a portion of the non-display area facing the first side of the display area, is spaced apart from the first central circuit portion in the first direction, and is electrically connected between the data line and the display driving circuit. Among the data supply lines, a first data supply line that transmits a data signal of a first data line may be electrically connected to the first data line through a first bypass auxiliary line and a second bypass auxiliary line. Among the data supply lines, a second data supply line that transmits a data signal of a second data line may be directly electrically connected to the second data line. The first data line may be adjacent to one of the gate bypass auxiliary lines in the first direction.

[0031] The edge of the display area may include: a first side and a second side extending in the first direction and facing each other in the second direction; and a third side and a fourth side connecting the first side to the second side, facing each other in the first direction, and each having a length shorter than the length of each of the first side and the second side. The gate drive circuit may include: a first central circuit portion facing the central portion of the first side in the second direction; and a second central circuit portion facing the central portion of the second side of the display area in the second direction. The display middle area of ​​the display area may be disposed between the first central circuit portion and the second central circuit portion in the second direction. A plurality of stages of each of the first central circuit portion and the second central circuit portion may be arranged in the first direction and electrically connected to the gate line through a gate bypass auxiliary line.

[0032] Each of the light-emitting pixel drivers of the circuit layer may include: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a third node and a first power line for transmitting a first power; a second transistor electrically connected between a data line and a first node; a third transistor electrically connected between a second node and a third node; a fourth transistor electrically connected between a third node and a gate initialization voltage line for transmitting a gate initialization voltage; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between a second node and a fourth node; and a seventh transistor electrically connected between a fourth node and an anode initialization voltage line for transmitting an anode initialization voltage. The first node may be electrically connected to a first electrode of the first transistor. The second node may be electrically connected to a second electrode of the first transistor. The third node may be electrically connected to a gate electrode of the first transistor. The fourth node may be electrically connected to a corresponding one of the light-emitting elements. The gate line may include: a scan write line for transmitting a scan write signal to the light-emitting pixel driver; a scan initialization line for transmitting a scan initialization signal to the light-emitting pixel driver; an emission control line for transmitting an emission control signal to the light-emitting pixel driver; and a gate control line for transmitting a gate control signal to the light-emitting pixel driver. The second transistor and the third transistor can be turned on by scanning the write signal. The fourth transistor can be turned on by scanning the initialization signal. The fifth transistor and the sixth transistor can be turned on by the emission control signal. The seventh transistor can be turned on by the gate control signal.

[0033] The edge of the display area may include: a first side and a second side extending in the first direction and facing each other in the second direction; and a third side and a fourth side connecting the first side to the second side, facing each other in the first direction, and each having a length shorter than the length of each of the first side and the second side. The gate drive circuit may include: a first central circuit portion facing the central portion of the first side in the second direction and including a first level of a plurality of levels arranged in the first direction; and a side circuit portion facing at least one of the third side and the fourth side of the display area in the first direction. The first level of the first central circuit portion may be arranged in the first direction and electrically connected to the gate line through a gate bypass auxiliary line. Each of the first central circuit portion and the second central circuit portion may be electrically connected to a scan write line, a scan initialization line, an emission control line, and a gate control line.

[0034] The edge of the display area may include: a first side and a second side extending in the first direction and facing each other in the second direction; and a third side and a fourth side connecting the first side to the second side, facing each other in the first direction, and each having a length shorter than the length of each of the first side and the second side. The gate drive circuit may include: a first central circuit portion facing the central portion of the first side in the second direction and including a first level of a plurality of levels arranged in the first direction; and a side circuit portion facing at least one of the third side and the fourth side of the display area in the first direction. The first level of the first central circuit portion may be arranged in the first direction and electrically connected to the gate line through a gate bypass auxiliary line. The second level of the side circuit portion among the plurality of levels may be arranged in the second direction. Some of the scan write lines, the scan initialization lines, the emission control lines, and the gate control lines may be electrically connected to the first central circuit portion. Other lines of the scan write lines, the scan initialization lines, the emission control lines, and the gate control lines may be electrically connected to the side circuit portion.

[0035] The display device according to the embodiment includes: a substrate; a circuit layer, which is arranged on the substrate; and an element layer, which is arranged on the circuit layer. The substrate includes a display area in which an emission area is arranged and a non-display area arranged around the display area. The element layer includes light-emitting elements respectively arranged in the emission area. The circuit layer may include: light-emitting pixel drivers, which are electrically connected to the light-emitting elements and arranged in parallel with each other in the first direction and the second direction; gate lines, which are arranged in the display area in the second direction, extend in the first direction, and are used to transmit gate signals to the light-emitting pixel drivers; a gate drive circuit, including a stage arranged in a part of the non-display area and electrically connected to the gate line respectively; a data line, which extends in the second direction and is used to transmit a data signal to the light-emitting pixel driver; a first auxiliary line, which extends in the first direction; and a second auxiliary line, which extends in the second direction and is adjacent to the data line. The second auxiliary line may include a gate bypass auxiliary line electrically connected between the gate line and the stage of the gate drive circuit arranged in the first direction.

[0036] Therefore, according to an embodiment, the circuit layer may include a second auxiliary line adjacent to the data line and extending in the second direction. In addition, a gate bypass auxiliary line of the second auxiliary line is electrically connected between the stages of the gate driving circuit arranged in the first direction and the gate line.

[0037] That is, the stages of the gate driving circuit arranged differently from the arrangement direction of the gate lines may be electrically connected to the gate lines through the gate bypass auxiliary lines.

[0038] Accordingly, the gate driving circuit may include stages arranged in a first direction different from the arrangement direction of the gate lines. As a result, at least a portion of the gate driving circuit may be disposed in a portion of the non-display area facing at least one side of the display area in the second direction.

[0039] That is, the portion of the non-display region of the substrate in which the gate driving circuit is disposed may not be limited to a portion of the non-display region facing at least one side of the display region in the first direction.

[0040] Accordingly, in the display device according to the embodiment, the gate driving circuit can be provided at any position in the non-display area, which can be advantageous in reducing the width of the non-display area.

[0041] Furthermore, according to the embodiment, even if the width of the display area in the first direction increases, the signal of the gate line can be stably supplied.

[0042] According to an embodiment, the circuit layer may further include a data supply line electrically connected between the data line and the display driving circuit supplying the data signal. The data line may include a first data line arranged in a display middle area and a second data line arranged in a bypass area, the display middle area faces the gate driving circuit arranged in the first direction in the second direction, and the bypass area contacts the display middle area in the first direction. The first auxiliary line may include a first bypass auxiliary line electrically connected to the first data line, and the second auxiliary line may further include a second bypass auxiliary line adjacent to the second data line and electrically connected to the first bypass auxiliary line.

[0043] That is, among the data supply lines, the first data supply line for transmitting the data signal of the first data line can extend to the bypass area instead of the display middle area where the first data line is set, and can be electrically connected to the first data line through the second bypass auxiliary line and the first bypass auxiliary line.

[0044] Accordingly, by disposing at least a portion of the gate driving circuit in a portion of the non-display area facing at least one side of the display area in the second direction, electrical connection between the data line and the data supply line can be achieved even if the portion of the non-display area in which the data supply line is disposed is limited to a portion in which the gate driving circuit is not disposed.

[0045] Furthermore, the gate bypass auxiliary line and the second bypass auxiliary line are provided as a portion of the second auxiliary line adjacent to the data line, which may be advantageous in making the display device slim or improving the resolution of the display device.

[0046] However, the effects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0048] Figure 1 is a plan view illustrating a display device according to an embodiment;

[0049] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0050] Figure 3 It is a graphic Figure 1 a layout diagram of part B;

[0051] Figure 4 It is shown Figure 3 An equivalent circuit diagram of a light-emitting pixel driver;

[0052] Figure 5 It is shown Figure 4 A cross-sectional view of a light emitting element and a first transistor and a sixth transistor;

[0053] Figure 6 It is shown Figure 1 a layout diagram of part C;

[0054] Figure 7 is along Figure 6 A cross-sectional view taken along line D-D';

[0055] Figure 8 It is shown Figure 6 The equivalent circuit diagram of the scan-write stage;

[0056] Fig. 9 It is shown Figure 6 The equivalent circuit diagram of the emission control stage;

[0057] Fig.10 is a diagram showing a method according to an embodiment Figure 1 a layout diagram of part C;

[0058] Fig.11 is a plan view illustrating a display device according to an embodiment;

[0059] Fig.12 It is a graphic Fig.11 a layout diagram of part E;

[0060] Fig.13 It is a graphic Fig.11 a layout diagram of part F;

[0061] Fig.14 is a plan view illustrating a display device according to an embodiment;

[0062] Fig.15 It is a graphic Fig.14 A layout diagram of part G;

[0063] Fig.16is a plan view illustrating a display device according to an embodiment;

[0064] Fig.17 is a plan view illustrating a display device according to an embodiment;

[0065] Fig.18 is a plan view illustrating a display device according to an embodiment;

[0066] Fig.19 is a plan view illustrating a display device according to an embodiment;

[0067] Fig. 20 It shows that according to Fig.19 An equivalent circuit diagram of a light-emitting pixel driver according to an embodiment of the present invention;

[0068] Fig.21 It is shown Fig. 20 a cross-sectional view of a first transistor, a second transistor, a sixth transistor, a fourth transistor, and a light emitting element; and

[0069] Fig. 22 is a plan view illustrating a display device according to an embodiment. DETAILED DESCRIPTION

[0070] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0071] In order to describe the embodiments of the present disclosure, some of various parts that are not related to the description may not be provided.

[0072] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0073] Further, the term "in a plan view" means when viewing the object portion from above (i.e., viewing in the third direction DR3), and the term "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object can be above or below or on the side of the second object, and / or vice versa. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending on..., covering or partially covering, or any other suitable term that a person of ordinary skill in the art will appreciate and understand. The expression "non-overlapping" may include meanings such as "separated from...", "set beside..." or "offset from..." and any other suitable equivalents that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is located between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0074] For ease of description, spatially relative terms such as "below", "below", "lower", "above", or "upper" may be used herein to describe the relationship between one element or component and another element or component as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, in the case where the device illustrated in the accompanying drawings is flipped, a device located "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0075] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. It will be further understood that when the terms "comprising", "having" and / or "including" are used, they may specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0076] It will be understood that although the terms "first", "second", or "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate description and explanation thereof. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0077] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0078] The terms used herein are only used for the purpose of describing a specific embodiment, and are not intended to be limited. As used herein, "one", "the (described)" and "at least one" do not represent a limitation on quantity, and are intended to include both the singular and the plural, unless otherwise clearly indicated in the context. For example, "element" has the same meaning as "at least one element", unless otherwise clearly indicated in the context. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". In the specification and claims, in terms of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B or A and B". The terms "and" and "or" can be used in a connected or separated sense, and can be understood to be equivalent to "and / or". In this specification and claims, in terms of its meaning and interpretation, the term "at least one of ..." is intended to include the meaning of "at least one selected from the group of ...". For example, "at least one of A and B" can be understood to be "A, B or A and B".

[0079] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0080] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0081] Figure 1 is a plan view illustrating a display device according to an embodiment.

[0082] As a device for displaying moving images or still images, the display device 100 can be used as a display screen for various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (“IOT”) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet “PCs”), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (“PMPs”), navigation systems, and ultra mobile PCs (“UMPCs”).

[0083] The display device 100 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micron or nanometer light-emitting display device using a micron or nanometer light-emitting diode ("LED"). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0084] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be formed to be flexible so that it may be bent, folded, or rolled.

[0085] refer to Figure 1 , a display device 100 according to one embodiment may include a substrate 110 .

[0086] The substrate 110 may include a display area DA disposed at the center and a non-display area NDA disposed around the display area DA.

[0087] The substrate 110 may be prepared in a rectangular plane.

[0088] One surface of the substrate 110 may correspond to a display surface through which light for image display is emitted. A majority area located at the center of the display surface may be a display area DA.

[0089] The display area DA may have a shape similar to that of the substrate 110 .

[0090] That is, the edge of the display area DA may include a first side SD1 and a second side SD2 extending in the first direction DR1 and opposite to each other in the second direction DR2, and a third side SD3 and a fourth side SD4 connecting the first side SD1 to the second side SD2, opposite to each other in the first direction DR1 and each having a length shorter than that of each of the first side SD1 and the second side SD2.

[0091] Corners where the first and second sides SD1 and SD2 and the third and fourth sides SD3 and SD4 meet each other may be right angles or may be rounded to have a predetermined curvature. The shape of the display area DA is not limited to a quadrilateral having four sides and may be a circle, an ellipse, or a polygon other than a quadrilateral.

[0092] The non-display area NDA may be disposed at an edge of the substrate 110 to surround the display area DA.

[0093] A portion of the non-display area NDA may be changed into a bent shape so that another portion of the non-display area NDA between the bent portion and the edge of the substrate 110 may be disposed on the rear surface of the substrate 110 .

[0094] The display device 100 according to one embodiment may further include a gate driving circuit GDR and a display driving circuit DDR disposed in a portion of the non-display area NDA of the substrate 110 .

[0095] According to one embodiment, the gate driving circuit GDR may include a first central circuit portion CNC1 facing a central portion of the first side SD1 of the display area DA.

[0096] According to one embodiment, the display driving circuit DDR may be provided as an integrated circuit (“IC”) and may be mounted in a portion of the non-display area NDA of the substrate 110 by a chip on glass (“COG”) method, a chip on plastic (“COP”) method, or an ultrasonic bonding method.

[0097] The display driving circuit DDR may face the first side SD1 of the display area DA and be spaced apart from the first central circuit portion CNC1 in the first direction DR1.

[0098] That is, the display driving circuit DDR and the first central circuit portion CNC1 may be arranged in the first direction DR1 in a portion of the non-display area NDA facing the first side SD1 of the display area DA.

[0099] The display area DA may include a display middle area DMDA facing the first central circuit portion CNC1 in the second direction DR2 and a bypass area BPA contacting the display middle area DMDA in the first direction DR1 .

[0100] In addition, the display area DA may further include a side area SDA disposed between the bypass area BPA and the non-display area NDA in the first direction DR1. In an embodiment, the first central circuit portion CNC1 may face only the display middle area DMDA among the display middle area DMDA, the bypass area BPA, and the side area SDA in the second direction DR2. In an embodiment, the display driving circuit DDR may face only the bypass area BPA and / or the side area SDA among the display middle area DMDA, the bypass area BPA, and the side area SDA in the second direction DR2.

[0101] Figure 2 is along Figure 1 A cross-sectional view taken along line AA'.

[0102] refer to Figure 2 According to an embodiment, a display device 100 includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0103] The display device 100 may further include an encapsulation layer 140 covering the element layer 130 , and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0104] The display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150 in order to reduce reflection of external light.

[0105] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled.

[0106] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0107] The substrate 110 may include a display area DA and a non-display area NDA.

[0108] Figure 3 It is a graphic Figure 1 Layout diagram of part B.

[0109] refer to Figure 3 , the display area DA of the substrate 110 according to one embodiment may include the emission area EA.

[0110] The display area DA may further include a non-emission area disposed in a gap between the emission areas EA.

[0111] The emission area EA may have a rhombus shape or a rectangular shape in a plan view. However, this is only an example, and the planar shape of the emission area EA according to one embodiment is not limited to Figure 3 That is, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular shape or an elliptical shape including curved edges.

[0112] The emission area EA may include a first emission area EA1 emitting a first color light in a predetermined band, a second emission area EA2 emitting a second color light in a band lower than the first color, and a third emission area EA3 emitting a third color light in a band lower than the second color.

[0113] For example, the first color may be red having a wavelength of approximately 600 nanometers (nm) to 750 nm. The second color may be green having a wavelength of approximately 480 nm to 560 nm. The third color may be blue having a wavelength of approximately 370 nm to 460 nm.

[0114] The first emission areas EA1 and the third emission areas EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0115] The second emission areas EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0116] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in oblique directions DR4 and DR5 intersecting the first direction DR1 and the second direction DR2 .

[0117] The pixels PX displaying their corresponding brightness and color may be provided by the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 adjacent to each other among the emission areas EA.

[0118] In other words, the pixel PX may be a basic unit for displaying various colors including white at a predetermined brightness.

[0119] Each of the pixels PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 adjacent to each other. Accordingly, each of the pixels PX may display various colors by mixing the light emitted from the first emission region EA1, the second emission region EA2, and the third emission region EA3 adjacent to each other.

[0120] According to one embodiment, the component layer 130 (see Figure 2) may include light emitting elements LE respectively arranged in the emission area EA (see Figure 4 ).

[0121] According to one embodiment, the circuit layer 120 (see Figure 2 ) may include a light-emitting pixel driver EPD electrically connected to the light-emitting elements LE of the element layer 130 respectively.

[0122] The light emitting pixel drivers EPD may be arranged side by side in the first direction DR1 and the second direction DR2.

[0123] Figure 4 It is shown Figure 3 Equivalent circuit diagram of the light-emitting pixel driver.

[0124] refer to Figure 4 , component layer 130 (see Figure 2 Each of the light emitting elements LE of the circuit layer 120 (see Figure 2 ) between a corresponding one of the light-emitting pixel drivers EPD and the second power ELVSS.

[0125] That is, the anode electrode 131 (see Figure 5 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (see Figure 5 ) may be applied with a second power ELVSS lower than the first power ELVDD.

[0126] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0127] The circuit layer 120 may include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, and a gate control line GCL for transmitting a gate control signal GC.

[0128] The circuit layer 120 may further include a first power line VDL for transmitting the first power ELVDD, a gate initialization voltage line VGIL for transmitting the gate initialization voltage VGINT, and an anode initialization voltage line VAIL for transmitting the anode initialization voltage VAINT.

[0129] Each light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1 , and at least one pixel capacitor PC1 .

[0130] The first transistor T1 and the light emitting element LE are connected in series between the first power ELVDD and the second power ELVSS.

[0131] That is, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. Further, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0132] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0133] The gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the pixel capacitor PC1. That is, the pixel capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0134] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained by the first power ELVDD of the first power line VDL.

[0135] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2 , a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may correspond to the first power ELVDD and the data signal Vdata.

[0136] In this case, when a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1, i.e., a gate-source voltage difference, becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0137] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0138] Accordingly, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0139] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0140] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by the scan write signal GW of the scan write line GWL.

[0141] The third transistor T3 may include a plurality of sub-transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. In this way, the potential of the gate electrode of the first transistor T1 may be prevented from changing due to leakage current through the cut-off third transistor T3.

[0142] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0143] The fourth transistor T4 may include a plurality of sub-transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. In this way, the potential of the gate electrode of the first transistor T1 may be prevented from changing due to leakage current through the turned-off fourth transistor T4.

[0144] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0145] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0146] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0147] The seventh transistor T7 may be electrically connected between the anode electrode 131 of the light emitting element LE and the anode initialization voltage line VAIL. The seventh transistor T7 may be turned on by a gate control signal GC of the gate control line GCL.

[0148] like Figure 4 As shown in , the first to seventh transistors T1 to T7 may be provided as P-type MOSFETs. However, this is only an example, and some of the first to seventh transistors T1 to T7 may be provided as N-type MOSFETs. For example, among the first to seventh transistors T1 to T7, the third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0149] Figure 5 It is shown Figure 4 A cross-sectional view of a light-emitting element and a first transistor and a sixth transistor.

[0150] refer to Figure 5 According to an embodiment, a display device 100 may include a substrate 110 , a circuit layer 120 located on the substrate 110 , and an element layer 130 located on the circuit layer 120 .

[0151] In addition, the display device 100 may further include an encapsulation layer 140 disposed on the element layer 130 , a touch sensor layer 150 disposed on the encapsulation layer 140 , and a polarization layer 160 disposed on the touch sensor layer 150 .

[0152] The touch sensor layer 150 may be disposed on the touch buffer layer covering the encapsulation layer 140 .

[0153] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may include polyimide.

[0154] like Figure 5 As shown in, according to an embodiment, the circuit layer 120 may include a first semiconductor layer (including channel portions CH1 and CH6, source portions S1 and S6, and drain portions D1 and D6) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1 and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer (including a pixel capacitor electrode CAE) disposed on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer, a first source-drain conductive layer (including a first anode connection electrode ANDE1) disposed on the first interlayer insulating layer 124, a first planarizing layer 125 covering the first source-drain conductive layer, a second source-drain conductive layer (including a second anode connection electrode ANDE2) disposed on the first planarizing layer 125, and a second planarizing layer 126 covering the second source-drain conductive layer.

[0155] The circuit layer 120 may further include a buffer layer 121 covering the substrate 110. In this case, the first semiconductor layer may be disposed on the buffer layer 121.

[0156] The circuit layer 120 may include light-emitting pixel drivers EPD electrically connected to the light-emitting elements LE disposed in the emission area EA, respectively, and wiring for transmitting various signals and voltages to the light-emitting pixel drivers EPD. Each of the light-emitting pixel drivers EPD may include a first transistor T1 and two or more transistors T2 to T7 electrically connected to the first transistor T1 (see Figure 4 ).

[0157] According to an embodiment, the first transistor T1 may include a channel portion CH1, a source portion S1, and a drain portion D1 disposed in a first semiconductor layer located on a substrate 110, and a gate electrode G1 disposed in a first gate conductive layer located on a first gate insulating layer 122 covering the first semiconductor layer. The source portion S1 and the drain portion D1 may be connected to both ends of the channel portion CH1. The source portion S1 and the drain portion D1 may be doped at a concentration higher than that of the channel portion CH1. The gate electrode G1 may overlap the channel portion CH1.

[0158] Similarly, the sixth transistor T6 may include a channel portion CH6 , a source portion S6 , and a drain portion D6 disposed in a first semiconductor layer on the substrate 110 , and a gate electrode G6 disposed in a first gate conductive layer on a first gate insulating layer 122 covering the first semiconductor layer.

[0159] According to an embodiment, the second to fifth transistors T2 to T5 and the seventh transistor T7 have substantially the same structure as those of the first transistor T1 and the sixth transistor T6 , and thus, redundant descriptions will be omitted below.

[0160] The pixel capacitor PC1 may be provided as an overlap region between the gate electrode G1 of the first transistor T1 and the pixel capacitor electrode CAE. The pixel capacitor electrode CAE may be disposed in a second gate conductive layer on the second gate insulating layer 123 covering the first gate conductive layer.

[0161] The anode electrode 131 of the element layer 130 may be electrically connected to the drain portion D6 of the sixth transistor T6 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2 .

[0162] The first anode connection electrode ANDE1 may be disposed in the first source-drain conductive layer on the first interlayer insulating layer 124 covering the second gate conductive layer. The first anode connection electrode ANDE1 may be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode contact hole ANCT1 penetrating the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0163] The second anode connection electrode ANDE2 may be disposed in the second source-drain conductive layer on the first planarization layer 125 covering the first source-drain conductive layer. The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 penetrating the first planarization layer 125.

[0164] The element layer 130 may include light emitting elements LE disposed on the second planarization layer 126 and corresponding to the emission areas EA, respectively.

[0165] Each of the light emitting elements LE may include an anode electrode 131 and a cathode electrode 134 facing each other and a light emitting layer 133 disposed therebetween.

[0166] Alternatively, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134 .

[0167] That is, the element layer 130 may include anode electrodes 131 corresponding to the emission areas EA, respectively, a pixel defining layer 132 corresponding to the non-emission area NEA and covering the edge of the anode electrode 131, a light-emitting layer 133 respectively arranged on the anode electrode 131, and a cathode electrode 134 arranged on the light-emitting layer 133 and the pixel defining layer 132.

[0168] The anode electrode 131 may be disposed in each of the emission areas EA, and may be electrically connected to a corresponding one of the light emitting pixel drivers EPD of the circuit layer 120. The anode electrode 131 may be referred to as a pixel electrode.

[0169] The anode electrode 131 may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second planarization layer 126 .

[0170] The light emitting layer 133 may be formed of an organic light emitting material that converts electron-hole pairs into light.

[0171] The cathode electrode 134 may be disposed on the pixel defining layer 132 and the light emitting layer 133 of the emission area EA. The second power ELVSS may be applied to the cathode electrode 134. The cathode electrode 134 may be referred to as a common electrode.

[0172] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0173] The encapsulation layer 140 may include: a first encapsulation layer 141 arranged on the element layer 130 and made of an inorganic insulating material; a second encapsulation layer 142 arranged on the first encapsulation layer 141, overlapping with the element layer 130 and made of an organic insulating material; and a third encapsulation layer 143 arranged on the first encapsulation layer 141, covering the second encapsulation layer 142 and made of an inorganic insulating material.

[0174] Figure 6 It is shown Figure 1 Layout diagram of part C.

[0175] refer to Figure 6 According to a display device 100 of an embodiment (see Figure 1) of the circuit layer 120 (see Figure 2 ) may include: a light emitting pixel driver EPD arranged in the first direction DR1 and the second direction DR2 and electrically connected to the light emitting elements LE of the element layer 130 respectively; a gate line GL arranged in the second direction DR2 in the display area DA, extending in the first direction DR1 and used to transmit a gate signal to the light emitting pixel driver EPD; a gate driving circuit GDR including stages GIST, GCST, ECST and GWST disposed in a portion of the non-display area NDA and electrically connected to the gate line GL; a gate driving circuit GDR extending in the second direction DR2 and used to transmit a data signal Vdata (see Figure 4 ) is transmitted to the data line DL of the light emitting pixel driver EPD; a first auxiliary line ASL1 extending in the first direction DR1; and a second auxiliary line ASL2 extending in the second direction DR2 and adjacent to the data line DL in the first direction DR1.

[0176] According to one embodiment, the second auxiliary line ASL2 may include a gate bypass auxiliary line GBAL electrically connected between the stages GIST, GCST, ECST, and GWST of the gate driving circuit GDR arranged in the first direction DR1 and the gate line GL.

[0177] According to one embodiment, the substrate 110 may include a display area DA in which the emission area EA is arranged and a non-display area NDA disposed around the display area DA.

[0178] That is, the edge of the display area DA may be in contact with the non-display area NDA. The edge of the display area DA may include a first side SD1 extending in the first direction DR1.

[0179] According to one embodiment, at least a portion of the gate driving circuit GDR and the display driving circuit DDR may be disposed in a portion of the non-display area NDA facing the first side SD1 of the display area DA.

[0180] The display driving circuit DDR may supply the data signal Vdata to the light emitting pixel driver EPD through the data line DL.

[0181] In addition, the display driving circuit DDR can supply a gate driving control signal for controlling the output of the gate driving circuit GDR through the gate driving control supply line GDCSPL. The gate driving control signal may include at least one gate clock signal and at least one input carry signal, and the like.

[0182] The gate driving circuit GDR may include stages GIST, GCST, ECST, and GWST electrically connected to the gate lines GL.

[0183] The gate line GL is generally connected to the transistors T2 to T7 of the light-emitting pixel driver EPD (see Figure 4 ) is a wiring connected to at least one gate electrode.

[0184] That is, the gate line GL may include a signal for transmitting a scan write signal GW (see Figure 4 ) of the scanning write line GWL, used to transmit the scanning initialization signal GI (see Figure 4 ) of the scanning initialization line GIL, used to transmit the gate control signal GC (see Figure 4 ) and a gate control line GCL for transmitting an emission control signal EC (see Figure 4 )'s emission control line ECL.

[0185] Accordingly, the stages GIST, GCST, ECST and GWST of the gate drive circuit GDR may include a scan write stage GWST electrically connected to the scan write line GWL, a scan initialization stage GIST electrically connected to the scan initialization line GIL, an emission control stage ECST electrically connected to the emission control line ECL, and a gate control stage GCST electrically connected to the gate control line GCL.

[0186] The gate driving circuit GDR may include a first central circuit portion CNC1 facing a central portion of the first side SD1 of the edge of the display area DA in the second direction DR2 .

[0187] The first central circuit portion CNC1 may include stages GIST, GCST, ECST, and GWST arranged in a direction (ie, the first direction DR1 ) different from an arrangement direction (ie, the second direction DR2 ) of the gate lines GL.

[0188] That is, the stages GIST, GCST, ECST, and GWST of the first central circuit portion CNC1 may be arranged in the first direction DR1 which is an extending direction of the gate lines GL.

[0189] According to one embodiment, the first central circuit portion CNC1 may include a scan write stage GWST, a scan initialization stage GIST, an emission control stage ECST, and a gate control stage GCST.

[0190] The display area DA may include a display middle area DMDA disposed in a central portion in the first direction DR1 to face the first central circuit portion CNC1 in the second direction DR2 and a bypass area BPA contacting the display middle area DMDA in the first direction DR1.

[0191] Accordingly, the data lines DL may include a first data line DL1 disposed in the display middle area DMDA and extending in the second direction DR2 and a second data line DL2 disposed in the bypass area BPA and extending in the second direction DR2.

[0192] The first auxiliary line ASL1 may include a first bypass auxiliary line BPAL1 electrically connected to the first data line DL1 of the display middle area DMDA.

[0193] The second auxiliary line ASL2 may further include a second bypass auxiliary line BPAL2 adjacent to the second data line DL2 of the bypass area BPA in the first direction DR1 , extending in the second direction DR2 , and electrically connected to the first bypass auxiliary line BPAL1 .

[0194] The gate bypass auxiliary line GBAL among the second auxiliary lines ASL2 may be used to implement electrical connection between the gate line GL and the stage of the first central circuit portion CNC1 and thus, may be disposed in the display middle area DMDA facing the first central circuit portion CNC1.

[0195] That is, the first data line DL1 may be adjacent to one of the gate bypass auxiliary lines GBAL in the first direction DR1.

[0196] The display device 100 according to one embodiment may further include a display driving circuit DDR supplying a data signal Vdata of the data line DL.

[0197] According to one embodiment, the display driving circuit DDR may be mounted in a portion of the non-display area NDA of the substrate 110 facing the first side SD1 of the edge of the display area DA. The display driving circuit DDR may be spaced apart from the first central circuit portion CNC1 in the first direction DR1.

[0198] According to one embodiment, the circuit layer 120 may further include a data supply line DSPL electrically connected between the display driving circuit DDR and the data line DL.

[0199] The data supply line DSPL may be arranged in a portion of the non-display area NDA facing the first side SD1 of the edge of the display area DA, and may be spaced apart from the first central circuit portion CNC1 in the first direction DR1.

[0200] That is, the data supply line DSPL may extend from the display driving circuit DDR to the remaining portion of the first side SD1 of the edge of the display area DA except for a portion of the first side SD1 facing the first central circuit portion CNC1 .

[0201] In other words, the data supply line DSPL may extend from the display driving circuit DDR to the remaining areas of the display area DA except for the display middle area DMDA.

[0202] According to one embodiment, the first data line DL1 disposed in the display middle area DMDA may be electrically connected to the second bypass auxiliary line BPAL2 of the bypass area BPA through the first bypass auxiliary line BPAL1 extending in the first direction DR1.

[0203] Accordingly, among the data supply lines DSPL, the first data supply line DSPL1 for transmitting the data signal of the first data line DL1 may extend to the second bypass auxiliary line BPAL2 of the bypass area BPA and be electrically connected to the first data line DL1 through the first and second bypass auxiliary lines BPAL1 and BPAL2.

[0204] On the other hand, among the data supply lines DSPL, the second data supply line DSPL2 for transmitting the data signal of the second data line DL2 may extend to the bypass area BPA and be directly electrically connected to the second data line DL2.

[0205] The first bypass auxiliary line BPAL1 may be disposed between the first data line DL1 and the second bypass auxiliary line BPAL2 .

[0206] The second bypass auxiliary line BPAL2 may be disposed between the first data supply line DSPL1 and the first bypass auxiliary line BPAL1 .

[0207] Accordingly, in order to reduce visibility of the first and second bypass auxiliary lines BPAL1 and BPAL2 , the first auxiliary line ASL1 may further include a power assist horizontal line VASHL, and the second auxiliary line ASL2 may further include a power assist vertical line VASVL.

[0208] That is, two of the power assist horizontal lines VASHL may extend from opposite ends of the first bypass assist line BPAL1 to the third side SD3 in the first direction DR1, respectively (see FIG. 2 ). Figure 1 ) and the fourth side SD4 (see Figure 1 ).

[0209] In addition, one of the power assist vertical lines VASVL may extend from one end of the second bypass assist line BPAL2 to the second side SD2 in the second direction DR2 (see FIG. 2 ). Figure 1 ).

[0210] First Power ELVDD (see Figure 4 ), the second power ELVSS (see Figure 4 ), gate initialization voltage VGINT (see Figure 4) and the anode initialization voltage VAINT (see Figure 4 ) can be applied to each of the power assist horizontal line VASHL and the power assist vertical line VASVL.

[0211] In this manner, the first power ELVDD (see FIG. 14 ) can be stably maintained in the display area DA through the power assist horizontal line VASHL and the power assist vertical line VASVL. Figure 4 ), the second power ELVSS (see Figure 4 ), gate initialization voltage VGINT (see Figure 4 ) and the anode initialization voltage VAINT (see Figure 4 ) constant voltage.

[0212] Meanwhile, according to one embodiment, the display area DA may further include a side area SDA disposed between the bypass area BPA and the non-display area NDA in the first direction DR1.

[0213] In this case, the data lines DL may further include a third data line DL3 disposed in the side area SDA and extending in the second direction DR2.

[0214] The data supply line DSPL may extend to the bypass area BPA and the side area SDA.

[0215] Accordingly, among the data supply lines DSPL, the third data supply line DSPL3 for transmitting the data signal of the third data line DL3 may be extended to the side area SDA and directly electrically connected to the third data line DL3.

[0216] The third data line DL3 may be adjacent to one of the power assist vertical lines VASVL in the first direction DR1 .

[0217] In addition, the circuit layer 120 may further include first power ELVDD (see FIG. 1 ) for transmitting the light emitting elements of the element layer 130, respectively. Figure 4 ) and the second power ELVSS (see Figure 4 )'s first power supply line VDSPL and second power supply line VSSPL.

[0218] The first power supply line VDSPL and the second power supply line VSSPL may be disposed in the non-display area NDA. At least one of the first power supply line VDSPL and the second power supply line VSSPL may be disposed to surround the periphery of the display area DA.

[0219] Figure 7 is along Figure 6 A cross-sectional view taken along line D-D'.

[0220] like Figure 7 As shown in FIG. 1 , according to one embodiment, the data lines DL ( DL1 , DL2 , and DL3 ) and the second auxiliary lines ASL2 ( BPAL2 , GBAL, and VASVL) may be disposed on an insulating layer (eg, first planarization layer 125 ) covering the first auxiliary lines ASL1 ( BPAL1 and VASHL).

[0221] In one example, the first auxiliary line ASL1 (BPAL1 and VASHL) can be set in a first source-drain conductive layer located on the first interlayer insulating layer 124, and the data line DL and the second auxiliary line ASL2 (BPAL2, GBAL and VASVL) can be set in a second source-drain conductive layer located on the first planarization layer 125 covering the first source-drain conductive layer.

[0222] The first bypass auxiliary line BPAL1 may be electrically connected to each of the second bypass auxiliary line BPAL2 and the first data line DL1 through a connection hole penetrating the first planarization layer 125 .

[0223] According to one embodiment, each of the gate lines GL (GWL, GIL, GCL, and ECL) may be disposed in a first gate conductive layer on the first gate insulating layer 122 or in a second gate conductive layer on the second gate insulating layer 123 .

[0224] In one example, the gate control line GCL of the gate line GL may be disposed in the first gate conductive layer located on the first gate insulating layer 122. In this case, the gate bypass auxiliary line GBAL in the second auxiliary line ASL2 may be electrically connected to the gate control line GCL through a connection hole penetrating the first planarization layer 125, the first interlayer insulating layer 124, and the second gate insulating layer 123.

[0225] However, Figure 7 The illustrations are only examples, and each of the gate lines GL (GWL, GIL, GCL and ECL) can be set in at least one of the first gate conductive layer located on the first gate insulating layer 122, the second gate conductive layer located on the second gate insulating layer 123, and the first source-drain conductive layer located on the first interlayer insulating layer 124.

[0226] That is, any one of the gate lines GL disposed in the second gate conductive layer located on the second gate insulating layer 123 may be electrically connected to the gate bypass auxiliary line GBAL through a connection hole penetrating the first planarizing layer 125 and the first interlayer insulating layer 124 .

[0227] In addition, transistors T1 to T7 (see Figure 4) can be provided in one of a first gate conductive layer located on the first gate insulating layer 122 and a second gate conductive layer located on the second gate insulating layer 123.

[0228] Some of the gate electrodes of the transistors T1 to T7 may be provided as a portion of the gate line GL, and others may be electrically connected to the gate line GL through connection holes.

[0229] Figure 8 It is shown Figure 6 Equivalent circuit diagram of the scan write stage.

[0230] refer to Figure 8 , the scanning write stage GWST according to one embodiment may include eleventh to eighteenth transistors T11 to T18.

[0231] The sixteenth transistor T16 outputs the scanning write signal GW of the first gate level voltage GVH, and the seventeenth transistor T17 outputs the scanning write signal GW of the second gate level voltage GVL. The fourteenth transistor T14 and the fifteenth transistor T15 control outputs through the sixteenth transistor T16.

[0232] The eleventh transistor T11 , the twelfth transistor T12 , and the thirteenth transistor T13 control output through the seventeenth transistor T17 .

[0233] The eighteenth transistor T18 controls the connection among the eleventh transistor T11 , the twelfth transistor T12 , the thirteenth transistor T13 , and the seventeenth transistor T17 .

[0234] The eleventh transistor T11 is turned on by the second gate clock signal CLK2. When the eleventh transistor T11 is turned on, the write input carry signal WCRY of the scan write stage GWST may be transmitted to the second electrode of the thirteenth transistor T13, the gate electrode of the fourteenth transistor T14, and the first electrode of the eighteenth transistor T18.

[0235] The fourteenth transistor T14 is turned on by writing the input carry signal WCRY. The second gate clock signal CLK2 may be applied to the first electrode of the fourteenth transistor T14, and the first gate level voltage GVH may be applied to the second electrode of the fourteenth transistor T14 through the capacitor. Accordingly, when the fourteenth transistor T14 is turned on, the potential of the second electrode of the fourteenth transistor T14 may be changed to the high voltage of the second gate clock signal CLK2.

[0236] The twelfth transistor T12 may be turned on according to the potential of the second electrode of the fourteenth transistor T14. The first gate level voltage GVH may be applied to the first electrode of the twelfth transistor T12, and the second electrode of the twelfth transistor T12 may be connected to the first electrode of the thirteenth transistor T13.

[0237] The thirteenth transistor T13 is turned on according to the first gate clock signal CLK1 .

[0238] Accordingly, when the potential of the second electrode of the fourteenth transistor T14 has a low voltage and the first gate clock signal CLK1 has a low voltage, the potential of the second electrode of the thirteenth transistor T13 may be changed to the first gate level voltage GVH.

[0239] When the second gate clock signal CLK2 has a low voltage, the fifteenth transistor T15 may be turned on.

[0240] When the fifteenth transistor T15 is turned on and the potential of the second electrode of the fifteenth transistor T15 becomes the second gate level voltage GVL, the sixteenth transistor T16 may be turned on In this case, the output terminal of the scanning write stage GWST may output the first gate level voltage GVH.

[0241] However, Figure 8 The illustration in FIG. 1 is only an example, and the scanning writing stage GWST of the gate driving circuit GDR according to one embodiment is not limited to Figure 8 .

[0242] Fig. 9 It is shown Figure 6 Equivalent circuit diagram of the transmit control stage.

[0243] refer to Fig. 9 , the emission control stage ECST according to one embodiment may include twenty-first to thirty-third transistors T21 to T33 .

[0244] The twenty-ninth transistor T29 outputs the emission control signal EC of the third gate level voltage GVH′.

[0245] The output of the twenty-ninth transistor T29 may be controlled by the voltage of the first node EM_QB.

[0246] The twenty-sixth transistor T26 , the twenty-seventh transistor T27 , and the twenty-eighth transistor T28 control the voltage of the first node EM_QB.

[0247] The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are controlled by the voltage of the third-first node SR_QB_F.

[0248] Since the third-first node SR_QB_F is connected to the third node SR_QB through the thirty-first transistor T31 , the twenty-sixth transistor T26 and the twenty-seventh transistor T27 may be controlled by the voltage of the third node SR_QB.

[0249] The twenty-fourth transistor T24 and the twenty-fifth transistor T25 control the voltage of the third node SR_QB.

[0250] The thirtieth transistor T30 outputs the emission control signal EC of the fourth gate level voltage GVL′.

[0251] The output of the thirtieth transistor T30 may be controlled by the voltage of the second node SR_Q.

[0252] The thirty-second transistor T32 controls the connection between the thirtieth transistor T30 and the second node SR_Q.

[0253] The third gate level voltage GVH' is applied to the first electrode of the twenty-ninth transistor T29, and the second electrode of the twenty-ninth transistor T29 is connected to the output terminal of the emission control stage ECST. Accordingly, when the potential of the first node EM_QB has a low voltage, the emission control signal EC can be output through the twenty-ninth transistor T29 with the third gate level voltage GVH'.

[0254] The fourth gate level voltage GVL' is applied to the first electrode of the thirtieth transistor T30, and the second electrode of the thirtieth transistor T30 is connected to the output terminal of the emission control stage ECST. Accordingly, when the potential of the second-first node SR_Q_F has a low voltage, the emission control signal EC can be output with the fourth gate level voltage GVL' through the thirtieth transistor T30. On the other hand, when the potential of the second-first node SR_Q_F has a high voltage, the thirtieth transistor T30 has no output.

[0255] The third gate level voltage GVH' is applied to the first electrode of the 28th transistor T28, the second electrode of the 28th transistor T28 is connected to the first node EM_QB, and the gate electrode of the 28th transistor T28 is connected to the second node SR_Q. Accordingly, when the second node SR_Q has a low voltage, the third gate level voltage GVH' can be transmitted to the first node EM_QB through the 28th transistor T28.

[0256] The twenty-first capacitor C21 may store the voltage of the first node EM_QB.

[0257] The sixth gate clock signal CLK6 may be applied to the gate electrode of the twenty-sixth transistor T26 , a first electrode of the twenty-sixth transistor T26 may be connected to the fourth node EM_C, and a second electrode of the twenty-sixth transistor T26 may be connected to the first node EM_QB.

[0258] A gate electrode of the twenty-seventh transistor T27 is connected to the third-first node SR_QB_F, the sixth gate clock signal CLK6 is applied to a first electrode of the twenty-seventh transistor T27, and a second electrode of the twenty-seventh transistor T27 is connected to the fourth node EM_C. Due to the twenty-sixth transistor T26 and the twenty-seventh transistor T27, when the potential of the third node SR_QB and the sixth gate clock signal CLK6 have a low voltage, the potential of the first node EM_QB can be changed to the sixth gate clock signal CLK6.

[0259] The fifth gate clock signal CLK5 is applied to the gate electrode of the twenty-first transistor T21, the emission carry input signal ECRY is input to the first electrode of the twenty-first transistor T21, and the second electrode of the twenty-first transistor T21 is connected to the second node SR_Q. Accordingly, due to the twenty-first transistor T21, when the fifth gate clock signal CLK5 has a low voltage, the potential of the second node SR_Q can be changed to the emission carry input signal ECRY.

[0260] Since the fourth gate level voltage GVL′ is applied to the gate electrode of the 32nd transistor T32 , since the 32nd transistor T32 is in a turned-on state, the potential of the second-first node SR_Q_F may be maintained at the same level as that of the second node SR_Q.

[0261] The gate turn-on signal ESR is applied to the gate electrode of the thirty-third transistor T33, the third gate level voltage GVH' is applied to the first electrode of the thirty-third transistor T33, and the second electrode of the thirty-third transistor T33 is connected to the second node SR_Q. In this way, since the thirty-third transistor T33 is maintained in the on state, the potential of the second node SR_Q can be maintained at the third gate level voltage GVH'.

[0262] A gate electrode of the twenty-second transistor T22 is connected to the third node SR_QB, a third gate level voltage GVH′ is applied to a first electrode of the twenty-second transistor T22 , and a second electrode of the twenty-second transistor T22 is connected to the fifth node EM_A.

[0263] A gate electrode of the twenty-third transistor T23 is connected to the second-first node SR_Q_F, the sixth gate clock signal CLK6 is applied to a first electrode of the twenty-third transistor T23 , and a second electrode of the twenty-third transistor T23 is connected to the fifth node EM_A.

[0264] Due to the twenty-second transistor T22 and the twenty-third transistor T23 , when both the potentials of the sixth gate clock signal CLK6 and the third node SR_QB have a low voltage, the potential of the second node SR_Q may be changed to a high voltage.

[0265] A gate electrode of the 24th transistor T24 is connected to the second node SR_Q, a fifth gate clock signal CLK5 is applied to a first electrode of the 24th transistor T24, and a second electrode of the 24th transistor T24 is connected to the third node SR_QB. The 24th transistor T24 may include two sub-transistors connected in series.

[0266] The fifth gate clock signal CLK5 is applied to the gate electrode of the twenty-fifth transistor T25 , the fourth gate level voltage GVL′ is applied to the first electrode of the twenty-fifth transistor T25 , and the second electrode of the twenty-fifth transistor T25 is connected to the third node SR_QB.

[0267] Accordingly, due to the twenty-fifth transistor T25, the potential of the third node SR_QB can be changed to the fourth gate level voltage GVL'. Further, due to the twenty-fourth transistor T24, when the potential of the second node SR_Q has a low voltage, the voltage of the third node SR_QB can be changed to the voltage of the fifth gate clock signal CLK5.

[0268] However, Fig. 9 The illustration in FIG. 1 is only an example, and the emission control stage ECST of the gate driving circuit GDR according to one embodiment is not limited to Fig. 9 .

[0269] In addition, each of the scan initialization stage GIST and the gate control stage GCST of the gate drive circuit GDR is similar to Figure 8 The scan write level GWST or Fig. 9 of the emission control stage ECST, and therefore, redundant description will be omitted below.

[0270] As described above, the display device 100 according to one embodiment includes a gate bypass auxiliary line GBAL provided as a part of the second auxiliary line ASL2 and adjacent to the data line DL in the first direction DR1. Accordingly, even if the stages GWST, GIST, ECST, and GCST of the gate driving circuit GDR are arranged in the first direction DR1 different from the arrangement direction of the gate line GL, the electrical connection between the stages GWST, GIST, ECST, and GCST arranged in the first direction DR1 and the gate line GL can also be achieved through the gate bypass auxiliary line GBAL.

[0271] Therefore, the gate driving circuit GDR may be disposed in a portion of the non-display area NDA facing the first side SD1 of the display area DA.

[0272] That is, the region in which the gate driving circuit GDR is disposed may not be limited to a portion of the non-display area NDA facing the third side SD3 or the fourth side SD4 of the display area DA.

[0273] Accordingly, through the gate bypass auxiliary line GBAL, the portion in which the gate driving circuit GDR is disposed can be more freely designed, which can be advantageous in reducing the width of the non-display area NDA.

[0274] Furthermore, since the lengths of the first and second sides SD1 and SD2 of the display area DA do not affect the separation distance between the gate line GL and the gate driving circuit GDR, the signal of the gate line GL may be stably supplied even if the width of the display area DA in the first direction DR1 increases.

[0275] In addition, according to one embodiment, since the stages GWST, GIST, ECST and GCST arranged in the first direction DR1 are opposite to the display middle area DMDA, the data supply line DSPL electrically connected between the display driving circuit DDR and the data line DL needs to extend to the remaining areas of the display area DA except the display middle area DMDA so as to avoid the stages GWST, GIST, ECST and GCST arranged in the first direction DR1.

[0276] However, since the display device 100 according to one embodiment includes a first bypass auxiliary line BPAL1 provided as a part of the first auxiliary line ASL1 and a second bypass auxiliary line BPAL2 provided as another part of the second auxiliary line ASL2, the first data line DL1 of the display middle area DMDA can be electrically connected to the first data supply line DSPL1 through the first bypass auxiliary line BPAL1 and the second bypass auxiliary line BPAL2.

[0277] In addition, according to one embodiment, the gate bypass auxiliary line GBAL and the second bypass auxiliary line BPAL2 are provided as a part of the second auxiliary line ASL2 and are adjacent to the data line DL in the first direction DR1. In other words, there is no need to provide a separate conductive layer or a separate area for arranging the gate bypass auxiliary line GBAL and the second bypass auxiliary line BPAL2, which can be beneficial to make the display device 100 slim and improve the resolution of the display device 100.

[0278] At the same time, according to Figure 6 In one embodiment shown in FIG. 1 , the gate bypass auxiliary line GBAL among the second auxiliary lines ASL2 extends from the first central circuit portion CNC1 to the second side SD2 of the display area DA.

[0279] However, since the gate bypass auxiliary lines GBAL are intended to provide electrical connections between the stages GWST, GIST, ECST, and GCST of the first central circuit portion CNC1 and the gate lines GL, they may not extend to the second side SD2.

[0280] Fig.10 is a diagram showing a method according to an embodiment Figure 1 Layout diagram of part C.

[0281] In addition to the gate bypass auxiliary lines GBAL extending from the first central circuit portion CNC1 to the gate lines GL, Fig.10 A display device 100 (see FIG. Figure 1 )and Figure 6 The display device 100 of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 1 . Therefore, redundant description will be omitted below.

[0282] according to Fig.10 In one embodiment, one of the power auxiliary vertical lines VASVL may extend from one end of one gate bypass auxiliary line GBAL to the second side SD2 (see Figure 1 ).

[0283] In this manner, the extension length of the gate bypass auxiliary line GBAL may be reduced, and thus, a coupling defect caused by the gate bypass auxiliary line GBAL may be reduced.

[0284] Fig.11 is a plan view illustrating a display device according to an embodiment. Fig.12 It is a graphic Fig.11 Layout diagram of section E. Fig.13 It is a graphic Fig.11 Layout diagram of section F.

[0285] In addition to the gate driving circuit GDR further including a second central circuit portion CNC2 facing a central portion of a second side SD2 of an edge of the display area DA, Fig.11 , Fig.12 and Fig.13 The display device 100A of one embodiment shown in FIG. Figures 1 to 10 The display device 100 of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 1 . Therefore, redundant description will be omitted below.

[0286] like Fig.11 As shown in, according to one embodiment, the display middle area DMDA of the display area DA may be disposed between the first central circuit portion CNC1 and the second central circuit portion CNC2 in the second direction DR2. In an embodiment, the first central circuit portion CNC1 and the second central circuit portion CNC2 may face only the display middle area DMDA among the display middle area DMDA, the bypass area BPA, and the side area SDA in the second direction DR2.

[0287] like Fig.12 and Fig.13 As shown in FIG. 1 , the stages GWST, GIST, ECST, and GCST of the second central circuit portion CNC2 may be arranged in the first direction DR1 and may be electrically connected to the gate lines GL (GWL, ECL, GCL, and GIL) through the gate bypass auxiliary lines GBAL.

[0288] That is, according to one embodiment, each of the first central circuit portion CNC1 and the second central circuit portion CNC2 may include a scan write stage GWST, a scan initialization stage GIST, an emission control stage ECST, and a gate control stage GCST.

[0289] According to one embodiment, the display area DA may include n pixel rows (where n is a natural number greater than or equal to 6), and each of the pixel rows may include emission regions arranged in the first direction DR1. Figure 2 ) may include gate line groups GL_1, GL_2, GL_3, GL_n-2, GL_n-1 and GL_n corresponding to the pixel rows respectively.

[0290] According to one embodiment, each of the gate line groups GL_1, GL_2, GL_3, GL_n-2, GL_n-1, and GL_n may include a signal for transmitting a scan write signal GW (see Figure 4 ) of the scanning write line GWL, used to transmit the scanning initialization signal GI (see Figure 4 ) of the scanning initialization line GIL, used to transmit the gate control signal GC (see Figure 4 ) and a gate control line GCL for transmitting an emission control signal EC (see Figure 4 )'s emission control line ECL.

[0291] The gate line groups GL_1 , GL_2 , GL_3 , GL_n- 2 , GL_n- 1 , and GL_n may be arranged between the first side SD1 and the second side SD2 in the second direction DR2 .

[0292] The gate line groups GL_1, GL_2, GL_3, GL_n-2, GL_n-1, and GL_n may be connected one-to-one with the stage groups STG_1, STG_2, STG_3, STG_n-2, STG_n-1, and STG_n of each of the first and second central circuit portions CNC1 and CNC2.

[0293] The stage groups STG_1 , STG_2 , STG_3 , STG_n- 2 , STG_n- 1 , and STG_n of each of the first and second central circuit portions CNC1 and CNC2 may be arranged between the third and fourth sides SD3 and SD4 in the first direction DR1 .

[0294] For example, Fig.12 As shown in FIG. 1 , the gate line groups GL_1 , GL_2 , and GL_3 adjacent to the first side SD1 may be connected to the stage groups STG_1 , STG_2 , and STG_3 adjacent to the third side SD3 .

[0295] In addition, if Fig.13 As shown in FIG. 1 , the gate line groups GL_n-2, GL_n-1, and GL_n adjacent to the second side SD2 may be connected to the stage groups STG_n-2, STG_n-1, and STG_n adjacent to the fourth side SD4.

[0296] In this manner, a difference in wiring resistance due to a separation distance between each gate line GL and the first side SD1 may be reduced, and thus, a difference in signal distortion of the gate lines GL (GWL, ECL, GCL, and GIL) may be reduced.

[0297] Fig.14 is a plan view illustrating a display device according to an embodiment. Fig.15 It is a graphic Fig.14 Layout diagram of part G.

[0298] In addition to further comprising a circuit board CB on which a display driving circuit DDR is mounted and a signal pad SPD connected to the circuit board CB, Fig.14 and Fig.15 The display device 100B of one embodiment shown in FIG. Figures 11 to 13 The display device 100A of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 10A . Therefore, redundant description will be omitted below.

[0299] According to one embodiment, since the display driving circuit DDR is prepared as an integrated circuit (IC), the display driving circuit DDR may be mounted on the circuit board CB using a chip on film ("COF") method.

[0300] The circuit board CB may be electrically connected to the circuit layer 120 by being connected and bonded to the signal pads SPD arranged in the non-display area NDA of the substrate 110 (see Figure 2 ).

[0301] like Fig.15 As shown in , the signal pad SPD may be disposed in a portion of the non-display area NDA of the substrate 110 facing the first side SD1 of the display area DA. The signal pad SPD may be spaced apart from the first central circuit portion CNC1 in the first direction DR1.

[0302] That is, in a portion of the non-display area NDA facing the first side SD1 of the display area DA, the signal pad SPD and the first central circuit portion CNC1 may be arranged in the first direction DR1.

[0303] The signal pad SPD may include a data signal Vdata for transmitting the data line DL (see Figure 4 ) data pad DTPD, used to transmit the first power ELVDD (see Figure 4 ) for transmitting the second power ELVSS (see Figure 4 ) and a second power pad VSPD for transmitting a gate driving control signal.

[0304] The data supply line DSPL may extend from the data pad DTPD to the bypass area BPA and the side area SDA beyond the first side SD1 .

[0305] Fig.16 is a plan view illustrating a display device according to an embodiment.

[0306] In addition to the gate driving circuit GDR further including a side circuit portion SDC facing at least one of the third side SD3 and the fourth side SD4 of the display area DA, Fig.16 The display device 100C of one embodiment shown in FIG. Figures 1 to 10 The display device 100 of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 1 . Therefore, redundant description will be omitted below.

[0307] like Fig.16As shown in, the gate lines GWL, ECL, GCL and GIL included in any one gate line group GL_i (i is a natural number greater than or equal to 1 and less than or equal to n) among the gate line groups corresponding to the pixel rows can be electrically connected to the first central circuit part CNC1 through the gate bypass auxiliary line GBAL, and can be extended in the first direction DR1 to be electrically connected to the side circuit part SDC.

[0308] according to Fig.16 In one embodiment, each of the first central circuit portion CNC1 and the side circuit portion SDC may include a reference Figure 6 The described scan write stage GWST, scan initialization stage GIST, emission control stage ECST and gate control stage GCST.

[0309] In this manner, even in a portion of the display area DA adjacent to the third side SD3 or the fourth side SD4 and spaced apart from the gate bypass auxiliary line GBAL, signals of the gate lines GWL, ECL, GCL, and GIL may be stably supplied by the side circuit portion SDC.

[0310] Fig.17 is a plan view illustrating a display device according to an embodiment.

[0311] In addition to the gate driving circuit GDR further including a second central circuit portion CNC2 facing a central portion of the second side SD2 of the display area DA and a side circuit portion SDC facing at least one of the third side SD3 and the fourth side SD4 of the display area DA, Fig.17 The display device 100D of one embodiment shown in FIG. Figures 1 to 10 The display device 100 of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 1 . Therefore, redundant description will be omitted below.

[0312] In this manner, a deviation in a separation distance between each portion of the display area DA and the gate driving circuit GDR may be reduced, so that signals of the gate lines GWL, ECL, GCL, and GIL may be more stably supplied throughout the display area DA.

[0313] Fig.18 is a plan view illustrating a display device according to an embodiment.

[0314] In addition to the gate drive circuit GDR including a first central circuit portion CNC1' and a side circuit portion SDC' including different stages, Fig.18 The display device 100E of one embodiment shown in FIG. Fig.16 The display device 100C of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 100C. Therefore, redundant description will be omitted below.

[0315] like Fig.18 As shown in , some of the write scan lines GWL, emission control lines ECL, gate control lines GCL and scan initialization lines GIL included in any one gate line group GL_i may be electrically connected to the first central circuit portion CNC1', and the other lines may be electrically connected to the side circuit portion SDC'.

[0316] That is, the first central circuit portion CNC1' may include some of the scan write stage GWST, the scan initialization stage GIST, the emission control stage ECST and the gate control stage GCST, and the side circuit portion SDC' may include other of the scan write stage GWST, the scan initialization stage GIST, the emission control stage ECST and the gate control stage GCST.

[0317] In one example, among the write scan line GWL, the emission control line ECL, the gate control line GCL and the scan initialization line GIL included in any one gate line group GL_i, the write scan line GWL and the emission control line ECL can be electrically connected to the first central circuit portion CNC1', and the gate control line GCL and the scan initialization line GIL can be electrically connected to the side circuit portion SDC'.

[0318] However, Fig.18 The illustration in FIG. 1 is only an example, and the electrical connection configuration between the write scan line GWL, the emission control line ECL, the gate control line GCL and the scan initialization line GIL and the first central circuit portion CNC1′ and the side circuit portion SDC′ may be changed to Fig.18 The icons are different.

[0319] In this way, since each of the first central circuit portion CNC1' and the side circuit portion SDC' does not include all the stages, the arrangement area of ​​each of the first central circuit portion CNC1' and the side circuit portion SDC' can be reduced. Accordingly, it is advantageous to reduce the width of the non-display area NDA.

[0320] Fig.19 is a plan view illustrating a display device according to an embodiment. Fig. 20 It shows that according to Fig.19 An equivalent circuit diagram of a light-emitting pixel driver of an embodiment. Fig.21 It is shown Fig. 20 A cross-sectional view of a first transistor, a second transistor, a sixth transistor, a fourth transistor and a light emitting element.

[0321] In addition to the gate line GL, it further includes a circuit for transmitting a bias control signal GB (see Fig. 20 ) in addition to the bias control line GBL, Fig.19 The display device 100F of one embodiment shown in FIG. Figures 1 to 10The display device 100 of the embodiment shown in FIG. 1 is substantially the same as that of the embodiment shown in FIG. 1 . Therefore, redundant description will be omitted below. However, the bias control line GBL may further include Figures 11 to 18 In the display devices 100A to 100E of the embodiments shown in .

[0322] refer to Fig. 20 , except for the circuit layer 120 (see Figure 2 ) further includes a bias control line GBL for transmitting a bias control signal GB and a bias voltage line VBL for transmitting a bias voltage VBS, each light-emitting pixel driver EPD of the circuit layer 120 further includes an eighth transistor T8 electrically connected between the first node N1 and the bias voltage line VBL, and the third transistor T3 and the fourth transistor T4 are provided as N-type MOSFETs, Fig.19 One embodiment shown in FIG. Fig. 20 The display device 100F including the light emitting pixel driver EPD shown in FIG. Figure 4 The display device of one embodiment of the light emitting pixel driver EPD shown in FIG. 1 is substantially the same as that of FIG. 1 . Therefore, redundant description will be omitted below.

[0323] The eighth transistor T8 may be turned on by the bias control signal GB of the bias control line GBL.

[0324] Unlike the second transistor T2 , the third transistor T3 may be provided as an N-type MOSFET, and thus, may be turned on by the gate control signal GC of the gate control line GCL.

[0325] The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0326] Unlike the fourth transistor T4 , the seventh transistor T7 may be provided as a P-type MOSFET, and thus, may be turned on by the bias control signal GB of the bias control line GBL.

[0327] according to Fig.21 In addition to further including a second semiconductor layer (including a channel portion CH4, a source portion S4, and a drain portion D4) disposed on the first interlayer insulating layer 124, a third gate insulating layer 127 covering the second semiconductor layer, a third gate conductive layer (including a gate electrode G4) disposed on the third gate insulating layer 127, and a second interlayer insulating layer 128 covering the third gate conductive layer, the circuit layer 120 and Figure 5 The circuit layer 120 of one embodiment of the present invention is substantially similar. Therefore, redundant description will be omitted below.

[0328] In this case, a first source-drain conductive layer may be disposed on the second interlayer insulating layer 128 .

[0329] The circuit layer 120 may further include a first light blocking layer LB1 overlapping the channel portion CH1 of the first transistor T1 of the first semiconductor layer and a second light blocking layer LB2 overlapping the channel portion CH4 of the fourth transistor T4 of the second semiconductor layer.

[0330] The buffer layer 121 may cover the first light blocking layer LB1 .

[0331] The second light blocking layer LB2 may be disposed in the second gate conductive layer.

[0332] The first source-drain conductive layer may further include a gate initialization voltage line VGIL, a gate connection electrode GCNE, and a data connection electrode DCE.

[0333] The gate initialization voltage line VGIL may be electrically connected to the source portion S4 of the fourth transistor T4 through the initialization connection hole VICH.

[0334] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 and the gate electrode G1 of the first transistor T1 through the first and second gate connection holes GCH1 and GCH2 , respectively.

[0335] The data line DL may be disposed in the second source-drain conductive layer and electrically connected to the data connection electrode DCE through the data connection hole DCH.

[0336] The data link electrode DCE may be electrically connected to the source portion S2 of the second transistor T2 through the data auxiliary connection hole DCAH.

[0337] As mentioned above, in Fig.19 , Fig. 20 and Fig.21 In the display device 100F of one embodiment shown in FIG. 1 , the gate driving circuit GDR may be electrically connected to the bias control line GBL through the gate bypass auxiliary line GBAL.

[0338] The gate driving circuit GDR may include a first central circuit portion CNC1 facing a central portion of the first side SD1 .

[0339] Alternatively, the gate driving circuit GDR may further include Fig.11 A second central circuit portion CNC2 facing the central portion of the second side SD2 is depicted.

[0340] Alternatively, the gate driving circuit GDR may further include Fig.16 A side circuit portion SDC facing the third side SD3 or the fourth side SD4 is described.

[0341] Each of the first central circuit part CNC1, the second central circuit part CNC2, and the side circuit part SDC may be electrically connected to the scan write line GWL, the scan initialization line GIL, the gate control line GCL, the emission control line ECL, and the bias control line GBL.

[0342] Fig. 22 is a plan view illustrating a display device according to an embodiment.

[0343] Except that some of the scan write lines GWL, the scan initialization lines GIL, the gate control lines GCL, the emission control lines ECL, and the bias control lines GBL are electrically connected to the first central circuit portion CNC1″ or the second central circuit portion CNC2″, and the other lines are electrically connected to the side circuit portion SDC′, Fig. 22 The display device 100G of one embodiment shown in FIG. Fig.19 , Fig. 20 and Fig.21 The display device 100F of one embodiment shown in FIG. 1 is substantially the same as that of FIG. 100F. Therefore, redundant description will be omitted below.

[0344] In this manner, the arrangement width of each of the first central circuit portion CNC1 ″ or the second central circuit portion CNC2 ″ and the side circuit portion SDC′ may be reduced, which may be advantageous in reducing the width of the non-display area NDA.

[0345] However, the effects of the present disclosure are not limited to the effects described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: a substrate including a display area in which the emission area is arranged and a non-display area disposed around the display area; A circuit layer is arranged on the substrate; as well as an element layer, which is disposed on the circuit layer and includes light emitting elements respectively disposed in the emission regions, Wherein, the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements, respectively, and arranged in parallel with each other in a first direction and a second direction intersecting the first direction; a gate line, arranged in the display area in the second direction, extending in the first direction, and used for transmitting a gate signal to the light-emitting pixel driver; a gate driving circuit including a plurality of stages disposed in a portion of the non-display area, arranged in the first direction and electrically connected to the gate lines; a data line extending in the second direction and used for transmitting a data signal to the light-emitting pixel driver; a first auxiliary line extending in the first direction; and a second auxiliary line extending in the second direction and adjacent to the data line in the first direction, Wherein, the second auxiliary line comprises a gate bypass auxiliary line electrically connected between the gate line and the plurality of stages, Wherein, the edge of the display area includes: a first side and a second side extending in the first direction and facing each other in the second direction; and a third side and a fourth side, connecting the first side to the second side, facing each other in the first direction, and each having a length shorter than a length of each of the first side and the second side, wherein the gate driving circuit includes a first central circuit portion, the first central circuit portion faces the central portion of the first side in the second direction, and includes a first stage among the plurality of stages arranged in the first direction, The display area further includes: a display middle area facing the first central circuit portion in the second direction; and a bypass area contacting the display middle area in the first direction. The first auxiliary line includes a first bypass auxiliary line, and the first bypass auxiliary line is electrically connected to a first data line disposed in the display middle area among the data lines. The second auxiliary line further includes a second bypass auxiliary line, the second bypass auxiliary line being adjacent to a second data line disposed in the bypass region among the data lines and being electrically connected to the first bypass auxiliary line, and The gate bypass auxiliary line is arranged in the display middle area.

2. The display device according to claim 1, further comprising a display driving circuit configured to supply the data signal to the data line, in, The circuit layer further comprises: a data supply line disposed in a portion of the non-display area facing the first side, spaced apart from the first central circuit portion in the first direction, and electrically connected between the data line and the display driving circuit, Among the data supply lines, a first data supply line transmitting the data signal of the first data line is electrically connected to the first data line through the first bypass auxiliary line and the second bypass auxiliary line, Among the data supply lines, a second data supply line transmitting the data signal of the second data line is directly electrically connected to the second data line, and The first data line is adjacent to one of the gate bypass auxiliary lines in the first direction.

3. The display device according to claim 2, wherein: The display driving circuit is mounted on a portion of the non-display area of ​​the substrate facing the first side and is spaced apart from the first central circuit portion in the first direction.

4. The display device according to claim 2, further comprising: A circuit board, wherein the display driving circuit is mounted on the circuit board; as well as a signal pad, the circuit board being connected to the signal pad, The signal pad is disposed in the non-display area of ​​the substrate, faces the first side, and is spaced apart from the first central circuit portion in the first direction.

5. The display device according to claim 2, wherein: Each of the light-emitting pixel drivers of the circuit layer comprises: a first transistor electrically connected between the first node and the second node; a pixel capacitor electrically connected between the third node and a first power line for transmitting the first power; a second transistor electrically connected between the data line and the first node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between the third node and a gate initialization voltage line for transmitting a gate initialization voltage; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between the second node and a fourth node; and a seventh transistor electrically connected between the fourth node and an anode initialization voltage line for transmitting an anode initialization voltage, wherein the first node is electrically connected to a first electrode of the first transistor, the second node is electrically connected to the second electrode of the first transistor, The third node is electrically connected to the gate electrode of the first transistor, The fourth node is electrically connected to a corresponding one of the light emitting elements, and Wherein, the gate line comprises: A scan write line, used for transmitting a scan write signal to the light-emitting pixel driver; A scan initialization line, used to transmit a scan initialization signal to the light-emitting pixel driver; an emission control line, used to transmit an emission control signal to the light-emitting pixel driver; and a gate control line, used to transmit a gate control signal to the light-emitting pixel driver, The second transistor and the third transistor are turned on by the scan write signal. The fourth transistor is turned on by the scan initialization signal, The fifth transistor and the sixth transistor are turned on by the emission control signal, and The seventh transistor is turned on by the gate control signal.

6. The display device according to claim 5, wherein: The gate driving circuit further comprises: a second central circuit portion facing the central portion of the second side of the display area, wherein the display middle area of ​​the display region is arranged between the first central circuit portion and the second central circuit portion in the second direction, wherein the second stage of the second central circuit part among the plurality of stages is arranged in the first direction and is electrically connected to the gate line through the gate bypass auxiliary line, and Wherein, each of the first central circuit portion and the second central circuit portion comprises: a scan write stage electrically connected to the scan write line; a scan initialization stage electrically connected to the scan initialization line; an emission control stage electrically connected to the emission control line; and A gate control stage is electrically connected to the gate control line.

7. The display device according to claim 5, wherein: The gate driving circuit further comprises: A side circuit portion faces at least one of the third side and the fourth side of the display area.

8. The display device according to claim 7, wherein: Each of the first central circuit portion and the side circuit portion comprises: a scan write stage electrically connected to the scan write line; a scan initialization stage electrically connected to the scan initialization line; an emission control stage electrically connected to the emission control line; and A gate control stage is electrically connected to the gate control line.

9. The display device according to claim 7, wherein: Some of the scan write lines, the scan initialization lines, the emission control lines, and the gate control lines are electrically connected to the first central circuit portion, and All of the scan write lines, the scan initialization lines, the emission control lines, and the gate control lines except for the some lines are electrically connected to the side circuit portion.

10. The display device according to claim 5, wherein: The grid line further comprises: A bias control line, used to transmit a bias control signal to the light-emitting pixel driver, Each of the light-emitting pixel drivers of the circuit layer further includes an eighth transistor electrically connected between a bias power line and the first node, and The eighth transistor is turned on by the bias control signal.

Images