Display panel and display device

Abstract

The application relates to a display panel and a display device, and relates to the technical field of display driving. The display panel comprises a plurality of first potential lines, a plurality of second potential lines, a plurality of reset signal lines and a display area. Each display area comprises a plurality of sub-display areas formed by a plurality of pixel structures. The pixel structure comprises a light-emitting device and a light-emitting control circuit arranged between the first potential line and the anode of the light-emitting device. The reset signal line is connected with the light-emitting control circuit, and the second potential line is connected with the cathode of the light-emitting device. The pixel structure of each sub-display area is connected with different reset signal lines, and the pixel structure of each sub-display area is connected with different first potential lines and / or different second potential lines. By allocating independent reset signal lines, first potential lines and / or second potential lines to the pixel structure of each sub-display area, the driving current of the light-emitting device in each sub-display area can be adjusted individually, and the uniformity of the brightness of the display panel can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) display panel is a display panel that utilizes the self-luminous characteristic of organic material under the action of current to achieve precise control at the pixel level, thereby presenting delicate and colorful images, and is widely used in various electronic devices such as smart phones, tablet computers, televisions and monitors.

[0003] However, in the OLED display panel, the Driver IC (Drive Integrated Circuit) is responsible for providing a driving voltage to light up the OLED pixels. However, the transmission of the driving voltage is gradually reduced due to the influence of the resistance on the transmission line, forming a voltage drop (IRDrop), thereby affecting the luminance of the pixels at different positions in the display panel.

[0004] Therefore, how to improve the uniformity of the luminance of the pixels at different positions in the display panel is a problem to be solved at present. SUMMARY

[0005] Embodiments of the present application provide a display panel to at least partially solve the above technical problems.

[0006] In order to achieve the above purpose, according to the first aspect of the present application, a display panel is provided, comprising:

[0007] a plurality of first potential lines;

[0008] a plurality of second potential lines;

[0009] a plurality of reset signal lines;

[0010] a display area, each display area comprising a plurality of sub-display areas formed by a plurality of pixel structures; the pixel structure comprises a light emitting device and a light emitting control circuit arranged between the first potential line and the anode of the light emitting device;

[0011] the reset signal line is connected with the light emitting control circuit, and the second potential line is connected with the cathode of the light emitting device;

[0012] wherein the pixel structure of each sub-display area is connected with a different reset signal line, and the pixel structure of each sub-display area is connected with a different first potential line and / or a different second potential line.

[0013] Optionally, the light emitting control circuit comprises a storage capacitor, a first drive transistor, a control sub-circuit, a data transmission sub-circuit, a compensation sub-circuit, a reset sub-circuit and an initialization sub-circuit;

[0014] The data transmission sub-circuit is connected with the control sub-circuit and a first electrode of the first drive transistor to a first node, and is configured to transmit a data signal to the first node according to a scan signal of a current stage;

[0015] The control sub-circuit is connected with the first potential line and the light emitting device, and is configured to control on-off between the first potential line and the light emitting device according to a light emitting control signal;

[0016] The initialization sub-circuit is connected with a control electrode of the first drive transistor to a second node, and is configured to initialize a potential of the second node;

[0017] A storage capacitor is connected with the first potential line and the second node;

[0018] The compensation sub-circuit is connected with the first drive transistor, and is configured to compensate a turn-on threshold voltage of the first drive transistor;

[0019] The reset sub-circuit is connected with the light emitting device and the reset signal line, and is configured to reset the light emitting device according to a signal transmitted by the reset signal line.

[0020] Optionally, the data transmission sub-circuit comprises a second transistor, the compensation sub-circuit comprises a third transistor, the initialization sub-circuit comprises a fourth transistor, the control sub-circuit comprises a fifth transistor and a sixth transistor, and the reset sub-circuit comprises a seventh transistor;

[0021] A control electrode of the second transistor is connected with a scan signal of a current stage, a first electrode is connected with a data signal, and a second electrode is connected with the first node;

[0022] A control electrode of the third transistor is connected with the scan signal of the current stage, a first electrode is connected with the second node, and a second electrode is connected with a second electrode of the first drive transistor;

[0023] A control electrode of the fourth transistor is connected with a scan signal of a previous stage, a first electrode is connected with the second node, and a second electrode is connected with the reset signal line;

[0024] A control electrode of the fifth transistor is connected with a light emitting control signal, a first electrode is connected with the first potential line, and a second electrode is connected with the first node;

[0025] A control electrode of the sixth transistor is connected with the light emitting control signal, a first electrode is connected with the second electrode of the first drive transistor, and a second electrode is connected with an anode of the light emitting device;

[0026] The control electrode of the seventh transistor is connected to the scan signal of the current stage, the first electrode is connected to the reset signal line, and the second electrode is connected to the anode of the light emitting device.

[0027] Optionally, when the size of the display panel is a first size, the display area is divided into 1*P sub-display areas according to the rows and columns of the pixel structure;

[0028] When the size of the display panel is a second size, the display area is divided into N*M sub-display areas according to the rows and columns of the pixel structure; the second size is greater than the first size, and P, N and M are positive integers.

[0029] Optionally, the display panel further comprises a plurality of first power supply circuits, each of which is connected to the first potential line, the second potential line and the reset signal line of a corresponding sub-display area, and is configured to:

[0030] When the brightness or refresh rate of the sub-display area is increased, the potential of the signal transmitted by the first potential line connected to each pixel circuit in the sub-display area is increased, and the potential of the signal transmitted by the second potential line and the reset signal line is decreased;

[0031] Or, when the brightness or refresh rate of the sub-display area is decreased, the potential of the signal transmitted by the second potential line and the reset signal line connected to each pixel circuit in the sub-display area is increased, and the potential of the signal transmitted by the first potential line is decreased.

[0032] Optionally, the display panel further comprises a plurality of second power supply circuits, each of which is connected to the second potential line and the reset signal line of a corresponding sub-display area, and is configured to:

[0033] When the brightness or refresh rate of the sub-display area is increased, the potential of the signal transmitted by the second potential line and the reset signal line connected to each pixel structure in the sub-display area is decreased;

[0034] When the brightness or refresh rate of the sub-display area is decreased, the potential of the signal transmitted by the second potential line and the reset signal line connected to each pixel structure in the sub-display area is increased.

[0035] Optionally, the display panel further comprises a third power supply circuit connected to the first potential line of each sub-display area.

[0036] Optionally, the display panel further comprises a plurality of fourth power supply circuits, each of which is connected to the first potential line and the reset signal line of a corresponding sub-display area, and is configured to:

[0037] when the brightness of the sub-display area is increased or the refresh rate is increased, the potential of the signal transmitted by the first potential line connected with the pixel structure in the sub-display area is increased, and the potential of the signal transmitted by the reset signal line is decreased; or

[0038] when the brightness of the sub-display area is decreased or the refresh rate is decreased, the potential of the signal transmitted by the first potential line connected with the pixel structure in the sub-display area is decreased, and the potential of the signal transmitted by the reset signal line is increased.

[0039] Optionally, the display panel further comprises a fifth power supply circuit connected with the second potential line of each sub-display area.

[0040] According to a second aspect of the present application, a display device is provided, comprising the display panel as described above.

[0041] In the display panel of the embodiments of the present application, by assigning the pixel structure of each sub-display area with independent reset signal line, first potential line and / or second potential line, the driving current of the light emitting device in each sub-display area can be adjusted individually, so as to offset the error of the driving current caused by the IR drop on the transmission line (including the first potential line, the second potential line and the reset signal line), and further to help improve the uniformity of the brightness of the display panel.

[0042] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0044] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0045] Figure 1 is a schematic diagram of a display device provided in an exemplary embodiment of the present disclosure;

[0046] Figure 2 is a schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0047] Figure 3 is a schematic diagram of a pixel structure provided in an exemplary embodiment of the present disclosure;

[0048] Figure 4This is a schematic diagram of the circuit connection of the pixel structure provided in an exemplary embodiment of this disclosure;

[0049] Figure 5 This is a timing control waveform diagram of the pixel structure provided in an exemplary embodiment of this disclosure;

[0050] Figure 6 This is a schematic diagram of a sub-display area division method provided in an exemplary embodiment of this disclosure;

[0051] Figure 7 This is a schematic diagram of another sub-display area division method provided in an exemplary embodiment of this disclosure;

[0052] Figure 8 This is a schematic diagram of a first power supply circuit provided in an exemplary embodiment of this disclosure;

[0053] Figure 9 This is a schematic diagram of a second power supply circuit and a third power supply circuit provided in an exemplary embodiment of this disclosure;

[0054] Figure 10 This is a schematic diagram of another second power supply circuit and a third power supply circuit provided in an exemplary embodiment of this disclosure;

[0055] Figure 11 This is a schematic diagram of the sub-display area and gate driving circuit provided in an exemplary embodiment of this disclosure.

[0056] Explanation of reference numerals in the attached diagram: 100, first power supply circuit; 200, second power supply circuit; 300, third power supply circuit; 400, fourth power supply circuit; 500, fifth power supply circuit. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0058] First, such as Figure 1 The diagram shown is a schematic representation of a display device provided in an embodiment of this application. The display device provided in this application includes a plurality of pixel structures 10 arranged in an array.

[0059] As an example, a plurality of pixel structures 10 are arranged to form a display area AA. As a further embodiment of the display device, the display device further comprises a gate driver 20, a data driver 30 and a power supply circuit 40 connected to the pixel structures 10 respectively. The gate driver 20, the data driver 30 and the power supply circuit 40 are configured to send a scan signal, a data signal and a light emitting control signal to the pixel structures 10 respectively, so as to drive the pixel structures 10 to emit light.

[0060] The gate driver 20 is connected to the pixel structures 10 through scan lines Gn respectively, and is configured to send a scan signal to the pixel structures 10 through the scan lines Gn. The data driver 30 is connected to the pixel structures 10 through data lines Data respectively, and is configured to send a data signal to the pixel structures 10 through the data lines Data. The power supply circuit 40 provides a driving voltage required for light emission to each pixel unit, so as to drive the light emitting device in each pixel unit to emit light, and realize the light emission display function of each pixel unit.

[0061] In the process of driving the pixel structures 10 to emit light by the gate driver 20, the data driver 30 and the power supply circuit 40 together, the gate driver 20 can first send a scan signal to the pixel structures 10 in the first row through the scan lines Gn, so as to select the pixel structures 10 in the first row. The data driver 30 sends a data voltage to the pixel structures 10 in the first row through the data signal lines Data. Then, the gate driver 20 continues to select the pixel structures 10 in the next row, and the data driver 30 sends a corresponding data signal to the pixel structures 10 in the next row. In this way, all the rows are selected and receive the data voltage. Under the control of the light emitting control signal, the power supply circuit 40 outputs a voltage signal required by the light emitting device to each pixel unit, so as to control the light emitting device in the pixel structure 10 to emit light, and complete the display of one frame of picture. By repeating the above process, the display device can display continuous pictures.

[0062] According to a first aspect of the present application, with reference to Figures 1 to 4 The display panel comprises a plurality of first potential lines VDD, a plurality of second potential lines VSS, a plurality of reset signal lines VI and a display area. Each display area comprises a plurality of sub-display areas formed by a plurality of pixel structures. The pixel structure comprises a light emitting device and a light emitting control circuit arranged between the first potential line VDD and the anode of the light emitting device. The reset signal line VI is connected to the light emitting control circuit, and the second potential line VSS is connected to the cathode of the light emitting device. The pixel structures of each sub-display area are connected to different reset signal lines VI, and the pixel structures of each sub-display area are connected to different first potential lines VDD and / or different second potential lines VSS.

[0063] The first potential line VDD is a power supply line or a positive power supply line, and is used to provide a driving voltage to the light emitting device in the pixel structure. The second potential line VSS is a reference line, and is used to provide a reference voltage to the light emitting device. The driving voltage is greater than the reference voltage, so that a potential difference is formed between the reference voltage and the driving voltage, thereby causing a current to flow from the first potential line VDD to the second potential line VSS through the light emitting device. By adjusting the voltage difference between the first potential line VDD and the second potential line VSS, the size of the driving current flowing through the light emitting device can be adjusted. The reset signal line VI is used to provide a reset potential of the light emitting device, and to reset the charge accumulated at the anode of the light emitting device. If the reset is not complete, the data signal that is written may not be accurately transmitted to the light emitting device, which affects the brightness and display effect of the light emitting device.

[0064] In the above embodiment, by assigning the pixel structure of each sub-display area with an independent reset signal line VI, first potential line VDD and / or second potential line VSS, the driving current of the light emitting device in each sub-display area can be adjusted individually, thereby helping to offset the error of the driving current caused by the voltage drop (IR drop) on the transmission line (including the first potential line VDD, the second potential line VSS and the reset signal line VI), and further helping to improve the uniformity of the brightness of the display panel.

[0065] Reference Figure 3 In some embodiments, the light emitting control circuit includes a storage capacitor Cst, a first driving transistor T1, a control sub-circuit, a data transmission sub-circuit, a compensation sub-circuit, a reset sub-circuit and an initialization sub-circuit. The data transmission sub-circuit is connected to the first node Q1 with the first electrode of the control sub-circuit and the first driving transistor T1, and is used to transmit a data signal to the first node Q1 according to a scan signal Scan(n) of the current stage. The control sub-circuit is connected to the first potential line VDD and the light emitting device, and is used to control the on-off of the first potential line VDD and the light emitting device according to a light emitting control signal EM. The initialization sub-circuit is connected to the second node Q2 with the control electrode of the first driving transistor T1, and is used to initialize the potential of the second node Q2. The storage capacitor Cst is connected to the first potential line VDD and the second node Q2. The compensation sub-circuit is connected to the first driving transistor T1, and is used to compensate the on-threshold voltage of the first driving transistor T1. The reset sub-circuit is connected to the light emitting device and the reset signal line VI, and is used to reset the light emitting device according to the signal transmitted by the reset signal line VI.

[0066] Reference Figure 4In some embodiments, the data transmission sub-circuit includes a second transistor T2, the compensation sub-circuit includes a third transistor T3, the initialization sub-circuit includes a fourth transistor T4, the control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, and the reset sub-circuit includes a seventh transistor T7. The control electrode of the second transistor T2 is connected to the current scanning signal Scan(n), the first electrode is connected to the data signal line, and the second electrode is connected to the first node Q1. The control electrode of the third transistor T3 is connected to the current scanning signal Scan(n), the first electrode is connected to the second node Q2, and the second electrode is connected to the second electrode of the first driving transistor T1. The control electrode of the fourth transistor T4 is connected to the previous scanning signal Scan(n-1), the first electrode is connected to the second node Q2, and the second electrode is connected to the reset signal line VI. The control electrode of the fifth transistor T5 is connected to the emission control signal EM, the first electrode is connected to the first potential line VDD, and the second electrode is connected to the first node Q1. The control electrode of the sixth transistor T6 is connected to the emission control signal EM, the first electrode is connected to the second electrode of the first driving transistor T1, and the second electrode is connected to the anode of the light emitting device. The control electrode of the seventh transistor T7 is connected to the current scanning signal Scan(n), the first electrode is connected to the reset signal line VI, and the second electrode is connected to the anode of the light emitting device.

[0067] As an example, the current scanning signal Scan(n), the previous scanning signal Scan(n-1), and the emission control signal EM can be output by the gate driver 20, which includes a plurality of gate drive circuits cascaded, each of which outputs the current scanning signal Scan(n) and the emission control signal EM to the pixel structure of the corresponding row, and outputs the previous scanning signal Scan(n-1) to the pixel structure of the next row.

[0068] As an example, in the state where the first driving transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, the source-drain voltage Vds between the first electrode and the second electrode of the first driving transistor T1 is substantially equal to the potential difference between the first potential line VDD and the second potential line VSS, and therefore, by adjusting the potential difference between the first potential line VDD and the second potential line VSS, it is helpful to make the first driving transistor T1 quickly enter the saturated on state.

[0069] In combination Figure 5 In combination with the control timing of the pixel structure, the light emitting principle of the pixel structure is described. Taking one frame period as an example, one frame period can include an initialization stage t1, a compensation stage t2, and a light emitting stage t3.

[0070] In the initialization stage t1, the previous-stage scan signal Scan(n-1) is high, the control electrode of the fourth transistor T4 is turned on according to the previous-stage scan signal Scan(n-1), the voltage difference across the storage capacitor Cst is increased, and the storage capacitor Cst starts to charge. At the same time, the reset signal transmitted by the reset signal line VI is transmitted to the control electrode of the first drive transistor T1 through the fourth transistor T4, so as to initialize the control electrode potential of the first drive transistor T1.

[0071] In the compensation stage t2, the current-stage scan signal Scan(n) is high, the third transistor T3 and the seventh transistor T7 are turned on according to the current-stage scan signal Scan(n), and the first drive transistor T1 is turned on. The data signal is transmitted back to the control electrode of the first drive transistor T1 in sequence through the second transistor T2, the first drive transistor T1 and the third transistor T3, the storage capacitor Cst gradually lifts the control electrode potential of the first drive transistor T1 to the sum of the data signal and the turn-on threshold voltage of the first drive transistor T1, so as to realize compensation of the turn-on threshold voltage Vth of the first drive transistor T1. At the same time, the reset signal VI is transmitted to the anode of the light-emitting device through the seventh transistor T7, so as to reset the anode voltage of the light-emitting device.

[0072] In the light-emitting stage t3, the light-emitting control signal EM is high, the fifth transistor T5 and the sixth transistor T6 are turned on according to the light-emitting control signal EM, and the first drive transistor T1 generates a drive current to make the light-emitting device emit light according to the drive current.

[0073] As an example, the power supply circuit 40 can increase the voltage difference between the first potential line VDD and the second potential line VSS, so as to increase the voltage difference between the first electrode and the second electrode of the first drive transistor T1, so that the first drive transistor T1 is more likely to enter a saturated conduction state, so as to quickly transmit the data signal of the first electrode of the first drive transistor T1 to the light-emitting device.

[0074] As an example, the reset signal output by the reset signal line VI can be adjusted to reset the residual charges at the second electrode of the sixth transistor T6 and the anode of the light-emitting device, so as to keep the anode of the light-emitting device at a lower potential, so that after the first drive transistor T1 is turned on, the data signal written to the first node Q1 can be quickly transmitted to the anode of the light-emitting device, and the first drive transistor T1 cannot generate a correct drive current due to the high anode potential of the light-emitting device.

[0075] Referring to Figure 6 In some embodiments, when the size of the display panel is a first size, the display area is divided into 1*P sub-display areas according to the rows and columns of the pixel structure.

[0076] As an example, when the width of the display panel is narrow, for example, the display panel is applied to a mobile phone, the display area can be divided into 1*P sub-display areas. In combination with Figure 2 Taking P=3 as an example, the first potential line VDD is the first power sub-line VDD1, the second power sub-line VDD2 and the third power sub-line VDD3 respectively; the second potential line VSS is the first reference sub-line VSS1, the second reference sub-line VSS2 and the third reference sub-line VSS3 respectively; and the reset signal line VI is the first reset sub-line VI1, the second reset sub-line VI2 and the third reset sub-line VI3 respectively. Among them, the first sub-display area is connected with the first power sub-line VDD1, the first reference sub-line VSS1 and the first reset sub-line VI1, the second sub-display area is connected with the second power sub-line VDD2, the second reference sub-line VSS2 and the second reset sub-line VI2, and the third sub-display area is connected with the third power sub-line VDD3, the third reference sub-line VSS3 and the third reset sub-line VI3.

[0077] Referring to Figure 7 In some embodiments, when the size of the display panel is a second size, the display area is divided into N*M sub-display areas according to the rows and columns of the pixel structure. The second size is larger than the first size, and P, N and M are positive integers.

[0078] As an example, when the display panel is of the second size, for example, the display panel is applied to a television or a display screen, the display area can be divided into N*M sub-display areas, including the sub-display area 11 to the sub-display area NM arranged in a matrix, each of which corresponds to an independent first potential line VDD, a second potential line VSS and a reset signal line VI. For example, the first potential line VDD includes a plurality of power sub-lines same as the number of sub-display areas, the second potential line VSS includes a plurality of reference sub-lines same as the number of sub-display areas, and the reset signal line VI includes a plurality of reset sub-lines same as the number of sub-display areas. The sub-display area 11 is connected with the power sub-line VDD11, the reference sub-line VSS11 and the reset sub-line VI11, the sub-display area 12 is connected with the power sub-line VDD12, the reference sub-line VSS12 and the reset sub-line VI12, the sub-display area 1M is connected with the power sub-line VDD1M, the reference sub-line VSS1M and the reset sub-line VI1M, and so on. Thus, each sub-display area is connected with an independent first potential line VDD, a second potential line VSS and a reset signal line VI.

[0079] It should be noted that the higher the luminance of the light emitting device, the greater the driving current flowing through the light emitting device needs to be, and the greater the potential difference between the first potential line VDD and the second potential line VSS needs to be, so that the first driving transistor T1 is saturated and turned on. When the refresh rate of the display panel is higher, data writing and reset operations need to be performed faster in order to improve the response speed of the pixel structure. Therefore, the potentials of the first potential line VDD, the second potential line VSS and the reset signal line VI can be adjusted according to different luminance requirements and refresh rate requirements of the display panel, which will be described in detail below.

[0080] Referring to Figure 8 In the first embodiment, the power supply circuit 40 includes a plurality of first power supply circuits, each of which is connected to the first potential line VDD, the second potential line VSS and the reset signal line VI of a corresponding sub-display area, for:

[0081] When the luminance or refresh rate of the sub-display area is increased, the potential of the signal transmitted by the first potential line VDD connected to each pixel circuit in the sub-display area is increased, and the potentials of the signals transmitted by the second potential line VSS and the reset signal line VI are decreased; or when the luminance or refresh rate of the sub-display area is decreased, the potentials of the signals transmitted by the second potential line VSS and the reset signal line VI connected to each pixel circuit in the sub-display area are increased, and the potential of the signal transmitted by the first potential line VDD is decreased.

[0082] As an example, the first potential line VDD, the second potential line VSS and the reset signal line VI of the same sub-display area are connected by the same first power supply circuit 100, which facilitates the first power supply circuit 100 to independently control the signals transmitted on the first potential line VDD, the second potential line VSS and the reset signal line VI of the sub-display area.

[0083] In the above embodiment, when the luminance or refresh rate of the sub-display area is increased, the potential of the signal transmitted by the first potential line VDD connected to each pixel circuit in the sub-display area is increased, and the potential of the second potential line VSS is decreased, which can increase the potential difference between the first potential line VDD and the second potential line VSS, thereby helping the first driving transistor T1 to enter a saturated and turned-on state. Decreasing the potential of the signal transmitted by the reset signal line VI can make the anode electrode of the light emitting device reset more fully, so as to increase the speed of writing data signals. Conversely, when the luminance or refresh rate of the sub-display area is decreased, the potentials of the signals transmitted by the second potential line VSS and the reset signal line VI connected to each pixel circuit in the sub-display area are increased, and the potential of the signal transmitted by the first potential line VDD is decreased, so as to reduce the voltage difference between the first potential line VDD and the second potential line VSS, thereby reducing power consumption while meeting the luminance and refresh rate requirements of the display area.

[0084] Referring to Figure 9 In the second embodiment, the power supply circuit 40 comprises a plurality of second power supply circuits 200, each of which is connected with the second potential line VSS and the reset signal line VI of a corresponding sub-display area, for: when the brightness or refresh rate of the sub-display area is increased, reducing the potential of the signals transmitted by the second potential line VSS and the reset signal line VI connected with each pixel structure in the sub-display area; when the brightness or refresh rate of the sub-display area is decreased, increasing the potential of the signals transmitted by the second potential line VSS and the reset signal line VI connected with each pixel structure in the sub-display area.

[0085] As an example, the power supply circuit 40 comprises a third power supply circuit 300 connected with the first potential line VDD of each sub-display area respectively.

[0086] As an example, different from the first embodiment, in this embodiment, when adjusting the brightness or refresh rate of the display area, only the potential transmitted by the first potential line VDD can be adjusted, while the potential transmitted by the second potential line VSS is maintained, and the adjustment of the potential difference between the first potential line VDD and the second potential line VSS can also be realized. Compared with the first embodiment, only the potential output by the first potential line VDD is adjusted, and the logic of adjusting the potential is simpler, but the adjustment range of the potential difference between the first potential line VDD and the second potential line VSS is relatively smaller than that of the first embodiment.

[0087] Referring to Figure 10 In the third embodiment, the power supply circuit 40 further comprises a plurality of fourth power supply circuits 400, each of which is connected with the first potential line VDD and the reset signal line VI of a corresponding sub-display area, for: when the brightness or refresh rate of the sub-display area is increased, increasing the potential of the signals transmitted by the first potential line VDD connected with each pixel structure in the sub-display area, and reducing the potential of the signals transmitted by the reset signal line VI; or, when the brightness or refresh rate of the sub-display area is decreased, reducing the potential of the signals transmitted by the first potential line VDD connected with each pixel structure in the sub-display area, and increasing the potential of the signals transmitted by the reset signal line VI.

[0088] As an example, the power supply circuit 40 further comprises a fifth power supply circuit 500 connected with the second potential line VSS of each sub-display area respectively.

[0089] As an example, different from the first embodiment, in this embodiment, when adjusting the brightness or refresh rate of the display area, only the potential transmitted by the second potential line VSS can be adjusted, while the potential transmitted by the first potential line VDD is maintained, and the adjustment of the potential difference between the first potential line VDD and the second potential line VSS can also be realized.

[0090] As an example, when only the potential of the signal outputted by one of the first potential line VDD and the second potential line VSS is adjusted, the other one of the first potential line VDD and the second potential line VSS does not need to be adjusted, and the first potential line VDD or the second potential line VSS in the display area that does not need to be adjusted can be provided by the same second power supply circuit 200. For example, in combination with Figure 9 When only the reference voltage transmitted by the second potential line VSS is adjusted, the third power supply circuit 300 provides the same driving voltage to each display area through the first potential line VDD. The number of the second power supply circuit 200 can be the same as the number of the sub-display areas, so that each second power supply circuit 200 provides the reference voltage transmitted by the second potential line VSS and the reset signal transmitted by the reset signal line VI to the corresponding sub-display area. For example, in combination with Figure 10 When only the driving voltage transmitted by the first potential line VDD is adjusted, the fifth power supply circuit 500 provides the same reference voltage to each display area through the second potential line VSS. The number of the fourth power supply circuit 400 can be the same as the number of the sub-display areas, so that each fourth power supply circuit 400 provides the driving voltage transmitted by the first potential line VDD and the reset signal transmitted by the reset signal line VI to the corresponding sub-display area.

[0091] Referring to Figure 11 In some embodiments, in order to realize the partition frequency driving of the display area, a plurality of independent gate driving circuits can be provided. For example, for the sub-display area 1 and the sub-display area N at the edge of the display area, the refresh rate requirement is small, and the refresh rate of the sub-display area 1 and the sub-display area N can be reduced by the gate driving circuit 1 and the gate driving circuit N respectively. For the sub-display area 21 to the sub-display area (N-1)M located in the middle part of the display area, a higher refresh rate is required, so the middle part of the display area can be divided into (N-2)*M sub-display areas according to rows and columns, and the edge part of the display area can be respectively regarded as the sub-display area 1 and the sub-display area N.

[0092] Each sub-display area can correspond to an independent first power supply circuit 100. For the sub-display area 1 and the sub-display area N with lower refresh rate requirement, only two first power supply circuits 100 are needed, which reduces the number of first power supply circuits 100 and helps to reduce the cost.

[0093] According to a second aspect of the present disclosure, a display device is provided, which includes the display panel described above. The display device has all the advantages of the display panel described above, and the present disclosure will not be repeated here.

[0094] In the description of the present application, the terms "first", "second", are only used for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0095] The embodiments, implementation manners and related technical features of the present application can be combined, replaced with each other without conflict.

[0096] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the description of each embodiment in the embodiment of the present application has its own emphasis, the part not described in detail in a certain embodiment can be referred to the related embodiments of other embodiments. Any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments, without departing from the technical solution content of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of first potential lines; a plurality of second potential lines; a plurality of reset signal lines; a plurality of display areas, each display area comprising a plurality of sub-display areas formed by a plurality of pixel structures; each pixel structure comprises a light emitting device and a light emitting control circuit disposed between the first potential line and the anode of the light emitting device; the reset signal line is connected to the light emitting control circuit, and the second potential line is connected to the cathode of the light emitting device; each pixel structure of each sub-display area is connected to a different reset signal line, and each pixel structure of each sub-display area is connected to a different first potential line and / or a different second potential line; the display panel further comprises a plurality of second power supply circuits, each second power supply circuit being connected to the second potential line and the reset signal line of a corresponding sub-display area, and being configured to: when the brightness of the sub-display area is increased or the refresh rate of the sub-display area is increased, reduce the potential of the signals transmitted by the second potential line and the reset signal line connected to each pixel structure in the sub-display area; and when the brightness of the sub-display area is decreased or the refresh rate of the sub-display area is decreased, increase the potential of the signals transmitted by the second potential line and the reset signal line connected to each pixel structure in the sub-display area; the display panel further comprises a third power supply circuit connected to the first potential line of each sub-display area.

2. The display panel of claim 1, wherein, The light emitting control circuit comprises a storage capacitor, a first drive transistor, a control sub-circuit, a data transmission sub-circuit, a compensation sub-circuit, a reset sub-circuit, and an initialization sub-circuit; the data transmission sub-circuit is connected to the first node at the first electrode of the control sub-circuit and the first drive transistor, and is configured to transmit a data signal to the first node according to a current stage scan signal; the control sub-circuit is connected to the first potential line and the light emitting device, and is configured to control the on-off state between the first potential line and the light emitting device according to a light emitting control signal; the initialization sub-circuit is connected to the second node at the control electrode of the first drive transistor, and is configured to initialize the potential of the second node; the storage capacitor is connected to the first potential line and the second node; the compensation sub-circuit is connected to the first drive transistor, and is configured to compensate the on-threshold voltage of the first drive transistor; the reset sub-circuit is connected to the light emitting device and the reset signal line, and is configured to reset the light emitting device according to the signal transmitted by the reset signal line.

3. The display panel of claim 2, wherein, The data transmission sub-circuit comprises a second transistor, the compensation sub-circuit comprises a third transistor, the initialization sub-circuit comprises a fourth transistor, the control sub-circuit comprises a fifth transistor and a sixth transistor, and the reset sub-circuit comprises a seventh transistor; the control electrode of the second transistor is connected to a current stage scan signal, the first electrode is connected to a data signal, and the second electrode is connected to the first node; the control electrode of the third transistor is connected to the current stage scan signal, the first electrode is connected to the second node, and the second electrode is connected to the second electrode of the first drive transistor; the control electrode of the fourth transistor is connected to a previous stage scan signal, the first electrode is connected to the second node, and the second electrode is connected to the reset signal line; The control electrode of the fifth transistor is connected to the light-emitting control signal, the first electrode is connected to the first potential line, and the second electrode is connected to the first node; The control electrode of the sixth transistor is connected to the light-emitting control signal, the first electrode is connected to the second electrode of the first driving transistor, and the second electrode is connected to the anode of the light-emitting device; The control electrode of the seventh transistor is connected to the current stage scan signal, the first electrode is connected to the reset signal line, and the second electrode is connected to the anode of the light-emitting device.

4. The display panel of claim 1, wherein, When the size of the display panel is a first size, the display area is divided into 1*P sub-display areas according to the rows and columns of the pixel structure; When the size of the display panel is a second size, the display area is divided into N*M sub-display areas according to the rows and columns of the pixel structure; The second size is greater than the first size, and P, N, and M are positive integers.

5. A display panel, characterized in that, a plurality of first potential lines; a plurality of second potential lines; a plurality of reset signal lines; a display area, each display area including a plurality of sub-display areas formed by a plurality of pixel structures; the pixel structure including a light-emitting device and a light-emitting control circuit disposed between the first potential line and the anode of the light-emitting device; the reset signal line is connected to the light-emitting control circuit, and the second potential line is connected to the cathode of the light-emitting device; wherein the pixel structure of each sub-display area is connected to a different reset signal line, and the pixel structure of each sub-display area is connected to a different first potential line and / or a different second potential line; The display panel further comprises a plurality of fourth power supply circuits, each of which is connected to the first potential line and the reset signal line of the corresponding sub-display area, for: when the brightness or refresh rate of the sub-display area is increased, the potential of the signal transmitted by the first potential line connected to each pixel structure in the sub-display area is increased, and the potential of the signal transmitted by the reset signal line is decreased; or, when the brightness or refresh rate of the sub-display area is decreased, the potential of the signal transmitted by the first potential line connected to each pixel structure in the sub-display area is decreased, and the potential of the signal transmitted by the reset signal line is increased; The display panel further comprises a fifth power supply circuit connected to the second potential line of each sub-display area.

6. A display device, characterized by comprising: The display panel of any one of claims 1 to 5. The display panel of any one of claims 1 to 5.

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