Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The problem that in the prior art, the production cost of products is high is solved. The array substrate is provided with a pixel circuit area and a fan-out area located on one side of the pixel circuit area, and the array substrate comprises a substrate body, a first electrode, a second electrode and a third electrode, the plurality of conductive layers are sequentially stacked on one side of the substrate; wherein the plurality of conductive layers comprise first direction signal lines, the first direction signal lines comprise first fan-out lines and first reference voltage signal lines, the first fan-out lines extend from the pixel circuit area to the fan-out area, and the first reference voltage signal lines are located in the pixel circuit area; the first fan-out line and the first reference voltage signal line are located on the same conductive layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In the display panel manufacturing industry, the fan-out in AA (FIAA) technology is increasingly being used to manufacture display panels due to its advantage of saving frame size. However, the current FIAA technology will add additional process steps, resulting in an increase in production costs. Summary of the invention

[0003] In view of this, the embodiments of the present application provide an array substrate, a display panel and a display device, which solve the problem of high production cost of FIAA products in the prior art.

[0004] In a first aspect, the present application provides an array substrate having a pixel circuit area and a fan-out area located on one side of the pixel circuit area, the array substrate comprising: a substrate substrate; and a plurality of conductive layers sequentially stacked on one side of the substrate substrate; wherein the plurality of conductive layers comprise a first direction signal line, the first direction signal line comprises a first fan-out line and a first reference voltage signal line, the first fan-out line extends from the pixel circuit area to the fan-out area, the first reference voltage signal line is located in the pixel circuit area; the first fan-out line and the first reference voltage signal line are located in the same conductive layer. According to the array substrate provided in this embodiment, by arranging the first fan-out line and the first reference voltage signal line in the same conductive layer, compared with the conventional arrangement of arranging them in different conductive layers, one conductive layer can be saved, thereby reducing costs.

[0005] In combination with the first aspect, in some possible implementations, the first direction signal line also includes a plurality of power signal lines, and the power signal line, the first fan-out line, and the first reference voltage signal line are located in the same conductive layer; the first fan-out line and the first reference voltage signal line are located between adjacent power signal lines; preferably, the first fan-out line and the first reference voltage signal line between adjacent power signal lines are axially symmetrical; preferably, the power signal line has a symmetry axis parallel to the first direction. According to the array substrate provided in this embodiment, by setting the first fan-out line and the first reference voltage signal line between adjacent power signal lines to be axially symmetrical, it is beneficial to the uniformity of the signal line distribution within the projection range of different subsequent sub-pixels, so that the overlapping area and overlapping position of different conductive layers are equivalent, which is beneficial to improving the uniformity of the brightness of the screen.

[0006] In combination with the first aspect, in some possible implementations, the first direction signal line further includes a plurality of data lines, and the data lines, the first fan-out lines, and the first reference voltage signal lines are located in the same conductive layer; two data lines are arranged between adjacent power signal lines; preferably, the two data lines between adjacent power signal lines are axially symmetrical. According to the array substrate provided in this embodiment, by arranging the two data lines between adjacent power signal lines to be axially symmetrical, it is beneficial to the uniformity of the distribution of signal lines within the projection range of different sub-pixels, so that the overlapping areas and overlapping positions of different conductive layers are comparable, which is beneficial to improving the uniformity of the brightness of the screen.

[0007] In combination with the first aspect, in some possible implementations, between adjacent power signal lines, a data line, a first fan-out line, a first reference voltage signal line, and another data line are arranged in sequence; or between adjacent power signal lines, a first fan-out line, a data line, another data line, and a first reference voltage signal line are arranged in sequence. The array substrate provided according to this embodiment is compatible with conventional power signal line layouts, that is, the conventional power signal line layout does not need to be changed, or only the line spacing between adjacent power signal lines needs to be adjusted, and the changes are minor, thereby reducing the difficulty of implementation.

[0008] In combination with the first aspect, in some possible implementations, the first direction signal line also includes a data line; the plurality of conductive layers also include a second direction signal line, and the second direction signal line and the first direction signal line have orthographic projections that intersect on the substrate; the second direction signal line includes a second fan-out line located in the display area, and the data line, the second fan-out line and the first fan-out line are electrically connected in sequence; preferably, the first direction signal line also includes a first sub-power line, and the second direction signal line also includes a second sub-power line; the first sub-power line and the first fan-out line are located in the same conductive layer, the second sub-power line and the second fan-out line are located in the same conductive layer, and the first sub-power line and the second sub-power line are electrically connected in a mesh; preferably, the voltage connected to the power signal line is higher than the first sub-power line and the second sub-power line. According to the array substrate provided in this embodiment, it is compatible with the conventional power signal line layout, that is, the conventional power signal line layout does not need to be changed, or only the line spacing between adjacent power signal lines needs to be adjusted, and the change is small, which reduces the difficulty of implementation.

[0009] In combination with the first aspect, in some possible implementations, the multiple conductive layers include a first conductive layer and a second conductive layer, the first conductive layer is located on the side of the second conductive layer away from the base substrate; the data line, the first fan-out line and the first reference voltage signal line are located in the first conductive layer, and the second fan-out line is located in the second conductive layer; preferably, at least one of the first conductive layer and the second conductive layer includes a first titanium layer, an aluminum layer and a second titanium layer stacked in sequence. According to the array substrate provided in this embodiment, FIAA, which conventionally requires three layers of Ti / Al / Ti, is realized by using two layers of Ti / Al / Ti, which simplifies the process difficulty and reduces the cost.

[0010] In combination with the first aspect, in some possible implementations, the plurality of conductive layers further include a third conductive layer, which is located on the side of the second conductive layer facing the base substrate; the second direction signal line further includes a second reference voltage signal line, which is located in the third conductive layer; preferably, the second reference voltage signal line and the first reference voltage signal line are electrically connected in a mesh shape; preferably, the material of the third conductive layer includes molybdenum. According to the array substrate provided in this embodiment, by setting the reference voltage signal line, including the second reference voltage signal line and the first reference voltage signal line being electrically connected in a mesh shape, the in-plane uniformity of the reference voltage signal in the reference voltage signal line can be improved.

[0011] A second aspect of the present application provides a display panel, comprising the array substrate provided by any of the above embodiments.

[0012] In combination with the second aspect, in some possible implementations, the display panel further includes a plurality of sub-pixels located on the side of the plurality of conductive layers away from the base substrate; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacently arranged in the first direction or the second direction, the orthographic projection of the first sub-pixel on the base substrate and the orthographic projection of the first direction signal line on the base substrate have a first overlapping region, the orthographic projection of the second sub-pixel on the base substrate and the orthographic projection of the first direction signal line on the base substrate have a second overlapping region, and the first overlapping region and the second overlapping region are axially symmetrical. According to the display panel provided in this embodiment, the symmetry of the two sub-pixels can be maintained as much as possible, so that the overlapping capacitance between the signal lines in different conductive layers within the projection range of adjacent sub-pixels is kept consistent to the greatest extent.

[0013] A third aspect of the present application provides a display device, comprising the display panel or array substrate provided by any of the above embodiments.

[0014] According to the array substrate, display panel and display device provided in the embodiments of the present application, by arranging the first fan-out line and the first reference voltage signal line extending along the first direction in the same conductive layer, the number of conductive layers in the display panel is saved compared to the conventional arrangement in different conductive layers, thereby simplifying the preparation process and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a wiring layout of a part of the conductive layer in the array substrate in the related art.

[0016] Figure 2 FIG. 4 is a circuit diagram of a 7T1C pixel circuit in the related art.

[0017] Figure 3 A schematic diagram of the cross-sectional structure of an array substrate provided in one embodiment of the present application.

[0018] Figure 4This is a wiring layout of a portion of the conductive layer in the array substrate provided in the first embodiment of the present application.

[0019] Figure 5 A wiring layout of a portion of the conductive layer in an array substrate provided in the second embodiment of the present application.

[0020] Figure 6 A wiring layout of a portion of the conductive layer in an array substrate provided in the third embodiment of the present application.

[0021] Figure 7 A schematic diagram of the cross-sectional structure of a display panel provided in one embodiment of the present application.

[0022] Figure 8 A schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] As mentioned in the background art, the production cost of the fan-out in AA (FIAA) display panel in the related art is relatively high.

[0024] Figure 1 It is a wiring layout of a part of the conductive layer in the display panel in the related art. Figure 1 The wiring layout of three Ti / Al / Ti layers is shown. In the process of realizing the present invention, the inventor found through long-term research that the reference voltage signal line Vref is arranged vertically in the first Ti / Al / Ti layer. The second fan-out line Fx is arranged horizontally in the second Ti / Al / Ti layer. The first fan-out line Fy, the data line Data, and the power signal line Elvdd are arranged vertically in the third Ti / Al / Ti layer. The number of conductive layers in the display panel is large, resulting in high production costs.

[0025] In order to reduce the production cost of the display panel, the present application provides an array substrate, a display panel and a display device. By arranging the vertically arranged reference voltage signal line Vref and the first fan-out line Fy on the same conductive layer, one conductive layer can be saved compared to arranging them on different conductive layers, thereby reducing the production cost.

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is understood that when a structure is referred to as being "on or under" another structure, the structure may be directly on or under the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. The structures mentioned herein include any of a film layer, an element, a device, a component, and an assembly.

[0028] When a structure is referred to as being “connected” to another structure, the structure may be directly connected to the other structure or indirectly connected to the other structure with one or more intervening structures interposed therebetween.

[0029] The display panel generally includes a pixel circuit and sub-pixels that are electrically connected. The pixel circuit drives the sub-pixels to emit light at a predetermined brightness to achieve a display function. Figure 2 FIG. 1 is a circuit diagram of a 7T1C pixel circuit in the related art. Figure 2 As shown, the pixel circuit includes a plurality of transistors and at least one capacitor C, for example, seven transistors and one capacitor C, and the seven transistors and one capacitor C are connected to form a pixel circuit 10 according to a predetermined connection relationship to drive a sub-pixel, such as an organic light-emitting diode (OLED) to emit light according to a predetermined gray scale. It should be understood that the OLED can also be replaced by a quantum dot light emitting diode (QLED). The pixel circuit may include part or all of the first transistor T1 to the seventh transistor T7.

[0030] Specifically, if Figure 2As shown, the control end (e.g., gate) of the second transistor T2 is connected to the third scan signal line Scan3, the first electrode of the second transistor T2 is connected to the reference voltage signal line Vref, and the second electrode of the second transistor T2 is connected to the first electrode (e.g., anode) of the light-emitting device (e.g., OLED). The control end of the first transistor T1 is connected to the first scan signal line Scan1, the first electrode of the first transistor T1 is connected to the reference voltage signal line Vref, and the second electrode of the first transistor T1 is connected to the control end of the seventh transistor T7. The control end of the third transistor T3 is connected to the second scan signal line Scan2, the first electrode of the third transistor T3 is connected to the data line Data, and the second electrode of the third transistor T3 is connected to the first electrode of the seventh transistor T7. The control end of the fifth transistor T5 is connected to the light-emitting control signal line Em, the first electrode of the fifth transistor T5 is connected to the power signal line Elvdd, and the second electrode of the fifth transistor T5 is connected to the first electrode of the seventh transistor T7. The control end of the fourth transistor T4 is connected to the second scan signal line Scan2, the first electrode of the fourth transistor T4 is connected to the second electrode of the seventh transistor T7, and the second electrode of the fourth transistor T4 is connected to the control end of the seventh transistor T7. The control end of the sixth transistor T6 is connected to the light emitting control signal line Em, the first electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, and the second electrode of the sixth transistor T6 is connected to the first electrode (e.g., anode) of the light emitting device. The control end of the seventh transistor T7 is connected to the first electrode of the storage capacitor C. The second electrode of the storage capacitor C is connected to the power supply signal line Elvdd.

[0031] The seventh transistor T7 is used as a driving transistor (DTFT). The first scanning signal line Scan1 is connected to the first scanning signal, which is used to select the first transistor T1, so as to provide the reference signal in the reference voltage signal line Vref to the control end of the seventh transistor T7 and the first electrode of the capacitor C, so as to reset the control end of the seventh transistor T7 and reset the capacitor. The second scanning signal line Scan2 is connected to the second scanning signal, which is used to select the third transistor T3 and the fourth transistor T4, so as to provide the data signal in the data line Data to the first electrode of the seventh transistor T7, so as to select the data signal, and compensate the threshold voltage of the seventh transistor T7 through the fourth transistor T4. The third scanning signal line Scan3 is connected to the third scanning signal, which is used to select the second transistor T2, so as to provide the reference signal in the reference voltage signal line Vref to the first electrode of the light-emitting device (such as OLED), so as to reset the light-emitting device (such as OLED). The light-emitting control signal line Em is connected to the light-emitting control signal, which is used to select the fifth transistor T5 and the sixth transistor T6, so that the seventh transistor T7 generates a driving current and transmits it to the light-emitting device, and lights the light-emitting device.

[0032] Combine the following Figure 3 and Figure 4Description, pixel circuit, e.g. Figure 2 The pixel circuit shown is a specific structure in the array substrate provided in an embodiment of the present application.

[0033] Figure 3 A schematic diagram of the cross-sectional structure of an array substrate provided in one embodiment of the present application. Figure 4 This is a wiring layout of a portion of the conductive layer in the array substrate provided in the first embodiment of the present application. Figure 3 The cross-sectional diagram shown corresponds to Figure 4 The cross-sectional line A1A2 is shown. Figure 3 and Figure 4 As shown, the array substrate has a pixel circuit area DA and a fan-out area FA located on one side of the pixel circuit area DA. The array substrate includes: a base substrate 10 and a plurality of conductive layers Mi sequentially stacked on one side of the base substrate 10, where i is a positive integer and refers to the number of the conductive layer. For example, in this embodiment, i is 1-4 in sequence.

[0034] Wherein, the plurality of conductive layers Mi include first direction signal lines. The first direction signal lines extend along the first direction y. The first direction signal lines include a first fan-out line Fy and a first reference voltage signal line Vrefy. The first fan-out line Fy extends from the pixel circuit area DA to the fan-out area FA. The first reference voltage signal line Vrefy is located in the pixel circuit area DA. The first fan-out line Fy and the first reference voltage signal line Vrefy are located in the same conductive layer.

[0035] The first reference voltage signal line Vrefy may be Figure 2 The reference voltage signal line Vref in the pixel circuit shown may also be a part of the reference voltage signal line Vref. In the case where the first reference voltage signal line Vrefy is a part of the reference voltage signal line Vref, the reference voltage signal line Vref may be meshed, including a line extending along the first direction y and a line extending along the second direction, and the first reference voltage signal line Vrefy is the line of the reference voltage signal line Vref along the first direction y.

[0036] like Figure 4 As shown, the first direction signal line also includes a plurality of data lines Data, which are sequentially arranged along the second direction x. The pixel circuit area DA can be divided into a central area DA2 arranged along the second direction x, and a first arc angle area DA1 and a second arc angle area DA3 respectively located on both sides of the central area DA2. The first fan-out line Fy is used to fan out the data lines Data in the first arc angle area DA1 and the second arc angle area DA3, and the data lines Data in the central area DA2 can be directly extended to the fan-out area FA for fanning out.

[0037] Specifically, combined Figure 3 and Figure 4As shown, the plurality of conductive layers Mi further include a second direction signal line, and the second direction signal line extends along the second direction x. The second direction x intersects with the first direction y, and accordingly, the orthographic projection of the second direction signal line on the base substrate 10 intersects with the orthographic projection of the first direction signal line on the base substrate 10. The second direction signal line includes a second fan-out line Fx. Any data line in the first arc angle area DA1 and the second arc angle area DA3, the second fan-out line Fx, and the first fan-out line Fy are electrically connected in sequence.

[0038] In one embodiment, the first direction signal line further includes a first sub-power line Elvssy, and the second direction signal line further includes a second sub-power line Elvssx. The first sub-power line Elvssy and the first fan-out line Fy are located in the same conductive layer, and the second sub-power line Elvssx and the second fan-out line Fx are located in the same conductive layer. The first sub-power line Elvssy and the second sub-power line Elvssx are electrically connected in a mesh shape. Exemplarily, the first sub-power line Elvssy and the second sub-power line Elvssx constitute a low-voltage power signal line for connecting to the Figure 2 The cathode of the light-emitting device in the pixel circuit shown.

[0039] The multiple conductive layers Mi include a first conductive layer M1 and a second conductive layer M2, and the first conductive layer M1 is located on the side of the second conductive layer M2 away from the base substrate 10. The data line Data, the first fan-out line Fy and the first reference voltage signal line Vref1 are located in the first conductive layer M1, and the second fan-out line Fy is located in the second conductive layer M2. Exemplarily, at least one of the first conductive layer M1 and the second conductive layer M2 includes a first titanium layer, an aluminum layer and a second titanium layer stacked in sequence. In this way, the wiring resistance can be reduced. Exemplarily, among the multiple conductive layers Mi, only the first conductive layer M1 and the second conductive layer M2 respectively include a first titanium layer, an aluminum layer and a second titanium layer stacked in sequence, that is, only two conductive layers are Ti / Al / Ti structures. In this way, the FIAA that conventionally requires three layers of Ti / Al / Ti is realized by using two layers of Ti / Al / Ti, which simplifies the process difficulty and reduces the cost.

[0040] In one embodiment, the plurality of conductive layers Mi further include a third conductive layer M3, which is located on the side of the second conductive layer M2 facing the substrate 10. The second direction signal line further includes a second reference voltage signal line Vrefx, which is located in the third conductive layer M3. Exemplarily, the second reference voltage signal line Vrefx and the first reference voltage signal line Vrefy are electrically connected in a mesh, and the mesh structure can improve the uniformity of the electrical signal surface. Exemplarily, the material of the third conductive layer M3 includes molybdenum.

[0041] like Figure 3As shown, the plurality of conductive layers Mi may further include a fourth conductive layer M4, which is located between the third conductive layer M3 and the base substrate 10. The fourth conductive layer M4 includes a first capacitor plate, and the third conductive layer M3 includes a second capacitor plate, and the orthographic projection of the second capacitor plate on the base substrate 10 and the orthographic projection of the first capacitor plate on the base substrate 10 at least partially overlap. The second direction signal line also includes a scan signal line Scan (for example, including Figure 2 At least one of the first scanning signal line Scan1, the second scanning signal line Scan2, the third scanning signal line Scan3, and the light emitting control signal line Em are located in the fourth conductive layer M4.

[0042] In some embodiments, the base substrate may be a glass-based substrate.

[0043] In some embodiments, the substrate substrate may include an organic resin material such as epoxy resin, triazine, silicone resin or polyimide. For example, the substrate substrate may be a FR4 type printed circuit board (PCB), or may be a flexible PCB that is easily deformed.

[0044] In some embodiments, the substrate may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or may include a metal or a metal compound. For example, the substrate may be a metal core printed circuit board (Metal Core PCB, MCPCB) or a metal-base copper-clad laminate (Metal-base Copper-Clad Laminate, MCCL).

[0045] According to the array substrate provided in this embodiment, the first fan-out line Fy and the first reference voltage signal line Vrefy are arranged in the same conductive layer Mi. Compared with the conventional arrangement in different conductive layers, the number of conductive layers in the display panel is saved, thereby simplifying the preparation process and reducing costs.

[0046] Figure 5 This is a wiring layout of a portion of the conductive layer in the array substrate provided in the second embodiment of the present application. Figure 5 The display panel and Figure 4The difference of the array substrate shown is that, in the present embodiment, the first direction signal line also includes a plurality of power signal lines Elvdd, and the power signal line Elvdd is located in the same conductive layer as the first fan-out line Fy and the first reference voltage signal line Vrefy. The first fan-out line Fy and the first reference voltage signal line Vrefy are located between adjacent power signal lines Elvdd. The voltage connected to the power signal line Elvdd is higher than that of the first sub-power line Elvssy and the second sub-power line Elvssx. Exemplarily, the first fan-out line Fy and the first reference voltage signal line Vrefy between adjacent power signal lines Elvdd are axially symmetrical. By setting the first fan-out line and the first reference voltage signal line between adjacent power signal lines to be axially symmetrical, it is beneficial to the uniformity of the distribution of signal lines within the projection range of subsequent different sub-pixels, so that the overlapping area and overlapping position of different conductive layers are equivalent, which is beneficial to improving the uniformity of the brightness of the screen.

[0047] In one embodiment, the power signal line Elvdd has a symmetry axis parallel to the first direction y. The power signal line Elvdd can connect two adjacent sub-pixels in the second direction x. For example, one side of the symmetry axis connects one sub-pixel, and the other side of the symmetry axis connects another sub-pixel.

[0048] In this embodiment, the first direction signal line further includes a plurality of data lines Data, and the data lines Data, the first fan-out lines Fy, and the first reference voltage signal lines Vrefy are located in the same conductive layer. Two data lines Data are arranged between adjacent power signal lines Elvdd. In one embodiment, the two data lines Data between adjacent power signal lines Elvdd are axially symmetrical. By arranging the two data lines between adjacent power signal lines to be axially symmetrical, it is beneficial to the uniformity of the distribution of signal lines within the projection range of subsequent different sub-pixels, so that the overlapping areas and overlapping positions of different conductive layers are comparable, which is beneficial to improving the uniformity of the brightness of the screen.

[0049] Between adjacent power signal lines Elvdd, a data line Data, a first fan-out line Fy, a first reference voltage signal line Vrefy, and another data line Data are arranged in sequence. For example, along the second direction x, a data line Data, a first fan-out line Fy, a first reference voltage signal line Vrefy, and another data line Data are arranged in sequence. For another example, along the second direction x, a data line Data, a first reference voltage signal line Vrefy, a first fan-out line Fy, and another data line Data are arranged in sequence. That is, the positions of the first fan-out line Fy and the first reference voltage signal line Vrefy are interchangeable. In this way, it can be compatible with the conventional power signal line layout, that is, the conventional power signal line layout does not need to be changed, or only the line spacing between adjacent power signal lines needs to be adjusted, and the changes are small, reducing the difficulty of implementation.

[0050] In this embodiment, the data line Data, the first fan-out line Fy, the first reference voltage signal line Vrefy and the power signal line Elvdd are all located in the same conductive layer, for example, the first conductive layer M1.

[0051] Figure 6 This is a wiring layout of a portion of the conductive layer in the array substrate provided in the third embodiment of the present application. Figure 6 The array substrate and Figure 5 The difference of the array substrate shown is that, in the present embodiment, the first fan-out line Fy, a data line Data, another data line Data, and the first reference voltage signal line Vrefy are arranged in sequence. For example, along the second direction x, the first fan-out line Fy, a data line Data, another data line Data, and the first reference voltage signal line Vrefy are arranged in sequence. For another example, along the second direction x, the first reference voltage signal line Vrefy, a data line Data, another data line Data, and the first fan-out line Fy are arranged in sequence. That is, the positions of the first fan-out line Fy and the first reference voltage signal line Vrefy are interchangeable. In this way, it can be compatible with the conventional power signal line layout, that is, the conventional power signal line layout does not need to be changed, or only the line spacing between adjacent power signal lines needs to be adjusted, and the changes are small, which reduces the difficulty of implementation.

[0052] The embodiment of the present application also provides a display panel. Figure 7 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application. Figure 7 As shown, the display panel includes the array substrate provided by any one of the above embodiments.

[0053] In one embodiment, in combination Figure 7 and Figure 5 or Figure 6 As shown, the display panel further includes a plurality of sub-pixels 30 , which are located on the side of the plurality of conductive layers Mi away from the base substrate 10 . Figure 5 A dotted rectangular box in FIG6 represents a sub-pixel 30. The sub-pixel 30 may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot light-emitting diode (QLED), or the like.

[0054] The sub-pixel 30 may be a light-emitting device of various colors, such as a red light-emitting device R, a green light-emitting device G, a blue light-emitting device B, etc. The sub-pixel 30 includes a first electrode 31, a light-emitting layer 32, and a second electrode 33 stacked in sequence. One of the first electrode 31 and the second electrode 33 is a cathode, and the other is an anode.

[0055] The sub-pixel 30 may further include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the light-emitting layer, and at least one of an electron injection layer, an electron transport layer, and a hole blocking layer located between the cathode and the light-emitting layer. Exemplarily, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may overlap slightly, or may be isolated from each other.

[0056] In one embodiment, see Figure 5 or Figure 6 As shown, the plurality of sub-pixels 30 include a first sub-pixel 310 and a second sub-pixel 320 that are adjacently arranged. The first sub-pixel 310 and the second sub-pixel 320 may be adjacent in the second direction x. The orthographic projection of the first sub-pixel 310 on the substrate substrate 10 and the orthographic projection of the first direction signal line on the substrate substrate 10 have a first overlapping region, and the orthographic projection of the second sub-pixel 320 on the substrate substrate 10 and the orthographic projection of the first direction signal line on the substrate substrate 10 have a second overlapping region, and the first overlapping region and the second overlapping region are axially symmetrical. In this way, the symmetry of the two sub-pixels 30 can be maintained as much as possible, so that the overlapping capacitance between the signal lines in different conductive layers Mi within the projection range of adjacent sub-pixels is kept consistent to the greatest extent.

[0057] The display panel and array substrate provided in the embodiments of the present application belong to the same inventive concept. The technical details not described in the display panel embodiments can be found in the array substrate embodiments and will not be described in detail here.

[0058] The embodiment of the present application also provides a display device. Figure 8 This is a schematic diagram of the structure of a display device provided by an embodiment of the present application. Figure 8 As shown, the display device 80 includes a display panel or an array substrate provided by any embodiment of the present application.

[0059] The display device 80 is a product with an image display function. For example, the display device 80 can be used to display static images, such as pictures or photos. The display device 80 can also be used to display dynamic images, such as videos.

[0060] The display device 80 can be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0061] In addition, the display device 80 may also have functions such as taking pictures, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device 80 also includes at least one functional module for realizing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0062] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0063] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: The array substrate has a pixel circuit area and a fan-out area located on one side of the pixel circuit area, and the array substrate includes: a substrate base plate; and A plurality of conductive layers sequentially stacked on one side of the substrate; Among them, the multiple conductive layers include a first direction signal line, the first direction signal line includes a first fan-out line and a first reference voltage signal line, the first fan-out line extends from the pixel circuit area to the fan-out area, and the first reference voltage signal line is located in the pixel circuit area; the first fan-out line and the first reference voltage signal line are located in the same conductive layer.

2. The array substrate according to claim 1, characterized in that: The first direction signal line further includes a plurality of power signal lines, and the power signal lines, the first fan-out lines, and the first reference voltage signal lines are located in the same conductive layer; the first fan-out lines and the first reference voltage signal lines are located between adjacent power signal lines; Preferably, the first fan-out line and the first reference voltage signal line between adjacent power signal lines are axially symmetrical; Preferably, the power signal line has a symmetry axis parallel to the first direction.

3. The array substrate according to claim 2, characterized in that: The first direction signal line further includes a plurality of data lines, and the data lines, the first fan-out lines, and the first reference voltage signal lines are located in the same conductive layer; two data lines are arranged between adjacent power signal lines; Preferably, the two data lines between adjacent power signal lines are axially symmetrical.

4. The array substrate according to claim 3, characterized in that: Between adjacent power signal lines, one data line, the first fan-out line, the first reference voltage signal line, and another data line are arranged in sequence; or Between adjacent power signal lines, the first fan-out line, one of the data lines, another of the data lines, and the first reference voltage signal line are arranged in sequence.

5. The array substrate according to claim 1, characterized in that: The first direction signal line also includes a data line; the plurality of conductive layers also include a second direction signal line, the second direction signal line and the first direction signal line intersect with each other in positive projection on the substrate; the second direction signal line includes a second fan-out line located in the pixel circuit area, the data line, the second fan-out line and the first fan-out line are electrically connected in sequence; Preferably, the first direction signal line further includes a first sub-power line, and the second direction signal line further includes a second sub-power line; the first sub-power line and the first fan-out line are located in the same conductive layer, the second sub-power line and the second fan-out line are located in the same conductive layer, and the first sub-power line and the second sub-power line are electrically connected in a mesh shape; Preferably, the first direction signal line further includes a plurality of power signal lines, and the voltage connected to the power signal lines is higher than that of the first sub-power line and the second sub-power line.

6. The array substrate according to claim 5, characterized in that: The multiple conductive layers include a first conductive layer and a second conductive layer, the first conductive layer is located on a side of the second conductive layer away from the base substrate; the data line, the first fan-out line and the first reference voltage signal line are located in the first conductive layer, and the second fan-out line is located in the second conductive layer; Preferably, at least one of the first conductive layer and the second conductive layer includes a first titanium layer, an aluminum layer and a second titanium layer stacked in sequence.

7. The array substrate according to claim 6, characterized in that: The plurality of conductive layers further include a third conductive layer located on the side of the second conductive layer facing the substrate; the second direction signal line further includes a second reference voltage signal line located on the third conductive layer; Preferably, the second reference voltage signal line and the first reference voltage signal line are electrically connected in a mesh shape; Preferably, the material of the third conductive layer includes molybdenum.

8. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

9. The display panel according to claim 8, characterized in that: It also includes multiple sub-pixels, which are located on the side of the multiple conductive layers away from the base substrate; the multiple sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in a second direction, the orthographic projection of the first sub-pixel on the base substrate and the orthographic projection of the first direction signal line on the base substrate have a first overlapping area, the orthographic projection of the second sub-pixel on the base substrate and the orthographic projection of the first direction signal line on the base substrate have a second overlapping area, and the first overlapping area and the second overlapping area are axially symmetrical.

10. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7, or the display panel according to claim 8 or 9.

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