Display substrate, preparation method thereof and display device

Abstract

The invention provides a display substrate. The display substrate comprises a substrate body; a driving circuit layer; a passivation layer including a first via hole; the planarization layer comprises a second via hole, and the orthographic projection of the second via hole on the substrate is at least partially overlapped with the orthographic projection of the first via hole on the substrate; the first electrode layer is electrically connected with the driving circuit layer through the second via hole and the first via hole; wherein the passivation layer comprises a protruding part, the protruding part protrudes towards the side away from the substrate, the planarization layer is provided with a first side wall facing the second via hole, and at least one part of the side, close to the substrate, of the first side wall makes contact with the surface, away from the substrate, of the protruding part; the first electrode layer comprises a first electrode connecting part, one end of the first electrode connecting part is located on the side, away from the substrate, of the planarization layer, the other end of the first electrode connecting part extends into the first via hole to be electrically connected with the driving circuit layer, and the orthographic projection of the first electrode connecting part on the substrate and the orthographic projection of the protruding part on the substrate are at least partially overlapped.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Transparent display panels are a new type of display product that is as transparent as ordinary glass when closed, can display images when working, and allow users to see the objects behind the display. With its unique transparent characteristics, transparent display panels have shown broad application prospects in commercial advertising, building facades, exhibitions, smart homes and other fields. Large-size OLED transparent panels have been used in commercial displays such as subways and shopping malls because of their self-luminous, thin and flexible, and good display effects. How to ensure the manufacturing yield of transparent panels and avoid poor display is one of the topics that display product developers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising:

[0005] substrate substrate;

[0006] A driving circuit layer, located on the substrate;

[0007] A passivation layer, located on a side of the driving circuit layer away from the substrate, the passivation layer comprising a first via hole;

[0008] a planarization layer, located on a side of the passivation layer away from the base substrate, the planarization layer comprising a second via hole, an orthographic projection of the second via hole on the base substrate at least partially overlapping with an orthographic projection of the first via hole on the base substrate; and

[0009] A first electrode layer, located at a side of the planarization layer away from the base substrate, the first electrode layer being electrically connected to the driving circuit layer through the second via hole and the first via hole;

[0010] The passivation layer includes a protrusion, the protrusion protrudes toward a side away from the base substrate, the planarization layer has a first side wall facing the second via hole, and at least a portion of the first side wall close to the side of the base substrate is in contact with a surface of the protrusion away from the base substrate; and

[0011] The first electrode layer includes a first electrode connecting portion, one end of the first electrode connecting portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the first via hole and is electrically connected to the driving circuit layer, and the orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with the orthographic projection of the protruding portion on the base substrate.

[0012] According to some exemplary embodiments, the driving circuit layer includes multiple driving function layers, at least one of the driving function layers includes a raised portion, the orthographic projection of the raised portion on the base substrate at least partially overlaps with the orthographic projection of the first electrode connecting portion on the base substrate, and the raised portion is located on a side of the raised portion away from the base substrate.

[0013] According to some exemplary embodiments, the driving circuit layer includes a gate metal layer and a source-drain metal layer, the raised portion includes a first raised portion, the first raised portion is located in the gate metal layer, and / or the raised portion includes a second raised portion, the second raised portion is located in the source-drain metal layer.

[0014] According to some exemplary embodiments, an orthographic projection of the first elevating portion on the base substrate at least partially overlaps with an orthographic projection of the second elevating portion on the base substrate.

[0015] According to some exemplary embodiments, the driving circuit layer includes an active layer and a light-shielding layer located on a side of the active layer away from the first electrode layer, the raised portion also includes a third raised portion located on the light-shielding layer, and / or the raised portion also includes a fourth raised portion located on the active layer.

[0016] According to some exemplary embodiments, the first electrode layer includes a first electrode, and one first electrode is electrically connected to the driving circuit layer through at least two first electrode connecting portions; and

[0017] The passivation layer includes at least two protrusions, and the two protrusions are respectively located on one side of the two first electrode connecting parts close to the base substrate.

[0018] According to some exemplary embodiments, the display substrate further comprises a conductive portion electrically connected to the first electrode connecting portion, the conductive portion being located on a side of the first electrode connecting portion away from the base substrate, and / or the conductive portion being located on a side of the first electrode connecting portion close to the base substrate; and

[0019] An orthographic projection of the conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first side wall on the base substrate.

[0020] According to some exemplary embodiments, one end of the conductive portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the second via hole and covers at least a portion of a surface of the first electrode connecting portion away from the first sidewall.

[0021] According to some exemplary embodiments, an orthographic projection of the conductive portion on the base substrate is spaced apart from an orthographic projection of the first via on the base substrate.

[0022] According to some exemplary embodiments, the first electrode layer includes a first sublayer, a second sublayer located on a side of the first sublayer away from the base substrate, and a third sublayer located on a side of the second sublayer away from the base substrate, the materials of the first sublayer and the third sublayer include transparent conductive materials, and the material of the second sublayer includes metal; and

[0023] The first electrode connecting portion is located in the first sub-layer, and the conductive portion is located in the second sub-layer.

[0024] According to some exemplary embodiments, the first electrode layer further includes a first electrode, the first electrode includes a first sub-electrode portion, a second sub-electrode portion, and a third sub-electrode portion, the first sub-electrode portion is located in the first sub-layer, the second sub-electrode portion is located in the second sub-layer, and the third sub-electrode portion is located in the third sub-layer; and

[0025] The first sub-electrode portion and the first electrode connecting portion are connected to form an integrated structure, and the second sub-electrode portion and the conductive portion are spaced apart.

[0026] In another aspect, a display device is provided, comprising the display substrate as described in any one of the above items.

[0027] In another aspect, a method for preparing a display substrate is provided, the method comprising:

[0028] forming a driving circuit layer on the base substrate;

[0029] forming a passivation layer on a side of the driving circuit layer away from the base substrate, wherein the passivation layer comprises a first via hole and a protrusion, and the protrusion protrudes toward a side away from the base substrate;

[0030] forming a planarization layer on a side of the passivation layer away from the base substrate, the planarization layer comprising a second via hole, an orthographic projection of the second via hole on the base substrate at least partially overlapping with an orthographic projection of the first via hole on the base substrate, the planarization layer having a first sidewall facing the second via hole, at least a portion of a side of the first sidewall close to the base substrate in contact with a surface of the protrusion away from the base substrate; and

[0031] A first electrode layer is formed on a side of the planarization layer away from the base substrate, the first electrode layer includes a first electrode connecting portion, one end of the first electrode connecting portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the first via hole to be electrically connected to the driving circuit layer, and the orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with the orthographic projection of the protruding portion on the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0033] Figure 1 A cross-sectional view of a display substrate in the related art is schematically shown.

[0034] Figure 2 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0035] Figure 3 Schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0036] Figure 4 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0037] Figure 5 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0038] Figure 6 The flowchart of a method for preparing a display substrate according to some embodiments of the present disclosure is schematically shown.

[0039] Figures 7A-7C The diagram schematically shows a preparation process diagram of a method for preparing a display substrate according to some embodiments of the present disclosure.

[0040] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0042] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0043] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on another element, directly connected to another element or directly coupled to another element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0044] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0045] Figure 1 A cross-sectional view of a display substrate in the related art is schematically shown.

[0046] Reference Figure 1 The display substrate includes a base substrate 100' and a driving circuit layer 200', a passivation layer PVX', a planarization layer PLN' and a light emitting device layer 300' sequentially arranged on the base substrate 100'. The first electrode layer 310' in the light emitting device layer 300' is electrically connected to the driving circuit layer 200' through a first via hole VH1' in the passivation layer PVX' and a second via hole VH2' in the planarization layer PLN'.

[0047] However, the inventors have discovered that, affected by the preparation process of the planarization layer PLN' and other subsequent preparation processes, a protruding structure is easily formed on the side wall of the planarization layer PLN' at the second via VH2'. The protruding structure may cause the first electrode layer 310' on the side wall to break, thereby affecting the connection between the first electrode layer 310' and the driving circuit layer 200', and causing display defects such as dark spots.

[0048] Figure 2 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown. Figure 3 A schematic plan view of a display substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 3 Only the first electrode layer, the pixel defining layer and the passivation layer in the display substrate are schematically shown. Figure 2 The schematic cross-sectional view can be taken along Figure 3 Cross-sectional view taken along the midline AA'.

[0049] According to some exemplary embodiments, referring to Figure 2 The display substrate includes a base substrate 100, a driving circuit layer 200 located on the base substrate 100, a passivation layer PVX located on a side of the driving circuit layer 200 away from the base substrate 100, a planarization layer PLN located on a side of the passivation layer PVX away from the base substrate 100, and a light emitting device layer 300 located on a side of the planarization layer PLN away from the base substrate 100.

[0050] The driving circuit layer 200 includes a plurality of pixel driving circuits, and the driving circuit layer 200 is stacked by a plurality of conductive layers, a plurality of insulating layers, and at least one active layer Act. For example, the driving circuit layer 200 may include a light shielding layer LS located on the base substrate 100, a buffer layer Buf located on the side of the light shielding layer LS away from the base substrate 100, an active layer Act located on the side of the buffer layer Buf away from the base substrate 100, a gate insulating layer GI located on the side of the active layer Act away from the base substrate 100, a gate metal layer Gate located on the side of the gate insulating layer GI away from the base substrate 100, an interlayer insulating layer ILD located on the side of the gate metal layer Gate away from the base substrate 100, and a source-drain metal layer SD located on the side of the interlayer insulating layer ILD away from the base substrate 100.

[0051] The light-emitting device layer 300 includes a plurality of light-emitting devices, and the plurality of light-emitting devices are electrically connected to a plurality of pixel driving circuits, respectively. The light-emitting device layer 300 may include a first electrode layer 310, a light-emitting functional layer 320 located on a side of the first electrode layer 310 away from the substrate 100, and a second electrode layer 330 located on a side of the light-emitting functional layer 320 away from the substrate 100. A pixel defining layer PDL is further provided between the first electrode layer 310 and the light-emitting functional layer 320, and the pixel defining layer PDL includes a pixel opening KK1, and the pixel opening KK1 exposes at least a portion of the first electrode layer 310, and the light-emitting functional layer 320 contacts the first electrode layer 310 through the pixel opening KK1.

[0052] Combined with reference Figure 2 and Figure 3 The passivation layer PVX includes a first via hole VH1, the planarization layer PLN includes a second via hole VH2, the orthographic projection of the first via hole VH1 on the base substrate 100 is located within the orthographic projection of the second via hole VH2 on the base substrate 100, and the planarization layer PLN includes a first side wall CB1 facing the second via hole VH2.

[0053] The first electrode layer 310 includes a first electrode 311 and a first electrode connecting portion 312 connected to each other, the pixel opening KK1 exposes a portion of the first electrode 311, and the pixel defining layer PDL covers the first electrode connecting portion 312. One end of the first electrode connecting portion 312 is located on a side of the planarization layer PLN away from the base substrate 100 and is electrically connected to the first electrode 311, and the other end of the first electrode connecting portion 312 extends through the first side wall CB1 to the first via hole VH1 and is electrically connected to the driving circuit layer 200.

[0054] The passivation layer PVX also includes a protrusion B, which protrudes toward a side away from the substrate 100, at least a portion of the side of the first side wall CB1 close to the substrate 100 contacts the surface of the protrusion B away from the substrate 100, and the orthographic projection of the first electrode connection portion 312 on the substrate 100 overlaps at least partially with the orthographic projection of the protrusion B on the substrate 100. By providing the protrusion B on the side of the first side wall CB1 close to the substrate 100, the side of the first side wall CB1 close to the substrate 100 is raised by the protrusion B, and the planarization layer PLN undergoes a leveling process during the manufacturing process, and the height of the side of the first side wall CB1 away from the substrate 100 does not substantially change, so that the width W of the first side wall CB1 (the distance between the side of the first side wall CB1 away from the substrate 100 and the side of the first side wall CB1 close to the substrate 100) can be reduced, thereby effectively reducing the risk of the first electrode connection portion 312 being broken at the first side wall CB1.

[0055] According to some exemplary embodiments, Figure 2 and Figure 3 The display substrate includes a plurality of light-emitting areas A1 and a plurality of transparent areas A2, and the plurality of light-emitting areas A1 and the plurality of transparent areas A2 are arranged alternately, and the specific arrangement is not limited in the embodiment of the present disclosure. Figure 2 and Figure 3 In the figure, only a part of a light-emitting area A1 and a part of a transparent area A2 are illustrated. The shape and size of the light-emitting area A1, as well as the shape and size of the transparent area A2 are set according to actual display requirements and are not limited in the embodiments of the present disclosure.

[0056] The pixel driving circuit and the light-emitting device are arranged in the light-emitting area A1 for emitting light to realize display. The transparent area A2 has a high transmittance, so that the user can see the scene behind the display substrate while the display substrate displays the image. The portion of the display substrate located in the transparent area A2 includes only a portion of the inorganic insulating layer and the transparent film layer such as the common film layer in the light-emitting device layer 300. For example, the film layer located in the transparent area A2 includes a buffer layer Buf, an interlayer insulating layer ILD, a passivation layer PVX, a light-emitting functional layer 320 and a second electrode layer 330.

[0057] The second via hole VH2 provided in the planarization layer PLN, on the one hand, is used to expose the first via hole VH1 of the passivation layer PVX so that the first electrode connection portion 312 can be electrically connected to the driving circuit layer 200; on the other hand, the setting range of the second via hole VH2 is relatively large, covering the setting range of the transparent area A2, that is, the planarization layer PLN is removed in the transparent area A2 to increase the transmittance of the display substrate in the transparent area A2.

[0058] Similarly, the pixel defining layer PDL also includes a transparent opening KK2 spaced apart from the pixel opening KK1, and the transparent opening KK2 is located in the transparent area A2. The orthographic projection of the transparent opening KK2 on the base substrate 100 partially overlaps with the orthographic projection of the second via hole VH2 on the base substrate 100, that is, the pixel defining layer PDL is removed in the transparent area A2 to increase the transmittance of the display substrate in the transparent area A2.

[0059] Continue to refer to Figure 3 In the display substrate provided with the transparent area A2, due to the setting of the transparent area A2, the opening size of the second via hole VH2 is larger, and the orthographic projection of the first electrode connecting portion 312 on the base substrate 100 only partially overlaps with the orthographic projection of the second via hole VH2 on the base substrate 100, that is, the first electrode connecting portion 312 only crosses one side of the first side wall CB1. Compared with the structure in which the first electrode connecting portion 312 completely covers the via hole of the planarization layer PLN in the non-transparent display substrate, the first electrode connecting portion 312 is more likely to be completely broken at the first side wall CB1 to cause poor display, and this problem can be effectively avoided by providing a protrusion B on the side of the first side wall CB1 close to the base substrate 100.

[0060] For example, the orthographic projection of the protrusion B on the base substrate 100 is roughly rectangular, including a first side B1 and a second side B2 arranged opposite to each other, and a third side B3 and a fourth side B4 arranged opposite to each other. The first side B1 and the second side B2 are respectively located on both sides of the orthographic projection of the first side wall CB1 on the base substrate 100, and the third side B3 and the fourth side B4 are respectively located on both sides of the orthographic projection of the first electrode connecting portion 312 on the base substrate 100.

[0061] According to some exemplary embodiments, referring to Figure 2 The first electrode layer 310 includes a first sublayer 310a, a second sublayer 310b located on a side of the first sublayer 310a away from the base substrate 100, and a third sublayer 310c located on a side of the second sublayer 310b away from the base substrate 100. The materials of the first sublayer 310a and the third sublayer 310c include transparent conductive materials, and the material of the second sublayer 310b includes metal. For example, the materials of the first sublayer 310a and the third sublayer 310c may include indium tin oxide, and the material of the second sublayer 310b may include at least one of silver, aluminum, molybdenum, and copper.

[0062] The first electrode 311 includes a first sub-electrode portion 311a located in the first sub-layer 310a, a second sub-electrode portion 311b located in the second sub-layer 310b, and a third sub-electrode portion 311c located in the third sub-layer 310c. The first electrode 311 is a three-layer structure. The second sub-electrode portion 311b of the first electrode 311 located in the second sub-layer 310b has a high reflectivity. The first electrode 311 acts as a reflective electrode, so that the light-emitting device can emit light in a direction away from the base substrate 100, that is, top emission display is realized. The first electrode connecting portion 312 is located in the first sub-layer 310a, that is, the first electrode connecting portion 312 only includes a transparent conductive material, which is conducive to improving the transparency of the display substrate.

[0063] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 3 , one first electrode 311 is electrically connected to the driving circuit layer 200 through at least two first electrode connecting portions 312, one end of the two first electrode connecting portions 312 is respectively connected to different positions of the first electrode 311, and the other ends of the two first electrode connecting portions 312 extend toward the direction close to the first via hole VH1 and are connected to form an integral structure at the first via hole VH1. By providing at least two first electrode connecting portions 312, even if one first electrode connecting portion 312 is broken at the first side wall CB1, the display signal can still be transmitted through the other first electrode connecting portions 312, which can further reduce the risk of poor display caused by the breakage of the first electrode connecting portion 312.

[0064] According to some exemplary embodiments, referring to Figure 3 The passivation layer PVX includes at least two protrusions B, which are respectively located on one side of the two first electrode connecting portions 312 close to the base substrate 100, that is, the protrusions B are arranged below the overlapping parts of the first side wall CB1 and the two first electrode connecting portions 312, so as to avoid the two first electrode connecting portions 312 from breaking when crossing the first side wall CB1.

[0065] According to some exemplary embodiments, referring to Figure 2 The driving circuit layer 200 includes multiple driving function layers, at least one driving function layer includes a padding portion C, the orthographic projection of the padding portion C on the base substrate 100 at least partially overlaps with the orthographic projection of the first electrode connecting portion 312 on the base substrate 100, and the orthographic projection of the padding portion C on the base substrate 100 at least partially overlaps with the orthographic projection of the first side wall CB1 on the base substrate 100, and the protrusion B is located on the side of the padding portion C away from the base substrate 100. The padding portion C can be provided at a specific position in the driving circuit layer 200, and the padding portion C pads a part of the passivation layer PVX to form the protrusion B.

[0066] According to some exemplary embodiments, referring to Figure 2 The driving circuit layer 200 includes a gate metal layer Gate and a source-drain metal layer SD, and the padding portion C includes a first padding portion C1 and a second padding portion C2, wherein the first padding portion C1 is located in the gate metal layer Gate, and the second padding portion C2 is located in the source-drain metal layer SD. The source-drain metal layer SD and the gate metal layer Gate are relatively thick, and the padding portions C can be respectively provided in the source-drain metal layer SD and the gate metal layer Gate, so that the protrusion B formed on the passivation layer PVX above the padding portion C has a relatively high protrusion height.

[0067] For example, the thickness of the gate metal layer Gate can be 4500 angstroms, the thickness of the source-drain metal layer SD can be 6000 angstroms, and the thickness of the planarization layer PLN at the thickest point is 1.5-2 μm. Then, the stacked first padding portion C1 and the second padding portion C2 can make the protrusion B formed in the passivation layer PVX have a protrusion height of about 1 μm, thereby shortening the width W of the first side wall CB1 by more than 50%.

[0068] It should be noted that the gate metal layer Gate and the gate insulating layer GI can be formed by a Mask. Therefore, when the first padding portion C1 is formed, a fifth padding portion C5 located on the side of the first padding portion C1 close to the base substrate 100 will also be formed. The fifth padding portion C5 is located in the gate insulating layer GI.

[0069] According to some exemplary embodiments, referring to Figure 2 The orthographic projection of the first raised portion C1 on the base substrate 100 at least partially overlaps with the orthographic projection of the second raised portion C2 on the base substrate 100. The first raised portion C1 and the second raised portion C2 are stacked and jointly raise the passivation layer PVX to form a protrusion B.

[0070] Figure 4 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0071] According to some exemplary embodiments, referring to Figure 4 The raised portion C may also include a third raised portion C3 located on the light-shielding layer LS and a fourth raised portion C4 located on the active layer Act, the orthographic projection of the third raised portion C3 on the base substrate 100 overlaps with the orthographic projections of the first raised portion C1 and the second raised portion C2 on the base substrate 100, and the orthographic projection of the fourth raised portion C4 on the base substrate 100 overlaps with the orthographic projections of the first raised portion C1 and the second raised portion C2 on the base substrate 100.

[0072] Figure 5 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0073] According to some exemplary embodiments, referring to Figure 5 , the display substrate further includes a conductive portion M electrically connected to the first electrode connection portion 312, and the thickness of the conductive portion M is greater than the thickness of the first electrode connection portion 312. The conductive portion M is located on a side of the first electrode connection portion 312 away from the base substrate 100, and / or, the conductive portion M is located on a side of the first electrode connection portion 312 close to the base substrate 100, and the orthographic projection of the conductive portion M on the base substrate 100 overlaps at least partially with the orthographic projection of the first side wall CB1 on the base substrate 100. By adding a thicker conductive portion M at a position where the first electrode connection portion 312 and the first side wall CB1 overlap, even if the first electrode connection portion 312 is broken at the first side wall CB1, the thicker thickness of the conductive portion M can still remain continuous at the first side wall CB1, so that the display signal can be transmitted normally.

[0074] According to some exemplary embodiments, referring to Figure 5 The conductive portion M is located in the second sub-layer 310b, and is disposed on a side of the first electrode connecting portion 312 away from the base substrate 100, that is, the conductive portion M is formed at the same time as the second sub-layer 310b is formed, without the need to add an additional preparation process for the display substrate.

[0075] According to some exemplary embodiments, referring to Figure 5 One end of the conductive portion M is located on a side of the planarization layer PLN away from the base substrate 100 , and the other end extends into the second via hole VH2 and covers at least a portion of the surface of the first electrode connecting portion 312 away from the first side wall CB1 .

[0076] According to some exemplary embodiments, referring to Figure 5 , one end of the conductive part M close to the first electrode 311 is located on the side of the planarization layer PLN away from the base substrate 100, and the conductive part M is spaced apart from the second sub-electrode part 311b. The raised portion B includes a second side wall CB2 facing the second via hole VH2, and one end of the conductive part M away from the first electrode 311 can extend to the side of the first electrode connecting part 312 away from the second side wall CB2, and the orthographic projection of the conductive part M on the base substrate 100 is spaced apart from the orthographic projection of the first via hole VH1 on the base substrate 100. That is, on the basis of ensuring that the conductive part M can completely cover the surface of the first electrode connecting part 312 away from the first side wall CB1, the area of ​​the orthographic projection of the conductive part M on the base substrate 100 is reduced, which is conducive to improving the transparency of the display substrate.

[0077] Figure 6 The flowchart of a method for preparing a display substrate according to some embodiments of the present disclosure is schematically shown.

[0078] At least some embodiments of the present disclosure also provide a method for preparing a display substrate, referring to Figure 6The preparation method includes the following steps S10 to S40.

[0079] In step S10 , a driving circuit layer is formed on a base substrate.

[0080] In step S20, a passivation layer is formed on a side of the driving circuit layer away from the base substrate, the passivation layer includes a first via hole and a protrusion, and the protrusion protrudes toward the side away from the base substrate.

[0081] In step S30, a planarization layer is formed on a side of the passivation layer away from the base substrate, the planarization layer includes a second via hole, an orthographic projection of the second via hole on the base substrate at least partially overlaps with an orthographic projection of the first via hole on the base substrate, and the planarization layer has a first side wall facing the second via hole, and at least a portion of the side of the first side wall close to the base substrate is in contact with a surface of the protrusion away from the base substrate.

[0082] In step S40, a first electrode layer is formed on a side of the planarization layer away from the base substrate, the first electrode layer includes a first electrode connecting portion, one end of the first electrode connecting portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the first via hole to be electrically connected to the driving circuit layer, and the orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with the orthographic projection of the protruding portion on the base substrate.

[0083] Figures 7A-7C The diagram schematically shows a preparation process diagram of a method for preparing a display substrate according to some embodiments of the present disclosure.

[0084] Combine as follows Figures 7A-7C The preparation process of a method for preparing a display substrate according to an embodiment of the present disclosure is described in detail.

[0085] Reference Fig. 7A , a driving circuit layer 200 is formed on a base substrate 100, and the driving circuit layer 200 includes sequentially forming a light shielding layer LS, a buffer layer Buf, an active layer Act, a gate insulating layer GI, a gate metal layer Gate, an interlayer insulating layer ILD, and a source-drain metal layer SD on the base substrate 100. The gate metal layer Gate includes forming a gate G and a first padding portion C1 arranged at intervals, and the source-drain metal layer SD includes forming a source S, a drain D, and a second padding portion C2 arranged at intervals, and the orthographic projection of the first padding portion C1 on the base substrate 100 at least partially overlaps with the orthographic projection of the second padding portion C2 on the base substrate 100.

[0086] Reference Figure 7B, a passivation layer PVX, a planarization layer PLN and a first electrode layer 310 are sequentially formed on the side of the driving circuit layer 200 away from the base substrate 100. The passivation layer PVX includes a first via hole VH1, and the first via hole VH1 exposes a portion of the driving circuit layer 200. The planarization layer PLN includes a second via hole VH2, and the orthographic projection of the first via hole VH1 on the base substrate 100 is located inside the orthographic projection of the second via hole VH2 on the base substrate 100.

[0087] Forming the first electrode layer 310 includes sequentially forming a first sublayer 310a, a second sublayer 310b, and a third sublayer 310c, and the first electrode layer 310 includes a connected first electrode 311 and a first electrode connecting portion 312. The first electrode 311 includes a first sub-electrode portion 311a located in the first sublayer 310a, a second sub-electrode portion 311b located in the second sublayer 310b, and a third sub-electrode portion 311c located in the third sublayer 310c, and the first electrode connecting portion 312 is located in the first sublayer 310a, and the first electrode connecting portion 312 is connected to the first sub-electrode portion 311a to form an integrated structure.

[0088] For example, forming the second sub-layer 310 b includes forming a second sub-electrode portion 311 b and a conductive portion M that are spaced apart, and an orthographic projection of the conductive portion M on the base substrate 100 at least partially overlaps with an orthographic projection of the protrusion B on the base substrate 100 .

[0089] Reference Figure 7C A pixel defining layer PDL, a light emitting functional layer 320 and a second electrode layer 330 are sequentially formed on a side of the first electrode layer 310 away from the base substrate 100. The pixel defining layer PDL includes a pixel opening KK1, which exposes a portion of the first electrode 311, and the light emitting functional layer 320 contacts the first electrode 311 through the pixel opening KK1.

[0090] At least some embodiments of the present disclosure also provide a display device, which includes a display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0091] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0092] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0093] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate substrate; A driving circuit layer, located on the substrate; A passivation layer, located on a side of the driving circuit layer away from the substrate, the passivation layer comprising a first via hole; a planarization layer, located on a side of the passivation layer away from the base substrate, the planarization layer comprising a second via hole, an orthographic projection of the second via hole on the base substrate at least partially overlapping with an orthographic projection of the first via hole on the base substrate; and A first electrode layer, located at a side of the planarization layer away from the base substrate, the first electrode layer being electrically connected to the driving circuit layer through the second via hole and the first via hole; The passivation layer includes a protrusion, the protrusion protrudes toward a side away from the base substrate, the planarization layer has a first side wall facing the second via hole, and at least a portion of the first side wall close to the side of the base substrate is in contact with a surface of the protrusion away from the base substrate; and The first electrode layer includes a first electrode connecting portion, one end of the first electrode connecting portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the first via hole and is electrically connected to the driving circuit layer, and the orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with the orthographic projection of the protruding portion on the base substrate.

2. The display substrate according to claim 1, wherein: The driving circuit layer includes multiple driving function layers, at least one of the driving function layers includes a raised portion, the orthographic projection of the raised portion on the base substrate at least partially overlaps with the orthographic projection of the first electrode connecting portion on the base substrate, and the raised portion is located on a side of the raised portion away from the base substrate.

3. The display substrate according to claim 2, wherein: The driving circuit layer includes a gate metal layer and a source-drain metal layer, the raised portion includes a first raised portion, the first raised portion is located in the gate metal layer, and / or the raised portion includes a second raised portion, the second raised portion is located in the source-drain metal layer.

4. The display substrate according to claim 3, wherein: An orthographic projection of the first raised portion on the base substrate at least partially overlaps with an orthographic projection of the second raised portion on the base substrate.

5. The display substrate according to claim 3 or 4, wherein: The driving circuit layer includes an active layer and a light shielding layer located on a side of the active layer away from the first electrode layer, the raised portion also includes a third raised portion located on the light shielding layer, and / or the raised portion also includes a fourth raised portion located on the active layer.

6. The display substrate according to claim 1, wherein: The first electrode layer includes a first electrode, and one of the first electrodes is electrically connected to the driving circuit layer through at least two first electrode connecting portions; and The passivation layer includes at least two protrusions, and the two protrusions are respectively located on one side of the two first electrode connecting parts close to the base substrate.

7. The display substrate according to any one of claims 1 to 6, wherein: The display substrate further comprises a conductive portion electrically connected to the first electrode connecting portion, the conductive portion being located on a side of the first electrode connecting portion away from the base substrate, and / or the conductive portion being located on a side of the first electrode connecting portion close to the base substrate; and An orthographic projection of the conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first side wall on the base substrate.

8. The display substrate according to claim 7, wherein: One end of the conductive portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the second via hole and covers at least a portion of a surface of the first electrode connecting portion away from the first side wall.

9. The display substrate according to claim 7 or 8, wherein: An orthographic projection of the conductive portion on the base substrate is spaced apart from an orthographic projection of the first via hole on the base substrate.

10. The display substrate according to any one of claims 7 to 9, wherein: The first electrode layer includes a first sublayer, a second sublayer located on a side of the first sublayer away from the substrate, and a third sublayer located on a side of the second sublayer away from the substrate, wherein the materials of the first sublayer and the third sublayer include transparent conductive materials, and the material of the second sublayer includes metal; and The first electrode connecting portion is located in the first sub-layer, and the conductive portion is located in the second sub-layer.

11. The display substrate according to claim 10, wherein: The first electrode layer further includes a first electrode, the first electrode includes a first sub-electrode portion, a second sub-electrode portion, and a third sub-electrode portion, the first sub-electrode portion is located in the first sub-layer, the second sub-electrode portion is located in the second sub-layer, and the third sub-electrode portion is located in the third sub-layer; and The first sub-electrode portion and the first electrode connecting portion are connected to form an integrated structure, and the second sub-electrode portion and the conductive portion are spaced apart.

12. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 11.

13. A method for preparing a display substrate, wherein: The preparation method comprises: forming a driving circuit layer on the base substrate; forming a passivation layer on a side of the driving circuit layer away from the base substrate, wherein the passivation layer comprises a first via hole and a protrusion, and the protrusion protrudes toward a side away from the base substrate; forming a planarization layer on a side of the passivation layer away from the base substrate, the planarization layer comprising a second via hole, an orthographic projection of the second via hole on the base substrate at least partially overlapping with an orthographic projection of the first via hole on the base substrate, the planarization layer having a first sidewall facing the second via hole, at least a portion of a side of the first sidewall close to the base substrate in contact with a surface of the protrusion away from the base substrate; and A first electrode layer is formed on a side of the planarization layer away from the base substrate, the first electrode layer includes a first electrode connecting portion, one end of the first electrode connecting portion is located on a side of the planarization layer away from the base substrate, and the other end extends into the first via hole to be electrically connected to the driving circuit layer, and the orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with the orthographic projection of the protruding portion on the base substrate.

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