Display panel, manufacturing method thereof and display device

Abstract

The present disclosure provides a display panel, a manufacturing method thereof and a display device, the display panel comprising a substrate, and a first region and a second region on the substrate, the display panel further comprising a plurality of pixels, wherein a plurality of first gate lines are included in the first region, and a plurality of second gate lines are included in the second region, a number of pixels connected by the first gate lines is less than a number of pixels connected by the second gate lines, the first gate lines comprise a first part arranged in an effective display area and a second part arranged in a non-display region outside the effective display area, the first part and the second part are electrically connected to each other, and the display panel further comprises a compensation structure, the compensation structure comprising a first electrode plate, and a normal projection of the first electrode plate on the substrate at least partially overlaps the second part.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device including the display panel. Background Technology

[0002] With the development of science and technology, more and more displays are being designed with irregular shapes. In panels with irregularly shaped display areas, the number of pixels per row is significantly reduced compared to normal areas. This results in a large difference in pixel load between normal and irregular areas, or a large difference in pixel load between adjacent rows, which can cause display problems.

[0003] For displays with irregular shapes, such as "notch" screens, the number of pixels in the "notch" area is less than that in the normal area, resulting in a large difference in load and causing display abnormalities. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a display panel, a method for manufacturing the same, and a display device including the display panel.

[0005] Embodiments of this disclosure provide a display panel, the display panel including a substrate, and a first region and a second region located on the substrate. The display panel also includes a plurality of pixels, wherein the first region includes a plurality of first gate lines, and the second region includes a plurality of second gate lines. The number of pixels connected by the first gate lines is less than the number of pixels connected by the second gate lines. The first gate line includes a first portion disposed in an effective display area and a second portion disposed in a non-display area outside the effective display area. The first portion and the second portion are electrically connected to each other. The display panel also includes a compensation structure, the compensation structure including a first electrode plate, the first electrode plate at least partially overlapping the orthographic projection of the second portion on the substrate.

[0006] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially, wherein the first portion is disposed in the gate line layer and the second portion is disposed in the source / drain layer.

[0007] According to an embodiment of the present disclosure, the first gate line further includes a third portion disposed in the conductive layer, the third portion being connected to the first portion disposed in the gate line layer via a via through the second insulating layer and the first insulating layer, and the third portion being connected to the second portion disposed in the source / drain layer via a via through the second insulating layer.

[0008] According to an embodiment of this disclosure, the compensation structure includes a first outer ring electrode disposed in the conductive layer. The first outer ring electrode is disposed in a non-display area outside the effective display area of ​​the display panel. The first electrode plate includes the first outer ring electrode, and the first outer ring electrode at least partially overlaps with the orthographic projection of the second portion disposed in the source / drain layer onto the substrate. The first outer ring electrode is disconnected from the third portion disposed in the conductive layer, and the first outer ring electrode is disconnected from the electrode in the conductive layer in the effective display area.

[0009] According to an embodiment of the present disclosure, the compensation structure further includes a second outer ring electrode disposed in the gate line layer. The second outer ring electrode is disposed in a non-display area outside the effective display area of ​​the display panel, and the second outer ring electrode at least partially overlaps with the orthographic projection of the second portion disposed in the source / drain layer onto the substrate. The second outer ring electrode is connected to the first outer ring electrode via a through-hole passing through the second insulating layer and the first insulating layer.

[0010] According to an embodiment of the present disclosure, the compensation structure further includes a first compensation unit disposed in the source / drain layer, and the second portion disposed in the source / drain layer is a gate fan-out line. The first compensation unit is formed between two adjacent gate fan-out lines and connected to one of the gate fan-out lines. The first outer ring electrode and the orthographic projection of the first compensation unit disposed in the source / drain layer on the substrate at least partially overlap.

[0011] According to an embodiment of the present disclosure, the compensation structure further includes a third outer ring electrode disposed in the gate line layer. The third outer ring electrode is disposed in a non-display area outside the effective display area of ​​the display panel. The third outer ring electrode at least partially overlaps with the orthographic projection of the first compensation unit disposed in the source-drain layer on the substrate. The third outer ring electrode is connected to the first outer ring electrode via a through-hole passing through the second insulating layer and the first insulating layer.

[0012] According to an embodiment of this disclosure, the first compensation unit and the third outer ring electrode have a mesh shape, and the third outer ring electrode overlaps with the orthographic projection of the first compensation unit on the substrate.

[0013] According to embodiments of this disclosure, the display panel further includes dummy pads disposed between adjacent second portions and disposed on the gate layer and / or the source / drain layer.

[0014] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially. The first gate line and the second gate line are formed in the gate line layer. The compensation structure includes a second compensation unit formed between two adjacent first gate lines and connected to one of the first gate lines.

[0015] According to an embodiment of the present disclosure, the second compensation unit includes a first sub-compensation unit disposed in the gate line layer, the first sub-compensation unit being connected to a first gate line in the gate line layer, and the first sub-compensation unit at least partially overlapping the orthographic projection of the conductive layer on the substrate.

[0016] According to an embodiment of this disclosure, the first sub-compensation unit includes a plurality of first sub-compensation units, and the overlap area of ​​at least one of the plurality of first sub-compensation units with the orthographic projection of the conductive layer on the substrate is different from the overlap area of ​​the other first sub-compensation units with the orthographic projection of the conductive layer on the substrate.

[0017] According to an embodiment of this disclosure, the second compensation unit further includes a second sub-compensation unit disposed in the source / drain layer, and the orthographic projections of the first sub-compensation unit and the second sub-compensation unit on the substrate at least partially overlap.

[0018] According to embodiments of this disclosure, the first sub-compensation unit includes a plurality of first sub-compensation units, the second sub-compensation unit includes a plurality of second sub-compensation units, and the overlap area of ​​the orthographic projection of at least one of the plurality of first sub-compensation units and at least one of the plurality of second sub-compensation units on the substrate is different from the overlap area of ​​the orthographic projection of the other first sub-compensation units and the other second sub-compensation units on the substrate.

[0019] According to an embodiment of this disclosure, the second sub-compensation unit is connected to the conductive layer via a through-hole passing through the second insulating layer.

[0020] According to embodiments of this disclosure, the first sub-compensation unit includes a plurality of first sub-compensation units, and the first gate line includes a plurality of first gate lines, wherein the number of first sub-compensation units connected to at least one of the plurality of first gate lines is different from the number of first sub-compensation units connected to the other first gate lines of the plurality of first gate lines.

[0021] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially. The first gate line and the second gate line are formed in the gate line layer, and a data line is formed in the source / drain layer. The compensation structure includes a data line extension portion disposed in the source / drain layer. The data line extension portion extends from the data line to the non-display area of ​​the display panel and at least partially overlaps with the orthographic projection of the second portion disposed in the gate line layer onto the substrate.

[0022] According to an embodiment of this disclosure, the line width of the data line extension is greater than the line width of the data line.

[0023] Embodiments of this disclosure also provide a method for manufacturing a display panel, used to manufacture a display panel according to various embodiments of this disclosure, the method comprising: preparing a compensation structure, the compensation structure including a first electrode plate, the first electrode plate at least partially overlapping the orthographic projection of a second portion on the substrate.

[0024] Embodiments of this disclosure also provide a display device, including a display panel according to various embodiments of this disclosure.

[0025] According to the various embodiments of the present disclosure, the display panel, by providing a compensation structure in the irregularly shaped region, compensates for the capacitance on each gate line in the irregularly shaped region, so that the load on each gate line in the irregularly shaped region is substantially the same as the load on each gate line in the normal region. While ensuring display effect, it saves display space, ensuring a narrow bezel and a high screen-to-body ratio. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 A display panel including irregularly shaped areas is shown schematically;

[0028] Figure 2 A schematic diagram of the layout of a display panel according to an embodiment of the present disclosure is shown;

[0029] Figure 3 A wiring diagram of a switching unit in a display panel according to an embodiment of the present disclosure is shown;

[0030] Figure 4 A cross-sectional view of a display panel according to an embodiment of the present disclosure is shown;

[0031] Figure 5 A schematic diagram showing the formation of overlapping capacitors in a display panel according to an embodiment of the present disclosure is shown;

[0032] Figure 6 A schematic diagram of a transition unit formed in a conductive layer in a display panel according to an embodiment of the present disclosure is shown;

[0033] Figure 7 Another layout schematic diagram of a display panel according to an embodiment of the present disclosure is shown;

[0034] Figure 8 Another schematic diagram showing the formation of overlapping capacitors in a display panel according to an embodiment of the present disclosure is shown;

[0035] Figure 9 A schematic diagram of an outer ring electrode formed in a gate line layer in a display panel according to an embodiment of the present disclosure is shown;

[0036] Figure 10 A comparative schematic diagram of the display panel before and after compensation according to an embodiment of the present disclosure is shown;

[0037] Figure 11 Another layout schematic diagram of a display panel according to an embodiment of the present disclosure is shown;

[0038] Figure 12 A schematic diagram of a first compensation unit formed in the source / drain layer in a display panel according to an embodiment of the present disclosure is shown;

[0039] Figure 13 Another layout schematic diagram of a display panel according to an embodiment of the present disclosure is shown;

[0040] Figure 14 A schematic diagram is shown of a display panel according to an embodiment of the present disclosure, in which a first compensation unit is formed in the source / drain layer and an outer ring electrode is formed in the gate layer;

[0041] Figure 15 Another layout schematic diagram of a display panel according to an embodiment of the present disclosure is shown;

[0042] Figure 16A and Figure 16B A schematic diagram of a second compensation unit in a display panel according to an embodiment of the present disclosure is shown;

[0043] Figure 17 Another layout schematic diagram of a display panel according to an embodiment of the present disclosure is shown;

[0044] Figure 18 A comparative schematic diagram of the display panel before and after compensation according to an embodiment of the present disclosure is shown;

[0045] Figure 19 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure is shown; and

[0046] Figure 20 A block diagram of a display device according to the present disclosure is shown. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions of this disclosure, the display panel, its manufacturing method, and display device including the display panel provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0048] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0049] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0050] As used herein, the term “and / or” includes any and all combinations of at least one related enumerated entry.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0053] Figure 1 A display panel including irregularly shaped areas is schematically shown. Specifically, Figure 1The diagram illustrates a "notch" screen (i.e., a display with a U-shaped notch). In the "notch" area (i.e., the U-shaped notch location), the length of the gate lines increases due to the influence of the U-shaped notch, leading to an increase in resistance R. However, since there are no pixels in the "notch" area, the overlap between the gate lines and data lines is reduced, resulting in a decrease in coupling capacitance C. Therefore, the load R*C per gate line in the "notch" area is reduced. Of course, display panels can include other irregularly shaped areas. It should be recognized that... Figure 1 The U-shaped groove shown is only one embodiment. The irregular area may also include blind holes formed in the display screen, and display pixels are formed around the blind holes.

[0054] For mobile devices, the display resolution is high, that is, it has a high pixel density unit (Pixels Per Inch, PPI), and the touch and display driver integration (TDDI) is also high. Therefore, there are many rows of grid lines, and the charging time of each row of grid lines is short. In addition, the touch time must be subtracted to make the charging time of each row of grid lines even shorter.

[0055] Assuming the load on each gate line in the irregular region is R1*C1, and the load on each gate line in the normal region is R2*C2, the voltage required for the highest grayscale is AV. When R2*C2 in the normal region is too large, the integrated circuit (IC) is insufficiently charged or nearing its critical value. The charging time for each row of gate lines is t, and the maximum voltage that can be charged is BV, where B < A. Therefore, after time t, the pixel voltage in the normal region cannot drive the liquid crystal to fully deflect, and the displayed grayscale is not the maximum grayscale. However, in the irregular region, because the load R1*C1 < R2*C2, the signal delay time is short. After time t, the pixel can be charged to the maximum voltage AV, achieving the maximum grayscale. Visually, this manifests as a noticeably darker image in the normal region, while the irregular regions on both sides of the U-shaped groove are brighter, resulting in uneven image display.

[0056] Load compensation is usually performed on the grid lines in the irregular area where the U-shaped groove is located. However, since display panels often have narrow bezel requirements, the space available for load compensation is limited. The compensated load often cannot meet the requirements, and the difference between the compensated load and the load of the normal area is still large, which will also result in uneven image quality.

[0057] This disclosure designs a compensation structure to ensure that the latency caused by the compensated load is close to the latency of the normal area, while simultaneously achieving narrow bezels and a high screen-to-body ratio.

[0058] See Figure 1Embodiments of this disclosure provide a display panel including a substrate (not shown), and a first region 10 (i.e., an irregularly shaped region) and a second region 20 (i.e., a normal region) located on the substrate. The first region 10 includes a plurality of first gate lines, and the second region 20 includes a plurality of second gate lines. Due to the presence of the irregularity, the number of pixels connected by the first gate lines is less than the number of pixels connected by the second gate lines. The display panel according to embodiments of this disclosure includes a compensation structure for compensating the capacitance on each first gate line in the first region 10.

[0059] According to embodiments of this disclosure, it is possible to Figure 1 Positions A, B, and / or C, as shown, compensate for the capacitance on each of the first gate lines in the first region 10.

[0060] Figure 2 A schematic diagram of the layout of a display panel near position A according to an embodiment of the present disclosure is shown. Figure 3 The diagram shows a wiring diagram of an adapter unit in a display panel according to an embodiment of the present disclosure. Figure 4 A cross-sectional view of an adapter unit in a display panel according to an embodiment of the present disclosure is shown.

[0061] like Figure 2 and Figure 3 As shown, the display panel may include multiple pixels. The first gate line includes a first portion 110 disposed in the active display area (AA) and a second portion 120 disposed in a non-display area outside the AA. The first portion 110 and the second portion 120 are electrically connected to each other. The compensation structure of the display panel includes a first electrode plate, which at least partially overlaps with the orthographic projection of the second portion 120 of the first gate line onto the substrate.

[0062] exist Figure 2The diagram illustrates the cutline of the display panel, which includes the array substrate cutline and the color filter substrate cutline. During display panel fabrication, a U-shaped groove for placing sensors (e.g., cameras) can be created by cutting away the substrate. Because the dielectric layer (such as PVX) is brittle, cracks are easily generated during cutting, allowing water vapor to enter the metal layer and cause corrosion. To prevent this, the edge 111 of the dielectric layer is recessed during display panel fabrication, creating a certain gap between the edge 111 and the cutline; this gap is related to the cutting precision. To avoid the influence of the external environment on the display panel's internal structure, a grounding wire (GND) 112 is also provided within the cutline. In some embodiments, the grounding wire (GND) 112 is located on the side of the dielectric layer edge 111 away from the cutline; in other embodiments, the grounding wire (GND) 112 is located between the edge 111 of the dielectric layer and the second portion 120 of the first gate line.

[0063] In some embodiments, a second portion 120 of the first gate line is formed as a gate line fan-out line arranged around a U-shaped slot. The second portion 120 of the first gate line is formed in a non-display area outside the AA area, and unlike the first portion 110 formed in the AA area, no pixel is directly connected to the second portion 120. The first gate line also includes a third portion 130 (hereinafter also referred to as a "transfer unit"), through which each gate line fan-out line is connected to the first portion 110 of the first gate line (i.e., the portion in the AA area connected to a pixel) via a respective transfer unit.

[0064] like Figure 3 As shown, the first portion 110 of the first gate line is connected to each pixel in the AA region via a thin film transistor (TFT) 150. When the signal on the first gate line causes the TFT 150 to be turned on, the data signal on the data line 160 is applied to the pixel electrode 170 via the TFT 150.

[0065] Figure 4 It shows Figure 3 The cross-sectional view of the adapter unit is shown. Figure 4As shown, the display panel according to an embodiment of this disclosure includes a gate layer 100, a gate insulating (GI) layer 200, a source / drain (SD) layer 300, a dielectric (PVX) layer 400, and an inductively coupled (ITO) layer 500 stacked sequentially. A first portion 110 of a first gate line located on the Gate layer 100 can be transferred to a second portion 120 of a first gate line disposed on the SD layer 300. That is, the first portion 110 of the first gate line is disposed in the Gate layer 100, and the second portion 120 of the first gate line (or a gate fan-out line) is disposed in the SD layer 300, thereby reducing the distance between the first gate line and the ITO layer 500.

[0066] Before the above transition is performed, when an overlapping capacitance is formed between the first gate line and the ITO layer 500, the dielectric layer between them includes the GI layer 200 and the PVX layer 400. Figure 5 A cross-sectional view is shown taken in a direction perpendicular to the fan-out line of the gate line (i.e., the second portion 120 of the first gate line). See also Figure 5 After the above-mentioned transfer, the first gate line is transferred to the SD layer 300. When the overlapping capacitance is formed between the first gate line and the ITO layer 500, the dielectric layer between them includes the PVX layer 400 but does not include the GI layer 200. That is, the distance between the first gate line and the ITO layer 500 is reduced, thereby increasing the overlapping capacitance, that is, providing greater compensation for the capacitance on each first gate line.

[0067] like Figure 4 As shown, an adapter unit (i.e., the third portion 130 of the first gate line) can be formed using the ITO layer 500. The adapter unit is connected to the first portion 110 of the first gate line located in the Gate layer 100 via vias passing through the PVX layer 400 and the GI layer 200, and is connected to the gate line fan-out line (i.e., the second portion 120 of the first gate line) located in the SD layer via vias passing through the PVX layer 400, thereby adaptering the first portion 110 of the first gate line in the Gate layer to the gate line fan-out line (i.e., the second portion 120 of the first gate line) in the SD layer. Figure 1 A transition unit (i.e., the third part 130 of the first gate line) is formed near positions A and B as shown.

[0068] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The switching unit is used to switch the gate line provided in the Gate layer 100 to the gate line fan-out line provided in the SD layer 300 to reduce the distance between the gate line (or gate line fan-out line) and the ITO layer 500, thereby increasing the overlapping capacitance to compensate for the capacitance on each gate line.

[0069] exist Figure 1At positions A and B of the U-shaped groove region shown, the narrow border restricts the grid linewidth, resulting in a relatively small linewidth. Compared to the normal region, the grid lines are longer, therefore the resistance on the grid lines is typically equal to or greater than that in the normal region. Thus, resistance compensation for the grid lines in the irregularly shaped region is usually unnecessary. Figure 2 As shown, the positions on both sides of the U-shaped groove area (i.e., Figure 1 As shown at positions A and B, the gate lines located on Gate layer 100 are transferred to the gate fan-out lines of SD layer 300. ITO layer 500 forms overlapping capacitance with all the gate fan-out lines formed on SD layer 300. The capacitance compensation value of each gate line is related to the length of the gate fan-out line. In irregular regions, a longer gate fan-out line means fewer pixels corresponding to that gate line, thus requiring a larger capacitance compensation. On the other hand, a longer gate fan-out line also means a larger overlap area with ITO layer 500, thereby increasing the obtainable capacitance compensation value. Therefore, it is not necessary to specifically calculate the compensation capacitance for each gate line.

[0070] See Figure 2 Dummy pads 140 can be placed between adjacent gate fan-out lines to reduce the step difference at the gate fan-out lines and improve flatness to make the cell thickness uniform. The dummy pads 140 can be placed on the Gate layer 100 and / or the SD layer 300.

[0071] Figure 6 A schematic diagram is shown of a display panel according to an embodiment of the present disclosure, in which a transition unit (i.e., the third portion 130 of the first gate line) is formed in the ITO layer 500.

[0072] See Figure 6 The ITO layer 500 can be used to form the transition unit, and the material used to form the transition unit is separated from the other materials of the ITO layer 500. For example... Figure 6 As shown, the ITO layer 500 can form a common (COM) electrode (AA_C) and / or a touch (Sensor) electrode (AA_S) in the AA area of ​​the display panel, and a first outer ring electrode 510 is formed in the non-display area outside the AA area. According to an embodiment of this disclosure, the first electrode plate of the compensation structure may include the first outer ring electrode 510 in the ITO layer 500.

[0073] In the context of this disclosure, "outer ring electrode" refers to an electrode formed in a non-display area outside the AA area, relative to the COM or Sensor electrodes formed in the inner ring of the AA area. For example... Figure 6As shown, the material of the ITO layer 500 located in the AA region is disconnected from the material of the ITO layer 500 in the non-display area outside the AA region, and the disconnection distance depends on the process exposure capability of the ITO layer 500. The material of the ITO layer used to form the transition unit is located in the non-display area outside the AA region, and the formed transition unit (i.e., the third portion 130 of the first gate line) is separated from the first outer ring electrode 510. That is, the first outer ring electrode 510 is independent of the COM or Sensor electrode (AA_C / AA_S), and the first outer ring electrode 510 is also independent of the transition unit.

[0074] Figure 7 A schematic diagram of the layout of a display panel near position C according to an embodiment of the present disclosure is shown.

[0075] like Figure 7 As shown, the compensation structure may further include a second outer ring electrode 520 formed in the Gate layer 100. After the gate line is transferred from the Gate layer 100 to the gate line fan-out line in the SD layer 300, a second outer ring electrode 520 can be formed in the Gate layer 100 to form an overlapping capacitance with the gate line fan-out line formed in the SD layer 300, so as to further compensate the capacitance on the first gate line.

[0076] Figure 8 It shows Figure 7 The diagram shows an overlapping capacitor formation in the display panel.

[0077] like Figure 8 As shown, an overlapping capacitance is formed between the gate fan-out line formed in the SD layer 300 and the ITO layer 500, and the dielectric layer between them includes a PVX layer 400; in addition, an overlapping capacitance is formed between the gate fan-out line formed in the SD layer 300 and the second outer ring electrode 520 formed in the Gate layer 100, and the dielectric layer between them includes a GI layer 200, thereby further compensating for the capacitance on each first gate line, thereby increasing the capacitance on the first gate line.

[0078] Figure 9 A schematic diagram showing a second outer ring electrode 520 formed in the Gate layer 100 in a display panel according to an embodiment of the present disclosure is shown. Specifically, Figure 9 It shows Figure 7 The layout design diagram at position D is shown.

[0079] like Figure 9 As shown, the second outer ring electrode 520 formed in the Gate layer 100 can be connected to the first outer ring electrode 510 formed in the ITO layer 500 through the PVX hole 450 (see...). Figure 6 In addition, in Figure 9The figure shows that the second outer ring electrode 520 formed in the Gate layer 100 overlaps with the gate fan-out line (i.e., the second portion 120 of the first gate line) formed in the SD layer 300. It is important to note that this layout design requires ensuring process accuracy (overlay) between the SD layer 300 and the Gate layer 100. However, the second outer ring electrode 520 formed in the Gate layer 100 is not limited to the formation shown in the figure, but can be formed in different ways. For example, similar to the first outer ring electrode 510 formed in the ITO layer 500, the second outer ring electrode 520 in the Gate layer 100 can be formed as a single unit.

[0080] It should be noted that the first outer ring electrode 510 formed in the ITO layer 500 and the COM or Sensor electrodes (AA_C / AA_S) in the AA area are independent of each other (i.e., disconnected and insulated from each other). However, in order to prevent display or touch problems caused by capacitive coupling between the electrodes in the AA area and the first outer ring electrode 510 due to signal differences, the signal of the first outer ring electrode 510 can be synchronized with the signal of the electrodes in the AA area. That is, when the AA area is in display mode, the signals applied to the electrodes in the AA area and the first outer ring electrode 510 are both COM signals; when the AA area is in touch mode, the signals applied to the electrodes in the AA area and the first outer ring electrode 510 are both touch pulse signals.

[0081] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The compensation structure includes a first outer ring electrode 510 formed in the ITO layer 500 and a second outer ring electrode 520 formed in the Gate layer 100. A switching unit is used to switch the gate lines disposed in the Gate layer 100 to the gate line fan-out lines disposed in the SD layer 300, thereby reducing the distance between the gate lines (or gate line fan-out lines) and the ITO layer 500. After the gate lines of the Gate layer 100 are switched to the gate line fan-out lines of the SD layer 300 via the switching unit, a double-layer capacitor can be formed in the second outer ring electrode 520 formed in the Gate layer 100, making it easier to meet the compensation capacitor requirements and simplifying the design for easy operation.

[0082] Figure 10 A comparative schematic diagram of the display panel before and after compensation according to an embodiment of the present disclosure is shown.

[0083] See Figure 10The graph shows the percentage changes before and after compensation on the vertical axis, and the number of compensation grid lines in the irregular region on the horizontal axis. Before compensation, the capacitance at the U-slot position is 30% to 50% of the capacitance at the normal position, the resistance at the U-slot position is 120% to 130% of the resistance at the normal position, and the load R*C at the U-slot position is 40% to 60% of the load R*C at the normal position. After compensation, the capacitance at the U-slot position is 90% to 100% of the capacitance at the normal position, the resistance at the U-slot position is the same as before compensation, and the load R*C at the U-slot position is 110% to 130% of the load R*C at the normal position.

[0084] According to an embodiment of this disclosure, if the capacitance compensation on the gate line still cannot meet the requirements after compensation at position C, compensation can be performed at positions A and B by increasing the gate line area.

[0085] Figure 11 Another layout schematic diagram of a display panel near position A according to an embodiment of the present disclosure is shown. Figure 12 A schematic diagram of a first compensation unit 310 formed in the SD layer 300 in a display panel according to an embodiment of the present disclosure is shown.

[0086] According to embodiments of this disclosure, the compensation structure may further include a first compensation unit 310 formed in the SD layer 300. Figure 2 Compared to the embodiments shown, in Figure 11 and Figure 12 In the display panel shown, a first compensation unit 310 is formed between two adjacent fan-out lines of the gate line (i.e., the second portion 120 of the first gate line), and the formed first compensation unit 310 is connected to one of the fan-out lines of the gate line. Figure 11 In the embodiment shown, by adding a first compensation unit 310 connected to the gate fan-out line, the overlap area between the gate fan-out line and the ITO layer 500 can be increased, thereby increasing the overlap capacitance formed between the first gate line and the ITO layer to compensate for the capacitance on the first gate line.

[0087] It should be recognized that, although in Figure 11 and Figure 12 The figure shows that the first compensation unit 310 has a mesh shape, but the shape of the first compensation unit 310 is not limited to the pattern shown in the figure, but can have various patterns. If the first compensation unit 310 is located in the sealant area, the pattern of the first compensation unit 310 needs to ensure an appropriate aperture ratio to ensure that sufficient ultraviolet (UV) light can pass through to cure the sealant.

[0088] Figure 13 Another layout schematic diagram of a display panel near position A according to an embodiment of the present disclosure is shown. Figure 14A schematic diagram is shown of a display panel according to an embodiment of the present disclosure, in which a first compensation unit 310 is formed in the SD layer 300 and a third outer ring electrode 530 is formed in the Gate layer 100.

[0089] According to embodiments of this disclosure, the compensation structure may further include a third outer ring electrode 530 in the Gate layer 100 corresponding to the first compensation unit 310. Figure 11 and Figure 12 Compared to the embodiments shown, in Figure 13 and Figure 14 In the display panel shown, a third outer ring electrode 530 is formed in the Gate layer 100 at a position corresponding to the first compensation unit 310 in the SD layer 300, and is connected to the first outer ring electrode 510 formed in the ITO layer 500 through a PVX hole 450. Therefore, not only is an overlapping capacitance formed between the gate fan-out line in the SD layer 300 and the first outer ring electrode 510 formed in the ITO layer 500, but also an overlapping capacitance is formed between the gate fan-out line in the SD layer 300 and the third outer ring electrode 530 in the Gate layer 100. Thus, by forming the third outer ring electrode 530 in the Gate layer 100 at a position corresponding to the first compensation unit 310, a double-layer capacitor can be formed to compensate for the capacitance on the first gate line.

[0090] With reference Figure 11 and Figure 12 Similar to the first compensation unit 310 described, according to the embodiments of this disclosure, the specific pattern of the third outer ring electrode 530 formed in the Gate layer 100 is not limited, as long as an appropriate aperture ratio can be ensured to ensure that sufficient UV light can be transmitted to cure the frame adhesive.

[0091] The above combination Figures 2 to 14 A display panel according to an embodiment of the present disclosure has been described, wherein by transferring the gate lines located on the Gate layer 100 to the gate line fan-out lines of the SD layer 300, the distance between the gate lines and the ITO layer 500 can be reduced, thereby compensating for the capacitance on the gate lines. However, the embodiments of the present disclosure are not limited thereto, and capacitance compensation on the gate lines can be achieved without transferring the gate lines of the Gate layer to the SD layer.

[0092] Figure 15 Another layout schematic diagram of a display panel near position A according to an embodiment of the present disclosure is shown. Figure 2 Compared to the embodiments shown, in Figure 15 In the display panel shown, no transition unit is formed, and the first portion 110 of the first gate line and the second portion 120' of the first gate line (i.e., the gate line fan-out line) are both formed on the Gate layer.

[0093] According to embodiments of this disclosure, the compensation structure may include a second compensation unit. For example... Figure 15 As shown, a second compensation unit is formed between two adjacent first grid lines, and the formed second compensation unit is connected to one of the first grid lines.

[0094] According to an embodiment of the present disclosure, the second compensation unit may include a first sub-compensation unit 105 formed on the Gate layer 100, wherein the first sub-compensation unit 105 is connected to the first gate line, and a capacitor is formed between the first sub-compensation unit 105 and the ITO layer 500 to compensate for the capacitance on the first gate line.

[0095] According to an embodiment of the present disclosure, the second compensation unit further includes a second sub-compensation unit 305 formed in the SD layer 300, and a capacitor is formed between the first sub-compensation unit 105 and the second sub-compensation unit 305 to compensate for the capacitance on the first gate line.

[0096] Figure 16A and Figure 16B A schematic diagram of a second compensation unit in a display panel according to an embodiment of the present disclosure is shown.

[0097] See Figure 16A A capacitor is formed between the first sub-compensation unit 105 of the Gate layer 100 and the ITO layer 500, and the dielectric layer between them includes the GI layer 200 and the PVX layer 400. The ITO layer 500 can be connected to the SD layer 300 through the PVX hole 450.

[0098] See Figure 16B A capacitor is formed between the first sub-compensation unit 105 of the Gate layer 100 and the second sub-compensation unit 305 of the SD layer 300, and the dielectric layer between them includes the GI layer 200. The second sub-compensation unit 305 of the SD layer 300 can be connected to the ITO layer 500 through the PVX hole 450.

[0099] Due to the different thicknesses of the dielectric layers, for the same area... Figure 16A The compensation unit shown and Figure 16B The compensation capacitors provided by the compensation units shown are different, and Figure 16A The compensation unit shown provides a compensation capacitor smaller than 1000. Figure 16B The compensation capacitor provided by the compensation unit shown.

[0100] like Figure 15 As shown, for different first grid lines, since the space available for the second compensation unit differs at positions A and B, different types of compensation units are provided to ensure compensation consistency, such as... Figure 16A and Figure 16BAs shown. If the space is large and the compensation is sufficient, more settings can be configured. Figure 16A The compensation units shown are used to fill the space. The number of various compensation units can be reasonably arranged according to actual needs to obtain the desired compensation capacitance. In addition, the desired compensation capacitance can also be obtained by adjusting the area of ​​the first sub-compensation unit 105 and / or the second sub-compensation unit 305, and / or by adjusting the thickness of the dielectric layer.

[0101] like Figure 16A and Figure 16B As shown, in order to ensure an appropriate aperture ratio so that sufficient UV light can be transmitted to cure the frame adhesive, openings can be made in the first sub-compensation unit 105 and / or the second sub-compensation unit 305.

[0102] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The compensation structure includes a second compensation unit, which includes a first sub-compensation unit 105 formed on the Gate layer 100 and / or a second sub-compensation unit 305 formed on the SD layer 300. The desired compensation capacitance can be obtained by adjusting the number of the first sub-compensation units 105 and / or the second sub-compensation units 305, the area of ​​the first sub-compensation units 105 and / or the second sub-compensation units 305, and the thickness of the dielectric layer, thereby providing different compensation capacitances for different first gate lines, so that the compensated load (i.e., the product of the compensated capacitance and resistance) on each first gate line is consistent.

[0103] Figure 17 Another layout schematic diagram of a display panel near position C according to an embodiment of the present disclosure is shown.

[0104] According to embodiments of this disclosure, the compensation structure may include a data line extension 360 formed in the SD layer 300. For example... Figure 17 As shown, it is possible to Figure 1 At position C shown, the data line in the SD layer 300 is extended beyond the AA area to form a data line extension portion 360, so as to form an overlapping capacitance with the gate fan-out line 120' formed in the Gate layer 100. The dielectric layer between them includes the GI layer (not shown in the diagram). Figure 17 (as shown in the image).

[0105] like Figure 17 As shown, the data lines disposed in the SD layer 300 may include touch data lines and display data lines. Each touch data line and the three display data lines between two adjacent touch data lines extend beyond the AA area to form a data line extension portion 360.

[0106] According to embodiments of this disclosure, the line width of the data line extension portion 360 can be widened to increase the overlapping area. In some embodiments, each data line extension portion 360 is larger than the line width of the data line in the corresponding AA area. For example, the data line extension portion 360 formed by the touch data line extending outside the AA area is larger than the line width of the touch data line.

[0107] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The compensation structure includes a data line extension portion 360 formed in the SD layer 300. By forming an overlapping capacitance between the data line extension portion 360 and the gate fan-out line 120' of the Gate layer 100, the capacitance on the first gate line can be compensated. In addition, the capacitance on the data line can also be compensated.

[0108] Figure 18 A comparative schematic diagram of the display panel before and after compensation according to an embodiment of the present disclosure is shown.

[0109] See Figure 18 The graph shows the percentages before and after compensation on the vertical axis, and the number of compensation grid lines in the irregular region on the horizontal axis. Before compensation, the capacitance at the U-slot position is 40% to 60% of the capacitance at the normal position, the resistance at the U-slot position is 130% to 150% of the resistance at the normal position, and the load R*C at the U-slot position is 60% to 90% of the load R*C at the normal position. After compensation, the capacitance at the U-slot position is 70% to 80% of the capacitance at the normal position, the resistance at the U-slot position is 120% to 130% of the resistance at the normal position, and the load R*C at the U-slot position is 85% to 100% of the load R*C at the normal position.

[0110] It should be recognized that, although in Figure 17 Only those shown in Figure 1 The compensation structure shown at position C compensates for the capacitance on the first gate line, but the ITO layer 500 can also be formed to completely cover it. Figure 1 The grid lines (or grid fan-out lines) at positions A and B are shown to increase the compensation capacitance.

[0111] The present disclosure provides a method for manufacturing a display panel, the display panel including a first region 10 (i.e., an irregular region) and a second region 20 (i.e., a normal region), wherein the number of pixels corresponding to each gate line in the first region 10 is less than the number of pixels corresponding to each gate line in the second region 20.

[0112] Figure 19 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure is shown.

[0113] like Figure 19As shown, the method includes step S100, in which a compensation structure is prepared, the compensation structure including a first electrode plate, the first electrode plate at least partially overlapping the orthographic projection of the second portion on the substrate.

[0114] According to embodiments of this disclosure, the display panel includes a Gate layer, a GI layer, an SD layer, a PVX layer, and an ITO layer stacked sequentially, and the manufacturing method further includes: transferring the gate lines located on the Gate layer to the SD layer.

[0115] According to an embodiment of the present disclosure, transferring a gate line located in the Gate layer to the SD layer includes: forming a transfer unit using an ITO layer to transfer the gate line located in the Gate layer to a gate line fan-out line in the SD layer.

[0116] According to embodiments of this disclosure, the manufacturing method further includes: arranging dummy pads between adjacent gate fan-out lines, the dummy pads being disposed in the Gate layer and / or SD layer.

[0117] According to an embodiment of this disclosure, the manufacturing method further includes: forming an outer ring electrode in the Gate layer, wherein the outer ring electrode in the Gate layer and the gate fan-out line in the SD layer form an overlapping capacitance.

[0118] According to an embodiment of the present disclosure, the manufacturing method further includes: forming a first compensation unit between two adjacent gate line fan-out lines in the SD layer, wherein the formed first compensation unit is connected to one of the gate line fan-out lines.

[0119] According to an embodiment of this disclosure, the manufacturing method further includes: forming an outer ring electrode in a Gate layer at a position corresponding to the first compensation unit in the SD layer, and connecting it to the ITO layer through a PVX hole.

[0120] According to an embodiment of the present disclosure, the manufacturing method further includes: forming a second compensation unit between two adjacent gate lines, and connecting the formed second compensation unit to one of the gate lines.

[0121] According to an embodiment of the present disclosure, forming a second compensation unit between two adjacent gate lines includes: forming a first sub-compensation unit in the Gate layer, wherein the first sub-compensation unit is connected to the gate line, and forming a capacitor between the first sub-compensation unit and the ITO layer.

[0122] According to an embodiment of the present disclosure, forming a second compensation unit between two adjacent gate lines further includes: forming a second sub-compensation unit in the SD layer, and forming a capacitor between the first sub-compensation unit and the second sub-compensation unit.

[0123] According to embodiments of this disclosure, the manufacturing method further includes: forming a data line extension in the SD layer to form an overlapping capacitance with a gate fan-out line in the Gate layer.

[0124] The method for manufacturing a display panel according to the embodiments of this disclosure can be used to manufacture display panels according to the various embodiments of this disclosure. Technical details can be referenced in conjunction with the provided methods. Figures 2 to 18 The various embodiments described herein will not be repeated here.

[0125] Figure 20 A block diagram of a display device according to the present disclosure is shown.

[0126] Embodiments of this disclosure provide a display device including a display panel according to various embodiments of this disclosure.

[0127] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A display panel, the display panel comprising a substrate, and a first region and a second region located on the substrate, the display panel further comprising a plurality of pixels, in, The first region includes multiple first gate lines, and the second region includes multiple second gate lines. The number of pixels connected by the first gate lines is less than the number of pixels connected by the second gate lines. Each first gate line includes a first portion disposed in the effective display area and a second portion disposed in a non-display area outside the effective display area. The first portion and the second portion are electrically connected to each other. The display panel further includes a compensation structure, which comprises a first electrode plate that at least partially overlaps with the orthographic projection of the second portion onto the substrate. The display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially, wherein the first gate line and the second gate line are formed in the gate line layer. The compensation structure includes a second compensation unit, which is formed between two adjacent first gate lines and connected to one of the first gate lines. The second compensation unit includes a first sub-compensation unit disposed in the gate line layer. The first sub-compensation unit is connected to a first gate line in the gate line layer, and the first sub-compensation unit at least partially overlaps with the orthographic projection of the conductive layer on the substrate.

2. The display panel according to claim 1, wherein, The first portion is disposed in the gate layer, and the second portion is disposed in the source / drain layer.

3. The display panel according to claim 2, wherein, The first gate line also includes a third portion disposed in the conductive layer. The third portion is connected to the first portion disposed in the gate layer via a through-hole passing through the second insulating layer and the first insulating layer, and The third part is connected to the second part disposed in the source / drain layer via a through-hole passing through the second insulating layer.

4. The display panel according to claim 3, wherein, The compensation structure includes a first outer ring electrode disposed in the conductive layer. The first outer ring electrode is disposed in a non-display area outside the effective display area of ​​the display panel. The first electrode plate includes the first outer ring electrode, and the first outer ring electrode at least partially overlaps with the orthographic projection of the second portion disposed in the source / drain layer onto the substrate. The first outer electrode is disconnected from the third portion disposed in the conductive layer, and The first outer ring electrode is disconnected from the electrode in the conductive layer in the effective display area.

5. The display panel according to claim 4, wherein, The compensation structure further includes a second outer ring electrode disposed in the gate line layer. The second outer ring electrode is disposed in a non-display area outside the effective display area of ​​the display panel, and the second outer ring electrode at least partially overlaps with the orthographic projection of the second portion disposed in the source / drain layer onto the substrate. The second outer ring electrode is connected to the first outer ring electrode via a through-hole passing through the second insulating layer and the first insulating layer.

6. The display panel according to claim 4, wherein, The compensation structure further includes a first compensation unit disposed in the source-drain layer, and the second portion disposed in the source-drain layer is a gate fan-out line. The first compensation unit is formed between two adjacent grid line fan-out lines and is connected to one of the grid line fan-out lines. The first outer electrode and the orthographic projection of the first compensation unit on the substrate at least partially overlap.

7. The display panel according to claim 6, wherein, The compensation structure also includes a third outer ring electrode disposed in the gate line layer. The third outer ring electrode is located in the non-display area outside the effective display area of ​​the display panel. The third outer electrode at least partially overlaps with the orthographic projection of the first compensation unit onto the substrate, and The third outer ring electrode is connected to the first outer ring electrode via a through-hole passing through the second insulating layer and the first insulating layer.

8. The display panel according to claim 7, wherein, Both the first compensation unit and the third outer ring electrode have a mesh shape, and the third outer ring electrode overlaps with the orthographic projection of the first compensation unit on the substrate.

9. The display panel according to claim 2 further includes a dummy pad. The dummy pads are arranged between adjacent second portions and are disposed in the gate layer and / or the source / drain layer.

10. The display panel according to claim 1, wherein, The first sub-compensation unit includes a plurality of first sub-compensation units, and the overlap area of ​​at least one of the plurality of first sub-compensation units with the orthographic projection of the conductive layer on the substrate is different from the overlap area of ​​the other first sub-compensation units with the orthographic projection of the conductive layer on the substrate.

11. The display panel according to claim 1, wherein, The second compensation unit further includes a second sub-compensation unit disposed in the source / drain layer, and the orthographic projections of the first sub-compensation unit and the second sub-compensation unit on the substrate at least partially overlap.

12. The display panel according to claim 11, wherein, The first sub-compensation unit includes a plurality of first sub-compensation units, and the second sub-compensation unit includes a plurality of second sub-compensation units. The overlap area of ​​the orthographic projection of at least one of the plurality of first sub-compensation units and at least one of the plurality of second sub-compensation units on the substrate is different from the overlap area of ​​the orthographic projection of the other first sub-compensation units and the other second sub-compensation units on the substrate.

13. The display panel according to claim 11, wherein, The second sub-compensation unit is connected to the conductive layer via a through-hole passing through the second insulating layer.

14. The display panel according to claim 1, wherein, The first sub-compensation unit includes multiple first sub-compensation units, and the first gate line includes multiple first gate lines, wherein at least one of the multiple first gate lines connects to a different number of first sub-compensation units than the other first gate lines connect to.

15. The display panel according to claim 1, wherein, Data lines are formed in the source and drain layers. The compensation structure includes a data line extension portion disposed in the source / drain layer. The data line extension extends from the data line to the non-display area of ​​the display panel and at least partially overlaps with the orthographic projection of the second portion disposed in the gate layer onto the substrate.

16. The display panel according to claim 15, wherein, The width of the extended portion of the data line is greater than the width of the data line itself.

17. A method for manufacturing a display panel, for manufacturing a display panel according to any one of claims 1 to 16, the method comprising: A compensation structure is prepared, the compensation structure including a first electrode plate, the first electrode plate at least partially overlapping the orthographic projection of the second portion on the substrate.

18. A display device comprising a display panel according to any one of claims 1 to 16.

Images