Apparatus, assembly and system for operating hardware-based artificial neural network, and method for training same

Abstract

The invention relates to an apparatus for operating a hardware-based artificial neural network, said apparatus comprising at least one hardware-based artificial neural network (11, 24, 32, 41, 51, 71, 81, 101, 111, 121, 131, 171), characterized in that said apparatus comprises at least one interference device (12, 22, 35, 42, 52a, 52b, 72, 82, 102, 112, 122, 132, 172) and at least one coupling device (15, 23, 34, 43, 53a, 53b, 73, 83, 103, 113, 123, 133, 173), the interference device is used for coupling at least one interference signal into at least one region of the hardware-based artificial neural network, and the coupling device is located between the interference device and the hardware-based artificial neural network and is designed to transmit the at least one interference signal from the interference device to the at least one region. The invention also relates to a method for training the device. The present invention provides an improved hardware-based artificial neural network that exhibits improved performance.

Description

Technical Field

[0001] The present invention relates to an apparatus, an arrangement and a system for operating a hardware-based artificial neural network, and a method for training the artificial neural network. Background Art

[0002] Artificial intelligence can be used to detect patterns in technical applications, such as image recognition or monitoring machine parameters. Artificial neural networks that mimic the function of biological neurons can provide artificial intelligence. These artificial neural networks can be trained with training data using evolution-based methods, where the training adjusts the artificial neural network, thereby improving its ability to perform its tasks. In each training iteration, the individual elements of the artificial neural network are reconnected.

[0003] In principle, such a system can be implemented as a hardware-based system, i.e. the hardware physically forms the network, and as a software-based system, in particular a virtual network, which is simulated or emulated on a piece of hardware, such as a RAM memory and / or a processor. In a hardware-based system, modifiable electronic components are linked together to form the artificial neural network. Dozens of linked components can be removed without the system losing its performance. Furthermore, a hardware-based artificial neural network may have elements that are not connected to the rest of the network, i.e. unconnected and unused elements, which cannot be removed without degrading or losing the performance of the hardware-based artificial neural network.

[0004] To reduce this effect, for example, Cramer, B., D., Kreft, M., Wibral, M., Schemmel, J., Meier, K., & Priesemann, V. Control of criticality and computation inspiking neuromorphic networks with plasticity, Nature Communications, 11(1) (2020) 2853, to achieve the highest possible signal-to-noise ratio between linked elements, as this allows the number of subcomponents to reach thousands and the number of evolvable links to reach tens of thousands.

[0005] Compared to software-based artificial neural networks, current hardware-based artificial neural networks have a much more limited number of components and connections, are less trainable, and have lower complexity and flexibility. Summary of the invention

[0006] It is therefore an object of the present invention to provide an improved hardware-based artificial neural network with which the above-mentioned disadvantages are eliminated.

[0007] This object is achieved by the features of the independent claim. Advantageous developments are the subject matter of the dependent claims and the following description.

[0008] According to a first aspect, the invention relates to an apparatus for operating a hardware-based artificial neural network, the apparatus comprising at least one hardware-based artificial neural network. The apparatus provided according to the invention comprises at least one jamming device for injecting at least one jamming signal into at least one area of ​​the hardware-based artificial neural network and at least one coupling device, the jamming device being arranged between the jamming device and the hardware-based artificial neural network and being designed to transmit the at least one jamming signal from the jamming device to the entire area of ​​the at least one area.

[0009] Hardware-based artificial neural networks are understood to include both biologically-based neural networks, in which the nodes generally have comparable properties (weights, transfer functions, etc.) and are arranged in layers, and electronic circuits, in which the nodes of the network have different digital and / or analog circuit elements, which is different from biologically-based neural networks. These can also not take the form of layers like biologically-based networks, but can be randomly connected like electronic circuits, so that in some of the circuit elements, for example, a port provided as an output can be used as an input, and vice versa. From the current electronics point of view, this may cause the overall circuit to become "dumb", which acquires "intelligence" through training. Therefore, hardware-based artificial neural networks can also be called trainable electronic networks. Circuit elements can also constitute nodes of the corresponding network. Hardware-based artificial neural networks can also be called physical neural networks.

[0010] Unlike software-based ANNs, where the output of each node in a layer of the network is determined sequentially, the output of the nodes of hardware-based ANNs are obtained simultaneously for all nodes in the layer. This means that, in software-based ANNs, the number of nodes affects the time required to calculate the output of the ANN. However, in hardware-based ANNs, the number of nodes in a layer does not have any effect on the time required to determine the output. Only the number of layers determines the time required to determine the output data.

[0011] The present invention provides a device for operating a hardware-based artificial neural network, in which an interference signal is injected into at least one area of ​​the hardware-based artificial neural network. The interference signal is injected into the entire area, that is, the interference signal exists in the entire area, or the area corresponds to the area of ​​the hardware-based artificial neural network covered by the interference signal. At least one area can be smaller than the entire hardware-based artificial neural network. In addition, the device has an interference device, which can inject interference signals into the hardware-based artificial neural network. In order to inject the interference signal, a coupling device is provided between the interference device and the hardware-based artificial neural network. In one example, the coupling device may simply include an air-filled space between the interference device and the hardware-based artificial neural network. The interference signal emitted by the interference device is transmitted to at least one area through the coupling device and injected into it. The injection of the interference signal causes an increase in noise in at least one area, thereby reducing the signal-to-noise ratio during the transmission of signals between elements (e.g., nodes) of the hardware-based artificial neural network. Contrary to all efforts made to implement electronic circuits, contrary to intuition, instead of increasing the signal-to-noise ratio in at least one area of ​​the hardware-based artificial neural network, the signal-to-noise ratio is reduced spatially and / or temporally and / or partially. This reduction is limited to at least one area where the interference signal is injected, that is, to certain electronic components of the hardware-based artificial neural network circuit. The signal-to-noise ratio (S / N) is defined as follows: S / N=10*log(useful power / noise), expressed in decibels (dB), or S / N=20*10*log(useful signal voltage / noise signal voltage). The S / N of easily transmittable signals is greater than 15dB, and an S / N less than 10dB is considered high noise. If the useful signal power is equal to the noise signal power, the receiver can no longer recognize the signal. Surprisingly, the performance of the hardware-based artificial neural network trained with the injected interference signal is improved. Since the training is carried out using the injected interference signal, the normal operation of the hardware-based artificial neural network is also achieved by injecting the interference signal. Improving performance is understood to mean, among other things, correctly performing the recognition of a pattern (such as an image or speech) with an increased probability without increasing the number of nodes in the network. Therefore, an improved hardware-based artificial neural network is provided, in which the above-mentioned disadvantages of the prior art are eliminated.

[0012] According to one example, a hardware-based artificial neural network in at least one area can have at least one component designed to reduce the signal-to-noise ratio when receiving at least one interference signal, wherein the interference device preferably generates an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal and / or ionization interference signal.

[0013] The signal-to-noise ratio is reduced by increasing the noise in the component. To this end, the component can be designed to be sensitive to the interference signal. For example, if an optical interference signal is used, the noise in the component can be increased during the transmission of the electronic signal in the component.

[0014] According to yet another example, the jamming device may have a plurality of individually actuatable jamming elements for injecting jamming signals into the hardware-based artificial neural network, wherein the jamming elements preferably inject the jamming signals into different regions of the hardware-based artificial neural network.

[0015] Therefore, multiple regions of the hardware-based artificial neural network, preferably the entire hardware-based artificial neural network, can be affected by the interference signal. Since the interference elements can be controlled independently of each other, each region in the hardware-based artificial neural network can be affected by its own interference signal separately. These regions can overlap and / or be separated from each other.

[0016] Further, a plurality of interfering elements may be arranged distributed over a layer, for example preferably in the form of an array, wherein the coupling device comprises a medium having a plurality of coupling elements for transmitting at least one interfering signal into at least one region, the coupling elements being distributed in the layer like the interfering elements.

[0017] Therefore, the interference element can be used to generate an interference signal pattern, which is correspondingly transmitted to the hardware-based artificial neural network through a coupling device with a coupling element. Since the distribution of the interference elements in the layer is known, specific areas in the hardware-based artificial neural network can be targeted with interference signals. Specifically, the distribution of the interference elements in the layer can be designed so that the arrangement of the interference elements is similar to the components of the neural network. This allows specific interference signals to be injected into individual components.

[0018] Furthermore, at least some of the plurality of interfering elements can be designed as resistive heaters, Peltier elements, light emitting diodes, electromagnetic radiators and / or transmitters, and / or piezoelectric components.

[0019] In another example, at least one region may have a range corresponding to a size of the hardware-based artificial neural network, or be designed to be smaller than the size of the hardware-based artificial neural network.

[0020] If the extent of at least one area is the same as the extent of the hardware-based artificial neural network, the interference device or coupling device can be formed uniformly so that the interference signal is applied uniformly to the entire hardware-based artificial neural network. A more sophisticated structure can inject interference signals into different areas of the components, for example, only into the signal input or signal output of the circuit elements of the hardware-based artificial neural network. For example, if the extent of at least one area is equal to the extent of the components of the hardware-based artificial neural network, and each component is assigned an area, an independent interference signal can be injected into each component of the neural network.

[0021] Thus, the structure of the plurality of coupling elements may be identical to the structure of the plurality of interfering elements. Furthermore, the structure of the coupling elements may also correspond to the structure of the hardware-based artificial neural network. However, this does not exclude the possibility that the structure of the coupling elements is finer or coarser than the structure of the interfering elements or the hardware-based artificial neural network.

[0022] According to another example, the device may include at least one semiconductor chip, wherein the semiconductor chip includes a hardware-based artificial neural network, and the hardware-based artificial neural network is preferably formed in an integrated circuit, more preferably in a field programmable gate array (FPGA) or in an application specific integrated circuit (ASIC).

[0023] A neural network can be designed as a circuit on a semiconductor chip, where the nodes of the neural network can be formed as components of the circuit. In an example where the elements of the neural network are designed as components of a field programmable gate array, the field programmable gate array can be configured so that the circuit structure of the elements of the field programmable gate array forms a neural network. A hardware-based artificial neural network, also implemented in a field programmable gate array, can be further trained. In contrast, a hardware-based artificial neural network is hardwired on a dedicated integrated circuit and must be optimized in other ways beforehand.

[0024] It is also conceivable that the apparatus may include a shielding device for shielding external interference signals of the same type as the at least one interference signal, wherein the shielding device surrounds the hardware-based artificial neural network, the coupling device and the interference device.

[0025] For example, the shielding device can be designed as a housing, forming the housing of the device. Thus, the interfering device, the coupling device and the hardware-based artificial neural network are surrounded by the shielding device. The shielding device can screen out external interfering signals, which could change the signal-to-noise ratio in an uncontrolled and unreproducible manner. As a result, the interfering signals of the interfering device almost only lead to a change in the signal-to-noise ratio in the area of ​​the neural network.

[0026] In a second aspect, the present invention relates to an arrangement of multiple devices according to the aforementioned description, wherein the hardware-based artificial neural network of each device is electrically connected to each other in series and / or in parallel, wherein the interference device of at least a first device among the multiple devices and the interference device of a second device among the multiple devices are preferably designed as a common interference device, and the output layer of the hardware-based artificial neural network of a third device among the multiple devices is also preferably also designed to control the interference device of a fourth device among the multiple devices.

[0027] The advantages, effects and improvements of this arrangement derive from the advantages, effects and improvements according to the above-described device. In this respect, to avoid repetitions, reference is therefore made to the previous description.

[0028] According to the previous description, the arrangement includes at least two devices. In the arrangement, the output layer of the hardware-based artificial neural network of the first device is electrically connected to the input of the interference device including but not limited to the second device or multiple other devices. The first device can then control the interference device of the second device or affect its function. In this way, each device can be coupled to the interference device of other devices of the arrangement through the electrical connection of its neural network.

[0029] Furthermore, in a third aspect, the invention relates to a system comprising a plurality of arrangements according to the preceding description, wherein a first arrangement of the plurality of arrangements is designed to control at least one interference device in a second arrangement of the plurality of arrangements.

[0030] The advantages, effects and improvements of the system are derived from the advantages, effects and improvements of the above-mentioned devices and arrangements. In this respect, to avoid repetition, reference is therefore made to the previous description.

[0031] For example, the first arrangement may form a base layer, whose devices send out output signals, which are processed by the devices of the second arrangement, for example, as input signals after further processing. In this case, at least one interference device of the device of the second arrangement may be coupled to the output layer of at least one device of the first arrangement. This can be referred to as forward coupling. It is further envisaged that at least one interference device of the device of the first arrangement may be coupled to the output layer of at least one device of the second arrangement. This can be referred to as backward coupling.

[0032] Furthermore, multiple systems can be considered as subsystems and combined into complex systems, where the subsystems are coupled to each other in the manner described above. In this way, more complex systems can be formed with further improved performance. For example, such a complex system can process various signals (optically and acoustically), where one subsystem processes optical signals and another subsystem processes acoustic signals.

[0033] In a fourth aspect, the present invention relates to a method for training an artificial neural network in an apparatus according to the aforementioned description, the method comprising at least the following steps: defining target output data during processing of provided training data; feeding the training data into a hardware-based artificial neural network, and injecting at least one interference signal into at least one area of ​​the hardware-based artificial neural network through at least one interference device; obtaining output data from the hardware-based artificial neural network; determining whether there is at least one deviation between the output data and the target output data, the deviation being outside a predetermined tolerance range; if the deviation is within the tolerance range: terminating the method; and if the deviation is outside the predetermined tolerance range: modifying the hardware-based artificial neural network, and preferably modifying at least one interference signal, and repeating the above steps.

[0034] The advantages, effects and improvements of the method are derived from the advantages, effects and improvements of the above-described device. In this respect, reference is therefore made to the previous description in order to avoid repetition.

[0035] The method is used to train a hardware-based artificial neural network in a state disturbed by an interference device. Thus, the training of the neural network is carried out in a state where the signal transmission is disturbed in at least one area, in which an interference signal is injected. During each training process, in addition to the changes to the hardware-based artificial neural network, at least one injected interference signal is also changed. To this end, at least one parameter of at least one interference signal can be changed, such as intensity, frequency, duration, etc. Changing at least one parameter also changes at least one interference signal. In this way, the interference device can therefore be integrated into the training of the neural network. Therefore, using this method, a trained hardware-based artificial neural network can be provided, which has a higher performance than a neural network without the injection of interference signals.

[0036] According to an example, by injecting an interference signal, a signal-to-noise ratio of no greater than 15 dB, preferably no greater than 10 dB, and further preferably no greater than 0 dB can be generated in at least one area.

[0037] Typically, the signal-to-noise ratio of an easily transmittable signal is greater than 15 dB. A signal-to-noise ratio of less than 10 dB is considered high noise. If the useful signal power is equal to the noise signal power, the signal cannot be recognized at the receiver. Nevertheless, the neural network can in principle also detect patterns in the noise when the signal-to-noise ratio is 0 dB or lower, so that even if the signal is no longer recognizable, the output of subsequent nodes of the neural network will still be affected. The signal-to-noise ratio can also be less than 0 dB, preferably at least -40 dB, more preferably -15 dB, and further preferably -10 dB.

[0038] It is also conceivable that, prior to the step of defining target output data during processing of provided training data, for example, a hardware-based artificial neural network may be trained without injecting interference signals.

[0039] This means that, as is known in the prior art, a neural network can first be trained to obtain an initial performance, such as a first accuracy value for recognizing certain patterns. By subsequent additional training with the injection of interference signals, the initial performance can be surpassed, wherein, for example, a second accuracy value for detecting a specific pattern is greater than the first accuracy value.

[0040] According to another example, at least one interference device may have at least a plurality of individually actuatable interference elements, wherein each interference element is designed to inject an interference signal into a hardware-based neural network, wherein each interference element preferably injects the interference signal into a different area of ​​the hardware-based artificial neural network, and the plurality of actuatable interference elements may be actuatable in such a manner that the interference signal forms a predetermined interference signal pattern above the hardware-based artificial neural network, wherein multiple training iterations of the hardware-based artificial neural network are preferably executed sequentially with different predetermined interference signal patterns.

[0041] For example, predetermined interference signal patterns can be used for initial training iterations. In subsequent training runs, interference signal patterns can be changed by changing single or multiple activities in individually actuable interference elements, such as by reducing or increasing signal strength. Due to the predetermined interference signal patterns that can be initially injected, training can be accelerated by using interference signal patterns that have been classified as suitable. In addition, predetermined interference signal patterns can also be used unchanged throughout the training.

[0042] According to a fifth aspect, the present invention relates to a method for training an artificial neural network in an arrangement according to the aforementioned description, wherein a method for training an artificial neural network in a device according to the aforementioned description is applied to a hardware-based artificial neural network of the device, preferably after the device has been trained separately outside the arrangement by the method for training an artificial neural network in a device according to the aforementioned description.

[0043] Advantages, effects and improvements of the method for training an artificial neural network in an arrangement result from the above-described apparatus, arrangement and additional advantages, effects and improvements of the previously described method. In this respect, reference is therefore made to the previous description to avoid repetitions.

[0044] Using the method for training an artificial neural network in an arrangement, it is possible to train all the devices of the arrangement to match each other, thereby improving the performance of the arrangement. To this end, the devices in the arrangement can be trained together from the beginning. Alternatively, each device can be trained separately first, wherein no corresponding interfering signal device is affected by the output signal of another device. Only in the second training run, the devices of the arrangement are matched to each other, and the interfering device can be affected by the output signal of other devices of the arrangement.

[0045] In a sixth aspect, the present invention relates to a method for training an artificial neural network in a system according to the preceding description, wherein the method for training an artificial neural network in an apparatus according to the preceding description is applied to a hardware-based artificial neural network of the apparatus, preferably after the arrangement has been separately trained outside the system by the method for training an artificial neural network in an arrangement according to the preceding description.

[0046] Advantages and effects and improvements of the method for training an artificial neural network in a system result from the advantages and effects and improvements of the above-mentioned apparatus, arrangement, system and other aforementioned methods. In this respect, in order to avoid repetition, reference is therefore made to the previous description.

[0047] In a method for training an artificial neural network in a system, different arrangements of the system are coordinated with each other. In this case, the arrangement can be initially trained separately without the devices of other arrangements affecting the interfering signal devices. In addition, in this case, before the arrangement is trained, the devices of the arrangement can be trained separately from each other without being affected by the interfering devices of other arrangements. Alternatively, in a single training of the system, the arrangement and the devices it contains can be matched with each other, wherein the output signal of the arrangement can affect the interfering devices of other arrangements. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the following, the present invention is described using exemplary embodiments with reference to the accompanying drawings, in which:

[0049] Figure 1A and 1B A schematic diagram of the device is shown;

[0050] Figure 2A and 2B Shown according to Figure 1A and 1B A schematic diagram of the device with more details;

[0051] Figure 3 A schematic diagram showing an example of a device having an FPGA chip;

[0052] Figure 4A and 4B Shown according to Figure 3 A schematic diagram of yet another embodiment of an example of;

[0053] Figure 5 A schematic diagram showing an example of an apparatus having two jamming devices;

[0054] Figure 6 A schematic diagram showing the basic structure of an FPGA chip;

[0055] Figure 7 A schematic diagram showing an example of an apparatus having a capacitive interference element;

[0056] Figure 8 A schematic diagram showing an example of an apparatus having a heating and cooling interference element;

[0057] Fig. 9 A schematic diagram showing an example of a device having a heating interference element;

[0058] Fig.10 A schematic diagram showing an example of a device having a sound-generating interference element;

[0059] Fig.11 A schematic diagram showing an example of an apparatus having an interfering element emitting electromagnetic radiation;

[0060] Fig.12 A schematic diagram showing an example of an apparatus having a pattern generating interference signal;

[0061] Fig.13 A schematic diagram showing an arrangement with a plurality of devices is shown;

[0062] Fig.14 A schematic diagram of a system having multiple devices is shown;

[0063] Fig.15 A schematic diagram showing another example of a system in an alternative schematic mode;

[0064] Fig.16 A schematic diagram showing an example of a plurality of systems interconnected by an interfering device is shown;

[0065] FIG17 is a schematic diagram showing yet another example of an arrangement of the device;

[0066] Fig.18 A flow chart of a method for training an artificial neural network in a system is shown. DETAILED DESCRIPTION

[0067] Figure 1A and 1B The device is shown, and the following will be further described: Figure 1A Shows the spatial arrangement of the device; Figure 1BA cross-sectional view of the main components of the device is shown. This example shows an FPGA chip, located on a control circuit board 13, whose individual components are linked by an evolutionary learning process, configured and trained to form a hardware-based artificial neural network 11. The layers of this hardware-based artificial neural network 11 largely correspond to industrially available chip-based systems and activation mechanisms that have been described in the prior art.

[0068] In the following, the term "FPGA" is used to denote all freely configurable electronic semiconductor chips. At a distance d, as will be described in more detail in the following examples, a further layer with an optional array-like structure is arranged as a jamming device 12, whose elements are shown here as small spheres and can be switched on / off or adjusted in a controlled manner as jamming elements. Actuating elements are not shown here.

[0069] The layer of this interference device 12 can generate interference signals in the form of a pattern and is called an "interference signal layer". It or its elements can generate interference signals and be cross-coupled into the layer of the hardware-based artificial neural network 11 through the partial space of the coupling device 15, and locally injected into at least one area of ​​the hardware-based artificial neural network 11, and the interference signal will be injected into the entire area. Therefore, this area corresponds to the area covered by the interference signal in the hardware-based artificial neural network 11. This area can cover the entire network, that is, the interference signal is injected into the entire network. This can be implemented uniformly. In addition, if, for example, multiple areas are provided, the range of the area can be allocated to groups of components of the FPGA, separate single components, or only to sub-areas of single components.

[0070] Suitable jammer array components may be micro-heating or cooling elements, optical, acoustic, resistive, electromagnetic, capacitive, mechanical or even quantum mechanical components. Any substance that can be injected into an electronic circuit, as implemented in the layers of a hardware-based artificial neural network 11, is applicable.

[0071] Through the coupling device 15, also referred to as the "coupling space" below, the signal generated in the interference device 12 can be cross-coupled as a pattern into the layer of the hardware-based artificial neural network 11. Corresponding to the elements of the layer of the interference device 12, the coupling device 15 can be a medium, for example, it transmits thermal, resistive, electromagnetic, capacitive, mechanical or even quantum mechanical signals. In the simplest case, it can be a uniform medium, such as a gas, liquid or solid. However, in general, the medium can include a combination of vertical and / or horizontal directions of different materials to achieve local effects in the layer direction of the hardware-based artificial neural network 11 and adapt to their array structure, that is, the medium of the coupling device 15 can be adapted to adapt the arrangement of the linkable elements of the FPGA chip to the hardware-based artificial neural network. The distance d can also be adjusted, but it will usually be selected to be small relative to the surface area of ​​the layer of the hardware-based artificial neural network 11, so that local effects can be generated in the hardware-based artificial neural network 11, especially in the FPGA chip.

[0072] Unlike the use of conventional semiconductor chips and semiconductor components, the components at the level of the hardware-based artificial neural network 11 may be partially but not completely shielded from external influences, so that injection can only come from the level of the interfering device 12.

[0073] Therefore, due to the increased sensitivity of the components of the hardware-based artificial neural network 11 to external signals, the packaging of the device can be provided as a shielding device 14 specifically for shielding these interfering signals.

[0074] In the basic arrangement of the hardware-based artificial neural network 11 according to the present invention, the main components of the evolutionary learning process are the layers of the hardware-based artificial neural network 11. The layers of interference devices 12 form a higher-level but secondary component, which makes this process of the layers of the hardware-based artificial neural network 11 more complex and can also be optimized by the or second evolutionary algorithm and learning process. The overall units 11 to 15 can be understood and referred to as intelligent hardware AI systems and can also be referred to as AI basic units.

[0075] The training process can be performed in two variants. In a first alternative, the hardware-based artificial neural network 11 and the jamming device 12 can be modified simultaneously during the evolution process. In a second alternative, first only the hardware-based artificial neural network 11 can be trained, and if this training shows positive results, the jamming device 12 can be added. If the device comprises more than one hardware-based artificial neural network 11 and more than one jamming device 12, any combination of separate or joint training can be performed according to the first or second alternative.

[0076] By avoiding undefined interference effects, clear separation of interference signals by the interference device 12 and the coupling device, highly complex systems are achievable and controllable, and the likelihood of achieving positive training results is increased compared to prior art systems.

[0077] Figure 2A and 2B An example of explaining spatial relationships is shown. Figure 2A shows a three-dimensional exploded view, and Figure 2B Shown along Figure 2A Cross-section view along the mid-SS line.

[0078] The FPGA chip 24, in which a hardware-based artificial neural network is implemented, can be arranged on a board 21, such as a multi-layer PCB board, for actuating and configuring the FPGA through a port 26. The configuration can be implemented by a digital computer. The FPGA 24 is not encapsulated in a shielded manner, but can be covered and replaced by a coupling medium 23 of a coupling device, followed by an interference device 22, which is shown here in an array form, in a checkerboard pattern, with individual interference elements for local generation of interference signals of the FPGA forming a checkerboard pattern. The interference device 22 is in turn connected to the board 25 through a port 27 for actuating the interference element. In the simplest case, any pattern can be generated by switching the interference elements of the interference device on and off, which act locally on the FPGA chip 24 through the coupling medium 23.

[0079] In this example, about Figure 1A The distance d in the FPGA chip 24 is smaller than the surface area. Usually, the distance is between 0.1 mm and 5 mm, preferably 0.5 mm. The geometric relationship can be Figure 2B Seen in the SS section.

[0080] For example, an array of jammers 22 may include small heating elements or Peltier elements structured through a medium 23 with high thermal conductivity, such as a metal or diamond layer coupled. The layer may be structured as an array of columns with good and poor thermal conductivity to transfer the temperature pattern to the FPGA. This allows the generation of variable, trainable and switchable jammer signal patterns.

[0081] The first level of structuring of the jammer (structured measure of the distribution of the jammer elements) can be adapted to the structuring of the FPGA, which can be specified in this example by the second level of structuring, i.e., by selecting geometric similarity. Then, in each area, the jammer injects the jammer signal into the hardware-based artificial neural network, which is implemented in the FPGA and arranges the basic elements of the FPGA. In other words, each jammer element then controls one basic element of the FPGA.

[0082] However, this is not necessary, since the first degree of structuring can be structured more finely or more coarsely just as well as the second degree of structuring, the ratio of the first degree of structuring to the second degree of structuring preferably being in the range 10:1 for finer structures to 0.1:1 for coarser structures.

[0083] The coupling medium 23 of the coupling device can have a structure which is specified by a third degree of structuring. The third degree of structuring can also be structured more finely or more coarsely as well as the second degree of structuring.

[0084] Figure 3 Shows Figure 1A and 1B A compact technical arrangement of the device described in . In a semiconductor chip holder (hoder) 31, for example a ceramic with a plurality of contact pads, an FPGA chip 32 can be arranged with a linkable electronic basic component 33. In addition, a coupling medium 34 and a jamming device 35 with an array of jamming elements can be arranged directly thereon.

[0085] The whole chip can then be encapsulated 36 to shield it from external influences. In the case of electromagnetic components in the jammer, the encapsulation can be, for example, a metal encapsulation, or in the case of optical jammers, an opaque coating.

[0086] This compact chip design allows such chips to be combined on one board to form complex structures or even stacked, as explained in the example below. Such a chip can be used to assemble multiple AI basic units and combine them into a hierarchical structure.

[0087] Figure 4A and 4B An example combination of a compact chip system is schematically shown. Figure 4A Shown according to Figure 3 The device as an AI basic unit comprises an FPGA 41, a coupling medium 43 of a coupling device, and an interference device 42 having an electrical contact pad 44. The thickness of the coupling medium can vary between 100 microns and 5 millimeters, preferably from 200 microns to 600 microns. In addition, the coupling medium can have multiple coupling elements, which can be structured or unstructured according to a third structuring degree. In particular, structuring of the coupling medium is provided for the use of signal patterns.

[0088] exist Figure 4B In FIG. 4 , two devices are shown combined together. The combination of the two devices has two FPGAs 41, which are connected to a common interference device 42 via two coupling media 43. The FPGAs are aligned head to head.

[0089] In a similar manner, more combinations can be realized as horizontal or vertical stacking.The advantage of a common jammer device for multiple FPGAs is reduced actuation complexity.

[0090] Furthermore, interference signal patterns can be generated which are either fixed in advance or have been optimized by evolution-based methods during training with the FPGA. Such systems also offer the advantage that the upper and lower FPGAs can be exposed to different interference signal patterns in a temporally separated sequence or alternately, thus enabling more complex training and more complex AI systems with lower switching complexity.

[0091] Figure 5 Another variant is shown. In this example, the FPGA 51 is arranged between two coupling media 53a and 53b and two interfering signal layers 52a and 52b. This leads to a variety of options for injecting interfering signals with increased device complexity but well defined.

[0092] For example, it is possible to provide for symmetrically injecting the same interference signal pattern into the center of the FPGA chip from above and below. Or, for example, it is possible to provide for asymmetrically injecting the same or different interference signal patterns into the FPGA chip. Alternatively, for example, injections separated in time from above and from below can be performed. In addition, for example, alternating injections of asymmetrical interference signals from above and below can be provided.

[0093] Figure 6 The basic principle and basic structure of the FPGA chip array are schematically shown. Since FPGA is usually structured as an array, for ease of understanding, the representation of row 1 to row m and column 1 to column n is selected.

[0094] By means of four connections A, B, C, D, electronic basic components can be connected to each other in a short-circuit-proof configuration to form a hardware-based artificial neural network, whose positions can be identified by the indexes 11, 12, […], m5, mn. Even incorrect wiring connections, such as using the output of a component as an input, are permitted in the hardware-based artificial neural network.

[0095] As shown in the example, the basic elements at positions 11 to 15 in the top row of the array shown, the elements of the FPGA can be digital circuits as well as analog circuits. The symbols used correspond to the electronic nomenclature. It is also possible to mix analog and digital devices. These electronic components mn do not have anti-interference shielding as usual, but may have components that are sensitive to optical, acoustic, thermal, electromagnetic and other signals generated by the interference device. The type of configuration used for training and the evolution program are prior art and are therefore not explained in detail here.

[0096] Figure 7 In FIG. 5 , the three layers of the apparatus (hardware-based artificial neural network, coupling device and interference device) are shown with capacitive interference.

[0097] In this example, the FPGA 71 as a hardware-based artificial neural network has a second level of structuring that is finer than the first and third levels of structuring of the interference signal device 72 and the coupling device 73. The structuring of the FPGA, the interference device and the coupling device can be of the same type or of different types. Thus, not only a single basic element of the FPGA can be controlled, but also a group of basic elements or only a sub-region of a basic element can be controlled simultaneously.

[0098] The jammer device 72 may include, for example, a small metal plate or metal pad 72a as a jammer element, which is embedded in an electrically insulating medium 72b. Each pad 72a can be activated by a computer program in the same way as the operation of an FPGA. In the simplest example, three assignments for each pad are possible, as shown at 74: 1. Applying a positive or negative voltage Ux; 2. Open pad, i.e., no potential binding, where the pad finds its potential by itself in the chip environment; 3. Ground connection so that an arbitrary charge pattern can be generated in the array.

[0099] In the example shown, the coupling device 73 is structured in the same way so that under each metal pad, a material 73a with a high dielectric constant, embedded in a medium 73b with a low dielectric constant, can be arranged as a coupling element. Through the surface of the FPGA 71, these metal pads form local capacitances, through which displacement currents can be injected into each of the local adjacent areas of the hardware-based artificial neural network.

[0100] During the evolutionary training process, the allocation of the interference element 72a can be changed by an evolutionary algorithm, using a method similar to the training of a hardware-based artificial neural network. This means that at the beginning, a random allocation of the input signal can be generated and applied for the interference device 72. Then, the artificial neural network implemented in the FPGA can receive the input signal. If this is correctly interpreted by the neural network at the output, the configuration of the interference device 72 remains unchanged and the next training signal is applied to the FPGA. If the input signal is evaluated incorrectly, for example, the allocation of several pads or interference elements will be randomly changed, and the switching connection in the FPGA is in the same situation. The two algorithms can match, but they do not have to match. If this process is repeated hundreds to thousands of times, which can be called a "generation" in the evolutionary algorithm, the entire device can achieve the expected success rate.

[0101] Figure 8A 3-layer AI chip is shown, in which interference signals can be generated by an array of heating and / or Peltier elements 82, which in this case represent interference elements. The temperature can be transferred from the interference elements to the local basic elements of the FPGA 81 via coupling devices 83. The basic elements arranged as an array at positions 11 to mn of the FPGA can be manufactured as temperature sensitive elements according to standard semiconductor manufacturing methods, or designed in such a way that they react in signal behavior to small temperature differences, for example, a few degrees or fractions thereof.

[0102] The coupling device 83 in this example also comprises two parts: a cylindrical region 83a of high thermal conductivity and a region 83b of low thermal conductivity located therebetween. For example, the material 83a may be a metal such as copper or silver, or a diamond layer processed by semiconductor technology. The insulating material 83b may be a plastic material, glass or even a ceramic material of low thermal conductivity.

[0103] The jammer 82 in this example may have a plurality of heating and / or cooling elements, such as micro-resistance elements or Peltier elements, as jammer elements. In this way, an arbitrary temperature pattern can be passed to the FPGA below. The temperature difference can be selected within a wide range, for example between -20°C and 100°C, but preferably within a range close to room temperature or below.

[0104] Figure 8 The top center box 85 shows the structure of the AI ​​basic unit in a vertical cross-section SS. Here, the array structures of the layers of interference devices, coupling devices and neural networks do not have to match, that is, the number of interference elements and coupling elements can correspond to the number of basic electronic components, but does not necessarily correspond.

[0105] The temperature patterns generated are usually static, meaning they are constant during the working cycle of the neural network, which corresponds to a decision run. However, they can also vary dynamically across multiple decision runs of the FPGA.

[0106] The training process is similar to Figure 7 Description in .

[0107] exist Fig. 9 In the example, the device is shown only by an interference device having a heating element. Figure 7 and Figure 8 Structured as described in .

[0108] exist Fig.10 In FIG. 1 , a jamming device 102 is shown, which has miniature sound emitters as jamming elements, which emit sound signals of different frequencies, for example by vibration. The sound emitters can be piezoelectric elements, piezoelectric crystals or small diaphragms that generate individually activated sound patterns.

[0109] In this example, the coupling device 103 may include a sound transmitting region 103a, such as a mechanical solid state coupling or a miniature ultrasound probe, and a sound dampening intermediate space 103b, such as a sound absorbing material, such as a material with very small cavities.

[0110] The basic elements of FPGA 101 can be designed in a way that they can be disturbed to a certain extent by sound frequencies. For example, if the basic electronic elements of FPGA have sound receiving components, the effect can be strengthened and designed to be more complicated. Some or all basic elements of FPGA may have this situation. The advantage of the application of sound is its wide frequency range, which ranges from infrasound to ultrasound in the range of human hearing. This allows not only the generation of single frequency sound patterns, but also the generation of different frequency sound patterns.

[0111] This example graphically illustrates the expanded possibilities associated with introducing jamming devices and coupling devices into a hardware-based artificial neural network. As illustrated in the following figures, in an interconnected arrangement and system, each of these jamming devices can vary in intensity with a fixed sound pattern, the overall frequency can vary, the frequency composition / spectrum can be modified, the pattern can be changed, or a combination of these options can operate.

[0112] If it is assumed that the overall system of hardware-based artificial neural networks, interference devices and coupling devices has been optimized for a certain frequency mode and achieves the highest success rate in this actuation mode, then the modification / detuning of the interference signal will lead to worse results. In extreme cases, the neural network may only work in a certain intensity interval or frequency interval. This means that if the device has been operated in a sub-optimal way before, it may be possible to deteriorate or improve it simply by using interference signals. This leads to the possibility of interconnecting many devices in a hierarchical or even non-hierarchical way, so that the success rate of a neural network can be used to influence other hardware-based artificial neural networks connected to it through its interference signals.

[0113] Fig.11 An FPGA 111 is shown which comprises an artificial neural network of the type already described. In this example, the jamming element of the jamming device 112 can be a microtransmitter for emitting high-frequency electromagnetic waves up to the microwave range, which can be designed as an antenna, for example, or can transmit its signal to the FPGA via the coupling device 113 via a waveguide 113a as a coupling element.

[0114] Similarly, the jamming device can have infrared or LED elements, in the visible spectral range or in the ultraviolet range, as jamming elements. In addition, the injection can be realized through optical fibers or pinholes as coupling elements. For this device, a very wide range of operation and training methods can also be obtained, similar to Fig.10 .

[0115] exist Fig.12 In the figure, an alternative arrangement is shown, in which the interference device can only generate interference signals with patterns. To this end, the coupling device 123 has two or more layers 123a, 123b, for example, on each layer can be applied a concentric circle pattern, these patterns are alternately transparent and opaque, wherein the centers of the concentric circles of the two layers are offset relative to each other. This will result in a symmetrical or asymmetrical superposition pattern. The interference device 122 can then have an array of light-emitting diodes. In this case, the coupling device 123 is not an array as in the aforementioned example. Alternatively, the pattern formed by the interference signal in the neural network can be defined by superimposing a pattern. The FPGA chip 121 can have, for example, a photosensitive component in its electronic basic elements.

[0116] Fig.13 Shown as Figures 3 to 5 Arrangement of the devices of the integrated body of the corresponding AI basic unit. On the control circuit board 135, the electrically connected FPGA chip 131 can be placed, wherein the interference device 132 can be electrically contacted on the bottom surface of the inverted, transparent schematic control circuit board 136. The coupling device 133 is arranged between them.

[0117] The AI ​​base units 134 can be trained individually and / or collectively in the manner previously described by means of a first actuator 139 of the control circuit board 135 for the FPGA 131 and a second actuator 140 of the control circuit board 136 for the jammer 132. If each AI base unit 134 has been trained on a different set of features, e.g., the first recognizes a cat, the second recognizes a dog, the third recognizes a horse, etc., then Fig.13 The arrangement in forms a more complex AI system with higher performance / intelligence than the AI ​​base unit as a single device.

[0118] The jamming devices may also be partially electrically connected to each other, as schematically shown by dashed lines 137 and 138. This provides another option for control and evolutionary training of the entire arrangement.

[0119] These connections can be used to transmit signals between the jammer devices 132 that change the performance of other AI basic units in a fixed way, for example, by injecting a jammer signal only, the corresponding artificial neural network in the FPGA can be manipulated by the jammer signal as explained above. For example, this can be achieved by increasing or decreasing the strength of the jammer signal in the connected AI basic units. This means that each AI basic unit can perform in an improved or even optimized manner, such as the devices connected by the dotted connection line 138, or also be detuned, thereby degrading or shutting down, such as the devices connected by the connection line 137. For example, in the animal recognition example above, assuming that half of the AI ​​basic units can recognize animals and the other half can recognize artwork that looks like animals, then the interconnection can ensure that the initial many of the AI ​​basic units are controlled within the sub-optimal range, through the detuning of each jammer device, and make them operate at, for example, 80% of the maximum performance. When an input signal is provided to these devices, such as an image of a mule, a single AI basic unit will classify the input signal into different results.

[0120] A device capable of recognizing a cat may output a 2% match for a mule to a cat, while a device capable of recognizing a horse may output a 90% match, for example in the case of a horse statue, and a device capable of recognizing a work of art may also respond to detections ranging from a few percentage points to 60%. The AI ​​base unit with the highest match, in this case the device capable of recognizing a horse, can then switch its jammer device to optimized operation. In addition, the jammer devices of the previously mis-tuned AI base units to which it is connected can also be simultaneously switched to optimized jammer signal mode, for example, one AI base unit for detecting wild horses, one AI base unit for detecting zebras, and one for identifying equine hybrids. At the same time, through the connection to the device capable of recognizing a work of art, it can suppress all but the one with the highest hit rate. This device for detecting a work of art with the highest hit rate can actuate other devices that can detect the work of art through its connection through the optimized adjustment of the jammer device.

[0121] Now, a new iteration of the mule image can be started until it is determined which object in the entire system the mule is closest to and whether it is an animal or an object.

[0122] Such an arrangement has an additional training layer compared to the AI ​​basic unit, that is, the interconnection of devices with each other, which can also be achieved through evolutionary optimization strategies.

[0123] By more than one, at least two, according to Fig.13 The arrangement of can build complex systems organized hierarchically or in other ways, such as Fig.14 As shown. A base layer 141 including any number of AI basic units is shown, for the sake of clarity, for example Fig.14Only four devices are shown, labeled a1 to a4, which can be connected to each other in an activating or inhibiting manner via electrical connections 143 between associated interfering devices. At this level, an input signal 144 can be fed into all AI basic units a1 to a4, for example by connecting the inputs of the devices in parallel.

[0124] The AI ​​basic unit with the highest probability of identification can be cross-coupled to the next higher layer 142. In this layer, the input signal 144 can now also be applied to all AI basic units, wherein, for the sake of clarity, the layer 142 only shows two devices b1, b2, which can also be partially or completely connected to each other via electrical connections 143 between interfering devices. In this layer, the AI ​​basic unit with the highest probability of identification can also be determined and then the output signal 147 can be generated.

[0125] Typically, the number of AI building blocks can be greatest at the lowest layers and decrease towards higher layers. Although this is not required. Each layer can also create expanded decision categories or new links. For example, in a higher layer patterns can be compared, and after an object has been identified, the next layer can add acoustic signals, revealing contradictions that would otherwise lead to misclassification. For example, if an object identified as a cat neighs like a horse. Such a system can have larger AI building blocks in higher layers than in lower layers.

[0126] exist Fig.15 , a system with a hierarchical AI structure is shown, comprising three layers 151, 152, and 153 with input 154 and output 155, similar to Fig.14 For ease of display, Fig.15 On the right side of FIG. 1 , these complex AI interconnections are grouped together as cylinders 156 with inputs 154 and outputs 155 to enable the representation of more complex structures.

[0127] Fig.16 A more complex structure is schematically shown. It includes multiple Fig.15 164-166. These cylinders can be oriented in the same direction in the layer, where, for clarity, for example, only cylinder 164 is shown with each input 161 oriented downward and each output 169 oriented upward.

[0128] These systems can be arranged in areas marked by specific patterns on top of corresponding cylinders, one pattern for each system marking an area.

[0129] exist Fig.16In FIG. 1 , three zones are shown, which may include three system types 164, 165, 166. As shown by system type 166, not all systems in a zone need to be directly adjacent. A single system may also be arranged as an independent unit in another zone (not shown here). In this way, strong and weak interactions can be achieved between zones by interfering with the device.

[0130] Systems within a zone may receive a common input signal. It is convenient to organize the zones in such a way that they each receive a different or modified input signal, such as a portion of a common input signal that is Fig.16 They are marked with reference numerals 161, 162 and 163.

[0131] There may be mutual or direct connections between systems, through which they can be stimulated or inhibited, or can also stimulate or inhibit other systems. These connections can usually start at the top level, the result level, such as Fig.15 When input signals 161 to 163 are applied, a single system can already achieve a more complex response with different recognition probabilities than a system without these connections.

[0132] Similar to Fig.14 and 15 The operation of individual systems within the area and outside the area can be enhanced or weakened. Connections to other areas (which can easily be far apart), such as the connection arrow from system 164a to system 164b, allow the activities of larger system integrations to be controlled by interfering devices. These integrations of systems have another training layer in addition to what has been described above.

[0133] The systems of the areas with the highest hit rates can be cross-coupled through the switching layer 167, which feeds the results into the projection layer 168, where the results and input signals of other areas with high hit rates can be input and displayed for comparison.

[0134] This arrangement allows the realization of, for example, a pandemonium-like structure, such as that thought to exist in the human brain. These systems correspond to the columnar structure of the cerebral cortex, and the regions correspond to the visual cortex, auditory cortex, tactile cortex or olfactory cortex. Through cross-connections between systems and between regions, it is possible to create and train association-like patterns, which ultimately represent only associations between phenomena that are actually unrelated, such as the realization of optical patterns with music. As shown, through basic devices, such as FPGAs with interference devices and their interconnection and manipulation through interference devices, the linking of devices to form a system arrangement and aggregation, and then by arranging the system in layers and regions, an overall artificial intelligence system can be created, which can achieve general intelligence by gradually or synchronously executing multiple evolutionary training cycles. The larger the scale of the system, the more complex the training structure can be executed.

[0135] Figures 17A to 17D An alternative arrangement is shown. If the jammer 172 is not arranged in close proximity to the FPGA 171 in order to inject the jammer signal in a less detailed pattern than in FIGS. 1 to 16 , but rather it is desired to inject the signal more broadly and in the same or similar manner to multiple FPGAs, the arrangement may include multiple FPGAs 171 and a control circuit board, for example, in a manner similar to that shown in FIG. Fig.17A As shown, the common jammer 172 is arranged in a square shape, which can be configured as a column. Such a group of four FPGAs 171, or for example a group of eight FPGAs (only seven are shown in the figure for clarity), can form an AI basic unit together with the jammer 172 and the coupling device 173 therein.

[0136] Figures 17B to 17D A further example of a device is shown in plan view. Fig. 17B The FPGAs of the devices are arranged in a triangular arrangement, Fig. 17C are arranged in a hexagonal arrangement.

[0137] Fig.17D The device is shown in which the FPGA and the hardware-based artificial neural network are arranged in a rectangular chain system. The coupling medium of the coupling device 173 can be a gas or a material that easily transmits the corresponding interference signal to the FPGA chip. Therefore, due to the wide effect, it can be uniformly formed according to the interference signal column 172. Alternatively, it can include a layered or other type of high-transmission material and low-transmission material. Other groupings can also be implemented in a similar manner. What they have in common is that they can be combined into more complex arrangements, systems and integrated bodies, such as Figures 13 to 16 described.

[0138] Fig.18A flow chart illustrating a method for training a system according to the above is shown, wherein firstly a method 180 for training an artificial neural network in an apparatus according to the above is performed. The apparatus of the system may be initially trained.

[0139] In a first optional step 187 of method 180, the hardware-based artificial neural network of the device can be initially trained without injecting interference signals. In this step, the hardware-based artificial neural network is trained to an initial performance value.

[0140] In a further step 181, target output data may be defined, which represents the desired result of processing the training data provided by the hardware-based artificial neural network. This step may also be performed at any time before the following step, and may also be performed synchronously with or before the optional step 187.

[0141] Furthermore, in step 182, the hardware-based artificial neural network may be trained using the provided training data. To this end, the training data is fed into an input layer of the neural network, wherein the jammer injects a jamming signal into at least one region of the hardware-based artificial neural network. In this process, a partial node, an entire node, or a plurality of nodes of the hardware-based artificial neural network may be arranged in at least one region.

[0142] In a further step 183, the output data of the hardware-based artificial neural network is obtained. Since the network is hardware-based, the training data is processed synchronously on all nodes of the network layer, so the output data is available within a few milliseconds.

[0143] Afterwards, in step 184, a deviation between the output data and the target output data is determined. If the deviation is outside a predetermined tolerance range, for example, if the deviation is greater than 1%, the hardware-based artificial neural network is reconfigured. At least one interference signal may also be selectively modified. If multiple interference signals are used, it is sufficient to modify a single interference signal, for example, by activating an interference element of the interference device.

[0144] Steps 182 to 184 are repeated by feeding the modified hardware-based artificial neural network and the possibly modified interference signal.

[0145] If the deviation is within the predetermined tolerance range, then training of the device is terminated at step 185 .

[0146] When all devices have been trained using the method 180, the arrangement of devices can be trained in a further method 188. To this end, the devices of the arrangement coupled to each other via the interfering device are trained according to steps 182 to 186. However, this does not exclude the possibility of also training the arrangement without first executing the method for the device.

[0147] In the training of the arrangement, which may be performed similarly to method 180, at least some of the interfering devices may be influenced or controlled by the hardware-based artificial neural network of other devices.

[0148] When all arrangements of the system have been trained using method 188, the system can be trained according to method 189. To this end, arrangements of devices or systems that are mutually coupled by means of interference devices will be trained according to steps 182 to 186. However, this does not exclude the possibility of also training the system without first executing the method for the arrangement or device.

[0149] Furthermore, the ensemble may be trained in the following manner: first the system is trained according to the above description and then the entire ensemble is trained. However, this does not exclude the possibility that the ensemble may also be trained without first training the system, arrangement and / or device.

[0150] The above examples do not limit the present invention in any way. Instead, the present invention can be modified in various ways. All the features of the present invention described above, whether alone or in combination with each other, may be essential to the present invention.

Claims

1. A device for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network (11, 24, 32, 41, 51, 71, 81, 101, 111, 121, 131, 171), characterized in that: The apparatus comprises at least one interference device (12, 22, 35, 42, 52a, 52b, 72, 82, 102, 112, 122, 132, 172) and at least one coupling device (15, 23, 34, 43, 53a, 53b, 73, 83, 103, 113, 123, 133, 173), wherein the at least one interference device is used to inject at least one interference signal into at least one area of ​​the hardware-based artificial neural network, and the coupling device is positioned between the interference device and the hardware-based artificial neural network and is designed to transmit the at least one interference signal from the interference device to the entire at least one area.

2. The device according to the preceding claim, wherein: The hardware-based artificial neural network has at least one component in at least one area that is designed to reduce the signal-to-noise ratio when receiving the at least one interference signal, wherein the interference device preferably generates an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal and / or ionization interference signal.

3. A device according to any one of the preceding claims, wherein: The jamming device has a plurality of individually actuatable jamming elements (72a) for injecting jamming signals into the hardware-based artificial neural network, wherein the jamming elements preferably inject jamming signals into different regions of the hardware-based artificial neural network.

4. The device according to claim 3, wherein: The plurality of interfering elements are arranged to be distributed on a layer, preferably in the form of an array, wherein the coupling device comprises a medium having a plurality of coupling elements (73a, 83a, 103a, 113a) for transmitting the at least one interfering signal to the at least one area, the coupling elements being distributed in the layer like the interfering elements.

5. The device according to any one of claims 1 to 4, wherein: The at least one region has a range corresponding to a size of the hardware-based artificial neural network, or is designed to be smaller than the size of the hardware-based artificial neural network.

6. A device according to any one of the preceding claims, wherein: The device has at least one semiconductor chip, wherein the semiconductor chip includes the hardware-based artificial neural network, wherein the hardware-based artificial neural network is preferably formed in an integrated circuit, more preferably formed in a field programmable gate array or formed in an application-specific integrated circuit.

7. A device according to any one of the preceding claims, wherein: The apparatus comprises a shielding device (14, 36) for shielding external interference signals of the same type as the at least one interference signal, wherein the shielding device surrounds the hardware-based artificial neural network, the coupling device and the interference device.

8. An arrangement comprising a plurality of devices according to any one of the preceding claims, wherein: The hardware-based artificial neural networks of the devices are electrically connected to each other in series and / or in parallel, wherein, preferably, the interference device of at least a first device among the multiple devices and the interference device of a second device among the multiple devices are designed as a common interference device, wherein, more preferably, the output layer of the hardware-based artificial neural network of a third device among the multiple devices is designed to control the interference device of a fourth device among the multiple devices.

9. A system comprising a plurality of arrangements according to claim 8, wherein: A first arrangement of the plurality of arrangements is designed to control at least one interference device in a second arrangement of the plurality of arrangements.

10. A method for training an artificial neural network in a device according to any one of claims 1 to 7, wherein: The method (180) comprises at least the following steps: - defining (181) target output data during processing of the provided training data; - feeding (182) the training data into the hardware-based artificial neural network and injecting at least one jamming signal into the at least one region of the hardware-based artificial neural network via the at least one jamming device; - obtaining (183) output data from the hardware-based artificial neural network; - determining (184) whether there is at least one deviation between the output data and the target output data, the deviation being outside a predetermined tolerance range; If the deviation is within the tolerance range, then: - terminating (185) the method; and If the deviation is outside the predetermined tolerance range, then: - Modifying (186) the hardware-based artificial neural network, preferably modifying the at least one interference signal, and repeating the above steps 182 to 184.

11. The method according to claim 10, wherein: A signal-to-noise ratio of no more than 15 dB, preferably no more than 10 dB, and further preferably no more than 0 dB is generated in the at least one region by the injected interference signal.

12. The method according to claim 10 or 11, wherein: Prior to the step of defining target output data during processing of provided training data, the hardware-based artificial neural network is trained (187) without injecting interference signals.

13. The method according to any one of claims 10 to 12, wherein: The at least one interference device is designed at least according to claim 3, and the multiple actuatable interference elements are actuated so that the interference signal forms a predefined interference signal pattern on the hardware-based artificial neural network, wherein, preferably, multiple training iterations of the hardware-based artificial neural network are executed sequentially with different predefined interference signal patterns.

14. A method for training an artificial neural network in an arrangement according to claim 8, wherein: The method (188) for training an artificial neural network in a device according to any one of claims 10 to 13 is applied to the hardware-based artificial neural network of the device, preferably after the device has been trained separately outside the arrangement by a method (180) according to any one of claims 10 to 13.

15. A method (189) for training an artificial neural network in a system according to claim 9, wherein: The method (180) for training an artificial neural network in an arrangement according to any one of claims 10 to 13 is applied to the hardware-based artificial neural network of the arrangement, preferably after the arrangement has been trained separately outside the system by means of the method (188) for training an artificial neural network in the arrangement according to claim 14.

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