Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a pixel driving circuit (PDC) having a first reset transistor (T1) and a second reset transistor (T6). At least a portion of a gate (G1) of the first reset transistor (T1) in a current row of the pixel driving circuit (PDC) and at least a portion of a gate (G6) of the second reset transistor (T6) in a previous row of the pixel driving circuit (PDC) are part of an overall structure. The gate (G1) of the first reset transistor (T1) in the current row of the pixel driving circuit (PDC) and the gate (G6) of the second reset transistor (T6) in the previous row of the pixel driving circuit (PDC) are arranged along a direction that is not parallel to an extension direction of a reset control signal line.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate including a pixel driving circuit having a first reset transistor and a second reset transistor; wherein at least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit are part of an integral structure; and the gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the previous row pixel driving circuit are arranged along a direction not parallel to the extension direction of a reset control signal line.

[0004] In some embodiments of this disclosure, the channel direction of the first reset transistor is not parallel to the channel direction of the second reset transistor; and the channel directions of the first reset transistor and the second reset transistor intersect each other, forming a non-zero angle.

[0005] In some embodiments of this disclosure, the array substrate further includes a plurality of first reset signal lines, a plurality of second reset control signal lines, and a plurality of second reset signal lines; wherein, the plurality of second reset control signal lines include the second reset control signal line of the current stage; in the same row of pixel driving circuits, the orthographic projection of a corresponding first reset signal line among the plurality of first reset signal lines on the substrate is located between the orthographic projection of the second reset control signal line of the current stage on the substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines on the substrate.

[0006] In some embodiments of this disclosure, the pixel driving circuit further includes a data writing transistor, a compensation transistor, and a driving transistor; the array substrate includes a semiconductor material layer; the semiconductor material layer includes: a continuous line including the active layer and second electrode of the compensation transistor and the second electrode of the first reset transistor; and a branch extending from the continuous line; wherein the branch is connected to the gate of the driving transistor; and the orthographic projection of the branch on the substrate does not overlap with the orthographic projection of the electrode block including the gate of the data writing transistor and the gate of the compensation transistor on the substrate.

[0007] In some embodiments of this disclosure, the array substrate further includes a plurality of first reset control signal lines; wherein each of the plurality of first reset control signal lines includes a main line portion extending along a direction substantially parallel to a first direction, and a protrusion extending in a direction substantially parallel to a second direction away from the main line portion, the second direction being different from the first direction; the protrusion includes at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit; and the main line portion includes at least a portion of the gate of the first reset transistor in the current row pixel driving circuit.

[0008] In some embodiments of this disclosure, the array substrate further includes a plurality of first reset control signal lines and a plurality of second reset control signal lines; wherein, the gate of the first reset transistor includes a first portion from a corresponding first reset control signal line among the plurality of first reset control signal lines and a second portion from a corresponding second reset control signal line among the plurality of second reset control signal lines; and the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the second portion on the substrate.

[0009] In some embodiments of this disclosure, the array substrate further includes a voltage supply network; wherein the voltage supply network includes a plurality of third voltage supply lines and a plurality of fourth voltage supply lines; each of the plurality of third voltage supply lines is connected to one or more of the plurality of fourth voltage supply lines; and each of the plurality of fourth voltage supply lines is connected to one or more of the plurality of third voltage supply lines; the plurality of third voltage supply lines are located in a first signal line layer; and the plurality of fourth voltage supply lines are located in a second signal line layer, the second signal line layer being located on the side of the first signal line layer away from the substrate.

[0010] In some embodiments of this disclosure, the array substrate further includes a plurality of light emission control signal lines and a plurality of second reset signal lines; wherein, the orthographic projection of a corresponding third voltage supply line among the plurality of third voltage supply lines on the substrate is located between the orthographic projection of a corresponding light emission control signal line among the plurality of light emission control signal lines on the substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines on the substrate.

[0011] In some embodiments of this disclosure, the array substrate further includes a first reset signal network and a second reset signal network; wherein the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines; the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines; each of the plurality of first reset signal lines is connected to one or more of the plurality of third reset signal lines; each of the plurality of third reset signal lines is connected to one or more of the plurality of first reset signal lines; each of the plurality of second reset signal lines is connected to one or more of the plurality of fourth reset signal lines; and each of the plurality of fourth reset signal lines is connected to one or more of the plurality of second reset signal lines.

[0012] In some embodiments of this disclosure, the array substrate further includes a plurality of data lines, a plurality of second voltage supply lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, and a plurality of fourth voltage supply lines; wherein, a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines is located between two adjacent data lines configured to provide data signals to adjacent two columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines configured to provide first reference voltage signals to adjacent two columns of pixel driving circuits; a corresponding third reset signal line among the plurality of third reset signal lines is located between the plurality of data lines, a plurality of second voltage supply lines, a plurality of third reset signal ... Between two adjacent data lines of the plurality of data lines configured to provide data signals to two adjacent pixel driving circuits, and between two adjacent second voltage supply lines of the plurality of second voltage supply lines configured to provide a first reference voltage signal to two adjacent pixel driving circuits; and between a corresponding fourth reset signal line of the plurality of fourth reset signal lines.

[0013] In some embodiments of this disclosure, the pixel driving circuit further includes a storage capacitor and a compensation transistor; wherein the storage capacitor includes a first capacitor electrode and a second capacitor electrode; the second capacitor electrode is configured to be provided with a first reference voltage signal; and the orthographic projection of the overall structure including the second capacitor electrode on the substrate at least partially overlaps the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

[0014] In some embodiments of this disclosure, the overall structure including the second capacitor electrode includes a body and an extension extending in a direction away from the body; the extension E includes a first portion, a second portion, and a third portion; the first portion connects the body and the second portion; the second portion connects the first portion and the third portion; the first portion and the third portion extend in a direction substantially parallel to the second direction; and the second portion extends in a direction substantially parallel to the first direction.

[0015] In some embodiments of this disclosure, the orthographic projection of the third portion on the substrate at least partially overlaps with the orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

[0016] In some embodiments of this disclosure, the array substrate further includes node connection lines and a plurality of gate lines; wherein the node connection lines are connected to the second electrode of the compensation transistor at a location between a corresponding gate line of the plurality of gate lines and a capacitor electrode of the storage capacitor; the orthographic projection of the node connection lines on the substrate does not overlap with the orthographic projection of the plurality of gate lines on the substrate; and the orthographic projection of the second electrode of the compensation transistor on the substrate partially overlaps with the orthographic projection of the corresponding gate line on the substrate.

[0017] In some embodiments of this disclosure, the array substrate further includes node connection lines and a plurality of data lines; wherein the second capacitor electrode spaces the node connection lines from a corresponding data line among the plurality of data lines configured to provide data signals to the pixel driving circuit.

[0018] In some embodiments of this disclosure, the array substrate further includes node connection lines and a plurality of data lines; wherein the extension spacers the node connection lines from a corresponding data line among the plurality of data lines configured to provide data signals to the pixel driving circuit.

[0019] In some embodiments of this disclosure, the array substrate further includes a shielding block and a plurality of first reset signal lines; wherein the pixel driving circuit further includes a compensation transistor; the shielding block is connected to a corresponding first reset signal line among the plurality of first reset signal lines; and the orthographic projection of the shielding block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor on the substrate.

[0020] In some embodiments of this disclosure, the pixel driving circuit further includes a compensation transistor and a data writing transistor; wherein at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit are part of an overall structure.

[0021] In some embodiments of this disclosure, the array substrate further includes a plurality of gate lines; wherein the overall structure including at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data write transistor in the previous column pixel driving circuit is connected to one of the plurality of gate lines.

[0022] In some embodiments of this disclosure, the array substrate further includes an anti-interference block and a plurality of second reset signal lines; wherein the anti-interference block is connected to a corresponding second reset signal line among the plurality of second reset signal lines; and the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

[0023] In some embodiments of this disclosure, the array substrate further includes an anti-interference block and a plurality of constant voltage signal lines; wherein the anti-interference block is connected to a corresponding constant voltage signal line among the plurality of constant voltage signal lines; the plurality of constant voltage signal lines are configured to provide a constant voltage signal to the anti-interference block; and the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

[0024] In some embodiments of this disclosure, the array substrate further includes a voltage supply network, a first reset signal network, a second reset signal network, and a pixel defining layer defining a plurality of sub-pixel openings; wherein, the voltage supply network includes a plurality of third voltage supply lines and a plurality of fourth voltage supply lines; the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines; the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines; vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network are substantially located outside the regions of the plurality of sub-pixel openings; and the orthographic projection of the pixel defining layer on the substrate substantially covers the orthographic projection of the conductive material in the vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network on the substrate.

[0025] In one aspect, this disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0026] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0027] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0028] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0030] FIG. 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] FIG. 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0032] FIG. 3B To show FIG. 3A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate.

[0033] FIG. 3C It is shown FIG. 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0034] FIG. 3D It is shownFIG. 3A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0035] FIG. 3E It is shown FIG. 3A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0036] FIG. 3F It is shown FIG. 3A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate.

[0037] FIG. 3G It is shown FIG. 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0038] FIG. 3H It is shown FIG. 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0039] FIG. 3I It is shown FIG. 3A The diagram shows a schematic of the structure of the second signal line layer in the array substrate.

[0040] FIG. 3J It is shown FIG. 3A A schematic diagram of the structure of the second planarization layer in the array substrate shown.

[0041] FIG. 3K It is shown FIG. 3A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0042] FIG. 3L It is shown FIG. 3A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown.

[0043] FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram.

[0044] FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram.

[0045] FIG. 5A This is a schematic diagram illustrating the structure of the semiconductor material layer and the second conductive layer according to some embodiments of the present disclosure.

[0046] FIG. 5B This is a schematic diagram illustrating the structure of the semiconductor material layer, the second conductive layer, and the first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0047] FIG. 5CThis is a schematic diagram illustrating the structure of the semiconductor material layer and the first conductive layer according to some embodiments of the present disclosure.

[0048] FIG. 6A This is a schematic diagram illustrating the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0049] FIG. 6B This is a schematic diagram illustrating the structure of the semiconductor material layer, the second conductive layer, and the first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0050] FIG. 7A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0051] FIG. 7B To show FIG. 7A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate.

[0052] FIG. 7C It is shown FIG. 7A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0053] FIG. 7D It is shown FIG. 7A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0054] FIG. 7E It is shown FIG. 7A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0055] FIG. 7F It is shown FIG. 7A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate.

[0056] FIG. 7G It is shown FIG. 7A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0057] FIG. 7H It is shown FIG. 7A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0058] FIG. 7I It is shown FIG. 7A The diagram shows a schematic of the structure of the second signal line layer in the array substrate.

[0059] FIG. 7J It is shown FIG. 7A A schematic diagram of the structure of the second planarization layer in the array substrate shown.

[0060] FIG. 7K It is shown FIG. 7A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0061] FIG. 7L It is shown FIG. 7A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown.

[0062] FIG. 8A It is along FIG. 7A A cross-sectional view of line C-C' in the diagram.

[0063] FIG. 8B It is along FIG. 7A A cross-sectional view of the D-D' line in the diagram.

[0064] FIG. 9A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0065] FIG. 9B To show FIG. 9A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate.

[0066] FIG. 9C It is shown FIG. 9A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0067] FIG. 9D It is shown FIG. 9A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0068] FIG. 9E It is shown FIG. 9A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0069] FIG. 9F It is shown FIG. 9A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate.

[0070] FIG. 9G It is shown FIG. 9A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0071] FIG. 9H It is shown FIG. 9A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0072] FIG. 9I It is shown FIG. 9A The diagram shows a schematic of the structure of the second signal line layer in the array substrate.

[0073] FIG. 9J It is shownFIG. 9A A schematic diagram of the structure of the second planarization layer in the array substrate shown.

[0074] FIG. 9K It is shown FIG. 9A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0075] FIG. 9L It is shown FIG. 9A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown.

[0076] FIG. 10 This is a schematic diagram illustrating a voltage supply network in an array substrate according to some embodiments of the present disclosure.

[0077] FIG. 11 This is a schematic diagram illustrating a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0078] FIG. 12 This is a schematic diagram illustrating the connection of signal lines in the display area and signal lines in the peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0079] FIG. 13 This is a schematic diagram illustrating the connection of signal lines in the display area and signal lines in the peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0080] FIG. 14 This is a schematic diagram illustrating a voltage supply network, a first reset signal network, a second reset signal network, and an anode layer in an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0081] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0082] This disclosure particularly provides an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a pixel driving circuit having a first reset transistor and a second reset transistor. Optionally, at least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the preceding row pixel driving circuit are part of an integral structure. Optionally, the gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the preceding row pixel driving circuit are arranged along a direction not parallel to the extension direction of the reset control signal line.

[0083] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0084] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 1 The array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, multiple first voltage supply lines Vdd, and corresponding second voltage supply lines (e.g., low voltage supply lines). The emission of light from each sub-pixel Sp is driven by the corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding first voltage supply line among the multiple first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the emission of light from the light-emitting element.

[0085] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIG. 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of the current stage, a source connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a source connected to a corresponding data line among a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and the driving transistor Td. The transistor has a gate and a source, and a drain connected to the drain of the driving transistor Td; a fourth transistor T4, which has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a source connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5, which has a gate connected to a corresponding light-emitting control signal line, a source connected to the drain of the driving transistor Td and the third transistor T3, and a drain connected to the anode of the light-emitting element LE; and a sixth transistor T6, which has a gate connected to the next stage reset control signal line rst(N+1), a source connected to a second reset signal line among a plurality of second reset signal lines Vint2, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0086] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0087] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (or, in other words, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (or, in other words, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0088] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0089] As used herein, a first electrode or a second electrode refers to one of the first and second terminals of a transistor, which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0090] FIG. 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIGS. 2A-2C During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. In the initial sub-stage t0, each of the plurality of gate lines GL is provided with a cutoff signal, therefore the second transistor T2 and the third transistor T3 are turned off.

[0091] In reset phase t1, a turn-on reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, turning on the first transistor T1; allowing the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding first voltage supply line in the plurality of first voltage supply lines Vdd. Due to the increase in the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, each gate line in the plurality of gate lines GL is provided with a cutoff signal, thus turning off the second transistor T2 and the third transistor T3. Each light emission control signal line in the plurality of light emission control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0092] During the data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the corresponding reset control signal line in the multiple reset control signal lines rst, thus turning off the first transistor T1. Each of the multiple gate lines GL is provided with a conduction signal, therefore the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The second transistor T2 is turned on during the data write sub-stage t2. The data voltage signal transmitted through each data line in the multiple data lines DL is received by the first electrode of the second transistor T2 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data writing sub-stage t2, the voltage level of node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. Each of the multiple light-emitting control signal lines em is provided with a high-voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0093] During the data writing sub-stage t2, the turn-on reset control signal is provided to the gate of the sixth transistor T6 through the corresponding reset control signal line in the multiple reset control signal lines rst of the next adjacent stage to turn on the sixth transistor T6; allowing the initialization voltage signal from the corresponding second reset signal line in the multiple second reset signal lines Vint2 to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to node N4. The anode of the light-emitting element LE is initialized.

[0094] In the light-emitting phase t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, so as to turn off the first transistor T1. Each of the plurality of gate lines GL is provided with a cutoff signal, and the second transistor T2 and the third transistor T3 are turned off. Each of the plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting phase t3, the voltage level of node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0095] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0096] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is C1-C2-C3-C4, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is C1-C2-C3-C2', where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0097] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0098] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0099] FIG. 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 3B To show FIG. 3A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate. FIG. 3A and FIG. 3B A portion of an array substrate is depicted having six pixel driving circuits, the six pixel driving circuits including PDC1, PDC2, PDC3, PDC4, PDC5 and PDC6.

[0100] FIG. 3C It is shown FIG. 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. FIG. 3D It is shown FIG. 3A A schematic diagram of the structure of the first conductive layer in the array substrate shown. FIG. 3E It is shown FIG. 3A A schematic diagram of the structure of the second conductive layer in the array substrate shown. FIG. 3F It is shown FIG. 3A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. FIG. 3G It is shown FIG. 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. FIG. 3H It is shown FIG. 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown. FIG. 3I It is shown FIG. 3A The diagram shows a schematic of the structure of the second signal line layer in the array substrate. FIG. 3J It is shown FIG. 3A A schematic diagram of the structure of the second planarization layer in the array substrate shown. FIG. 3K It is shown FIG. 3A A schematic diagram of the structure of the anode layer in the array substrate shown. FIG. 3L It is shown FIG. 3A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown. FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram. FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram.

[0101] refer to FIGS. 3A-3L and FIGS. 4A-4BIn some embodiments, the array substrate includes a substrate BS; a semiconductor material layer SML located on the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN; and a first signal line layer SL1. The first planarization layer PLN1 is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2 is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2 is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL is located on the side of the anode layer ADL away from the substrate BS.

[0102] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3CEach pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number indicating the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes active layer ACT1, first electrode S1, and second electrode D1. Second transistor T2 includes active layer ACT2, first electrode S2, and second electrode D2. Third transistor T3 includes active layer ACT3, first electrode S3, and second electrode D3. Fourth transistor T4 includes active layer ACT4, first electrode S4, and second electrode D4. Fifth transistor T5 includes active layer ACT5, first electrode S5, and second electrode D5. Sixth transistor T6 includes active layer ACT6, first electrode S6, and second electrode D6. Driving transistor Td includes active layer ACTd, first electrode Sd, and second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0103] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0104] In some embodiments, the channel direction of the first transistor T1 is not parallel to the channel direction of the sixth transistor T6. The channel directions of the first transistor T1 and the sixth transistor T6 intersect each other, forming a non-zero angle. As used herein, the term "channel direction" refers to the direction from the first electrode to the second electrode of the transistor. In one example, the channel direction of the first transistor T1 is substantially parallel to the second direction DR2, and the channel direction of the sixth transistor T6 is substantially parallel to the first direction DR1.

[0105] refer to FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3DIn some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst1 (including the first reset signal line rst1N of the current stage and the first reset signal line rst1(N+1) of the next stage), a plurality of light emission control signal lines em, an electrode block including one or more gates G3 of the third transistor T3 and the gate G2 of the second transistor T2, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first reset control signal lines rst1, the plurality of light emission control signal lines em, the electrode block including one or more gates G3 of the third transistor T3 and the gate G2 of the second transistor T2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0106] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple light-emitting control signal lines em and first capacitor electrodes Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple light-emitting control signal lines em and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple light-emitting control signal lines em and the step of forming the first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0107] Reference FIG. 2A , FIG. 2B , FIG. 3A as well as FIG. 3E In some embodiments, the second conductive layer includes an anti-interference block IPB and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0108] FIG. 3FThe text describes vias extending through the interlayer dielectric layer (ILD).

[0109] refer to FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3G In some embodiments, the first signal line layer includes node connection lines Cln, multiple second reset control signal lines rst2 (including the current stage's second reset control signal line rst2N and the next stage's second reset control signal line rst2(N+1)), multiple first reset signal lines Vint1, multiple second reset signal lines Vint2, multiple gate lines GL, multiple first voltage supply lines Vdd1, relay electrodes RE, and data signal connection pads DCP. The node connection lines Cln connect the first capacitor electrode Ce1 and the first electrode of the driving transistor Td in each pixel driving circuit together. The data signal connection pads DCP are configured to connect a corresponding data line among the multiple data lines to the first electrode of the second transistor T2. The relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pads are in the second signal line layer and connected to the anode in each sub-pixel. The multiple first voltage supply lines Vdd1 are interconnected with the multiple second voltage supply lines to form an interconnected reset signal network. Each of the plurality of first voltage supply lines Vdd1 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the plurality of first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1; the plurality of second voltage supply lines extend in a direction substantially parallel to the second direction DR2. As used herein, the term “substantially parallel” means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0110] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the node connection line Cln, multiple second reset control signal lines rst2 (including the second reset control signal line rst2N of the current stage and the second reset control signal line rst2(N+1) of the next stage), multiple first reset signal lines Vint1, multiple second reset signal lines Vint2, multiple gate lines GL, multiple first voltage supply lines Vdd1, relay electrodes RE, and data signal connection pads DCP are located on the same layer.

[0111] In some embodiments, in the same row pixel driving circuit, the orthographic projection of the corresponding first reset signal line in the plurality of first reset signal lines Vint1 on the substrate is located between the orthographic projection of the current stage second reset control signal line rst2N in the plurality of second reset control signal lines rst2 on the substrate and the orthographic projection of the corresponding second reset signal line in the plurality of second reset signal lines Vint2 on the substrate.

[0112] FIG. 3H The vias extending through the first planarization layer PLN1 are shown.

[0113] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3I In some embodiments, the second signal line layer includes multiple second voltage supply lines Vdd2, multiple data lines DL, and an anode contact pad ACP. The anode contact pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit. The anode contact pad ACP is also electrically connected to the anode in each sub-pixel. The multiple second voltage supply lines Vdd2 are interconnected with multiple first voltage supply lines to form an interconnected reset signal network. Each of the multiple data lines is electrically connected via a data signal connection pad to the first electrode of the second transistor T2.

[0114] Various suitable conductive materials and manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple second voltage supply lines Vdd2, multiple data lines DL, and anode contact pads ACP are located in the same layer.

[0115] FIG. 3J The vias extending through the second planarization layer PLN2 are described.

[0116] Reference FIG. 2A , FIG. 2B , FIG. 3A as well as FIG. 3K The array substrate also includes an anode layer (ADL). FIG. 3K The text represents multiple sub-pixel openings (SA) that correspond to multiple anodes. FIG. 3J The vias extending through the second planarization layer PLN2 are described. Each anode is connected to its corresponding anode contact pad via a corresponding via extending through the second planarization layer PLN2.

[0117] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3L The array substrate also includes a pixel definition layer (PDL) that defines multiple sub-pixel openings (SA).

[0118] refer to FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3D , FIG. 3E , FIG. 3G and FIG. 4A In some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and extends the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as at least one of the following: a plurality of second reset control signal lines rst2, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of gate lines GL, a plurality of first voltage supply lines Vdd1, a relay electrode RE, or a data signal connection pad DCP.

[0119] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor, such as... FIG. 4A As shown.

[0120] In some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The third via v3 extends through the first planarization layer PLN1. The fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, corresponding data lines in a plurality of data lines DL are connected to the data signal connection pad DCP via the third via v3. The data signal connection pad DCP is connected to the first electrode S2 of the second transistor via the fourth via v4.

[0121] Reference FIG. 2A , FIG. 2B , FIGS. 3A-3I as well as FIG. 4B In some embodiments, the array substrate further includes a fifth via v5, a sixth via v6, a seventh via v7, and an eighth via v8. The fifth via v5 extends through the first planarization layer PLN1. The sixth via v6 and the seventh via v7 extend through the interlayer dielectric layer ILD, respectively. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding second voltage supply line among the plurality of second voltage supply lines Vdd2 is connected to a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 via the fifth via v5. Optionally, a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 is connected to the second capacitor electrode Ce2 of the storage capacitor Cst via one or more vias (e.g., the sixth via v6 and the seventh via v7). Optionally, a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 is connected to the first electrode S4 of the fourth transistor T4 via the eighth via v8.

[0122] refer to FIG. 3A , FIG. 3E and FIG. 4AIn some embodiments, the second capacitor electrode Ce2 includes a body MB and an extension E extending away from the body MB. In some embodiments, the extension E includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 connects the body MB and the second portion P2, and the second portion P2 connects the first portion P1 and the third portion P3. Optionally, the first portion P1 and the third portion P3 extend in directions substantially parallel to the second direction DR2. Optionally, the second portion P2 extends in a direction substantially parallel to the first direction DR1.

[0123] FIG. 5A This is a schematic diagram illustrating the structure of the semiconductor material layer and the second conductive layer according to some embodiments of the present disclosure. FIG. 5B This is a schematic diagram illustrating the structure of the semiconductor material layer, the second conductive layer, and the first signal line layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 3A , FIG. 3E , FIG. 4A , FIG. 5A as well as FIG. 5B In some embodiments, the orthographic projection of the third portion P3 onto the substrate BS at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., the two channel portions) of the third transistor T3 onto the substrate BS. The inventors of this disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0124] FIG. 5C This is a schematic diagram illustrating the structure of the semiconductor material layer and the first conductive layer according to some embodiments of the present disclosure. FIG. 3C , FIG. 3D , FIG. 3G In some embodiments, the semiconductor material layer includes a branch Br that branches off from a continuous line; the continuous line includes the active layer ACT3 of the third transistor T3 and the second electrode D3, and the second electrode D1 of the first transistor T2. The branch Br is connected to a node connection line Cln. Optionally, the orthographic projection of the branch Br onto the substrate does not overlap with the orthographic projection of the electrode block including the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 onto the substrate. The electrode block including the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 is an integral structure. By providing the branch Br, the electrode blocks located in the first conductive layer (each electrode block including the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3) can be connected to corresponding gate lines among a plurality of gate lines GL located in the first signal line layer.

[0125] Various suitable alternative implementation methods can be implemented to enhance the stability of the third transistor T3. FIG. 6AThis is a schematic diagram illustrating the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure. FIG. 6B This is a schematic diagram illustrating the structure of the semiconductor material layer, the second conductive layer, and the first signal line layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 6A and FIG. 6B In some embodiments, the second conductive layer includes a shield block SDB. Optionally, the shield block SDB is connected to a corresponding first reset signal line in a plurality of first reset signal lines Vint1. Optionally, the shield block SDB is configured to receive a reset signal. In some embodiments, the orthographic projection of the shield block SDB onto the substrate BS at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., the two channel portions) of the third transistor T3 onto the substrate BS. The inventors of this disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0126] Reference FIG. 3A , FIG. 3C , FIG. 3E , FIG. 3G , FIG. 5B and FIG. 6B In some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 are located in the same layer. Optionally, the anti-interference block IPB is connected to a corresponding second reset signal line in a plurality of second reset signal lines Vint2. Optionally, the anti-interference block IPB is configured to receive a reset signal. In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate BS. Optionally, the orthographic projection of the portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate BS does not overlap with the orthographic projection of any reset signal line on the substrate. The inventors of this disclosure have found that this unique structure enhances the stability of the first transistor T1.

[0127] Reference FIG. 3A , FIG. 3C , FIG. 3E , FIG. 3G , FIG. 4A , FIG. 5B and FIG. 6BIn some embodiments, the node connection line Cln is positioned between each gate line in the plurality of gate lines GL and the capacitor electrode of the storage capacitor, connected to the second electrode D3 of the third transistor T3. Optionally, the orthographic projection of the node connection line Cln on the substrate BS does not overlap with the orthographic projection of the corresponding gate line GL in the plurality of gate lines GL on the substrate BS. Optionally, the orthographic projection of the second electrode D3 of the third transistor T3 on the substrate BS partially overlaps with the orthographic projection of the corresponding gate line in the plurality of gate lines GL on the substrate BS. The inventors of this disclosure have found that this unique structure reduces or prevents interference from gate scan signals transmitted in the respective gate lines to the node connection line Cln (corresponding to the first node N1). Furthermore, the length of the node connection line Cln can be reduced, thereby reducing potential interference from data signals transmitted in the respective data lines of the plurality of data lines SL to the node connection line Cln (corresponding to the first node N1).

[0128] Reference FIG. 3A , FIG. 3C , FIG. 3E , FIG. 3G and FIG. 3I In some embodiments, the second capacitor electrode Ce2 spaces the first node N1 in each pixel driving circuit from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 spaces the node connection line Cln from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 includes an extension E; and the extension E spaces the second electrode D3 of the third transistor T3 (connected to the node connection line Cln) from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. The inventors of this disclosure have found that this unique structure reduces interference from data signals transmitted in each of the plurality of data lines SL to the node connection line Cln (corresponding to the first node N1) and the second electrode D3 of the third transistor T3.

[0129] See FIG. 3A , FIG. 3C , FIG. 3D and FIG. 3G In some embodiments, the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are configured to receive the same reset control signal.

[0130] In some embodiments, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are part of an integral structure. Optionally, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are portions of the same reset control signal line.

[0131] In some embodiments, a corresponding first reset control signal line among a plurality of first reset control signal lines (e.g., the first reset control signal line rst1N of the current stage) includes a main line portion extending along a direction substantially parallel to the first direction DR1, and a protrusion P protruding along a direction substantially parallel to the second direction DR2 in a direction away from the main line portion MLP. The protrusion P protrudes away from the current row pixel driving circuit from the preceding row pixel driving circuit. Optionally, the protrusion P includes at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the preceding row pixel driving circuit. Optionally, the main line portion MLP includes at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit.

[0132] In some embodiments, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction not parallel to the extension direction of the reset control signal line of the array substrate. Optionally, the gates of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction not parallel to the first direction DR1.

[0133] In some embodiments, the gate of the first reset transistor (e.g., T1) includes a first portion of a corresponding first reset control signal line from a plurality of first reset control signal lines and a second portion of a corresponding second reset control signal line from a plurality of second reset control signal lines.

[0134] In some embodiments, the orthographic projection of a corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate at least partially overlaps with the orthographic projection of a corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

[0135] In some embodiments, the orthographic projection of a first portion of the gate of the first reset transistor from a plurality of first reset control signal lines on the substrate at least partially overlaps with the orthographic projection of a second portion of the gate of the first reset transistor from a plurality of second reset control signal lines on the substrate.

[0136] The inventors of this disclosure have discovered that by providing two reset control signal lines for the reset control signal, the resistance of the reset control signal lines can be reduced, and the drive power of the reset control signal lines can be ensured. With this unique structure, the first reset transistor and the second reset transistor can share the same reset control signal generated by the same reset control generation circuit. This reduces the total number of scan circuits and further reduces the peripheral area of ​​the array substrate.

[0137] See FIG. 3A , FIG. 3D , FIG. 3G In some embodiments, along the second direction DR2, the first reset signal line of the plurality of first reset signal lines Vint1 configured to provide a reset signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit, and the second reset signal line of the plurality of second reset signal lines Vint2 configured to provide a reset signal to the second reset transistor (e.g., T6) in the previous row pixel driving circuit, are located on both sides of the second reset control signal line of the plurality of second reset control signal lines configured to provide a reset control signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit. Optionally, the second reset control signal line of the plurality of second reset control signal lines configured to provide a reset control signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit is spaced apart from the first reset signal line of the plurality of first reset signal lines Vint1 configured to provide a reset signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset signal line of the plurality of second reset signal lines Vint2 configured to provide a reset signal to the second reset transistor (e.g., T6) in the previous row pixel driving circuit.

[0138] See FIG. 3A , FIG. 3D , FIG. 3GIn some embodiments, along the second direction DR2, the first reset signal line of the plurality of first reset signal lines Vint1, which is configured to provide a reset signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit, and the second reset signal line of the plurality of second reset signal lines Vint2, which is configured to provide a reset signal to the second reset transistor (e.g., T6) in the previous row pixel driving circuit, are located on both sides of the main line portion of the first reset control signal line of the plurality of first reset control signal lines, which is configured to provide a reset control signal to the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset transistor (e.g., T6) in the previous row pixel driving circuit. Optionally, the main line portion of the first reset control signal line in the plurality of first reset control signal lines configured to provide reset control signals to the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset transistor (e.g., T6) in the previous row pixel driving circuit is spaced apart from the first reset signal line in Vint1 configured to provide reset signals to the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset signal line in Vint2 configured to provide reset signals to the second reset transistor (e.g., T6) in the previous row pixel driving circuit.

[0139] In some embodiments, the orthographic projection of the reset signal line in the array substrate onto the substrate does not overlap with the orthographic projection of any main line portion of any reset control signal line in the array substrate onto the substrate. This can reduce interference from the reset control signal to the reset signal line.

[0140] See FIG. 3A , FIG. 3C , FIG. 3D and FIG. 3G In some embodiments, the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are configured to receive, for example, the same gate scan signal generated by the same gate scan circuit. With this unique structure, the data write transistor and the compensation transistor can share the same gate scan signal generated by the same gate scan circuit (e.g., gate circuit on the same array). This reduces the total number of scan circuits and further reduces the peripheral area of ​​the array substrate.

[0141] In some embodiments, at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are portions of an integral structure (e.g., an integral electrode block). Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is connected to gate lines in a plurality of gate lines GL. Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is in a first conductive layer, and the plurality of gate lines GL are in a first signal line layer.

[0142] FIG. 7A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 7B To show FIG. 7A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate. FIG. 7C It is shown FIG. 7A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. FIG. 7D It is shown FIG. 7A A schematic diagram of the structure of the first conductive layer in the array substrate shown. FIG. 7E It is shown FIG. 7A A schematic diagram of the structure of the second conductive layer in the array substrate shown. FIG. 7F It is shown FIG. 7A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. FIG. 7G It is shown FIG. 7A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. FIG. 7H It is shown FIG. 7A A schematic diagram of the structure of the first planarization layer in the array substrate shown. FIG. 7I It is shown FIG. 7A The diagram shows a schematic of the structure of the second signal line layer in the array substrate. FIG. 7J It is shown FIG. 7A A schematic diagram of the structure of the second planarization layer in the array substrate shown. FIG. 7K It is shown FIG. 7A A schematic diagram of the structure of the anode layer in the array substrate shown. FIG. 7L It is shown FIG. 7A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown. FIG. 8A It is alongFIG. 7A A cross-sectional view of line C-C' in the diagram. FIG. 8B It is along FIG. 7A A cross-sectional view of the D-D' line in the diagram.

[0143] Reference FIG. 2A , FIG. 2B , FIG. 7A and FIG. 7C Each pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number indicating the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes active layer ACT1, first electrode S1, and second electrode D1. Second transistor T2 includes active layer ACT2, first electrode S2, and second electrode D2. Third transistor T3 includes active layer ACT3, first electrode S3, and second electrode D3. Fourth transistor T4 includes active layer ACT4, first electrode S4, and second electrode D4. Fifth transistor T5 includes active layer ACT5, first electrode S5, and second electrode D5. Sixth transistor T6 includes active layer ACT6, first electrode S6, and second electrode D6. Driving transistor Td includes active layer ACTd, first electrode Sd, and second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0144] refer to FIG. 2A ,FIG. 2B , FIG. 7A and FIG. 7D In some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst1 (including the first reset signal line rst1N of the current stage and the first reset signal line rst1(N+1) of the next stage), a plurality of light emission control signal lines em, an electrode block including one or more gates G3 of the third transistor T3 and the gate G2 of the second transistor T2, and a first capacitor electrode Ce1 of the storage capacitor Cst.

[0145] Reference FIG. 2A , FIG. 2B , FIG. 7A and FIG. 7E In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vint1, an anti-interference block IPB, and a second capacitor electrode Ce2 of a storage capacitor Cst.

[0146] FIG. 7F The text describes vias extending through the interlayer dielectric layer (ILD).

[0147] refer to FIG. 2A , FIG. 2B , FIG. 7A and FIG. 7G In some embodiments, the first signal line layer includes node connection lines Cln, multiple constant voltage signal lines X, multiple second reset control signal lines rst2 (including the second reset control signal line rst2N of the current stage and the second reset control signal line rst2(N+1) of the next stage), multiple gate lines GL, multiple first voltage supply lines Vdd1, relay electrodes RE, and data signal connection pads DCP. The node connection lines Cln connect the first capacitor electrode Ce1 and the first electrode of the driving transistor Td in each pixel driving circuit together. The data signal connection pads DCP are configured to connect a corresponding data line among the multiple data lines to the first electrode of the second transistor T2. The relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pad is in the second signal line layer and is connected to the anode in each sub-pixel. The multiple first voltage supply lines Vdd1 are interconnected with the multiple second voltage supply lines to form an interconnected reset signal network. Each of the plurality of first voltage supply lines Vdd1 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the plurality of first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1; the plurality of second voltage supply lines extend in a direction substantially parallel to the second direction DR2.

[0148] In some embodiments, the plurality of constant voltage signal lines X can be configured to transmit any suitable constant voltage signal, such as a first reference voltage signal (high reference voltage signal) or a second reference voltage signal (low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0149] In some embodiments, a corresponding constant voltage signal line among the plurality of constant voltage signal lines X in the first signal line layer is connected to an anti-interference block IPB in the second conductive layer and is configured to provide a constant voltage signal to the anti-interference block IPB.

[0150] FIG. 7H The vias extending through the first planarization layer PLN1 are shown.

[0151] Reference FIG. 2A , FIG. 2B , FIG. 7A and FIG. 7I In some embodiments, the second signal line layer includes multiple second voltage supply lines Vdd2, multiple data lines DL, and an anode contact pad ACP. The anode contact pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit. The anode contact pad ACP is also electrically connected to the anode in each sub-pixel. The multiple second voltage supply lines Vdd2 are interconnected with multiple first voltage supply lines to form an interconnected reset signal network. Each of the multiple data lines is electrically connected via a data signal connection pad to the first electrode of the second transistor T2.

[0152] FIG. 7J The vias extending through the second planarization layer PLN2 are shown.

[0153] Reference FIG. 2A , FIG. 2B , FIG. 7A as well as FIG. 7K The array substrate also includes an anode layer (ADL). FIG. 7K The text represents multiple sub-pixel openings (SA) that correspond to multiple anodes. FIG. 7J The vias extending through the second planarization layer PLN2 are described. Each anode is connected to its corresponding anode contact pad via a corresponding via extending through the second planarization layer PLN2.

[0154] Reference FIG. 2A , FIG. 2B , FIG. 7A and FIG. 7L The array substrate also includes a pixel defining layer (PDL) that defines multiple sub-pixel openings (SA).

[0155] refer to FIG. 2A ,FIG. 2B , FIG. 7A , FIG. 7D , FIG. 7E , FIG. 7G and FIG. 8A In some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and extends the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as at least one of the following: a plurality of constant voltage signal lines X, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, a plurality of first voltage supply lines Vdd1, a relay electrode RE, and a data signal connection pad DCP.

[0156] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor, such as... FIG. 8A As shown.

[0157] In some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The third via v3 extends through the first planarization layer PLN1. The fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, corresponding data lines in a plurality of data lines DL are connected to the data signal connection pad DCP via the third via v3. The data signal connection pad DCP is connected to the first electrode S2 of the second transistor via the fourth via v4.

[0158] Reference FIG. 2A , FIG. 2B , FIGS. 7A-7I as well as FIG. 8BIn some embodiments, the array substrate further includes a fifth via v5, a sixth via v6, a seventh via v7, and an eighth via v8. The fifth via v5 extends through the first planarization layer PLN1. The sixth via v6 and the seventh via v7 extend through the interlayer dielectric layer ILD, respectively. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding second voltage supply line among the plurality of second voltage supply lines Vdd2 is connected to a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 via the fifth via v5. Optionally, a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 is connected to the second capacitor electrode Ce2 of the storage capacitor Cst via one or more vias (e.g., the sixth via v6 and the seventh via v7). Optionally, a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd1 is connected to the first electrode S4 of the fourth transistor T4 via the eighth via v8.

[0159] refer to FIG. 7A , FIG. 7E and FIG. 8A In some embodiments, the second capacitor electrode Ce2 includes a body MB and an extension E extending away from the body MB. In some embodiments, the extension E includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 connects the body MB and the second portion P2, and the second portion P2 connects the first portion P1 and the third portion P3. Optionally, the first portion P1 and the third portion P3 extend along a direction substantially parallel to the second direction DR2. Optionally, the second portion P2 extends along a direction substantially parallel to the first direction DR1. In some embodiments, the orthographic projection of the third portion P3 onto the substrate BS at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the third transistor T3 onto the substrate BS. The inventors of this disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0160] Reference FIG. 7A , FIG. 7C , FIG. 7E and FIG. 7GIn some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 are located in the same layer. Optionally, the anti-interference block IPB is connected to a constant voltage signal line among a plurality of constant voltage signal lines X and is configured to receive a constant voltage signal. In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate BS. Optionally, the orthographic projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate BS does not overlap with the orthographic projection of any reset signal line on the substrate. The inventors of this disclosure have found that this unique structure enhances the stability of the first transistor T1.

[0161] Reference FIG. 7A , FIG. 7C , FIG. 7E , FIG. 7G and FIG. 8A In some embodiments, the node connection line Cln is positioned between each gate line in the plurality of gate lines GL and the capacitor electrode of the storage capacitor, connected to the second electrode D3 of the third transistor T3. Optionally, the orthographic projection of the node connection line Cln on the substrate BS does not overlap with the orthographic projection of the corresponding gate line GL in the plurality of gate lines GL on the substrate BS. Optionally, the orthographic projection of the second electrode D3 of the third transistor T3 on the substrate BS partially overlaps with the orthographic projection of the corresponding gate line in the plurality of gate lines GL on the substrate BS. The inventors of this disclosure have found that this unique structure reduces or prevents interference from gate scan signals transmitted in the respective gate lines to the node connection line Cln (corresponding to the first node N1). Furthermore, the length of the node connection line Cln can be reduced, thereby reducing potential interference from data signals transmitted in the respective data lines of the plurality of data lines SL to the node connection line Cln (corresponding to the first node N1).

[0162] Reference FIG. 7A , FIG. 7C , FIG. 7E , FIG. 7G and FIG. 7IIn some embodiments, the second capacitor electrode Ce2 spaces the first node N1 in each pixel driving circuit from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 spaces the node connection line Cln from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 includes an extension E; and the extension E spaces the second electrode D3 of the third transistor T3 (connected to the node connection line Cln) from each of the plurality of data lines DL configured to provide data signals to each pixel driving circuit. The inventors of this disclosure have found that this unique structure reduces interference from data signals transmitted in each of the plurality of data lines SL to the node connection line Cln (corresponding to the first node N1) and the second electrode D3 of the third transistor T3.

[0163] See FIG. 7A , FIG. 7C , FIG. 7D and FIG. 7G In some embodiments, the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are configured to receive the same reset control signal.

[0164] In some embodiments, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are part of an integral structure. Optionally, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are portions of the same reset control signal line.

[0165] In some embodiments, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction substantially parallel to the extension direction of the reset control signal line of the array substrate. Optionally, the gates of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction substantially parallel to the first direction DR1.

[0166] In some embodiments, the gate of the first reset transistor (e.g., T1) includes a first portion of a corresponding first reset control signal line from a plurality of first reset control signal lines and a second portion of a corresponding second reset control signal line from a plurality of second reset control signal lines.

[0167] In some embodiments, the orthographic projection of a corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate at least partially overlaps with the orthographic projection of a corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

[0168] In some embodiments, the orthographic projection of a first portion of the gate of the first reset transistor from a plurality of first reset control signal lines on the substrate at least partially overlaps with the orthographic projection of a second portion of the gate of the first reset transistor from a plurality of second reset control signal lines on the substrate.

[0169] The inventors of this disclosure have discovered that by providing two reset control signal lines for the reset control signal, the resistance of the reset control signal lines can be reduced, and the drive power of the reset control signal lines can be ensured. With this unique structure, the first reset transistor and the second reset transistor can share the same reset control signal generated by the same reset control generation circuit. This reduces the total number of scan circuits and further reduces the peripheral area of ​​the array substrate.

[0170] See FIG. 7A , FIG. 7C , FIG. 7D and FIG. 7G In some embodiments, the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are configured to receive, for example, the same gate scan signal generated by the same gate scan circuit. With this unique structure, the data write transistor and the compensation transistor can share the same gate scan signal generated by the same gate scan circuit (e.g., gate circuit on the same array). This reduces the total number of scan circuits and further reduces the peripheral area of ​​the array substrate.

[0171] In some embodiments, at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are portions of an integral structure (e.g., an integral electrode block). Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is connected to gate lines in a plurality of gate lines GL. Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is in a first conductive layer, and the plurality of gate lines GL are in a first signal line layer.

[0172] FIG. 9A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 9B To show FIG. 9A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate. FIG. 9C It is shown FIG. 9A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. Figure 9D It is shown Figure 9A A schematic diagram of the structure of the first conductive layer in the array substrate shown. Figure 9E It is shown Figure 9A A schematic diagram of the structure of the second conductive layer in the array substrate shown. Figure 9F It is shown Figure 9A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. Figure 9G It is shown Figure 9A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 9H It is shown Figure 9A A schematic diagram of the structure of the first planarization layer in the array substrate shown. Figure 9I It is shown Figure 9A The diagram shows a schematic of the structure of the second signal line layer in the array substrate. Figure 9J It is shown Figure 9A A schematic diagram of the structure of the second planarization layer in the array substrate shown. Figure 9K It is shown Figure 9A A schematic diagram of the structure of the anode layer in the array substrate shown. Figure 9L It is shown Figure 9A A schematic diagram of the structure of the pixel-defining layer in the array substrate shown.

[0173] like Figure 9C , Figure 9D , Figure 9E and Figure 9K The structure of the semiconductor material layer, the first conductive layer, the second conductive layer, and the anode layer shown is similar to... Figure 3C , Figure 3D , Figure 3E and Figure 3K The structures shown are basically similar.

[0174] refer to Figure 2A , Figure 2B , Figure 9A and Figure 9G ,and Figure 3G Compared to the structure shown, in some embodiments, the first signal line layer further includes a plurality of third voltage supply lines Vss1. Optionally, the plurality of third voltage supply lines Vss1 extend along a direction substantially parallel to the first direction DR1. In some embodiments, the plurality of first voltage supply lines Vdd1 and the plurality of second voltage supply lines Vdd2 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of third voltage supply lines Vss1 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal).

[0175] like Figure 9G As shown, in some embodiments, the first signal line layer includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2. Optionally, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1.

[0176] In some embodiments, the orthographic projection of a corresponding third voltage supply line among the plurality of third voltage supply lines Vss1 onto the substrate lies between the orthographic projection of a corresponding light emission control signal line among the plurality of light emission control signal lines em onto the substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines Vint2 onto the substrate. The inventors of this disclosure have discovered that this unique arrangement minimizes interference from the second reference voltage signal from the plurality of third voltage supply lines Vss1 to nearby nodes.

[0177] refer to Figure 2A , Figure 2B , Figure 9A and Figure 9I ,and Figure 3ICompared to the structure shown, in some embodiments, the second signal line layer further includes a plurality of fourth voltage supply lines Vss2, a plurality of third reset signal lines Vint3, and a plurality of fourth reset signal lines Vint4. Optionally, the plurality of fourth voltage supply lines Vss2, the plurality of third reset signal lines Vint3, and the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. In some embodiments, a plurality of first voltage supply lines Vdd1 and a plurality of second voltage supply lines Vdd2 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and a plurality of third voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal).

[0178] Figure 10 This is a schematic diagram illustrating a voltage supply network in an array substrate according to some embodiments of the present disclosure. Reference Figure 10 In some embodiments, the voltage supply network includes a plurality of third voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2 interconnected with each other. Optionally, the plurality of third voltage supply lines Vss1 extend along a direction substantially parallel to a first direction DR1. Optionally, the plurality of fourth voltage supply lines Vss2 extend along a direction substantially parallel to a second direction DR2. Optionally, the plurality of third voltage supply lines Vss1 are in a first signal line layer. Optionally, the plurality of fourth voltage supply lines Vss2 are in a second signal line layer. Optionally, each third voltage supply line in the plurality of third voltage supply lines Vss1 is connected to one or more fourth voltage supply lines in the plurality of fourth voltage supply lines Vss2. Optionally, each fourth voltage supply line in the plurality of fourth voltage supply lines Vss2 is connected to one or more third voltage supply lines in the plurality of third voltage supply lines Vss1.

[0179] Figure 11 This is a schematic diagram illustrating a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 11In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to a second direction DR2. Optionally, the plurality of first reset signal lines Vint1 are located in a first signal line layer. Optionally, the plurality of third reset signal lines Vint3 are located in a second signal line layer. Optionally, each first reset signal line in the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each third reset signal line in the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1.

[0180] Reference Figure 11 In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, the plurality of second reset signal lines Vint2 are located in a first signal line layer. Optionally, the plurality of fourth reset signal lines Vint4 are located in a second signal line layer. Optionally, each second reset signal line in the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each fourth reset signal line in the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0181] See Figure 9I , Figure 10 and Figure 11 In some embodiments, a plurality of fourth voltage supply lines Vss2, a plurality of third reset signal lines Vint3, and a plurality of fourth reset signal lines Vint4 are arranged alternately along a first direction DR1. In one example, the fourth voltage supply lines in the plurality of fourth voltage supply lines Vss2, the reset signal lines in the plurality of third reset signal lines Vint3, and the fourth reset signal lines in the plurality of fourth reset signal lines Vint4 are arranged sequentially along the first direction DR1. In another example, the reset signal lines in the plurality of third reset signal lines Vint3, the fourth voltage supply lines in the plurality of fourth voltage supply lines Vss2, and the fourth reset signal lines in the plurality of fourth reset signal lines Vint4 are arranged sequentially along the first direction DR1.

[0182] In some embodiments, a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines Vss2 is configured among the plurality of data lines DL to provide a data signal between two adjacent data lines of two adjacent columns of pixel driving circuits, and is configured among the plurality of second voltage supply lines Vdd2 to provide a first reference voltage signal between two adjacent second voltage supply lines of two adjacent columns of pixel driving circuits. In some embodiments, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is configured among the plurality of data lines DL to provide a data signal between two adjacent data lines of two adjacent columns of pixel driving circuits, and is configured among the plurality of second voltage supply lines Vdd2 to provide a first reference voltage signal between two adjacent second voltage supply lines of two adjacent columns of pixel driving circuits. In some embodiments, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is configured among the plurality of data lines DL to provide a data signal between two adjacent data lines of two adjacent columns of pixel driving circuits, and is configured among the plurality of second voltage supply lines Vdd2 to provide a first reference voltage signal between two adjacent second voltage supply lines of two adjacent columns of pixel driving circuits.

[0183] Figure 12 This is a schematic diagram illustrating the connection of signal lines in the display area and signal lines in the peripheral area of ​​an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 12 In some embodiments, the array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the array substrate in a display panel where the actual image is displayed. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the array substrate in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display device, non-transparent or opaque components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0184] In some embodiments, the array substrate includes a first peripheral voltage supply line PVdd located in the peripheral region PA. A plurality of second voltage supply lines Vdd2 located in the display region DA are respectively connected to the first peripheral voltage supply line PVdd located in the peripheral region PA. Optionally, the first peripheral voltage supply line PVdd includes a first sublayer in a first signal line layer and a second sublayer in a second signal line layer.

[0185] In some embodiments, the array substrate includes a second peripheral voltage supply line PVss located in the peripheral region PA. A plurality of fourth voltage supply lines Vss2 located in the display region DA are respectively connected to the second peripheral voltage supply line PVss located in the peripheral region PA. Optionally, the second peripheral voltage supply line PVss is located in the first signal line layer.

[0186] In some embodiments, the array substrate includes a first peripheral reset signal line PVint1 located in the peripheral region PA. A plurality of third reset signal lines Vint3 located in the display region DA are respectively connected to the first peripheral reset signal line PVint1 located in the peripheral region PA. Optionally, the first peripheral reset signal line PVint1 is located in a first signal line layer.

[0187] In some embodiments, the array substrate includes a second peripheral reset signal line PVint2 located in the peripheral region PA. A plurality of fourth reset signal lines Vint4 located in the display region DA are respectively connected to the second peripheral reset signal line PVint2 located in the peripheral region PA. Optionally, the second peripheral reset signal line PVint2 is located in the first signal line layer.

[0188] Figure 13 This is a schematic diagram illustrating the connection of signal lines in the display area and signal lines in the peripheral area of ​​an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 13 Multiple first reset signal lines Vint1 located in the display area DA are respectively connected to first peripheral reset signal lines PVint1 located in the peripheral area PA. Optionally, a corresponding first reset signal line among the multiple first reset signal lines Vint1 is connected to the first peripheral reset signal line PVint1 via a first connection line cl1. In one example, the first connection line cl1 is located in the first conductive layer, the first peripheral reset signal line PVint1 is located in the first signal line layer, and the multiple first reset signal lines Vint1 are located in the first signal line layer.

[0189] In some embodiments, a plurality of second reset signal lines Vint2 located in the display area DA are respectively connected to a second peripheral reset signal line PVint2 located in the peripheral area PA. Optionally, a corresponding second reset signal line among the plurality of second reset signal lines Vint2 is connected to the second peripheral reset signal line PVint2 via a second connecting line cl2. In one example, the second connecting line cl2 is located in a second conductive layer, the second peripheral reset signal line PVint2 is located in a first signal line layer, and the plurality of second reset signal lines Vint2 are located in the first signal line layer.

[0190] In some embodiments, a plurality of third voltage supply lines Vss1 located in the display area DA are respectively connected to a second peripheral voltage supply line PVss located in the peripheral area PA. Optionally, a corresponding third voltage supply line among the plurality of third voltage supply lines Vss1 is connected to the second peripheral voltage supply line PVss via a third connection line cl3. In one example, the third connection line cl3 is located in the second conductive layer, the second peripheral voltage supply line PVss is located in the first signal line layer, and the plurality of third voltage supply lines Vss1 are located in the first signal line layer.

[0191] Figure 14 This is a schematic diagram illustrating a voltage supply network, a first reset signal network, a second reset signal network, and an anode layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 14 In some embodiments, the vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network are substantially outside the region of the plurality of sub-pixel openings SA. In some embodiments, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the conductive material in the vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network on the substrate.

[0192] In some embodiments, the array substrate includes a plurality of first connection vias cv1, which are respectively connected to a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3. Optionally, the plurality of first connection vias cv1 are substantially outside the regions of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the conductive material in the plurality of first connection vias cv1 on the substrate.

[0193] In some embodiments, the array substrate includes a plurality of second connection vias cv2, which are respectively connected to a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4. Optionally, the plurality of second connection vias cv2 are substantially outside the regions of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the conductive material in the plurality of second connection vias cv2 on the substrate.

[0194] In some embodiments, the array substrate includes a plurality of third connection vias cv3 that respectively connect a plurality of third voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2. Optionally, the plurality of third connection vias cv3 are substantially outside the regions of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the conductive material in the plurality of third connection vias cv3 on the substrate.

[0195] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0196] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a pixel driving circuit having a first reset transistor and a second reset transistor. Optionally, at least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the preceding row pixel driving circuit are part of an integral structure. Optionally, the gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the preceding row pixel driving circuit are arranged along a direction not parallel to the extension direction of the reset control signal line.

[0197] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising a pixel driving circuit having a first reset transistor and a second reset transistor; in, At least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit are part of an overall structure. as well as The gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the previous row pixel driving circuit are arranged in a direction that is not parallel to the extension direction of the reset control signal line.

2. The array substrate according to claim 1, wherein, The channel direction of the first reset transistor is not parallel to the channel direction of the second reset transistor; and The channel directions of the first reset transistor and the second reset transistor intersect each other, forming a non-zero angle.

3. The array substrate according to claim 1 further includes a plurality of first reset signal lines, a plurality of second reset control signal lines, and a plurality of second reset signal lines; in, The plurality of second reset control signal lines includes the second reset control signal line of the current stage; In the same row of pixel driving circuits, the orthographic projection of the corresponding first reset signal line among the plurality of first reset signal lines on the substrate is located between the orthographic projection of the second reset control signal line of the current stage on the substrate and the orthographic projection of the corresponding second reset signal line among the plurality of second reset signal lines on the substrate.

4. The array substrate according to claim 1, wherein, The pixel driving circuit also includes a data writing transistor, a compensation transistor, and a driving transistor; The array substrate includes a semiconductor material layer; The semiconductor material layer includes: A continuous line comprising the active layer and second electrode of the compensation transistor and the second electrode of the first reset transistor; and A branch that arises from the continuous line; Wherein, the branch is connected to the gate of the driving transistor; and The orthographic projection of the branch on the substrate does not overlap with the orthographic projection of the electrode block, including the gate of the data writing transistor and the gate of the compensation transistor, on the substrate.

5. The array substrate according to claim 4, further comprising a plurality of first reset control signal lines; in, Each of the plurality of first reset control signal lines includes a main line portion extending along a direction substantially parallel to a first direction, and a protrusion extending in a direction substantially parallel to a second direction away from the main line portion, the second direction being different from the first direction; The protrusion includes at least a portion of the gate of the second reset transistor in the preceding row pixel driving circuit; and The main line portion includes at least a portion of the gate of the first reset transistor in the current row pixel driving circuit.

6. The array substrate according to claim 1 further includes a plurality of first reset control signal lines and a plurality of second reset control signal lines; in, The gate of the first reset transistor includes a first portion of a corresponding first reset control signal line from the plurality of first reset control signal lines and a second portion of a corresponding second reset control signal line from the plurality of second reset control signal lines; as well as The orthographic projection of the first portion onto the substrate overlaps at least partially with the orthographic projection of the second portion onto the substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising a voltage supply network; in, The voltage supply network includes multiple third voltage supply lines and multiple fourth voltage supply lines; Each of the plurality of third voltage supply lines is connected to one or more of the plurality of fourth voltage supply lines; as well as Each of the plurality of fourth voltage supply lines is connected to one or more of the plurality of third voltage supply lines; The plurality of third voltage supply lines are located in the first signal line layer; the first signal line layer includes a plurality of first voltage supply lines; as well as The plurality of fourth voltage supply lines are located in the second signal line layer, which is located on the side of the first signal line layer away from the substrate.

8. The array substrate according to claim 7 further includes a plurality of light emission control signal lines and a plurality of second reset signal lines; in, The orthographic projection of the corresponding third voltage supply line among the plurality of third voltage supply lines on the substrate is located between the orthographic projection of the corresponding light emission control signal line among the plurality of light emission control signal lines on the substrate and the orthographic projection of the corresponding second reset signal line among the plurality of second reset signal lines on the substrate.

9. The array substrate according to any one of claims 1 to 6, further comprising a first reset signal network and a second reset signal network; in, The first reset signal network includes multiple first reset signal lines and multiple third reset signal lines; The second reset signal network includes multiple second reset signal lines and multiple fourth reset signal lines; Each of the plurality of first reset signal lines is connected to one or more of the plurality of third reset signal lines; Each of the plurality of third reset signal lines is connected to one or more of the plurality of first reset signal lines; Each of the plurality of second reset signal lines is connected to one or more of the plurality of fourth reset signal lines; and Each of the plurality of fourth reset signal lines is connected to one or more of the plurality of second reset signal lines.

10. The array substrate according to any one of claims 1 to 6, further comprising a plurality of data lines, a plurality of second voltage supply lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, and a plurality of fourth voltage supply lines; in, The respective fourth voltage supply line of the plurality of fourth voltage supply lines is located between two adjacent data lines of the plurality of data lines that are configured to provide data signals to two adjacent column pixel driving circuits, and is located between two adjacent second voltage supply lines of the plurality of second voltage supply lines that are configured to provide a first reference voltage signal to two adjacent column pixel driving circuits. The corresponding third reset signal line of the plurality of third reset signal lines is located between two adjacent data lines of the plurality of data lines configured to provide data signals to adjacent two columns of pixel driving circuits, and is located between two adjacent second voltage supply lines of the plurality of second voltage supply lines configured to provide first reference voltage signals to adjacent two columns of pixel driving circuits; and The respective fourth reset signal line of the plurality of fourth reset signal lines is located between two adjacent data lines of the plurality of data lines that are configured to provide data signals to adjacent two columns of pixel driving circuits, and is located between two adjacent second voltage supply lines of the plurality of second voltage supply lines that are configured to provide first reference voltage signals to adjacent two columns of pixel driving circuits.

11. The array substrate according to claim 5, wherein, The pixel driving circuit also includes a storage capacitor and a compensation transistor; The storage capacitor includes a first capacitor electrode and a second capacitor electrode. The second capacitor electrode is configured to be supplied with a first reference voltage signal; The orthographic projection of the overall structure including the second capacitor electrode on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

12. The array substrate according to claim 11, wherein, The overall structure including the second capacitor electrode includes a body and an extension extending away from the body; The extension includes a first part, a second part, and a third part; The first part connects the main body and the second part; The second part connects the first part and the third part; The first portion and the third portion extend in directions substantially parallel to the second direction; as well as The second portion extends in a direction substantially parallel to the first direction.

13. The array substrate according to claim 12, wherein, The orthographic projection of the third portion on the substrate at least partially overlaps with the orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

14. The array substrate according to claim 11, further comprising node connection lines and a plurality of gate lines; in, The node connection line is connected to the second electrode of the compensation transistor at a position between the corresponding gate line of the plurality of gate lines and the capacitor electrode of the storage capacitor; The orthogonal projection of the node connection line on the substrate does not overlap with the orthogonal projection of the plurality of gate lines on the substrate. as well as The orthographic projection of the second electrode of the compensation transistor on the substrate partially overlaps with the orthographic projection of the corresponding gate line on the substrate.

15. The array substrate according to claim 11, further comprising node connection lines and a plurality of data lines; in, The second capacitor electrode separates the node connection line from the corresponding data line among the plurality of data lines configured to provide data signals to the pixel driving circuit.

16. The array substrate according to claim 12, further comprising node connection lines and a plurality of data lines; in, The extension spacees the node connection line from the corresponding data line among the plurality of data lines that is configured to provide data signals to the pixel driving circuit.

17. The array substrate according to claim 4 or 5, further comprising a shielding block and a plurality of first reset signal lines; in, The pixel driving circuit also includes a compensation transistor; The shielding block is connected to a corresponding first reset signal line among the plurality of first reset signal lines; as well as The orthographic projection of the shielding block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor on the substrate.

18. The array substrate according to any one of claims 1 to 6, wherein, The pixel driving circuit also includes a compensation transistor and a data writing transistor; In this configuration, at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit are part of the overall structure.

19. The array substrate according to claim 18, further comprising a plurality of gate lines; in, The overall structure, including at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data write transistor in the previous column pixel driving circuit, is connected to one of the plurality of gate lines.

20. The array substrate according to claim 4 or 5, further comprising an anti-interference block and a plurality of second reset signal lines; in, The anti-interference block is connected to a corresponding second reset signal line among the plurality of second reset signal lines; and The orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

21. The array substrate according to claim 4 or 5, further comprising an anti-interference block and a plurality of constant voltage signal lines; in, The anti-interference block is connected to the corresponding constant voltage signal line among the plurality of constant voltage signal lines; The plurality of constant voltage signal lines are configured to provide constant voltage signals to the anti-interference block; as well as The orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

22. The array substrate according to any one of claims 1 to 6, further comprising a voltage supply network, a first reset signal network, a second reset signal network, and a pixel defining layer defining a plurality of sub-pixel openings; in, The voltage supply network includes multiple third voltage supply lines and multiple fourth voltage supply lines; The first reset signal network includes multiple first reset signal lines and multiple third reset signal lines; The second reset signal network includes multiple second reset signal lines and multiple fourth reset signal lines; The vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network are substantially located outside the area of ​​the plurality of sub-pixel openings; as well as The orthographic projection of the pixel defining layer on the substrate substantially covers the orthographic projection of the conductive material in the via connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network on the substrate.

23. A display device comprising an array substrate according to any one of claims 1 to 22 and one or more integrated circuits connected to the array substrate.

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