Method and system for operating PNP bidirectional double-base bipolar junction transistor

Abstract

The present disclosure relates to operating a PNP dual-side dual-base bipolar junction transistor (DSDB.BJT). One example is a method of operating a DSDB-BJT, the method including: conducting a first load current from an upper terminal of a power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then in response to assertion of a first interrupt signal, interrupting the first load current from the lower base to the lower terminal by opening a lower main FET and reversing a first turn-off current to the lower terminal through a lower collector-emitter of the transistor; and blocking a current from the upper terminal to the lower terminal by the transistor.

Description

[0001] Related Applications Cross Reference

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 382,924, filed on November 9, 2022, and entitled “Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor (B-TRAN)” which is incorporated herein by reference as if reproduced in its entirety below. Background Art

[0003] A double-sided double base (DSDB) bipolar junction transistor (BJT) (hereinafter referred to as a DSDB-BJT) is a junction transistor that is constructed with a base and a collector-emitter on a first side of a bulk region, and a different and separate base and collector-emitter on a second side of the bulk region opposite the first side. When properly configured by an external driver, current can selectively flow through the collector-emitter of the DSDB-BJT in either direction, and thus the DSDB-BJT device is considered a bidirectional device. Based on the bidirectionality, whether the collector-emitter is considered a collector or an emitter depends on the polarity of the applied external voltage and therefore depends on the direction of the current flowing through the DSDB-BJT.

[0004] A DSDB-BJT device can be configured as an NPN device, which is normally off or normally non-conducting from the upper collector-emitter to the lower collector-emitter (and vice versa). A DSDB-BJT device can also be configured as a PNP device, which is normally on or normally conducting from the upper collector-emitter to the lower collector-emitter (and vice versa). Summary of the invention

[0005] At least one example is a method of operating a power module having a bidirectional dual-base bipolar junction transistor, the method comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then in response to assertion of a first interrupt signal, interrupting the first load current from the lower base to the lower terminal by disconnecting a lower main FET and commutating a first off current to the lower terminal through a lower collector-emitter of the transistor; and blocking current from the upper terminal to the lower terminal through the transistor.

[0006] In the exemplary method, during the conduction, the method further includes injecting charge carriers into an upper collector-emitter, and the method may further include, in response to the assertion of the first interrupt signal, stopping the injection of charge carriers into the upper collector-emitter. Stopping the injection of charge carriers may further include stopping the injection of charge carriers for a non-zero predetermined time before the interruption of the first load current by turning off the lower main FET.

[0007] In the exemplary method: interrupting the first load current may further include interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less; and blocking current may further include blocking at an applied voltage of 600 volts or more across the upper terminal and the lower terminal.

[0008] In the exemplary method, commutating the first off current may further include coupling the lower collector-emitter to the lower terminal. Coupling the lower collector-emitter to the lower terminal may further include coupling the lower collector-emitter to the lower terminal via a voltage source or a current source.

[0009] The exemplary method may further include, after blocking current from the upper terminal to the lower terminal: conducting a second load current from the lower terminal of the power module to the lower base, through the transistor, and from the upper base to the upper terminal; and then in response to assertion of a second interrupt signal, interrupting the second load current from the upper base to the upper terminal by disconnecting an upper main FET and commutating a second off current to the upper terminal through an upper collector-emitter; and blocking current from the lower terminal to the upper terminal through the transistor. Interrupting the second load current may further include interrupting the second load current using the upper main FET having a breakdown voltage of 100 volts or less, and blocking current from the lower terminal to the upper terminal may further include blocking at an applied voltage of 600 volts or more across the lower terminal and the upper terminal.

[0010] Another example is a switch assembly comprising: an upper terminal, a lower terminal and an upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper base and a gate; a lower main FET defining a first lead coupled to the lower base, a second lead coupled to the lower terminal and a gate; and a controller coupled to the upper control input, the gate of the upper main FET and the gate of the lower main FET, and for a first applied voltage across the upper terminal and the lower terminal. The controller may be configured to: assert the gate of the upper main FET to render the upper main FET conductive, arrange the transistor for conduction from the upper base to the lower base, and assert the gate of the lower main FET to render the lower main FET conductive such that a first load current flows from the upper terminal to the lower terminal; sense de-assertion of the upper control input; and in response to de-assertion of the upper control input, de-assert the gate of the lower main FET to interrupt the first load current from the lower base.

[0011] In the exemplary switch assembly, the breakdown voltage of the transistor may be 600 volts or more, and the breakdown voltage of the lower main FET may be 100 volts or less.

[0012] In the exemplary switch assembly, the breakdown voltage of the transistor may be approximately 1200 volts, and the breakdown voltage of the lower main FET may be 80 volts or less.

[0013] The exemplary switch assembly may further include: an upper CE source and an upper CE FET, the upper CE source being arranged to selectively inject charge carriers into the upper collector-emitter through the upper CE FET; and when the controller arranges the transistor for conduction from the upper base to the lower base, the controller is further configured to make the upper CE FET conductive, thereby injecting charge carriers into the upper collector-emitter; and wherein when the controller senses de-assertion of the upper control input, the controller is further configured to make the upper CE FET non-conductive, thereby ceasing to inject charge carriers into the upper collector-emitter. When the controller makes the upper CE FET non-conductive, the controller may be configured to make the upper CE FET non-conductive for a non-zero predetermined time period before de-asserting the gate of the lower main FET. When the controller senses de-assertion of the upper control input, the controller may be further configured to electrically float the upper collector-emitter.

[0014] The exemplary switch assembly may further include: a lower CE FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate coupled to the controller; wherein when the controller senses de-assertion of the upper control input, the controller is further configured to assert the gate of the lower CE FET, thereby commutating an off current to the lower terminal. The switch assembly may further include: a lower CE source arranged to selectively extract charge carriers from the lower collector-emitter through the lower CE FET; wherein when the controller senses de-assertion of the upper control input, the controller may be further configured to render the lower CE FET conductive, thereby extracting charge carriers from the lower collector-emitter.

[0015] The exemplary switch assembly may further include: a lower control input coupled to the controller; and wherein for a second applied voltage across the upper terminal and the lower terminal, the second applied voltage has a polarity opposite to the first applied voltage, the controller may be further configured to: assert the gate of the lower main FET to make the lower main FET conductive, arrange the transistor for conduction from the lower base to the upper base, and assert the gate of the upper main FET to make the upper main FET conductive so that a second load current flows from the lower terminal to the upper terminal; sense de-assertion of the lower control input; and in response to de-assertion of the lower control input, de-assert the gate of the upper main FET to interrupt the second load current from the upper base. The exemplary switch assembly may further include: a lower CE source and a lower CE FET, the lower CE source being arranged to selectively inject charge carriers into the lower collector-emitter through the lower CE FET; and wherein when the controller arranges the transistor for conduction from the lower base to the upper base, the controller may be further configured to render the lower CE FET conductive, thereby injecting charge carriers into the lower collector-emitter; and wherein when the controller senses the de-assertion of the lower control input, the controller may be further configured to render the lower CE FET non-conductive, thereby ceasing to inject charge carriers into the lower collector-emitter.

[0016] Another example is a second exemplary method of operating a bidirectional dual base bipolar junction transistor, the method comprising: rendering the transistor conductive from an upper base to a lower base by supplying current to an upper collector-emitter of the transistor and electrically floating a lower collector-emitter of the transistor; and then rendering the transistor non-conductive by electrically floating the upper collector-emitter, electrically floating the lower base, and conducting an off current through the lower collector-emitter of the transistor.

[0017] In the second exemplary method, electrically floating the lower base may further include rendering a lower main electrical control switch having a first lead coupled to the lower base non-conductive.

[0018] In the second exemplary method, rendering the transistor conductive may further include: closing an upper main electrical control switch coupled between an upper terminal and the upper base; and closing a lower main electrical control switch coupled between a lower terminal and the lower base. Rendering the transistor non-conductive may further include: opening the upper main electrical control switch;

[0019] The off current is conducted to the upper base through a diode associated with the upper main electrical control switch; and the off current is commutated from the lower base to the lower collector-emitter by opening the lower main electrical control switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To describe in detail exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0021] Figure 1 Shows a partial block diagram and partial electrical schematic of a power module using NPN DSDB-BJT;

[0022] Figure 2 Shows a partial block diagram and partial electrical schematic of a power module using PNP DSDB-BJT;

[0023] Figure 3 A partial block diagram, partial electrical schematic diagram showing a power module using a PNP DSDB-BJT according to at least some embodiments;

[0024] Figure 4 shows a cross-sectional elevation view of a PNP DSDB-BJT according to at least some embodiments;

[0025] Figures 5A to 5G An NPN DSDB-BJT is shown in shorthand form with exemplary external electrical connections to illustrate several operating states of the NPN DSDB-BJT in accordance with at least some embodiments;

[0026] Figure 6 A partial block diagram, partial electrical schematic diagram showing a switch assembly according to at least some embodiments;

[0027] Figure 7 A partial electrical schematic diagram showing an exemplary switch assembly according to at least some embodiments;

[0028] Figure 8 presenting methods according to at least some embodiments; and

[0029] Fig. 9 Methods according to at least some embodiments are presented.

[0030] definition

[0031] Various terms are used to refer to specific system components. Different companies may refer to components by different names, and this document is not intended to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended manner, and thus should be interpreted to mean "including, but not limited to...". In addition, the terms "couple" or "couples" are intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.

[0032] "About" with respect to a stated parameter shall mean the stated parameter plus or minus ten percent (+ / - 10%) of the stated parameter.

[0033] "Asserting" shall mean creating or maintaining a first predetermined state of a Boolean signal. At the discretion of the circuit designer, a Boolean signal may be asserted high or with a higher voltage, and a Boolean signal may be asserted low or with a lower voltage. Similarly, "de-asserting" shall mean creating or maintaining a second predetermined state of a Boolean, which is opposite to the asserted state.

[0034] "FET" shall mean a field effect transistor such as a junction gate FET (JFET) or a metal oxide silicon FET (MOSFET).

[0035] "Closing" with respect to an electrically controlled switch (eg, a FET) shall mean making the electrically controlled switch conductive. For example, closing a FET used as an electrically controlled switch may mean driving the FET to a fully conductive state.

[0036] "Opening" with respect to an electrically controlled switch (eg, a FET) shall mean rendering the electrically controlled switch non-conductive.

[0037] "Double-sided dual-base bipolar junction transistor" shall mean a junction transistor having a base and collector-emitter on a first face or side of a bulk region and a base and collector-emitter on a second face or side of the bulk region. The base and collector-emitter on the first side are different from the base and collector-emitter on the second side.

[0038] The "collector-emitter region" of a PNP bidirectional device shall mean a P-type doped region that forms a junction with an N-type doped bulk substrate and / or base region. + ) should not be considered as different doping types.

[0039] "Collector-emitter" shall mean an electrical pin or terminal directly coupled to the collector-emitter region. The presence of intervening wire bonds and bond pads shall not preclude the collector-emitter from being directly coupled to the collector-emitter region.

[0040] "Upper collector-emitter" shall mean the collector-emitter of a double-sided double base bipolar junction transistor located on a first side of the bulk region of the transistor, and shall not be construed to imply the position of the collector-emitter relative to gravity.

[0041] "Lower collector-emitter" shall mean the collector-emitter of a double-sided double base bipolar junction transistor located on a second side of the bulk region of the transistor opposite the first side, and shall not be construed as implying the position of the collector-emitter relative to gravity.

[0042] The "base region" of a PNP bidirectional device shall mean the N-type doped region adjacent to the N-type doped bulk substrate. + ) should not be considered as different doping types.

[0043] "Base" shall mean an electrical pin or terminal that is directly coupled to the base region. The presence of intervening wire bonds and bond pads shall not preclude direct coupling of the base to the base region.

[0044] "Upper base" shall mean the base of a double-sided double base bipolar junction transistor that is located on a first side of the transistor, and shall not be construed as implying the position of the base relative to gravity.

[0045] "Lower base" shall mean the base of a double-sided double base bipolar junction transistor that is located on a second side of the transistor opposite to the first side, and shall not be construed as implying a position of the base relative to gravity.

[0046] The terms "input" and "output" when used as nouns refer to connections (e.g., electrical, software), and should not be construed as verbs requiring action. For example, a timer circuit may define a clock output. An exemplary timer circuit may create or drive a clock signal on the clock output. In a system implemented directly in hardware (e.g., on a semiconductor substrate), these "inputs" and "outputs" define electrical connections. In a system implemented in software, these "inputs" and "outputs" define parameters that are read or written, respectively, by instructions that implement a function.

[0047] “Controller” shall mean, alone or in combination, an individual circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing device (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC) that is configured to read inputs and drive outputs in response to the inputs. DETAILED DESCRIPTION

[0048] The following discussion is directed to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it will be understood by those skilled in the art that the following description has broad application, and the discussion of any embodiment is intended only to be exemplary of the embodiment, and is not intended to imply that the scope of the present disclosure, including the claims, is limited to the embodiment.

[0049] Various examples are directed to methods and systems for operating a PNP double-sided double base (DSDB) bipolar junction transistor (BJT) (hereinafter referred to as DSDB-BJT). The specification first turns to the related technical methods and systems for operating an NPN DSDB-BJT. Co-pending and commonly assigned U.S. Application No. 17 / 537,726, filed on November 30, 2021, describes a power module using a DSDB-BJT device, wherein the main current flowing through the DSDB-BJT device is from an upper collector-emitter to a lower collector-emitter, and vice versa. Figure 1 A partial block diagram and a partial electrical schematic diagram of a power module using a DSDB-BJT in an NPN configuration are shown. Specifically, Figure 11 is a DSDB-BJT 100 that defines an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. As shown by the circuit symbol, the DSDB-BJT 100 has an NPN configuration. A DSDB-BJT of an NPN configuration is a normally off or normally non-conductive device. In order to arrange the DSDB-BJT 100 to selectively conduct in either direction, the DSDB-BJT 100 is associated with a driver circuit. In particular, the upper collector-emitter 112 and the upper base 114 can be associated with an upper driver 130, and the lower collector-emitter 120 and the lower base can be associated with a lower driver 132. The upper driver 130 is designed and constructed to selectively: float the upper base 114; short the upper base 114 to the upper terminal 140; and inject charge carriers into the upper base 114 to reduce the V CEON Similarly, lower driver 132 is designed and constructed to selectively: float lower base 122; short lower base 122 to lower terminal 142; and inject charge carriers into lower base 122 to reduce V of DSDB-BJT 100 during the conduction cycle from lower terminal 142 to upper terminal 140. CEON .

[0050] exist Figure 1 In the example of , the DSDB-BJT 100 of the NPN configuration is arranged for cascode operation with current flowing in either direction. In particular, the DSDB-BJT 100 is associated with a lower electrically controlled switch (hereinafter referred to as switch 144) coupled between the lower collector-emitter 120 and the lower terminal 142. The switch 144 is selected and implemented to interrupt the load current from the upper terminal 140 through the collector-emitter 112 and 120 to the lower terminal 142 when the externally applied voltage is more positive on the upper terminal 140. Relatedly, the DSDB-BJT 100 is associated with an upper electrically controlled switch (hereinafter referred to as switch 146) coupled between the upper terminal 140 and the upper collector-emitter 112. Switch 146 is selected and implemented to interrupt the load current from lower terminal 142 through collector-emitter 120 and 112 to upper terminal 140 when the externally applied voltage is more positive on lower terminal 142. Figure 1 In the arrangement of , load current flows through collector-emitters 112 and 120 as controlled by the voltage and current applied to upper base 114 and lower base 122 .

[0051] The above-mentioned co-pending and commonly assigned applications indicate that similar power modules can be implemented using DSDB-BJTs in a PNP configuration. Figure 2 A partial block diagram and a partial electrical schematic diagram of a power module using a DSDB-BJT in a PNP configuration are shown. Specifically, Figure 2 1 is a DSDB-BJT 200. As shown by the circuit symbol, the DSDB-BJT 200 has a PNP configuration. The DSDB-BJT 200 defines an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. Since a PNP transistor is a normally-on or normally-conducting device, the upper driver 130 and the lower driver 132 will be designed and constructed to arrange the DSDB-BJT 200 to be non-conductive during the period when the power module blocks current. Again, as previously described, even in the case of a power module implementing a DSDB-BJT 200 in a PNP configuration, the DSDB-BJT can also be arranged for cascode operation, where current interruption is implemented by switches 144 or 146, depending on the direction of current flow.

[0052] Also refer to Figure 1 and 2 The inventor of this specification believes that a person skilled in the art who is assigned to implement a power module using a DSDB-BJT of a PNP structure will implement Figure 2 A design in which the collector-emitter is used as the primary load current path through the DSDB-BJT device. In other words, one skilled in the art will implement a design in which the load current flows through the collector-emitter with significantly smaller controlled voltages and currents applied to the bases 114 and 122 as a function of the polarity of the externally applied voltage.

[0053] However, the results showed that Figure 2 The arrangement of the DSDB-BJT in a PNP configuration is not able to sufficiently reduce the forward voltage drop across the device when conducting, V CEON That is to say, Figure 1 The DSDB-BJT 100 can reduce the forward voltage drop V across the device by injecting minority carriers into the bulk region or the base region. CEON Biasing the base on the same side of the device where the collector-emitter acts as the collector further reduces V CEON The base on the same side of the BTRAN is called the c-base, in contrast to a three-terminal PNP transistor where the base is on the side opposite the collector.

[0054] The inventors of the present specification have discovered that a reduction in the forward voltage drop V across a DSDB-BJT in a PNP configuration can be achieved if the majority of the load current through the PNP device is carried through the base rather than the collector-emitter and minority carriers are provided and / or injected through the collector-emitter on the electrically more positive side of the device. CEON .

[0055] Figure 3 A partial block diagram, partial electrical schematic diagram of a power module using a DSDB-BJT in a PNP configuration according to various embodiments is shown. Figure 3 308. As shown in the circuit symbol, DSDB-BJT 300 has a PNP configuration, but has a continuous base region ranging from region 304 to region 308. In a related art NPN or PNP device, the base region is sandwiched by the collector and emitter. In order to control the conduction of DSDB-BJT 300, DSDB-BJT 300 is associated with a driver circuit. In particular, upper collector-emitter 302 and upper base 304 can be associated with upper driver 310, and lower collector-emitter 306 and lower base 308 can be associated with lower driver 312. The upper driver 310 is designed and constructed to selectively: float the upper collector-emitter 302; float the upper base 304; short the upper collector-emitter 302 to the upper terminal 314; and inject minority carriers into the drift region between the upper base 304 and the lower base 308. Similarly, the lower driver 312 is designed and constructed to selectively: float the lower collector-emitter 306; float the lower base 308; short the lower collector-emitter 306 to the lower terminal 316; and inject minority carriers into the drift region between the lower base 308 and the upper base 304. During conduction, the injection of minority carriers into the drift region significantly reduces the V CEON .

[0056] exist Figure 3In the example of , DSDB-BJT 300 is arranged for cascode operation with current flowing in either direction. Specifically, DSDB-BJT 300 is associated with a lower electrically controlled switch (hereinafter referred to as lower main switch 318) coupled between lower base 308 and lower terminal 316. Lower main switch 318 is selected and implemented to interrupt load current from upper terminal 314 through base 304 and 308 to lower terminal 316 when the externally applied voltage is more positive on upper terminal 314. Relatedly, DSDB-BJT 300 is associated with an upper electrically controlled switch (hereinafter referred to as upper main switch 320) coupled between upper terminal 314 and upper base 304. The upper main switch 320 is selected and implemented to interrupt the load current from the lower terminal 316 through the bases 308 and 304 to the upper terminal 314 when the externally applied voltage is more positive on the lower terminal 316. Figure 2 The opposite of the arrangement Figure 3 In the arrangement of , the primary load current flows through bases 304 and 308 as controlled by the voltage and current applied to upper collector-emitter 302 and lower collector-emitter 306. The description now turns to exemplary DSDB-BJT 300 in greater detail.

[0057] Figure 4 A cross-sectional elevation view of an exemplary DSDB-BJT showing a PNP configuration. Specifically, Figure 4 DSDB-BJT 300 is shown having an upper face or side 400 and a lower face or side 402. The designations "upper" and "lower" are arbitrary and are used merely for ease of discussion. Upper side 400 faces in the opposite direction from lower side 402. In other words, an outward pointing vector normal to upper side 400 (the vector not specifically shown) points in the opposite direction relative to an outward pointing vector normal to lower side 402 (the vector not specifically shown).

[0058] The upper side 400 includes collector-emitter regions 404 that form a junction with a drift region or bulk substrate 406. The upper side 400 further defines a base region 408 disposed between the collector-emitter regions 404. The collector-emitter regions 404 are coupled together to form an upper collector-emitter 302. The base regions 408 are coupled together to form an upper base 304. Similarly, the lower side 402 includes a lower collector-emitter region 410 that forms a junction with the bulk substrate 406. The lower side 402 further defines a lower base region 412 disposed between the lower collector-emitter regions 410. The lower collector-emitter regions 410 are coupled together to form a lower collector-emitter 306. The lower base regions 412 are coupled together to form a lower base 308.

[0059] In the exemplary DSDB-BJT 300, the collector-emitter regions 404 and 410 are P-type, and the base regions 408 and 412 are N-type. In the exemplary system, the shallow P+ region provides ohmic contact from the collector-emitter regions 404 and 410 to the metallization layer (not specifically numbered) and thus to the corresponding collector-emitter 302 and 306. Further in the exemplary system, the shallow N+ contact doping provides ohmic contact from the base regions 408 and 412 to the metallization layer (not specifically numbered) and thus to the corresponding base 304 and 308. In this example, the optional dielectric-filled trench 414 provides lateral separation between the base region and the collector-emitter region.

[0060] In the exemplary case, the various structures and dopings associated with the upper side 400 are intended to be mirror images of the various structures and dopings associated with the lower side 402. However, in some cases, the various structures and dopings associated with the upper side 400 are constructed at a different time than the various structures and dopings on the lower side 402, and thus there may be slight structural and doping differences between the two sides that may be attributable to manufacturing tolerances, but which do not adversely affect the operation of the device as a bidirectional dual-base bipolar junction transistor.

[0061] According to an exemplary embodiment, and in the claims, the status of a region as a base region or a collector-emitter region is defined based on the doping type and the formation of the junction. It can be seen that the status of a terminal or connection as a base or collector-emitter is based on the underlying region to which the terminal is coupled. In particular, the collector-emitter region of the PNP structured DSDB-BJT 300 shall mean a P-type doped region that forms a junction with an N-type doped bulk substrate and / or base region. Still referring to Figure 4, and considering the upper collector-emitter region 404, the exemplary upper collector-emitter region 404 of P type forms a junction with the bulk substrate 406 of N type. In the case of the DSDB-BJT 300, due to the adjacent N-type doping (i.e., N in the bulk substrate 406), the - to the N in the base region 408 to the N for forming an ohmic contact + ), so the bulk region 406 is actually the base region. The collector-emitter region has a varying carrier concentration but the same doping type (e.g., P is transformed into P + ) should not be considered as different doping types.

[0062] Similarly, the base region of the DSDB-BJT 300 shall mean the N-type doped region adjacent to the N-type doped bulk substrate. Figure 4 , and considering the upper base region 408, the exemplary upper base region 408 of N type is adjacent to the bulk substrate doped with N type. Again, in the case of DSDB-BJT 300, the bulk substrate 406 is actually the base region due to the adjacent N type doping. The base region has varying carrier concentrations but has the same doping type (e.g., N - Transforms to N and then to N + ) should not be considered as different doping types.

[0063] Thus, the state of being a terminal or connection of the base or collector-emitter is not defined by the path of the primary load current and / or the location where the control voltage or current is applied; rather, the state of being a terminal or connection of the base or collector-emitter is defined by the doping type within the transistor device. Electrically tracing from the upper base 304 to the lower base 308, there are only N-type regions where varying carrier concentrations do not change the fact that there are N-type regions from the upper base 304 to the lower base 308. However, from the upper collector-emitter 302 to the lower collector-emitter 306, there is a PN junction—the P-type upper collector-emitter region 404 forms a junction with the N-type bulk substrate 406, and the N-type bulk substrate forms a junction with the P-type lower collector-emitter region 410.

[0064] Figures 5A to 5G A cross-sectional view of a DSDB-BJT in a PNP configuration with exemplary external electrical connections is shown in abbreviated form to illustrate several operating states. Specifically, Figures 5A to 5G Seven exemplary states of a DSDB-BJT 300 arranged for carrying a major load current across or through the base region are shown, the seven states being (from left to right): passive off ( Figure 5A ); Active shutdown ( Figure 5B ); diode is turned on ( Figure 5C ); Passive connection ( Figure 5D ); Active on ( Figure 5E ); Pre-shutdown( Fig. 5F ); and bidirectional blocking ( Figure 5G ). Each state will be processed in turn.

[0065] First reference Figure 5A , Figure 5A An exemplary upper terminal 314 and lower terminal 316 are shown. Between the upper terminal 314 and the lower terminal resides the DSDB-BJT 300, which is shown in shorthand form and defines an upper collector-emitter 302, an upper base 304, a lower collector-emitter 306, and a lower base 308. Figures 5A to 5G In the example of , it is assumed that the externally applied voltage has a more positive polarity associated with the upper terminal 314 relative to the lower terminal 316. Figure 5A In the exemplary passive turn-off arrangement of , the DSDB-BJT 300 has an electrically floating upper collector-emitter 302, an upper base 304 coupled to an upper terminal 314, a lower collector-emitter 306 coupled to a lower terminal 316, and a lower base 308 electrically floating. Figure 5A In an arrangement of , in some cases, DSDB-BJT 300 can have a breakdown voltage of 600 volts or more and in some cases about 1200 volts. Therefore, due to the reverse biased PN junction formed between lower collector-emitter 306 and upper base 304, no significant current flows through DSDB-BJT 300. Figure 5A The exemplary state of is called "passive off" because Figure 5A The electrical arrangement of the embodiment can be implemented using purely passive components (eg, diodes and resistors), and thus the driver circuit does not need to have operating power to implement Figure 5A The arrangement.

[0066] Figure 5B An example of an active turn-off arrangement of a DSDB-BJT 300 is shown. Specifically, the upper collector-emitter 302 is electrically floating, the upper base 304 is coupled to the upper terminal 314, the lower collector-emitter 306 is coupled to the lower terminal 316 through the voltage source 500, and the lower base 308 is electrically floating. The voltage source 500 provides a negative bias to the lower collector-emitter 306. As will be discussed in more detail below, in a transition from one of the conducting states (also discussed below) to the non-conducting state, the voltage source 500 can accelerate the transition of the DSDB-BJT 300 to the non-conducting state. In Figure 5BIn the arrangement of , in some cases, DSDB-BJT 300 can have a breakdown voltage of 600 volts or more and in some cases about 1200 volts. Therefore, again, in the active-off arrangement, no significant current flows through DSDB-BJT 300 due to the reverse biased PN junction formed between lower collector-emitter 306 and upper base 304. Figure 5B The exemplary state is called "active off" because Figure 5B In an electrical arrangement of FIG. 5 , an associated driver circuit uses operating power to implement the arrangement (eg, to power voltage source 500).

[0067] Figure 5C An exemplary diode-on arrangement of DSDB-BJT 300 is shown. In particular, the upper collector-emitter is coupled to upper terminal 314, the upper base 304 is electrically floating, the lower collector-emitter 306 is electrically floating, and the lower base 308 is coupled to lower terminal 316. In the diode-on arrangement, the PN junction formed by the upper collector-emitter 302 and the bulk substrate is forward biased, and thus current flows from the upper terminal 314 to the lower terminal 316. Figure 5C In the arrangement of , the voltage drop across DSDB-BJT 300 is about the diode forward voltage drop of about 0.7 volts. For consistency with the description of the diode-on arrangement of the DSDB-BJT (not shown) in NPN configuration, the voltage drop across DSDB-BJT 300 is about the diode forward voltage drop of about 0.7 volts. Figure 5C The diode-connection arrangement is shown in FIG. 1 , but in practice, the diode-connection arrangement can only be used in limited circumstances, or not at all.

[0068] Figure 5D An exemplary passive turn-on arrangement of DSDB-BJT 300 is shown. In particular, upper collector-emitter 302 is electrically floating, upper base 304 is coupled to upper terminal 314, lower collector-emitter 306 is electrically floating, and lower base 308 is coupled to lower terminal 316. Figure 5D In the arrangement of , the voltage drop across the DSDB-BJT 300 is based on the substrate resistance (eg, about 2 ohms for a 260 μm thick substrate). Figure 5D The exemplary state of is referred to as “passive on” because the conduction state does not involve injection of charge carriers in an attempt to reduce the forward voltage drop V CEON ,like Figure 5E As shown in the active connection arrangement of .

[0069] Figure 5EAn exemplary active-on arrangement of the DSDB-BJT 300 is shown. Specifically, the upper collector-emitter 302 is coupled to the upper terminal 314 through a voltage source 502, the upper base 304 is coupled to the upper terminal 314, the lower collector-emitter 306 is electrically floating, and the lower base 308 is coupled to the lower terminal 316. The voltage source 502 provides a positive bias to the upper collector-emitter 302 relative to the upper base 304, and the voltage source 502 can provide any suitable bias voltage (e.g., 0.2V to 2V). The voltage source 502 injects charge carriers across the PN junction into the bulk substrate, which for a primary current of 30 amperes (A) flowing through the base will cause a forward voltage drop V from base to base of CEON to about 0.2 V (compared to about 10 V to 20 V in the absence of charge carrier injection).

[0070] Fig. 5F An exemplary pre-turnoff arrangement of DSDB-BJT 300 is shown. Specifically, upper collector-emitter 302 is coupled to upper terminal 314, upper base 304 is coupled to upper terminal 314, lower collector-emitter 306 is coupled to lower terminal 316, and lower base 308 is coupled to lower terminal 316. An equivalent arrangement may be to omit the coupling of upper collector-emitter 302 to upper terminal 314. Fig. 5F In the pre-turn-off arrangement, the resistance of the DSDB-BJT 300 across terminals 314 and 316 increases as additional minority carriers are pushed out of the base region. The highest resistance occurs when the base region returns to the intrinsic doping density (e.g., when the minority carrier density increases from about 1E17 / cm 3 (high minority injection in the on state) down to about 5E13 / cm 3 (substrate intrinsic doping), the specific resistance Rsp can be from 0.2mOhm.cm 2 Increase to 2Ohm.cm 2 ). The change in minority carrier density increases the voltage drop between the upper terminal 314 and the lower terminal 316. For example, for a 0.2 mOhm.cm 2 Rsp 30A load, Fig. 5F The pre-shutdown arrangement presents a voltage drop of approximately 60V from the upper terminal 314 to the lower terminal 316.

[0071] exist Figure 5G In the exemplary bidirectional blocking of , for DSDB-BJT 300, upper collector-emitter 302 is coupled to upper terminal 314, upper base 304 is electrically floating, lower collector-emitter 306 is coupled to the lower terminal, and lower base 308 is electrically floating. Therefore, no significant current flows through DSDB-BJT 300. Figure 5G In the arrangement, the breakdown voltage of the DSDB BJT300 depends on the reverse PN junction breakdown voltage of either polarity. The reverse PN junction breakdown voltage is determined by the junction profile, taking into account the V CEON For example, for 5E13 / cm 3 For a doped 300 μm thick N-type substrate, the breakdown voltage between the P-type region and the N-type region can be greater than 1200V.

[0072] In many cases, the DSDB-BJT 300 will be arranged to Figure 5A Passive shutdown arrangement or Figure 5B The active shutdown arrangement directly transforms into Figure 5E active-on arrangement without implementing intermediate arrangements or states. Figure 5C The diode connection arrangement and Figure 5D The passive turn-on arrangement is an optional configuration, but may still find use in some situations. Regarding the transition from conducting to non-conducting, in many cases the DSDB-BJT 300 will be Figure 5E The active switch arrangement directly transforms into Figure 5B Active shutdown arrangement, Figure 5A Passive shutdown arrangement or Figure 5G bidirectional blocking arrangement without implementing intermediate arrangements or states. That is, Figure 5C The diode connection arrangement, Figure 5D Passive connection arrangement and Fig. 5F The pre-turnoff arrangement of is an optional intermediate configuration in the transition from conducting to non-conducting, but may still find use in some situations.

[0073] Figures 5A to 5G The example of applies to the case where the externally applied voltage has a positive polarity at the upper terminal 314. However, the exemplary DSDB-BJT 300 is a symmetrical device, and now that it is understood how to control current flow through the DSDB-BJT with the exemplary polarity shown, it is straightforward to control current flow in the opposite direction.

[0074] Figure 6A partial block diagram, partial electrical schematic diagram of an exemplary power module or switch assembly is shown. In particular, the exemplary switch assembly 600 includes a DSDB-BJT 300 in a PNP configuration and a driver 602. The DSDB-BJT 300 is shown by an exemplary circuit symbol having two emitters and two bases. The circuit symbol shows an upper collector-emitter 302, an upper base 304, a lower collector-emitter 306, and a lower base 308. The exemplary driver 602 defines an upper collector-emitter terminal 608 coupled to the upper collector-emitter 302, an upper conduction terminal 610 coupled to the upper base 304, a lower collector-emitter terminal 612 coupled to the lower collector-emitter 306, and a lower conduction terminal 614 coupled to the lower base 308. The upper base 304 is coupled to the upper terminal 314 of the switch assembly 600 through the upper conduction terminal 610. Lower base 308 is coupled to lower terminal 316 of switch assembly 600 through lower conduction terminal 614 .

[0075] The exemplary driver 602 includes a controller 616, an electrical isolator 618, and an isolation transformer 620. To place the DSDB-BJT 300 in various conducting and non-conducting modes, the exemplary driver 602 includes a plurality of electrically controlled switches and a charge carrier source. In particular, the exemplary driver 602 includes a switch 622 having its first lead coupled to the upper terminal 314, a second lead coupled to the upper collector-emitter 302, and a control input coupled to the controller 616. The exemplary switch 622 is shown as a single-pole single-throw switch, but in reality the switch 622 may be a FET whose control input is the gate of the FET. Thus, when the switch 622 is conducting by assertion of its control input, the upper collector-emitter 302 is coupled to the upper terminal 314.

[0076] The driver 602 further includes a charge carrier source 624, illustratively shown as a battery. The charge carrier source 624 has a negative lead coupled to the upper terminal 314. Another electrically controlled switch 626 (hereinafter referred to as switch 626) has a first lead coupled to the positive terminal of the charge carrier source 624, a second lead coupled to the upper collector-emitter 302, and a control input coupled to the controller 616. The exemplary switch 626 is also shown as a single-pole single-throw switch, but in reality the switch 626 can be a FET, whose control input is the gate of the FET. Therefore, when the switch 626 is conducting, the charge carrier source 624 is coupled between the upper terminal 314 and the upper collector-emitter 302. The driver 602 further includes another charge carrier source 628, illustratively shown as a battery. The charge carrier source 628 has a positive lead coupled to the upper terminal 314. Another electrically controlled switch 630 (hereinafter referred to as switch 630) has a first lead coupled to the negative terminal of the charge carrier source 628, a second lead coupled to the upper collector-emitter 302, and a control input coupled to the controller 616. The exemplary switch 630 is also shown as a single-pole single-throw switch, but in practice the switch 630 can be a FET, whose control input is the gate of the FET. Therefore, when the switch 630 is conducting, the charge carrier source 628 is coupled between the upper terminal 314 and the upper collector-emitter 302.

[0077] The driver 602 further includes an upper main switch 320 having a first lead coupled to an upper terminal 314, a second lead defining an upper conduction terminal 610 coupled to the upper base 304, and a control input coupled to the controller 616. As previously described, the exemplary upper main switch 320 is shown as a single-pole single-throw switch, but in practice the upper main switch 320 may be a FET whose control input is the gate of the FET. Thus, when the upper main switch 320 is conducting, for example by assertion of its control input, the upper terminal 314 is coupled to the upper base 304.

[0078] Turning now to the lower side of the DSDB-BJT 300, the exemplary driver 602 further includes a switch 632 having a first lead coupled to the lower terminal 316, a second lead coupled to the lower collector-emitter 306, and a control input coupled to the controller 616. The exemplary switch 632 is shown as a single-pole single-throw switch, but in reality the switch 632 may be a FET whose control input is the gate of the FET. Thus, when the switch 632 is conducting by assertion of its control input, the lower collector-emitter 306 is coupled to the lower terminal 316.

[0079] The driver 602 further includes a charge carrier source 634, illustratively shown as a battery. The charge carrier source 634 has a negative lead coupled to the lower terminal 316. Another electrically controlled switch 636 (hereinafter referred to as switch 636) has a first lead coupled to the positive terminal of the charge carrier source 634, a second lead coupled to the lower collector-emitter 306, and a control input coupled to the controller 616. The exemplary switch 636 is shown as a single-pole single-throw switch, but in practice the switch 636 can be a FET, whose control input is the gate of the FET. Therefore, when the switch 636 is conducting, the charge carrier source 634 is coupled between the lower terminal 316 and the lower collector-emitter 306. The exemplary driver 602 further includes another charge carrier source 638, illustratively shown as a battery. The charge carrier source 638 has a positive lead coupled to the lower terminal 316. Another electrically controlled switch 640 (hereinafter referred to as switch 640) has a first lead coupled to the negative terminal of the charge carrier source 638, a second lead coupled to the lower collector-emitter 306, and a control input coupled to the controller 616. The exemplary switch 640 is shown as a single-pole single-throw switch, but in practice the switch 640 can be a FET, whose control input is the gate of the FET. Therefore, when the switch 640 is conducting, the charge carrier source 638 is coupled between the lower terminal 314 and the lower collector-emitter 306.

[0080] The exemplary driver 602 further includes a lower main switch 318 having a first lead coupled to a lower terminal 316, a second lead defining a lower conduction terminal 614 coupled to the lower base 308, and a control input coupled to the controller 616. As previously described, the exemplary lower main switch 318 is shown as a single-pole single-throw switch, but in practice the lower main switch 318 may be a FET whose control input is the gate of the FET. Thus, when the lower main switch 318 is conducting, such as by assertion of its control input, the lower terminal 314 is coupled to the lower base 308.

[0081] Controller 616 defines control inputs 642 and 644, and control outputs 646, 648, 650, 652, 654, 656, 657, and 658 that are respectively coupled to the control inputs of switches 320, 630, 626, 622, 632, 636, 640, and 318. When control input 642 is asserted, controller 616 is designed and constructed to arrange DSDB-BJT 300 for conducting from upper terminal 314 to lower terminal 316. Conversely, when control input 642 is de-asserted, controller 616 is designed and constructed to arrange DSDB-BJT 300 to block current flow from upper terminal 314 to lower terminal 316. Similarly, when control input 644 is asserted, controller 616 is designed and constructed to arrange DSDB-BJT 300 for conducting from lower terminal 316 to upper terminal 314. And conversely, when control input 644 is de-asserted, controller 616 is designed and constructed to arrange DSDB-BJT 300 to block current flow from lower terminal 316 to upper terminal 314. When control inputs 642 and 644 are both asserted, controller 816 arranges DSDB-BJT 300 for current flow in both directions (e.g., AC circuit breaker service), and when control inputs 642 and 644 are both de-asserted, controller 616 blocks current flow in both directions.

[0082] Arranging the DSDB-BJT 300 to be non-conductive is dependent on the polarity of the applied voltage. Thus, the exemplary controller 616 may further define a polarity input 660 that receives a Boolean indication of the applied polarity. In the exemplary driver 602, a comparator 662 has a first input coupled to the upper terminal 314 (the connection shown by the bubble "A") and a second input coupled to the lower terminal 316. The comparator 662 defines a comparison output coupled to the polarity input 660. Although Figure 6 The first and second inputs are shown coupled directly to respective conduction terminals, but in reality, when non-conducting, the voltage across DSDB-BJT 300 may be larger (e.g., 1200V) and thus each of the first and second inputs may be coupled to its respective conduction terminal through respective voltage divider circuits. In still further scenarios, the applied polarity may be determined by systems and devices external to switch assembly 600, and a Boolean signal is sent across electrical isolator 618 to polarity input 660.

[0083] Transitioning DSDB-BJT 300 from non-conducting to conducting and then back to non-conducting can be a multi-step process. To implement the multi-step process, controller 616 can be individual circuit components, application specific integrated circuits (ASICs), microcontrollers with control software, reduced instruction set computing devices (RISCs), digital signal processors (DSPs), processors with control software, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), programmable system-on-chips (PSOCs), and / or combinations thereof configured to read control inputs 642 and 644, read polarity input 660, and drive control outputs to implement mode transitions of DSDB-BJT 300.

[0084] In the exemplary system, the switch assembly 600 is electrically floating. In order to receive the control inputs 642 and 644 in the electrical domain of the switch assembly 600, the exemplary driver 602 implements an electrical isolator 618. The exemplary electrical isolator 618 can take any suitable form, such as an optocoupler or a capacitive isolation device. Regardless of the precise nature of the electrical isolator 618, an external control signal (e.g., a Boolean signal) can be coupled to the control inputs 664 and 666 of the electrical isolator 618. The electrical isolator 618 in turn passes the control signal to the electrical domain of the switch assembly 600. In the example, the external control signal is passed to become the control inputs 642 and 644 of the controller 616.

[0085] Now turn to the isolation transformer 620. Various devices within the switch assembly 600 may use operating power. For example, the controller 616 may use the bus voltage and power to implement various operating modes of the DSDB-BJT 300. In addition, the charge carrier sources within the system may actually be implemented as individual voltage sources in the form of switching power converters, or individual current sources also implemented using switching power converters. The switching power converters that implement the charge carrier sources may use the bus voltage and power. In order to provide operating power within the electrical domain of the switch assembly 600, an isolation transformer 620 is provided. An external system (not specifically shown) may provide an alternating current (AC) signal (e.g., 15VAC) across the primary leads 668 and 670 of the isolation transformer 620. The isolation transformer 620 generates an AC voltage on the secondary leads 672 and 674. The AC voltage on the secondary of the isolation transformer 620 may be provided to an AC-DC power converter 676, which rectifies the AC voltage and converts the AC voltage to a bus voltage V relative to the common terminal 678. BUS(e.g., 3.3V, 5V, 12V). The power provided by the AC-DC power converter 676 can be used by various components of the switch assembly 600. In other cases, there may be multiple isolation transformers (e.g., one isolation transformer for each side of the DSDB-BJT). In addition, a single isolation transformer with multiple secondary windings may be used. The discussion now turns to an exemplary arrangement for making the DSDB-BJT 300 conductive and / or non-conductive in the context of the switch assembly 600.

[0086] As an example, consider a situation where the applied voltage has a positive polarity on the upper terminal 314. Further consider that the control input 664 applied to the electrical isolator 618 is de-asserted, and thus the control signal applied to the control input 642 of the controller 616 is de-asserted. Based on the de-asserted state of the control input 642, the controller 616 is designed and constructed to place the DSDB-BJT 300 in a non-conductive arrangement, taking into account the applied polarity (e.g., read by the controller 616 through the polarity input 660). Therefore, in the exemplary arrangement, the upper main switch 320 is conductive, the lower main switch 318 is non-conductive, and: 1) the switch 632 is conductive (passively turned off); or 2) the switch 640 is conductive (actively turned off). In some examples, the upper main switch 320 is made conductive by the controller 616 asserting the control output 646. However, in other cases, and as described in more detail below, the upper main switch 320 is implemented as a FET having an internal body diode. Thus, the conductivity of the upper main switch 320 may be based, at least initially, on an applied voltage that forward biases the body diode of the FET implementing the upper main switch 320. A similar arrangement and / or operation may exist for the lower main switch 318 when the lower main switch is arranged to block current of the opposite polarity.

[0087] Still considering the exemplary arrangement of positive polarity at upper terminal 314, now consider that the control signal applied to control input 664 of galvanic isolator 618 is asserted, and thus the control signal applied to control input 642 of controller 616 is asserted. Based on the assertion, in the exemplary switch assembly 600, controller 616 can be designed and constructed to place DSDB-BJT 300 directly in an active-on arrangement ( Figure 5E). To do this, the controller 616 may assert the control output 646 (if not already asserted) to make the upper main switch 320 conductive, assert the control output 650 to make the switch 626 conductive, assert the control output 658 to make the lower main switch 318 conductive, and de-assert or keep the remaining control outputs de-asserted. In still other cases, to place the DSDB BJT 300 in a conductive state, the controller 616 may be designed and constructed to make the switch 626 conductive within a predetermined time period (e.g., from about 0.1 μs to 5 μs) before making the lower main switch 318 conductive. Making the switch 626 conductive before making the lower main switch 318 conductive may charge the collector-emitter 302 to the base 304 capacitance, thereby making the DSDB BJT 300 fully conductive more quickly once the lower main switch 318 is made conductive.

[0088] Optionally, again with positive polarity at upper terminal 314, controller 616 may be designed and constructed to cause DSDB-BJT 300 to pass through an intermediate conduction arrangement before reaching the active on arrangement. For example, controller 616 may briefly place DSDB-BJT 300 in a passive on arrangement by asserting control output 646 to cause upper primary switch 320 to be conductive, asserting control output 658 to cause lower primary switch 318 to be conductive, and de-asserting or keeping the remaining control outputs de-asserted ( Figure 5D ). When used, the passive-on arrangement may last for a predetermined period (e.g., from about 0.1 μs to 5 μs). As another example of an intermediate conduction state, the controller 616 may briefly place the DSDB-BJT 300 in a diode-on arrangement ( ) by asserting control output 652 to make switch 622 conductive, asserting control output 658 to make lower main switch 318 conductive, and de-asserting or keeping the remaining control outputs de-asserted. Figure 5C ). When used, the diode-on arrangement may last for a predetermined period (e.g., from about 0.1 μs to 5 μs). In practice, the upper main switch 320 may have an internal body diode or be associated with a discrete shunt diode, making the diode-on arrangement impossible to implement because the body diode or discrete shunt diode will be forward biased when the positive polarity is at the upper terminal 314. If the lower main switch 318 has a body diode or a discrete shunt diode, then there may be a similar situation where the diode-on arrangement cannot be implemented when the positive polarity is at the lower terminal 316. However, after the intermediate conduction arrangement, the controller 616 places the DSDB-BJT 300 in the active-on arrangement.

[0089] In the active-on arrangement, and for positive polarity at the upper terminal 314, the charge carrier source 624 injects charge carriers into the upper collector-emitter 302. Injecting charge carriers into the upper collector-emitter 302 increases the number of charge carriers in the drift region of the DSDB-BJT 300, which reduces the V measured across the bases 304 and 308. CEON In one example, for a current of about 30A to 100A flowing through the bases 304 and 308, the charge carrier source 624 injecting the charge carriers may be configured to increase the V across the bases 304 and 308 by 1. CEON to about 0.2 V. Charge carrier source 624 may employ any suitable voltage between and including 0.5 V and 5.0 V, in some cases between 0.6 V and 1.5 V.

[0090] Still refer to Figure 6 , and the positive polarity on the upper terminal 314 is still considered. Further consider that the control input 664 applied to the electrical isolator 618 changes from being asserted to being de-asserted, and therefore the control signal applied to the control input 642 of the controller 616 changes from being asserted to being de-asserted. Based on the transition, the controller 616 is designed and constructed to place the DSDB-BJT 300 in a non-conducting arrangement again. In an exemplary case, the controller 616 can directly implement a passive shutdown arrangement or an active shutdown arrangement as previously discussed from the conductive state of the DSDB-BJT 300. In other cases, the controller 616 can turn off the switch 626 within a predetermined amount of time (e.g., from about 0.1 μs to 5 μs) before turning off the lower main FET 318, which reduces the minority carriers in the drift region and thereby reduces the peak value of the commutation current and / or shortens the duration of the commutation current. Furthermore, with respect to the timing of changing the states of the upper main switch 320 and the lower main switch 318, when transitioning to the non-conducting state of the DSDB-BJT 300 having the assumed polarity, the lower main switch 318 can be made non-conducting, but as the current through the switch assembly 600 decreases, the upper main switch 320 can remain in a conducting state for a predetermined time period (e.g., approximately 450 nanoseconds or less), which can reduce the reverse recovery time of the body diode associated with the upper main switch 320.

[0091] Optionally, the controller 616 may be designed and constructed to cause the DSDB-BJT 300 to pass through an intermediate conducting arrangement before reaching a non-conducting arrangement. For example, the controller 616 may briefly place the DSDB-BJT 300 in a diode-on arrangement ( Figure 5C ), passive connection arrangement ( Figure 5D ) or pre-shutdown arrangement ( Fig. 5FWhen used, the intermediate arrangement between active-on and active-off may last for a predetermined period (eg, from about 0.1 μs to 5 μs).

[0092] about Figure 6 The exemplary operation discussed is for positive polarity at upper terminal 314. However, again, the exemplary DSDB-BJT 300 and associated driver are symmetrical, and now understanding how to arrange the DSDB-BJT 300 into various conducting and non-conducting states, then directly control current flow in opposite directions.

[0093] Figure 6 600 shows an exemplary DSDB-BJT 300 arranged for cascode operation. In this arrangement, interruption of current flow through the device (e.g., in a transition from conduction to non-conduction) is primarily implemented by the upper main switch 320 and the lower main switch 318. For example, with a positive polarity on the upper terminal 314, current flow through the switch assembly 600 is initially interrupted by the lower main switch 318, and then further blocked by the DSDB-BJT 300. Conversely, with a positive polarity on the lower terminal 316, current flow through the switch assembly 600 is initially interrupted by the upper main switch 320, and then further blocked by the DSDB-BJT 300. As can be seen, because the blocking is implemented by the DSDB-BJT 300, the breakdown voltage of the upper main switch 320 and the lower main switch 318 can be significantly lower than the breakdown voltage of the DSDB-BJT 300. For example, each of upper main switch 320 and lower main switch 318 may have a breakdown voltage of 100V or less, in some cases 80V or less, while the breakdown voltage of DSDB-BJT 300 may be 600V or more and in some cases approximately 1200V.

[0094] In the transition from the conducting state to the non-conducting state through the bases 304 and 308, a relatively small amount of current (the off current) may briefly flow through the collector-emitter on the side opposite to the positive polarity. For example, with a positive polarity on the upper terminal 314 and current flowing from the upper base 304 through the DSDB-BJT 300 and out of the lower base 308, interruption of the current flow by the lower main switch 318 may cause the off current to briefly flow through the lower collector-emitter 306. In other words, when the load current through the DSDB-BJT 300 is interrupted by the lower main switch 318, the off current is commutated through the lower collector-emitter 306 for a short period of time as the lower PN junction is reverse biased (remember, for the assumption that the lower collector-emitter 306 is electrically floating during conduction). Thus, the passive shutdown arrangement ( Figure 5A) and active shutdown arrangements ( Figure 5B ) provides a current path for the shutdown current to the lower terminal 316. In the active shutdown arrangement ( Figure 5B ), the charge carrier source 638 (corresponding to Figure 5B The voltage source 500 of FIG. 500 can accelerate the transition to the non-conducting state of the DSDB-BJT 300 by extracting charge carriers from the bulk region and more quickly reverse biasing the PN junction formed between the lower collector-emitter 306 and the bulk region. Now that the commutation of the current through the lower collector-emitter 306 when the more positive voltage is at the upper terminal 314 is understood, the commutation of the current through the upper collector-emitter 302 when the more positive voltage is at the lower terminal 316 is directly discussed next.

[0095] Figure 7 A partial electrical schematic diagram of an exemplary switch assembly is shown. In particular, Figure 7 An exemplary DSDB-BJT 300 is shown along with portions of an exemplary driver 602. Driver 602 may also have an isolation transformer, an AC-DC power converter, a galvanic isolator, a controller, and a comparator, but those components are separated from each other. Figure 7 For the purpose of discussion, Figure 7 The upper side of shows switches 320, 622, 626, and 630, and exemplary charge carrier sources 624 and 628. The lower side shows switches 318, 632, 636, and 640, and exemplary charge carrier sources 634 and 368.

[0096] As mentioned above, many of the switches are implemented as FETs. Figure 7 In the exemplary switch assembly of FIG. 6 , the upper main switch 320 is shown as a FET having a source coupled to the upper terminal 314, a drain coupled to the upper base 304, a gate defining a control input, and a body diode coupled between the source and the drain. When the applied voltage has a positive polarity on the upper terminal 314, the body diode is forward biased, making the upper main switch 320 conductive (without the need for a controller 616 ( Figure 6 ) action). During the conduction state of the DSDB-BJT 300, the controller 616 drives the gate to make the FET conductive, thereby reducing the overall voltage drop. In an exemplary case, the FET used to implement the upper main switch 320 may have a breakdown voltage of 100V or less and in some cases about 80V, although the DSDB-BJT 300 may have a breakdown voltage of 600V or more and in some cases about 1200V.

[0097] An exemplary switch 622 is shown as a pair of back-to-back FETs. Specifically, the switch 622 is shown as a first FET having a source coupled to the upper terminal 314, a second FET having a source coupled to the upper collector-emitter 302, and the drains of the FETs are coupled together. The gates of the FETs may be individually coupled to the controller 616 ( Figure 6 ), or the gates may be coupled together and driven by controller 616 as a single unit. The FETs each have a body diode, and in the arrangement shown, the cathodes of the body diodes are coupled together. Having back-to-back FETs achieves bidirectional current blocking and bidirectional current flow despite the presence of the body diodes. With positive polarity on upper terminal 314, switch 622 may be in an optional diode-on arrangement ( Figure 5C ) or optional pre-shutdown arrangement ( Fig. 5F ) during conduction. However, in the active-on arrangement ( Figure 5E ), switch 622 may be non-conductive (e.g., to enable other devices to inject charge carriers into the upper collector-emitter 302) during the period of positive polarity on the upper terminal 314. Thus, for a positive polarity on the upper terminal 314, when the gate is de-asserted, the back-to-back FETs block current flow, even though the body diode of the first FET is forward biased. In the case where there is a positive polarity on the lower terminal 316, switch 622 may also be conductive in the transition to the passive shutdown arrangement (although the passive shutdown using switch 622 will be performed with the driver 602 powered). For example, the shutdown current in the passive shutdown arrangement may be carried by switch 622.

[0098] Similarly, switch 626 is shown as a pair of back-to-back FETs. Specifically, switch 626 is shown as FET 700 having a source coupled to charge carrier source 624, FET 702 having a source coupled to upper collector-emitter 302, and the drains of FETs 700 and 702 are coupled together. The gates of FETs 700 and 702 may be individually coupled to controller 616 ( Figure 6 ), or the gates may be coupled together and driven by the controller 616 as a single unit. FETs 700 and 702 each have a body diode, and in the arrangement shown, the cathodes of the body diodes are coupled together. Having back-to-back FETs achieves bidirectional current blocking as well as bidirectional current flow despite the presence of the body diodes. With a positive polarity on the upper terminal 314, an active-on arrangement may be implemented by injecting charge carriers into the upper collector-emitter 302 through the FETs 700 and 702 using the charge carrier source 624. In other modes, current flow from the charge carrier source 624 to the upper collector-emitter 302 may be blocked by the FET 702, although the body diode of the FET 700 may be forward biased by the charge carrier source 624.

[0099] Still considering switch 626 and resistors 704 and 706 (and corresponding resistors 708 and 710 associated with switch 636 on the lower side), the body diode can be used to enable a power-on safety mode. That is, resistors 704 and 706 ensure that a race condition when switch assembly 600 turns on the power does not result in unintentional conduction through DSDB-BJT 300. In particular, switch assembly 600 can couple upper terminal 314 and lower terminal 316 within the overall system. In AC-DC power converter 676 ( Figure 6 ) before power is turned on, and / or before controller 616 has a chance to boot into an operational state, a voltage may appear across upper terminal 314 and lower terminal 316 in either polarity. As an example, consider a power-on condition in which a positive polarity appears at lower terminal 316 before controller 616 is operational. In this case, the body diode of the FET implementing lower main switch 318 is conductive. In addition, the body diode of FET 702 of switch 626 will be forward biased, causing an off current and / or leakage current to flow from upper collector-emitter 302 to upper terminal 314, thus implementing a passive turn-off arrangement ( Figure 5A ). When a positive polarity is present on upper terminal 314, a similar arrangement occurs, with leakage current flowing through the body diode of FET 712, resistor 708, and resistor 710. Thus, even in the absence of control by controller 616, DSDB-BJT 300 enters a non-conducting safety mode regardless of the polarity of the voltage applied across upper terminal 314 and lower terminal 316.

[0100] According to an exemplary system, an active on arrangement ( Figure 5E ). In particular, the exemplary switch assembly 600 further includes a charge carrier source 718, illustratively shown as a battery, having a negative lead coupled to the upper terminal 314. The switch, illustratively shown as a FET 720, has a source coupled to the positive lead of the charge carrier source 718, a drain coupled to the upper collector-emitter 302, and a switch coupled to the controller 616 ( Figure 6) control input or gate. With a positive polarity on the upper terminal 314, the active-on arrangement may initially be implemented by the FET 720 and the charge carrier source 718. Thus, in the active-on arrangement, the charge carrier source 718 may initially inject charge carriers into the upper collector-emitter 302 at a first rate. After a predetermined time period, the controller 616 may be designed and constructed to reduce the rate of charge carrier injection by making the FET 720 non-conductive and substantially simultaneously making the switch 626 conductive and thereby injecting charge carriers into the upper collector-emitter 302 at a lower rate using the charge carrier source 624. That is, once the V is increased using the charge carrier source 718, the charge carrier source 718 may be electrically conductive to the upper collector-emitter 302. CEON By driving LOW, the charge carrier source 624 can be used to maintain the reduced V CEON Now understanding the use of charge carrier sources 624 and 718 in implementing an active switch arrangement with a positive polarity on upper terminal 314 , it is directly next to discuss the equivalent use of charge carrier sources 638 and 716 (along with switch 714 ) to implement an active switch arrangement with a positive polarity on lower terminal 316 .

[0101] Still refer to Figure 7 , and in particular the upper side. Switch 630 is shown as a single FET having a source coupled to the upper collector-emitter 302, a drain coupled to the negative lead of the charge carrier source 628, a limiting coupled to the controller 616 ( Figure 6 ) and a body diode coupled between the source and drain. When the FET itself is non-conducting, the voltage associated with the charge carrier source 628 can keep the body diode of the FET reverse biased, and thus back-to-back FETs may not be required relative to the switch 630. In order to block the flow of current from the upper terminal 314 to the upper collector-emitter 302 in power loss and / or startup situations, a diode 722 is disposed between the source of the FET and the upper collector-emitter 302. In particular, the diode 722 has its anode coupled to the upper collector-emitter 302 and its cathode coupled to the cathode of the body diode of the switch 630. As discussed above, when the positive polarity is on the lower terminal 316, the switch 630 and the charge carrier source 628 can be used to implement an active shutdown arrangement. When the positive polarity is on the upper terminal 314, a similar function is provided by the switch 640, the charge carrier source 624 and the diode 724.

[0102] Figure 7The lower main switch 318 is further shown as a FET having a source coupled to the lower terminal 316, a drain coupled to the lower base 308, a gate defining a control input, and a body diode coupled between the source and the drain. When a positive polarity is on the lower terminal 316, the body diode is forward biased, thus making the lower main switch 318 conductive (without the need for the controller 616 ( Figure 6 ) action). During the conduction state of the DSDB-BJT 300, the controller 616 drives the gate to make the FET conductive, thereby reducing the overall voltage drop. In an exemplary case, the FET used to implement the lower main switch 318 may have a breakdown voltage of 100V or less and in some cases about 80V, although the DSDB-BJT 100 may have a breakdown voltage of 600V or more and in some cases about 1200V.

[0103] In a similar manner as switch 622, switch 632 may be implemented as a back-to-back FET. Also, in a similar manner, switch 636 may be implemented as a back-to-back FET. The description of the operation of switches 632 and 636 is redundant with that of switches 622 and 626, taking into account the polarity of the applied voltage, and will not be repeated here to avoid unduly lengthening the description.

[0104] like Figure 7 As shown in FIG. 6 , when the various switches are implemented as FETs with body diodes, the controller 616 ( Figure 6 ) can more easily and quickly implement state transitions. As an example, consider a positive polarity on upper terminal 314 and driver 602 puts DSDB-BJT 300 in an active-on arrangement. In this case, upper main switch 320 is conductive, switch 626 or FET 720 is conductive, lower main switch 318 is conductive, and the remaining switches are non-conductive. Now consider that driver 602 receives a command to make DSDB-BJT 300 non-conductive (e.g., control input 642 ( Figure 6 ) deassertion). When the switches are implemented as FETs as shown, arranging driver 602 to implement active off mode may involve having controller 616 ( Figure 6) deasserts all gates of all FETs. Based on the body diode being forward biased and conductive, the upper main switch 320 remains conductive. The lower main switch 318 interrupts the current flow and its body diode is reverse biased. The interruption of the current flow causes the shutdown current to commutate to flow through the body diode of the FET 712 of the switch 636 and the resistors 708 and 710. At some point in the exemplary case, the controller 616 may make the switch 640 conductive to implement the active shutdown arrangement, but the timing is not critical. In other words, if only to reduce the timing constraints, the controller 616 may be designed and constructed to briefly implement the passive shutdown arrangement before implementing the active shutdown arrangement. A similar discussion is next made for interrupting the current flow in the case of a positive voltage on the lower terminal 316.

[0105] Figure 6 and 7 The various charge carrier sources shown in are illustratively shown as batteries. However, in practice, these charge carrier sources may be individual DC-DC converters, or for charge carrier sources with corresponding polarity on the same side (e.g., charge carrier sources 624 and 718), a single DC-DC conversion with a controlled voltage output may be implemented. In other cases, the DC-DC converters may be implemented as controlled current sources rather than voltage sources.

[0106] Figure 8 Methods according to at least some embodiments are shown. Specifically, the method starts (block 800) and includes: conducting a first load current from an upper terminal of a power module to an upper base of a transistor, through the transistor, and from a lower base to a lower terminal of the power module (block 802); and then in response to assertion of a first interrupt signal, interrupting the first load current from the lower base to the lower terminal by disconnecting a lower main FET and commutating a first off current to the lower terminal through a lower collector-emitter of the transistor (block 804); and blocking current from the upper terminal to the lower terminal through the transistor (block 806). Thereafter, the method ends (block 808).

[0107] Fig. 9 Methods according to at least some embodiments are shown. In particular, the method starts (block 900) and includes: making a transistor conductive from an upper base to a lower base by supplying a current to an upper collector-emitter of the transistor and electrically floating a lower collector-emitter of the transistor (block 902); and then making the transistor non-conductive by electrically floating the upper collector-emitter, electrically floating the lower base, and conducting an off current through the lower collector-emitter of the transistor (block 904). Thereafter, the method ends (block 906).

[0108] Although the upper main switch and the lower main switch each have a corresponding voltage drop when fully conducting, when implemented as a power FET, the forward voltage drop is small (e.g., 0.01V to 0.1V) compared to the forward voltage drop of the associated DSDB-BJT (e.g., 0.2V to 0.6V), and can be ignored in many cases. In addition, it should be noted that during the transition from conduction to non-conduction, the turn-off current flowing through the collector-emitter on the side opposite to the positive polarity can have a peak current approximately equal to the load current; however, although the collector-emitter region and connections may not be designed to handle the full load current for an extended period of time, the inventors of the present specification have found through simulation that, given the instantaneous nature of the turn-off current (e.g., 1μs to 3μs), even a turn-off current with a peak value equal to the load current does not adversely affect the operation of the device.

[0109] Many electrical connections in the drawings are shown as direct couplings without intervening devices, but are not explicitly stated as such in the above description. However, this paragraph should be used as antecedent basis in the claims to refer to any electrical connection as a "direct coupling" with respect to an electrical connection shown in the drawings without intervening devices. Furthermore, this paragraph should not deny that a base electrically connected to a collector-emitter through a transistor can be referred to as a "direct coupling."

[0110] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, a person skilled in the art will understand numerous changes and modifications. It is intended that the appended claims be interpreted as encompassing all such changes and modifications.

Claims

1. A method of operating a power module having a bidirectional dual base bipolar junction transistor, the method comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then in response to assertion of a first interrupt signal, interrupting said first load current from said lower base to said lower terminal by turning off a lower main FET and commutating a first off current to said lower terminal through a lower collector-emitter of said transistor; and Current flow from the upper terminal to the lower terminal is blocked by the transistor.

2. The method according to claim 1: in, During the conduction, the method further comprises injecting charge carriers into the upper collector-emitter; and The method further includes, in response to the assertion of the first interrupt signal, stopping the injection of charge carriers into the upper collector-emitter. 3 . The method of claim 2 , wherein stopping the injection of charge carriers further comprises stopping the injection of charge carriers for a non-zero predetermined time before interrupting the first load current by turning off the lower main FET.

4. The method according to claim 1: wherein interrupting the first load current further comprises interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less; and Wherein blocking current further comprises blocking at an applied voltage of 600 volts or more across the upper terminal and the lower terminal. 5 . The method of claim 1 , wherein commutating the first off current further comprises coupling the lower collector-emitter to the lower terminal. 6 . The method of claim 5 , wherein coupling the lower collector-emitter to the lower terminal further comprises coupling the lower collector-emitter to the lower terminal via a voltage source or a current source.

7. The method of claim 1 , further comprising, after interrupting the flow of current from the upper terminal to the lower terminal: conducting a second load current from the lower terminal of the power module to the lower base, through the transistor, and from the upper base to the upper terminal; and then in response to assertion of a second interrupt signal, interrupting said second load current from said upper base to said upper terminal by turning off an upper main FET and commutating a second off current to said upper terminal through an upper collector-emitter; and Current flow from the lower terminal to the upper terminal is blocked by the transistor.

8. The method according to claim 7: wherein interrupting the second load current further comprises interrupting the second load current using the upper main FET having a breakdown voltage of 100 volts or less; and Wherein blocking current flow from the lower terminal to the upper terminal further comprises blocking at an applied voltage of 600 volts or more across the lower terminal and the upper terminal.

9. A switch assembly, comprising: Upper terminals, lower terminals and upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper base, and a gate; a lower main FET defining a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate; a controller coupled to the upper control input, the gate of the upper main FET, and the gate of the lower main FET, and for a first applied voltage across the upper terminal and the lower terminal, the controller is configured to: asserting the gate of the upper main FET to render the upper main FET conductive, arranging the transistor for conduction from the upper base to the lower base, and asserting the gate of the lower main FET to render the lower main FET conductive such that a first load current flows from the upper terminal to the lower terminal; sensing a de-assertion of the upper control input; and in response to the de-assertion of the upper control input, The gate of the lower main FET is de-asserted to interrupt the first load current from the lower base.

10. The switch assembly of claim 9, wherein the breakdown voltage of the transistor is 600 volts or more and the breakdown voltage of the lower main FET is 100 volts or less.

11. The switch assembly of claim 9, wherein the breakdown voltage of the transistor is approximately 1200 volts and the breakdown voltage of the lower main FET is 80 volts or less.

12. The switch assembly according to claim 9, further comprising: an upper CE source and an upper CE FET, the upper CE source being arranged to selectively inject charge carriers into the upper collector-emitter through the upper CE FET; and wherein when the controller arranges the transistor for conduction from the upper base to the lower base, the controller is further configured to render the upper CE FET conductive, thereby injecting charge carriers into the upper collector-emitter; and Wherein when the controller senses de-assertion of the upper control input, the controller is further configured to render the upper CE FET non-conductive, thereby ceasing injection of charge carriers into the upper collector-emitter.

13. The switch assembly of claim 12, wherein when the controller renders the upper CE FET non-conductive, the controller is configured to render the upper CE FET non-conductive for a non-zero predetermined time period before de-asserting the gate of the lower main FET.

14. The switch assembly of claim 12, wherein when the controller senses de-assertion of the upper control input, the controller is further configured to electrically float the upper collector-emitter.

15. The switch assembly according to claim 9, further comprising: a lower CE FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate coupled to the controller; Wherein when the controller senses de-assertion of the upper control input, the controller is further configured to assert the gate of the lower CE FET, thereby commutating an off current to the lower terminal.

16. The switch assembly according to claim 15, further comprising: a lower CE source arranged to selectively extract charge carriers from the lower collector-emitter through the lower CE FET; Wherein when the controller senses de-assertion of the upper control input, the controller is further configured to render the lower CE FET conductive, thereby extracting charge carriers from the lower collector-emitter.

17. The switch assembly according to claim 9, further comprising: a lower control input coupled to the controller; and wherein for a second applied voltage across the upper terminal and the lower terminal, the second applied voltage has an opposite polarity to the first applied voltage, the controller is further configured to: asserting the gate of the lower main FET to render the lower main FET conductive, arranging the transistor for conduction from the lower base to the upper base, and asserting the gate of the upper main FET to render the upper main FET conductive such that a second load current flows from the lower terminal to the upper terminal; sensing de-assertion of the lower control input; and in response to de-assertion of the lower control input, The gate of the upper main FET is de-asserted to interrupt the second load current from the upper base.

18. The switch assembly of claim 17, further comprising: a lower CE source and a lower CE FET, the lower CE source being arranged to selectively inject charge carriers into the lower collector-emitter through the lower CE FET; and wherein when the controller arranges the transistor for conduction from the lower base to the upper base, the controller is further configured to render the lower CE FET conductive, thereby injecting charge carriers into the lower collector-emitter; and Wherein when the controller senses de-assertion of the lower control input, the controller is further configured to render the lower CE FET non-conductive, thereby ceasing injection of charge carriers into the lower collector-emitter.

19. A method of operating a bidirectional dual base bipolar junction transistor, the method comprising: making the transistor conductive from an upper base to a lower base by supplying current to an upper collector-emitter of the transistor and electrically floating a lower collector-emitter of the transistor; and then The transistor is rendered non-conductive by electrically floating the upper collector-emitter, electrically floating the lower base, and conducting an off current through the lower collector-emitter of the transistor.

20. The method of claim 19, wherein electrically floating the lower base further comprises rendering a lower main electrical control switch having a first lead coupled to the lower base non-conductive.

21. The method of claim 19, wherein rendering the transistor conductive further comprises: closing an upper main electrical control switch coupled between an upper terminal and the upper base; and A lower main electrical control switch coupled between a lower terminal and the lower base is closed.

22. The method of claim 21 , wherein rendering the transistor non-conductive further comprises: Disconnect the upper main electrical control switch; conducting the off current to the upper base through a diode associated with the upper main electrical control switch; and The off current is commutated from the lower base to the lower collector-emitter by opening the lower main electrical control switch.

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