High-side n-type power transistor gate drive technique without bootstrap capacitor

Abstract

Techniques and apparatus for driving a gate of a high-side transistor in a switched mode power supply (SMPS) circuit, such as an inverted buck-boost converter or buck converter. One example technique for pulling down a gate voltage of a high-side transistor involves a multi-step approach in which the gate voltage is initially discharged to a lower voltage level and an auxiliary switch can take over to fully turn off the high-side transistor once the gate voltage falls below a certain level. One example SMPS circuit generally includes a high-side transistor, a pull-down gate driver having an output coupled to a gate of the high-side transistor, a pulse generator having an output coupled to an input of the pull-down gate driver, and a first switch coupled between the gate and a source of the high-side transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial No. 17 / 934,487 filed on September 22, 2022, and the above application is hereby incorporated herein by reference. Technical Field

[0003] Generally speaking, certain aspects of the present disclosure relate to electronic circuits, and more particularly, certain aspects of the present disclosure relate to gate driver architectures and methods for gate driving in switch mode power supplies. Background Art

[0004] A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. Although linear regulators tend to be small and compact, many applications may benefit from the increased efficiency of switching regulators (also called "switching converters"). Linear regulators can be implemented, for example, by low dropout (LDO) regulators. Switching regulators can be implemented by a switch mode power supply (SMPS), such as a buck converter, a boost converter, a buck-boost converter, or a charge pump.

[0005] For example, a buck converter is a type of SMPS that typically includes: (1) a high-side switch coupled between a relatively high voltage rail and a switch node, (2) a low-side switch coupled between the switch node and a relatively low voltage rail, and (3) an inductor (e.g., represented by a shunt capacitive element) coupled between the switch node and the load. The high-side and low-side switches can be implemented with transistors, although the low-side switch can alternatively be implemented with a diode.

[0006] A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., buck converters or buck-boost converters). A PMIC may be used in battery-operated devices (such as mobile phones, tablets, laptops, wearable devices, etc.) to control the flow and direction of power in the device. The PMIC may perform various functions of the device, such as DC to DC conversion (e.g., using a voltage regulator as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. Summary of the invention

[0007] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired attributes. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and especially after reading the section entitled "Detailed Description," it will be understood how the features of the present disclosure provide the advantages described herein.

[0008] Certain aspects of the present disclosure provide a switch mode power supply (SMPS) circuit. In summary, the SMPS circuit includes a high-side transistor, a pull-down gate driver having an output coupled to a gate of the high-side transistor, a pulse generator having an output coupled to an input of the pull-down gate driver, and a first switch coupled between the gate and a source of the high-side transistor.

[0009] Certain aspects of the present disclosure provide a power management integrated circuit (PMIC) including at least a portion of the SMPS circuit described herein.

[0010] Certain aspects of the present disclosure provide a method of supplying power. In summary, the method includes: pulling down a gate voltage of a high-side transistor in an SMPS circuit; and when the gate voltage is pulled down to a specific voltage level, closing a first switch to effectively short-circuit the gate and source of the high-side transistor to turn off the high-side transistor.

[0011] To achieve the aforementioned and related purposes, one or more aspects include features fully described below and specifically pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features indicate only some of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By referring to various aspects (some of which are shown in the accompanying drawings), a more specific description of the above brief summary can be obtained so that the above-mentioned features of the present disclosure can be understood in detail. However, it is to be noted that the accompanying drawings only illustrate certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the description may admit of other equally effective aspects.

[0013] Figure 1 is a block diagram of an example device including a switched mode power supply (SMPS) circuit in which aspects of the present disclosure may be practiced.

[0014] Figure 2A is a block diagram of an example SMPS circuit in which aspects of the present disclosure may be practiced.

[0015] Figure 2B is a circuit diagram of an example gate driver and an example inverting buck-boost converter in which aspects of the present disclosure may be practiced.

[0016] FIG. 3A is a circuit diagram of an example gate driver architecture for an inverting buck-boost converter using a bootstrap capacitor to power the high-side gate driver (in Figure 3A-1 ) and the corresponding timing diagram (in Figure 3A-2 middle). Figure 3A-1 and Figure 3A-2 It will be considered as Figure 3A hereinafter.

[0017] Figure 3B is a cross section of an example semiconductor fabricated using a triple-well process.

[0018] 3C is a circuit diagram of an example gate driver architecture for an inverting buck-boost converter using a bootstrap capacitor to power the pull-down portion of a segmented high-side gate driver (in Figure 3C-1 ) and the corresponding timing diagram (in Figure 3C-2 middle). Figure 3C-1 and 3C-2 It will be considered as Figure 3C hereinafter.

[0019] 3D is a circuit diagram of an example gate driver architecture for an inverting buck-boost converter using a pulse generator and one or more auxiliary switches in accordance with certain aspects of the present disclosure (see FIG. Figure 3D-1 ) and the corresponding timing diagram (in Figure 3D-2 middle). Figure 3D-1 and 3D-2 It will be considered as Figure 3D hereinafter.

[0020] Figure 3E is a circuit diagram of an example implementation of an auxiliary switch using back-to-back n-channel field effect transistors (NFETs) according to certain aspects of the present disclosure.

[0021] Figure 3F is a circuit diagram of an example implementation of a pull-down portion of a segmented high-side gate driver according to certain aspects of the present disclosure.

[0022] Figure 4 is a circuit diagram of an example gate driver architecture for a buck converter using a pulse generator and an auxiliary switch according to certain aspects of the present disclosure.

[0023] Figure 5 is a flow diagram of example operations for powering according to certain aspects of the present disclosure.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0025] Certain aspects of the present disclosure provide techniques and apparatus for driving the gate of a high-side transistor in a switched mode power supply (SMPS) circuit, such as an inverting buck-boost converter or a buck converter. One example technique for pulling down the gate voltage of the high-side transistor involves a multi-step approach, where the gate voltage is initially discharged to reduce the voltage, and once the gate voltage drops below a certain level, an auxiliary switch can take over to completely turn off the high-side transistor.

[0026] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. More specifically, these aspects are provided so that the present disclosure will be thorough and complete, and these aspects will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether the aspect is implemented independently or in combination with any other aspect. For example, using any number of aspects set forth herein, a device can be implemented or a method can be implemented. In addition, the scope of the present disclosure is intended to cover such a device or method implemented using various aspects of the present disclosure set forth herein or other structures, functions, or structures and functions different therefrom. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the claims.

[0027] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0028] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that component A is directly connected to component B, or that other components may be connected between components A and B (i.e., component A is indirectly connected to component B). In the case of electrical components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect components A and B (and any components electrically connected therebetween).

[0029] Example Device

[0030] It should be understood that aspects of the present disclosure may be used in a variety of applications. Although the present disclosure is not limited in this regard, the circuits disclosed herein may be used in any of a variety of suitable devices, such as in a power supply, battery charging circuit or power management circuit of a communication system, a video codec, an audio device such as a music player and a microphone, a television, a camera device, and a test device such as an oscilloscope. By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), Internet of Things (IoT) devices, and the like.

[0031] Figure 1 An example device 100 is shown in which aspects of the present disclosure may be implemented. Device 100 may be a battery operated device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop, a tablet, a smartphone, an IoT device, a wearable device, an augmented reality device, or the like.

[0032] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106 (which may include both read-only memory (ROM) and random access memory (RAM)) provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0033] In some aspects, the device 100 may also include a transmitter 110 and / or a receiver 112 to allow data to be sent and / or received, respectively, between the device 100 and a remote location. For some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 of the device 100 and electrically coupled to the transceiver 114. For some aspects, the device 100 may include multiple transmitters, multiple receivers, and / or multiple transceivers (not shown).

[0034] The device 100 may also include a signal detector 118, which may be used to facilitate detection and quantification of the level of the signal received by the transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0035] Device 100 may also include a battery 122 for powering various components of device 100. For certain aspects, battery 122 may be rechargeable.

[0036] The device 100 may also include a power management integrated circuit (PMIC) 124 (also referred to as a "power management unit (PMU)") for managing power from the battery to various components of the device 100. The PMIC 124 may perform various functions of the device, such as DC to DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In some aspects, the PMIC 124 may include at least a portion of a power supply circuit, which may include a switch mode power supply (SMPS) circuit 125. The SMPS circuit 125 may be implemented by any of a variety of suitable switch mode power supply circuit topologies, such as a buck converter, a boost converter, an inverting buck-boost converter, or a charge pump. For some aspects, the SMPS circuit 125 may include a high-side gate driver architecture having a pulse generator, a pull-down gate driver having an input coupled to the output of the pulse generator and an output coupled to the gate of the high-side transistor, and one or more switches coupled between the gate and source of the high-side transistor, as described below. For some aspects, the PMIC 124 may include a battery charging circuit (e.g., a master-slave battery charging circuit) for charging the battery 122.

[0037] The various components of the device 100 may be coupled together via a bus system 126 , which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0038] Example power supply circuit with gate driver and switching circuit

[0039] Figure 2A is a block diagram of an example switch mode power supply (SMPS) circuit 200 in which aspects of the present disclosure may be practiced. The SMPS circuit 200 may include a control logic 210, a gate driver 220, and a switch circuit 230. The control logic 210 may output a control signal to control the timing of components in the gate driver 220. The gate driver 220 may output a signal having a specified output signal swing to control a control input (e.g., a gate) of a switching device (e.g., a power field effect transistor (FET)) in the switch circuit 230. The gate driver 220 may be powered by any of a variety of suitable supply voltages.

[0040] Figure 2B2 is a circuit diagram 250 of a portion of an example gate driver 220 and an example switch circuit 230 in which aspects of the present disclosure may be practiced. The gate driver 220 may include logic buffers 222, 224 and switches, which may be implemented by transistors M10 and M11, as shown. The logic buffer 222 may have an input coupled to the output of the control logic 210, and may have an output coupled to the control input of the transistor M10. In this example, the transistor M10 is implemented as a p-type field effect transistor (PFET) having a source coupled to a first voltage rail (labeled "Vdd1"), a gate coupled to the output of the logic buffer 222, and a drain coupled to an output node 226 of this portion of the gate driver 220. The logic buffer 224 may have an input coupled to another output of the control logic 210, and may have an output coupled to the control input of the transistor M11. In this example, transistor M11 is implemented as an n-type field effect transistor (NFET) having a drain coupled to the output node 226 of this portion of the gate driver 220, having a gate coupled to the output of the logic buffer 224, and having a source coupled to a second voltage rail (labeled "Vdd2") having a lower voltage than the first voltage rail (Vdd1). The power supply inputs of the logic buffers 222, 224 may be coupled to the first and second voltage rails, or may be coupled to one or more different power supply rails.

[0041] In this example, the switching circuit 230 is implemented as an inverting buck-boost converter. However, it should be understood that the switching circuit can alternatively be implemented as any other various suitable switching converter topologies, such as a boost converter or a buck converter. As shown, the inverting buck-boost converter includes power transistors M0, M1, an inductive element L1 (e.g., implemented by one or more inductors) and a capacitive element C1 (e.g., implemented by one or more capacitors). The high-side transistor M0 is an NFET having a drain coupled to an input node 227 (also referred to herein as an "input voltage node") of the inverting buck-boost converter (having a voltage Vin provided by a power supply 234), a gate coupled to the output of the gate driver 220 (i.e., the output node 226), and a source coupled to a switch node 228 (also referred to herein as a "switching voltage (VSW) node"). The low-side transistor M1 is also an NFET having a drain coupled to the switch node 228, a gate coupled to the gate driver 220 ( Figure 2B2 (not shown) and has a source coupled to an output node 232 (also referred to herein as an "output voltage node") of an inverting buck-boost converter (having a voltage Vout). A portion of a control input of a gate driver 220 (e.g., a low-side gate driver) for controlling low-side transistor M1 is not shown, but can be implemented in a manner similar to that described above for a portion of a control input of a gate driver 220 (e.g., a high-side gate driver) for controlling high-side transistor M0. For some aspects, transistor M1 can be replaced with another suitable component, such as a diode having an anode coupled to output node 232 and a cathode coupled to switch node 228.

[0042] A first terminal of the inductive element L1 is coupled to the switch node 228, and a second terminal of the inductive element L1 is coupled to a reference potential node (e.g., electrical ground) of the inverting buck-boost converter. A first terminal of the capacitive element C1 is coupled to the output node 232, and a second terminal of the capacitive element C1 is coupled to the reference potential node. An output voltage Vout of the inverting buck-boost converter is generated across the capacitive element C1, as shown. In an inverting buck-boost converter, Vout typically has an opposite polarity to Vin and is adjustable (e.g., between -3V and -10V) based on the duty cycle of the switching transistors M0 and M1.

[0043] During operation, the logic buffers 222, 224 can receive control signals (e.g., logic level signals of lower amplitude) from the control logic and generate signals for driving the control inputs (e.g., gates) of the transistors M10, M11. In some aspects, the buffer output signal can have a higher voltage swing than the control signal received from the control logic 210. In this way, the output signal from the gate driver 220 on the output node 226 can be pulled up to turn on the power transistor M0 and can be pulled down to turn off the transistor M0, depending on the switching frequency and duty cycle of the inverting buck-boost converter. Similarly, another output signal from the gate driver 220 can be used to control the operation of the power transistor M1, where the gate can be pulled up to turn on the transistor M1 and can be pulled down to turn off the transistor M1. The gate signal can be operated in a break-before-make manner so that the transistor M0 is turned off before the transistor M0 is turned on, and vice versa. As described above, Vout is controlled based on the duty cycle of the switching power transistors M0 and M1.

[0044] The gate drive signal from gate driver 220 may exceed Vin (e.g., exceed 5V) at the drain of transistor M0 in order to fully turn on the n-type transistor. And in order to completely turn off transistor M0, the gate drive signal can be driven to be at least as low as the switching voltage (VSW) at the source of the n-type transistor. Therefore, the output node 226 should be driven (by gate driver 220) to Vin plus some additional voltage (e.g., 5V) and down to VSW (e.g., which can reach -10V). Therefore, if Vin is +5V, the gate can be driven with a swing between +10V and -10V. This voltage swing can be challenging, especially when trying to keep transistor M0 off in an inverting buck-boost converter.

[0045] Example gate driver for high-side transistor with bootstrap capacitor

[0046] 3A is a circuit diagram 300 of an inverting buck-boost converter, an example implementation of a gate driver, and a corresponding timing diagram 310. An inverting buck-boost converter is similar to Figure 2B An inverting buck-boost converter is shown and the same reference numerals are used.

[0047] 3A includes a floating rail generator 301, a switch Sboot, a bootstrap capacitor Cboot, a high-side (HS) level shifter 302, a low-side (LS) level shifter 303, a HS gate driver 304, and a LS gate driver 305. The gate driver may also include a deep n-well (DNW) bias circuit 306.

[0048] The floating rail generator 301 can be a voltage source (e.g., a power supply circuit) configured to generate a floating voltage (Vfloat,n) referenced to Vout, where Vfloat,n can be approximately 3 to 5V higher than Vout, for example, to provide sufficient gate-to-source voltage (Vgs) to turn on transistor M1. The higher the floating voltage Vfloat,n, the higher the Vgs that the LS gate driver 305 can apply to transistor M1, and the higher the drain-to-source on-resistance R that can be achieved. DS,on For some aspects, as an example, if Vout is −10V, then Vfloat,n may be −5V. Floating rail generator 301 is coupled between output node 232 and floating power rail 311 .

[0049] The LS level shifter 303 and the LS gate driver 305 can each have a power input coupled between the floating power rail 311 and the output node 232 to receive power from the floating rail generator 301. The LS level shifter 303 has an input coupled to the output of the control logic 210 for receiving a low-side control signal (labeled "LS_CTL"). The LS level shifter 303 can also have a separate power input coupled between a digital voltage rail (labeled "DVDD") and (digital domain) electrical ground, as shown in FIG. 3A. In this way, the LS level shifter 303 can level shift a logic level signal (LS_CTL) received from the control logic 210 and swinging from 0V to DVDD to a LS drive signal (labeled "LS_DRV") that swings from Vout to Vfloat,n. The LS gate driver 305 has an input coupled to the output of the LS level shifter 303 and has an output coupled to the gate of the low-side transistor M1. In this way, the gate of transistor M1 can be driven with a control signal that swings from Vout to Vfloat,n, which should be sufficient to turn transistor M1 off or on.

[0050] In FIG3A , switch Sboot is coupled between floating power rail 311 and a first terminal of bootstrap capacitor Cboot. A second terminal of capacitor Cboot is coupled to switch node 228 at switch voltage VSW. By selectively charging bootstrap capacitor Cboot from Vfloat,n through switch Sboot (e.g., when high-side transistor M0 is off and VSW is low), a bootstrap power rail 313 with floating bootstrap voltage Vboot is generated, referenced to VSW. Thus, the Vboot domain moves dynamically with VSW. In the bootstrap case, when transistor M0 is on, Vboot can rise as high as VIN plus the voltage across floating rail generator 301, as shown in the waveform of Vboot in timing diagram 310. When transistor M0 is off, Vboot drops due to the drop in VSW.

[0051] The HS level shifter 302 and the HS gate driver 304 can each have a power input coupled between the bootstrap power rail 313 and the switch node 228 to receive power from the capacitor Cboot when the switch Sboot is open, and to receive power from the floating rail generator 301 when the switch Sboot is closed. The HS level shifter 302 has an input coupled to the output of the control logic 210 for receiving a high-side control signal (labeled “HS_CTL”). Similar to the LS level shifter 303, the HS level shifter 302 can also have a separate power input coupled between the digital voltage rail (DVDD) and the (digital domain) electrical ground. In this way, the HS level shifter 302 can level shift a logic level signal (HS_CTL) received from the control logic 210 and swinging from 0V to DVDD to a HS drive signal (labeled “HS_DRV”) swinging from VSW to Vboot, as shown in the timing diagram 310. HS gate driver 304 has an input coupled to the output of HS level shifter 302 and has an output coupled to the gate of high-side transistor M0. In this manner, the gate of transistor M0 may be driven with a control signal that swings from VSW to Vboot.

[0052] As mentioned above about Figure 2B As described, the HS gate driver 304 (and / or the LS gate driver 305) may include a p-type metal oxide semiconductor (PMOS) transistor (e.g., transistor M10) and an n-type metal oxide semiconductor (NMOS) transistor (e.g., transistor M11). For certain aspects, the gate driver may be fabricated using a triple well semiconductor process, such as Figure 3B 386, a deep n-well 387, a p-well 388, and an n-well 389. Doping is used to create an NMOS transistor 390 (with n+ doped regions for source (S) and drain (D)) above the p-well 388 and a PMOS transistor 392 (with p+ doped regions for source (S) and drain (D)) above the n-well 389. The PMOS transistor 392 has deep n-well isolation (but may have no other isolation), and the deep n-well 387 is located on the p-substrate 386. The body of the PMOS transistor 392 may be n+ doped and may be shorted to the deep n-well 387, as shown. Figure 3BAs shown. When the PMOS gate (G) swings negative, the n-well should not go negative, lest the body diode 394 from the p substrate 386 becomes forward biased, which could cause latch-up. To avoid latch-up (and forward biased body diode), the PMOS gate voltage can be effectively clamped at a certain voltage level (e.g., ≥0V). Therefore, if the gate driver swings down into the negative voltage domain, the body connection can be isolated and a separate reference voltage or supply voltage can be provided to prevent latch-up effects.

[0053] 3A may also include a DNW bias circuit 306 having an output coupled to the PFET transistor body in the HS gate driver 304. The DNW bias circuit 306 may provide a separate power supply for the body to prevent latch-up.

[0054] In an inverting buck-boost converter such as that shown in circuit diagram 300, there are several design challenges associated with driving the high-side n-type transistor M0. The HS gate driver 304 is referenced to VSW, which can typically switch from a negative voltage domain (VOUT) to a positive voltage domain (VIN) very quickly, as shown by the waveform of VSW in timing diagram 310. For example, in some converters, VSW can swing from -10V to +10V and back, in some cases, for 1 to 3ns. The floating voltage source Vboot in this topology can call on a large capacitor Cboot to provide charge to the HS level shifter 302 and the HS gate driver 304 (e.g., when the switch Sboot is open). Due to this large size, the bootstrap capacitor Cboot can be external to an integrated circuit (e.g., a PMIC) with the remaining components of the inverting buck-boost converter and can occupy some considerable area in a device with the converter. Additionally, using Vfloat,n (from the floating rail generator 301 referenced to Vout) to charge the capacitor Cboot may be inefficient, and there may be issues with recharging the capacitor Cboot during high impedance states (e.g., when both transistors M0, M1 are off and VSW is 0V), during startup, during pulse skipping mode, when the HS driver is not switching, or over time. Additionally, the design of the HS level shifter 302 may be challenging because HS_DRV swings between negative and positive voltage domains, where the power supply inputs (Vboot and VSW) of the HS level shifter move together. Preventing the HS level shifter 302 from losing its state during the transition between the negative and positive domains may be a design challenge. Additionally, for the same reasons, deep n-well (DNW) biasing may also be challenging in an inverting buck-boost converter, where the DNW bias voltage should be positive (e.g., clamped to >0V) to prevent parasitic diodes (e.g., body diode 394) from switching during the transition. Figure 3Bis forward biased in a triple-well process.

[0055] FIG3C is used for Figure 2B 3C and 3A. Much of the circuit diagram 320 of FIG. 3C is similar to the circuit diagram 300 of FIG. 3A, uses the same reference numerals, and will not be described again.

[0056] The main difference between circuit diagrams 300 and 320 is that the HS gate driver is divided into a HS pull-up gate driver 324 and a HS pull-down gate driver 326 (referred to as a "segmented HS gate driver") in FIG. 3C, each operating using a different power domain, but having an output coupled to the gate of transistor M0. The pull-up driver 324 can be used as a buffer without pull-down capability, while the pull-down driver 326 can be used as an inverting buffer without pull-up capability. For example, the pull-up driver 324 can be implemented by an inverter having an output coupled to the gate of a p-type field effect transistor (PFET). In contrast, the pull-down driver 326 can be implemented by two cascaded inverters having an output coupled to the gate of an n-type field effect transistor (NFET).

[0057] In addition to the segmented HS gate drivers, the gate driver architecture of FIG. 3C also includes segmented level shifters: HS level shifter 302 and another HS level shifter 322. The input of HS level shifter 322 is coupled to the output of control logic 210 for receiving HS_CTL, and the input of HS level shifter 302 may be coupled to the output of control circuit 210 via inverter 321. In this case, the input of inverter 321 is coupled to the output of control logic 210 for receiving the HS_CTL signal, and the output of inverter 321 is coupled to the input of HS level shifter 302. The output of HS level shifter 322 is coupled to the input of pull-up driver 324, and the output of HS level shifter 302 is coupled to the input of pull-down driver 326.

[0058] Here, the pull-down driver 326 and the HS level shifter 302 may each have a power input coupled between the bootstrap power rail 313 and the switch node 228 to receive power from the capacitor Cboot when the switch Sboot is open, and to receive power from the floating rail generator 301 when the switch Sboot is closed, similar to that described above for the HS gate driver 304 and the HS level shifter 302 of FIG. 3A . However, the HS level shifter 322 and the pull-up driver 324 receive power from different power domains.

[0059] For certain aspects, a power supply circuit (e.g., a boost converter) referenced to Vin or another suitable voltage may be used to generate a voltage (labeled “CBST”) on the boost power rail 323 that is greater than Vin (e.g., 3 to 5V greater, e.g., 4V greater). In this case, the HS level shifter 322 and the pull-up driver 324 may each have a power input coupled between the boost power rail 323 and the input node 227 having Vin. The HS level shifter 322 may also have a separate power input coupled between the digital voltage rail (DVDD) and (digital domain) electrical ground, similar to the HS level shifter 302 and the LS level shifter 303. In this manner, the HS level shifter 322 may level shift a logic level signal (HS_CTL) received from the control logic 210 and swinging from 0V to DVDD to a HS pull-up drive signal (labeled “HS_DRV_PU”) that swings from Vin to CBST, as shown in the timing diagram 330. Vin and CBST are DC voltages and do not track VSW. Additionally, HS level shifter 302 may level shift HS_CTL to a HS pull-down drive signal (labeled “HS_DRV_PD”) that swings from VSW to Vboot, as shown in timing diagram 330. In this manner, the gate of transistor M0 may be pulled up to CBST by pull-up driver 324 (when HS_CTL is logic high) and pulled down to VSW by pull-down driver 326 (when HS_CTL is logic low).

[0060] With the segmented gate driver of FIG. 3C , the size and capacitance of the bootstrap capacitor Cboot can be significantly reduced compared to the capacitor Cboot of FIG. 3A . This is because the bootstrap capacitor Cboot of FIG. 3C is used to bias the HS level shifter 302 instead of actually providing power to the gate of transistor M0 as in FIG. 3A . Therefore, the capacitor Cboot can be implemented as an internal capacitor in an integrated circuit of a switching regulator using the topology of FIG. 3C . However, Vfloat,n is still used to charge the capacitor Cboot, which may be inefficient. In addition, the design of the HS level shifter 302 on the Vboot domain and the DNW bias design are still challenging for this implementation.

[0061] Example gate driver for high-side transistor without bootstrap capacitor

[0062] Certain aspects of the present disclosure provide apparatus and techniques for driving the gate of a high-side power transistor in a switching regulator using a segmented driver, wherein the pull-down has a two-step approach. In this approach, the high-side gate voltage is pulled down to a voltage below which an auxiliary switch can take over to completely shut down the high-side transistor using the output voltage domain rather than the VSW domain. This two-step conversion can be achieved by introducing a pulse generator and an auxiliary switch into the high-side pull-down path of the gate driver architecture and by powering the HS level shifter, pulse generator, and HS pull-down gate driver from rails at Vfloat,n and Vout.

[0063] FIG. 3D is a diagram for use in accordance with certain aspects of the present disclosure. Figure 2B 3A and a corresponding timing diagram 350. Much of the circuit diagram 340 of FIG. 3D is similar to the circuit diagram 320 of FIG. 3C, uses the same reference numerals, and will not be described again.

[0064] The circuit diagram 340 of Figure 3D adds a pulse generator 344 and a switch S1. For certain aspects, the circuit diagram 340 may also include a control logic 348 (eg, for implementing a high impedance (Hi-Z) detection circuit) and a switch S2, as shown in Figure 3D.

[0065] 3C , the input of inverter 321 is coupled to the output of control logic 210 for receiving the HS_CTL signal, and the output of inverter 321 is coupled to the input of HS level shifter 302. Pulse generator 344 can be implemented by, for example, a one-shot circuit (referred to as a monostable multivibrator). The input of pulse generator 344 can be coupled to the output of HS level shifter 302, and the output of the pulse generator can be coupled to the input of pull-down driver 326. The outputs of pull-up driver 324 and pull-down driver 326 are coupled to the gate of transistor M0.

[0066] In contrast to the circuit diagram 320 of FIG. 3C , the HS level shifter 302, pulse generator 344, and pull-down driver 326 of FIG. 3D may each have a power supply input coupled between the floating power rail 311 and the output node 232. The inverter 321 and the HS level shifter 302 may also have a power input coupled between a digital voltage rail (DVDD) and (digital domain) electrical ground. In this manner, the HS level shifter 302 may level shift the HS_CTL signal to a first HS pull-down drive signal (labeled “HS_DRV_GS_SW”) that swings from Vout to Vfloat,n, as shown in the timing diagram 350. Due to the inverter 321, the HS_DRV_GS_SW at the output of the HS level shifter 302 is the inversion of the HS_CTL signal.

[0067] The pulse generator 344 is configured to generate output pulses when a suitable trigger signal is applied. In this case, the pulse generator 344 can be triggered by the rising edge of the HS_DRV_GS_SW signal, causing the pulse generator to output a second HS pull-down drive signal (labeled "HS_DRV_PD") having a single pulse on each rising edge of the HS_DRVG_GS_SW signal, as shown in the timing diagram 350. Due to the power rail coupled to the pulse generator 344, the pulse swings from Vout to Vfloat,n.

[0068] 3C , HS level shifter 322 and pull-up driver 324 each have a power supply input coupled between boosted power rail 323 and input node 227 having Vin. In this manner, HS level shifter 322 can level shift the HS_CTL signal to a HS pull-up drive signal (labeled “HS_DRV_PU”) that swings from Vin to CBST, as shown in timing diagram 350, and when HS_CTL (and HS_DRV_PU) are logic high, the HS_DRV_PU signal can control pull-up driver 324 with the correct timing to pull up the gate of transistor M0 to CBST.

[0069] Switch S1 is coupled between the gate and source of transistor M0. A control input of switch S1 can be coupled to the output of HS level shifter 302 (i.e., to the input of pulse generator 344). For some aspects, switch S1 can be implemented by back-to-back transistors (such as back-to-back n-type field effect transistors (NFETs) M2 and M3), as shown in FIG. Figure 3E In this case, the sources of NFETs M2 and M3 may be coupled together, and the gates of NFETs M2 and M3 may be coupled together and to the control input of switch S1, which is switched on in Figure 3E The drain of NFET M2 may be coupled to one terminal of switch S1 (labeled as “terminal 1”), and the drain of NFET M2 may be coupled to the other terminal of switch S1 (labeled as “terminal 2”).

[0070] Figure 3Fis a circuit diagram of an example implementation of a pull-down driver 326 according to certain aspects of the present disclosure. In this example, the pull-down driver 326 is implemented as a first complementary metal oxide semiconductor (CMOS) inverter (including PFET M4 and NFET M5), a second CMOS inverter (including PFET M6 and NFET M7) coupled in series with the first CMOS inverter, and an NFET M9 having a gate coupled to the output of the second CMOS inverter. The input of the pull-down driver 326 can be coupled to the gates of the PFET M4 and NFET M5 in the first inverter. The drains of the PFET M4 and NFET M5 can be coupled together and coupled to the gates of the PFET M6 and NFET M7 in the second inverter. The drains of the PFET M6 and NFET M7 can be coupled together and coupled to the gate of the NFET M9. The pull-down driver 326 can also have an NFET M8 having a source and body coupled to the drain of the NFET M9, and having a drain coupled to the output of the pull-down driver. The sources of PFETs M4 and M6 (and the gate of NFET M8) may be coupled to a higher supply voltage rail (labeled "SUPPLY 2"), and the sources of NFETs M5, M7, and M9 may be coupled to a lower supply voltage rail (labeled "SUPPLY 1"). A deep n-well bias voltage (labeled "DNW", which may be the output of DNW bias circuit 306) may be coupled to the bodies of PFETs M4 and M6. Although Figure 3F , but this may alternatively be replaced with a deep p-well bias voltage, depending on the semiconductor process used to implement the pull-down driver circuit. Figure 3F With this implementation of the pull-down driver 326 in , a logic high signal applied to the input of the pull-down driver will pull the output low (to the supply 1 level), while a logic low signal applied to the input will present a high impedance to the output (off).

[0071] As described above, the high-side pull-down path (with pulse generator 344, pull-down driver 326, and switch S1) can use a two-step transition to pull down the gate voltage of transistor M0. When the HS_CTL signal transitions from logic high to logic low, the HS_DRV_GS_SW signal transitions from Vout to Vfloat,n. When Vfloat,n is applied to the control input of switch S1, the gate of transistor M0 is initially at CBST and the source is initially at Vin, but the goal is to pull the gate down to VSW to completely shut down the high-side transistor M0. Switch S1, whose control input is at Vfloat,n, cannot initially close to short the gate of transistor M0 to the source. Therefore, pulse generator 344 is triggered to output a pulse on the rising edge of the HS_DRV_GS_SW signal to control the pull-down driver 326. The pull-down driver 326 has a pull-down stage with an n-type transistor having a source coupled to the output node 232 (at Vout). Applying a pulse at Vfloat,n to the gate of the pull-down n-type transistor in the pull-down driver 326 will pull charge from the gate of transistor M0 , causing the pull-down n-type transistor to function as a first discharge path 352 , and the gate voltage of transistor M0 will drop toward Vout.

[0072] Once VSW or the gate voltage of transistor M0 drops below Vfloat,n, switch S1 will begin to close (e.g., the back-to-back n-channel transistors turn on), and when switch S1 is fully closed (e.g., the gate-to-source voltage of the back-to-back transistors is high enough, such as above the threshold voltage), the gate of transistor M0 will effectively be shorted to the switch node 228. Closing switch S1 ensures that the gate voltage of transistor M0 follows VSW to turn off transistor M0, and also forms a second discharge path 354 from the gate of transistor M0 through switch S1. Depending on the pulse length from the pulse generator 344, the discharge paths 352, 354 can be discharged simultaneously in a short period of time. The pulse length should be set long enough to ensure that the gate voltage of transistor M0 is pulled down below Vfloat,n before the pulse on the HS_DRV_PD signal ends, thereby turning off the pull-down driver 326.

[0073] For certain aspects, a closed loop method for initially pulling down the gate voltage of transistor M0 can be used rather than relying on a fixed pulse length of the HS_DRV_PD signal set by the pulse generator 344. In this case, the gate voltage of the high-side transistor M0 can be sensed, and the pull-down driver 326 can end applying Vfloat,n when the gate voltage is at a predetermined voltage below Vfloat,n. This can help ensure that the discharge path 352 is on long enough so that the switch S1 can be activated to discharge the remaining voltage on the gate of transistor M0.

[0074] This gate drive architecture and two-step approach of FIG. 3D has several advantages. For example, closing switch S1 as described above ensures that transistor M0 is completely turned off when HS_CTL is logic low, even when VSW becomes more negative than Vout due to the significant voltage drop across the low-side transistor M1 (e.g., in the case of high load current). In addition, by referencing the high-side pull-down path to Vout rather than VSW (in step one of the conversion), the pull-down path references a stable voltage rather than a changing voltage, and the design of the high-side pull-down path is much easier in the absence of a bootstrap capacitor Cboot. Eliminating capacitor Cboot reduces the area occupied by the power supply circuit and avoids the problems described above with respect to capacitor Cboot (e.g., recharging). In addition, the HS level shifter 302 is powered by a stable Vfloat,n domain rather than a more temperature-sensitive Vboot domain, which can make the design of the HS level shifter easier.

[0075] Additionally, the output of the DNW bias circuit 306 may be coupled to a transistor body input of a pull-down driver 326 (eg, Figure 3B The PMOS body input or Figure 3F Because Vfloat,n and Vout are stable voltages (compared to the shifted Vboot domain), the output of DNW bias circuit 306 does not need to switch up and down very quickly to track a moving voltage, such as VSW. Therefore, the design of DNW bias circuit 306 can be simpler than previous implementations.

[0076] For certain aspects, the gate driver architecture may further include another auxiliary switch S2 and control logic 348 for controlling switch S2 to address additional complexity that occurs in circuit diagram 340 of FIG. 3D in some cases, for example. Switch S2 may be coupled between the gate and source of high-side transistor M0, and the output of control logic 348 may be coupled to the control input of switch S2. Switch S2 may be implemented by back-to-back NFETs, similar to Figure 3E . However, switch S2 can be driven by a positive voltage (e.g., Vin) from control logic 348 to close switch S2, and driven by a negative voltage (e.g., Vout) to open switch S2. For some aspects, control logic 348 can be part of control logic 210, while in other aspects, control circuit 348 can be physically separate from control logic 210.

[0077] The control logic 348 may include or may be part of a high impedance (Hi-Z) detection circuit configured to determine when the switch node 228 (or the source of transistor M0) enters a high impedance state, such as when the SMPS circuit is disabled, when the SMPS circuit is in a discontinuous mode (DCM) or a pulse skipping mode, or when both transistors M0 and M1 should be turned off. Most of the time, switch S2 is open. However, when the gate driver enters a high impedance state and both power transistors M0 and M1 are turned off, there is a DC short circuit (i.e., VSW=0V) from the switch node 228 to ground via the inductive element L1. In order to use switch S1 in a closed state to keep transistor M0 off in this scenario, the control input of switch S1 should be above 0V (e.g., at least above the threshold voltage (Vth) of the back-to-back NFET). However, the control signal HS_DRV_GS_SW for switch S1 may operate in a negative voltage domain (e.g., between Vout and Vfloat,n), which does not ensure that switch S1 is closed. In other words, when Vfloat,n<Vth, the switch S1 may not be able to keep the transistor M0 off.

[0078] Thus, when the SMPS circuit enters DCM mode (or another high impedance state), and in some cases, when the control logic determines that the low-side transistor M1 is turned off (e.g., using a zero-crossing detector in the control logic 348 or based on LS_CTL from the control logic 210), the control logic 348 can determine that the switch node 228 has entered a high impedance state. Therefore, the control logic 348 can apply a positive voltage (e.g., from the DVDD rail, the input node 227 (with Vin), or another power rail that powers the control logic 348) to the control input of the switch S2, thereby closing the switch S2 and shorting the gate and source of the high-side transistor M0, thereby keeping the transistor M0 off.

[0079] In this case, pulling down the gate voltage of high-side transistor M0 can be considered to involve three steps. The first step can be to pull VSW down toward Vout using pulse generator 344, the second step can be to short the gate of transistor M0 to the source using switch S1, and the third step (if in a high impedance condition during the switching cycle) is to short the gate of transistor M0 to the source using switch S2. As described above, switch S2 may be triggered infrequently and may remain open in most cases, but for light load conditions (and other high impedance scenarios),

[0080] The techniques and apparatus described above (eg, with respect to FIG. 3D ) for implementing a two-step conversion for pulling down the gate voltage of the high-side transistor M0 may also be applied to other switching converter topologies, such as a buck converter. Figure 4is a circuit diagram 400 of an example gate driver architecture for a buck converter having a pulse generator 344 and a switch S1 according to certain aspects of the present disclosure. Figure 4 Much of the circuit diagram 400 of FIG. 3D is similar to the circuit diagram 340 of FIG. 3D , uses the same reference numerals, and will not be described again. Figure 4 3A , 3C , and 3D , the LS gate drive path 349 may represent, for example, the LS level shifter 303 and the LS gate driver 305 of FIGS. 3A , 3C , and 3D .

[0081] In a buck converter, an output node 402 (having a positive output voltage Vout) is coupled to an inductive element L1 and a capacitive element C1, and the low-side transistor M1 and the capacitive element are referenced to a reference potential node 404 (eg, electrical ground) of the buck converter, as shown in FIG. Figure 4 Due to these differences between the buck converter and the inverting buck-boost converter, Figure 4 There are some differences between the gate driver implementation of the buck converter of FIG. 3D and the gate driver implementation of the inverting buck-boost converter of FIG. 3D . For example, the HS level shifter 302, the pulse generator 344, and the HS pull-down gate driver 326 each have a power supply input coupled between the input node 227 (having Vin) and the reference potential node 404. Therefore, the HS_DRV_GS_SW signal and the HS_DRV_PD signal swing between Vin and 0V, rather than between Vfloat,n and Vout. In addition, since Vin is a higher positive voltage than Vout, and because the common mode voltage of the buck converter is Vout, it is not necessary to include switch S2 and control logic 348 for detecting a high impedance state and the floating rail generator 301. In addition, since Vin is already available and provides a stable voltage for powering the components in the high-side pull-down path, it is not necessary to include the floating rail generator 301. In addition, there is no need to use a bootstrap capacitor.

[0082] In this case, as described above, the high-side pull-up gate driver 324 can use CBST to turn on the transistor. When transistor M0 should be turned off, a two-step approach is used in which the pulse generator 344 generates a pulse with amplitude Vin in the HS_DRV_PD signal, which turns on the n-type transistor in the pull-down driver 326 and creates a discharge path for the gate of transistor M0 to be pulled down toward 0 V. Once the gate voltage of transistor M0 becomes sufficiently lower than Vin, HS_DRV_GS_SW at Vin can close switch S1, thereby shorting the gate and source of transistor M0 and turning off the high-side transistor.

[0083] As described above, certain aspects of the present disclosure provide a switch mode power supply (SMPS) circuit. The SMPS circuit typically includes a high-side n-channel transistor, a segmented gate driver (also referred to as a "split driver") for the high-side n-channel transistor, and a two-stage pull-down path. The first stage can be pulled down to the output (or ground), and the second stage can be pulled down to the switch node.

[0084] Example Operation for Power Supply

[0085] Figure 5 is a flow diagram of example operations 500 for supplying power according to certain aspects of the present disclosure. Operations 500 may be performed by a switch mode power supply (SMPS) circuit having a pulse generator and one or more auxiliary switches, such as the SMPS circuits of circuit diagrams 340 and 400 having pulse generator 344 and switches S1 and S2 of FIGS. 3D and 4 .

[0086] Operation 500 may begin by pulling down a gate voltage of a high-side transistor (e.g., transistor M0) in a SMPS circuit at block 502. When the gate voltage is pulled down to a certain voltage level (e.g., below a threshold voltage of Vfloat,n or Vin), a first switch (e.g., switch S1) is closed at block 504 to effectively short-circuit the gate and source of the high-side transistor to turn off the high-side transistor.

[0087] According to certain aspects, the pull-down at block 502 involves generating a pulse (e.g., in HS_DRV_PD) for turning on an n-type transistor (not shown) in a pull-down gate driver (e.g., HS pull-down gate driver 326). For certain aspects, the SMPS circuit includes an inverting buck-boost converter, and the pull-down gate driver can be referenced to an output voltage (e.g., Vout) of the inverting buck-boost converter. In this case, the pulse can be generated from a pulse generator (e.g., pulse generator 344); the pulse generator and the pull-down gate driver can receive power from a floating power supply (e.g., floating rail generator 301) at a floating voltage (e.g., Vfloat,n); the floating power supply can be referenced to the output voltage of the inverting buck-boost converter; and the particular voltage level can be a transistor threshold voltage (Vth) that is lower than the floating voltage of the floating power supply. For other aspects, the SMPS circuit includes a buck converter, and the pull-down gate driver can be referenced to a reference potential of the buck converter. In this case, the pulses can be generated from a pulse generator; the pulse generator and the pull-down gate driver can receive power from an input voltage source at an input voltage (e.g., Vin); the input voltage source is referenced to a reference potential of the buck converter (e.g., electrical ground of 0V); and the particular voltage level is a transistor threshold voltage (e.g., Vth) that is lower than the input voltage of the input voltage source.

[0088] According to certain aspects, operation 500 may also include receiving a control signal (e.g., HS_DRV_GS_SW) from a level shifter (e.g., HS level shifter 302). In this case, the pulse generator may be a one-shot pulse generator, and the generation may involve triggering the generation of the pulse based on a rising edge of the control signal from the level shifter.

[0089] According to certain aspects, operation 500 may further include determining that the SMPS circuit is in a discontinuous conduction mode (DCM), the source of the high-side transistor is in a high impedance (Hi-Z) state, or the SMPS circuit is disabled. Based on the determination, a second switch (e.g., switch S2) may be closed to short the gate of the high-side transistor to the source.

[0090] Example aspects

[0091] In addition to the above-mentioned various aspects, specific combinations of the various aspects are also within the scope of the present disclosure, some of which are as follows:

[0092] Aspect 1: A switched mode power supply (SMPS) circuit comprising: a high-side transistor; a pull-down gate driver having an output coupled to the gate of the high-side transistor; a pulse generator having an output coupled to the input of the pull-down gate driver; and a first switch coupled between the gate and source of the high-side transistor.

[0093] Aspect 2: The SMPS circuit according to aspect 1, further comprising: a first level shifter having an output coupled to an input of the pulse generator.

[0094] Aspect 3: The SMPS circuit according to aspect 2, wherein the output of the first level shifter is also coupled to a control input of the first switch.

[0095] Aspect 4: The SMPS circuit according to any one of aspects 1 to 3 further includes: a second switch coupled between the gate and the source of the high-side transistor; and control logic having an output coupled to a control input of the second switch.

[0096] Aspect 5: The SMPS circuit according to Aspect 4, wherein the control logic is configured to: close the second switch when at least one of the following is true: the SMPS circuit is in a discontinuous conduction mode (DCM), the source of the high-side transistor is in a high impedance state, or the SMPS circuit is disabled.

[0097] Aspect 6: An SMPS circuit according to any one of Aspects 2 to 5, wherein: the SMPS circuit includes an inverting buck-boost converter, the inverting buck-boost converter includes the high-side transistor; the inverting buck-boost converter also includes an input voltage node coupled to the drain of the high-side transistor, an output voltage node, and a low-side transistor, the low-side transistor having a drain coupled to the source of the high-side transistor at a switching node and having a source coupled to the output voltage node; the SMPS circuit also includes a voltage source coupled between the output voltage node and a floating power rail; and the first level shifter, the pulse generator and the pull-down gate driver each have a first power input coupled to the floating power rail and a second power input coupled to the output voltage node.

[0098] Aspect 7: The SMPS circuit according to Aspect 6, wherein the SMPS circuit further comprises: a pull-up gate driver having an output coupled to the gate of the high-side transistor; and a second level shifter having an output coupled to the input of the pull-up gate driver, wherein the second level shifter and the pull-up gate driver each have a first power supply input coupled to a power supply rail referenced to the input voltage node and a second power supply input coupled to the input voltage node.

[0099] Aspect 8: An SMPS circuit according to Aspect 6 or 7, wherein the pulse generator is configured to output a pulse having a width greater than a transition of a gate voltage at the gate of the high-side transistor from an input voltage at the input voltage node to an output voltage at the output voltage node.

[0100] Aspect 9: The SMPS circuit of any one of aspects 6 to 8, wherein the SMPS circuit lacks a bootstrap capacitor selectively coupled between the floating power rail and the switch node.

[0101] Aspect 10: An SMPS circuit according to any one of Aspects 6 to 9, wherein the first switch is implemented as a back-to-back n-channel transistor, so that the first switch is configured to close when the gate voltage of the high-side transistor is lower than the voltage of the floating power rail by at least a threshold voltage of one of the back-to-back n-channel transistors.

[0102] Aspect 11: The SMPS circuit according to any of the preceding aspects, further comprising: a deep n-well bias circuit having an output coupled to a transistor body input of the pull-down gate driver.

[0103] Aspect 12: An SMPS circuit according to any one of Aspects 1 to 3, wherein: the SMPS circuit includes a buck converter, the buck converter includes the high-side transistor and has an input voltage node coupled to the drain of the high-side transistor; and the first level shifter, the pulse generator and the pull-down gate driver each have a first power supply input coupled to the input voltage node and a second power supply input coupled to a reference potential node of the SMPS circuit.

[0104] Aspect 13: An SMPS circuit according to Aspect 12, wherein the SMPS circuit further includes: a pull-up gate driver having an output coupled to the gate of the high-side transistor; and a second level shifter having an output coupled to the input of the pull-up gate driver, wherein the second level shifter and the pull-up gate driver each have a first power supply input coupled to a power supply rail referenced to the input voltage node and a second power supply input coupled to the input voltage node.

[0105] Aspect 14: The SMPS circuit according to Aspect 12 or 13, wherein the first switch is implemented as a back-to-back n-channel transistor, so that the first switch is configured to close when the gate voltage of the high-side transistor is lower than the voltage of the input voltage node by at least a threshold voltage of one of the back-to-back n-channel transistors.

[0106] Aspect 15: The SMPS circuit according to any one of Aspects 2 to 14, wherein the pulse generator comprises a one-shot pulse generator configured to output a pulse triggered based on a rising edge of an output signal from the first level shifter.

[0107] Aspect 16: A power management integrated circuit (PMIC), comprising at least a portion of the SMPS circuit according to any of the preceding aspects.

[0108] Aspect 17: A method of supplying power, comprising: pulling down a gate voltage of a high-side transistor in a switch mode power supply (SMPS) circuit; and when the gate voltage is pulled down to a specific voltage level, closing a first switch to effectively short-circuit the gate and source of the high-side transistor to turn off the high-side transistor.

[0109] Aspect 18: The method according to aspect 17, wherein the pulling down comprises: generating a pulse for turning on an n-type transistor in a pull-down gate driver.

[0110] Aspect 19: The method of aspect 18, wherein the SMPS circuit comprises an inverting buck-boost converter, and wherein the pull-down gate driver is referenced to an output voltage of the inverting buck-boost converter.

[0111] Aspect 20: A method according to Aspect 19, wherein: the pulse is generated from a pulse generator; the pulse generator and the pull-down gate driver receive power from a floating power supply at a floating voltage; the floating power supply is referenced to the output voltage of the inverting buck-boost converter; and the specific voltage level is a transistor threshold voltage that is lower than the floating voltage of the floating power supply.

[0112] Aspect 21: The method of aspect 18, wherein the SMPS circuit comprises a buck converter, and wherein the pull-down gate driver is referenced to a reference potential of the buck converter.

[0113] Aspect 22: A method according to Aspect 21, wherein: the pulse is generated from a pulse generator; the pulse generator and the pull-down gate driver receive power from an input voltage source at an input voltage; the input voltage source is referenced to the reference potential of the buck converter; and the specific voltage level is a transistor threshold voltage that is lower than the input voltage of the input voltage source.

[0114] Aspect 23: The method according to Aspect 22 further includes: receiving a control signal from a level shifter, wherein the pulse generator includes a single-shot pulse generator, and wherein the generating includes: triggering the generation of the pulse based on a rising edge of the control signal from the level shifter.

[0115] Aspect 24: The method according to any one of Aspects 17 to 23, further comprising: determining that the SMPS circuit is in a discontinuous conduction mode (DCM), the source of the high-side transistor is in a high-impedance state, or the SMPS circuit is disabled; and based on the determination, closing the second switch to short the gate of the high-side transistor to the source.

[0116] Additional considerations

[0117] The various operations of the above method can be performed by any suitable unit capable of performing the corresponding function. The unit may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, where there are operations shown in the accompanying drawings, generally, where there are operations shown in the drawings, those operations may have corresponding paired units plus functional components with similar numbers.

[0118] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, and the like. Furthermore, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0119] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0120] The methods disclosed herein include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0121] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A switch mode power supply (SMPS) circuit, comprising: High-side transistor; a pull-down gate driver having an output coupled to a gate of the high-side transistor; a pulse generator having an output coupled to an input of the pull-down gate driver; as well as A first switch is coupled between the gate and source of the high-side transistor.

2. The SMPS circuit according to claim 1, further comprising: A first level shifter has an output coupled to an input of the pulse generator.

3. The SMPS circuit according to claim 2, wherein: The output of the first level shifter is also coupled to a control input of the first switch.

4. The SMPS circuit according to claim 1, further comprising: a second switch coupled between the gate and the source of the high-side transistor; as well as A control logic has an output coupled to a control input of the second switch.

5. The SMPS circuit according to claim 4, wherein: The control logic is configured to close the second switch when at least one of the following is true: the SMPS circuit is in a discontinuous conduction mode (DCM), the source of the high-side transistor is in a high impedance state, or the SMPS circuit is disabled.

6. The SMPS circuit according to claim 2, wherein: The SMPS circuit comprises an inverting buck-boost converter, the inverting buck-boost converter comprising the high-side transistor; The inverting buck-boost converter further comprises: an input voltage node coupled to a drain of the high-side transistor; an output voltage node; and a low-side transistor having a drain coupled to the source of the high-side transistor at a switch node and having a source coupled to the output voltage node; The SMPS circuit also includes a voltage source coupled between the output voltage node and a floating power rail; and The first level shifter, the pulse generator, and the pull-down gate driver each have a first power supply input coupled to the floating power supply rail and a second power supply input coupled to the output voltage node.

7. The SMPS circuit according to claim 6, wherein: The SMPS circuit further comprises: a pull-up gate driver having an output coupled to the gate of the high-side transistor; and a second level shifter having an output coupled to the input of the pull-up gate driver, wherein the second level shifter and the pull-up gate driver each have a first power supply input coupled to a power supply rail referenced to the input voltage node and a second power supply input coupled to the input voltage node.

8. The SMPS circuit according to claim 6, wherein: The pulse generator is configured to output a pulse having a width greater than a transition of a gate voltage at the gate of the high-side transistor from an input voltage at the input voltage node to an output voltage at the output voltage node.

9. The SMPS circuit according to claim 6, wherein: The SMPS circuit lacks a bootstrap capacitor selectively coupled between the floating power rail and the switch node.

10. The SMPS circuit according to claim 6, wherein: The first switch is implemented as back-to-back n-channel transistors such that the first switch is configured to close when a gate voltage of the high-side transistor is lower than a voltage of the floating power rail by at least a threshold voltage of one of the back-to-back n-channel transistors.

11. The SMPS circuit according to claim 6, further comprising: A deep n-well bias circuit has an output coupled to the transistor body input of the pull-down gate driver.

12. The SMPS circuit of claim 2, wherein: The SMPS circuit includes a buck converter including the high-side transistor and having an input voltage node coupled to a drain of the high-side transistor; and The first level shifter, the pulse generator, and the pull-down gate driver each have a first power supply input coupled to the input voltage node and a second power supply input coupled to a reference potential node of the SMPS circuit.

13. The SMPS circuit according to claim 12, wherein: The SMPS circuit further comprises: a pull-up gate driver having an output coupled to the gate of the high-side transistor; and a second level shifter having an output coupled to the input of the pull-up gate driver, wherein the second level shifter and the pull-up gate driver each have a first power supply input coupled to a power supply rail referenced to the input voltage node and a second power supply input coupled to the input voltage node.

14. The SMPS circuit according to claim 12, wherein: The first switch is implemented as back-to-back n-channel transistors such that the first switch is configured to close when a gate voltage of the high-side transistor is lower than a voltage of the input voltage node by at least a threshold voltage of one of the back-to-back n-channel transistors.

15. The SMPS circuit according to claim 2, wherein: The pulse generator includes a one-shot pulse generator configured to output a pulse triggered based on a rising edge of an output signal from the first level shifter.

16. A power management integrated circuit (PMIC) comprising at least a portion of the SMPS circuit according to claim 1.

17. A method for supplying power, comprising: Pulling down the gate voltage of the high-side transistor in a switched-mode power supply (SMPS) circuit; as well as When the gate voltage is pulled down to a specific voltage level, the first switch is closed to effectively short-circuit the gate and source of the high-side transistor to turn off the high-side transistor.

18. The method according to claim 17, wherein: The pulling down includes generating a pulse for turning on an n-type transistor in a pull-down gate driver.

19. The method according to claim 18, wherein: The SMPS circuit comprises an inverting buck-boost converter, and wherein the pull-down gate driver is referenced to an output voltage of the inverting buck-boost converter.

20. The method of claim 19, wherein: The pulses are generated from a pulse generator; The pulse generator and the pull-down gate driver receive power from a floating power supply at a floating voltage; The floating power supply is referenced to the output voltage of the inverting buck-boost converter; and The specific voltage level is a transistor threshold voltage lower than the floating voltage of the floating power supply.

21. The method according to claim 18, wherein: The SMPS circuit comprises a buck converter, and wherein the pull-down gate driver is referenced to a reference potential of the buck converter.

22. The method of claim 21, wherein: The pulses are generated from a pulse generator; The pulse generator and the pull-down gate driver receive power from an input voltage source at an input voltage; said input voltage source being referenced to said reference potential of said buck converter; and The specific voltage level is a transistor threshold voltage lower than the input voltage of the input voltage source.

23. The method according to claim 22, further comprising: A control signal is received from a level shifter, wherein the pulse generator comprises a one-shot pulse generator, and wherein the generating comprises triggering the generation of the pulse based on a rising edge of the control signal from the level shifter.

24. The method of claim 17, further comprising: determining that the SMPS circuit is in a discontinuous conduction mode (DCM), the source of the high-side transistor is in a high impedance state, or the SMPS circuit is disabled; as well as Based on the determination, a second switch is closed to short the gate of the high-side transistor to the source.

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