Solid-state imaging device, comparator, and electronic device

Abstract

[Problem] To reduce noise in an image sensor. [Solution] A solid-state imaging device is provided with a light-receiving element, a first amplifier circuit, a second amplifier circuit, and a control circuit. The first amplifier circuit amplifies and outputs a difference between a reference signal and an input signal output from the light receiving element. The second amplifier circuit amplifies and outputs the first amplified signal output from the first amplifier circuit. The control circuit controls the active load of the first amplifier circuit or the transconductance of the at least one amplifier transistor of the second amplifier circuit based on a reference signal.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, a comparator, and an electronic device. Background Art

[0002] With the development of semiconductor technology, the miniaturization and high performance of sensors have been advanced, and high resolution and high speed in image sensors have also been developed at a remarkable rate. Even today, such high resolution and high speed are strongly desired improvements. Specifically, image sensors may become a bottleneck for high performance of other functions, and high speed is desired, but there is a problem of increased circuit area or power consumption. In addition, the most important issue is not to reduce image quality and to improve image quality, and the requirement for low noise is very high.

[0003] A technology for achieving low noise by reducing the transconductance of the active load of the comparator without increasing the band limiting capacitance has been studied. In this technology, for example, a current source for bypass is added to reduce the current flowing through the active load, thereby reducing the transconductance. However, there are problems that parasitic capacitance increases due to an increase in area, the area increases due to an increase in the number of current sources and elements connected to the input terminal of the comparator, and the signal is attenuated.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0404208 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] Therefore, the present disclosure provides a low-noise comparator and an image sensor including the comparator.

[0009] Solution to the problem

[0010] According to an embodiment, a solid-state imaging device includes a light receiving element, a first amplifier circuit, a second amplifier circuit, and a control circuit.

[0011] The first amplifier circuit amplifies and outputs a difference between a reference signal and an input signal output from the light receiving element.

[0012] The second amplifier circuit amplifies and outputs the first amplified signal output from the first amplifier circuit.

[0013] The control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifier transistor of the second amplifier circuit based on a reference signal.

[0014] The first amplifier circuit may include:

[0015] a first transistor, wherein a current based on the reference signal flows to a first end and the first end is connected to a control terminal;

[0016] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0017] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0018] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor; and

[0019] a switch connected between a first end or a second end of any one of the first transistor, the second transistor, the third transistor, and the fourth transistor and a power supply voltage, the switch being configured to switch a connection state of the first transistor and the third transistor, and the second transistor and the fourth transistor to a series connection or a parallel connection, and

[0020] A signal obtained by amplifying the input signal may be output from the first terminal of the second transistor.

[0021] The first amplifier circuit may include:

[0022] a first transistor, wherein a current based on the reference signal flows to a first end and the first end is connected to a control terminal;

[0023] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0024] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0025] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0026] A first switch connected between the second end of the first transistor and a power supply voltage;

[0027] a second switch connected between the second end of the second transistor and the power supply voltage;

[0028] a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor;

[0029] a fourth switch connected between the first end of the second transistor and the second end of the fourth transistor;

[0030] a fifth switch connected between the second terminal of the third transistor and a power supply voltage; and

[0031] a sixth switch connected between the second end of the fourth transistor and the power supply voltage, and

[0032] A signal obtained by amplifying the input signal may be output from the first terminal of the second transistor.

[0033] The control circuit may perform control to switch between an on state and an off state of the first switch, the second switch, the third switch, and the fourth switch at the same time, and

[0034] Control may be performed to switch between the on state and the off state of the fifth switch and the sixth switch at the same timing, and not to turn on the fifth switch and the sixth switch at the same timing as the first switch.

[0035] The control circuit may control the switch to be turned on based on an analog gain of the reference signal.

[0036] The control circuit may control the switch to be turned on based on an addition mode of the pixel signal.

[0037] The control circuit may control the switch to be turned on based on the conversion efficiency of the pixel signal.

[0038] The first amplifier circuit may include:

[0039] a first transistor, wherein a current based on the reference signal flows to a first end and the first end is connected to a control terminal;

[0040] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0041] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0042] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0043] a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second terminal of the third transistor, a second terminal of the fifth transistor is connected to a power supply voltage, and a control terminal of the fifth transistor is connected to the control terminal of the first transistor;

[0044] a sixth transistor, a first terminal of the sixth transistor being connected to the second terminal of the fourth transistor, a second terminal of the sixth transistor being connected to the power supply voltage, and a control terminal of the sixth transistor being connected to the control terminal of the first transistor; and

[0045] a switch connected between a first end or a second end of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and a power supply voltage, the switch being configured to switch a connection state of the first transistor, the third transistor, and the fifth transistor with the second transistor, the fourth transistor, and the sixth transistor to a series connection or a parallel connection, and

[0046] A signal obtained by amplifying the input signal may be output from the first terminal of the second transistor.

[0047] The first amplifier circuit may include:

[0048] a first transistor, wherein a current based on the reference signal flows to a first end and the first end is connected to a control terminal;

[0049] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0050] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0051] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0052] a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second terminal of the third transistor, a second terminal of the fifth transistor is connected to a power supply voltage, and a control terminal of the fifth transistor is connected to the control terminal of the first transistor;

[0053] a sixth transistor, a first terminal of the sixth transistor being connected to the second terminal of the fourth transistor, a second terminal of the sixth transistor being connected to the power supply voltage, and a control terminal of the sixth transistor being connected to the control terminal of the first transistor;

[0054] A first switch connected between the second end of the first transistor and a power supply voltage;

[0055] a second switch connected between the second end of the second transistor and the power supply voltage;

[0056] a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor; and

[0057] a fourth switch connected between the first terminal of the second transistor and the second terminal of the fourth transistor, and

[0058] A signal obtained by amplifying the input signal is output from a first terminal of the second transistor.

[0059] The control circuit may perform control to turn on and off the first switch, the second switch, the third switch, and the fourth switch at the same time.

[0060] The second amplifier circuit may include:

[0061] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0062] an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor; and

[0063] a switch connected between the first end or the second end of the seventh transistor or the eighth transistor and a power supply voltage, the switch being configured to switch the seventh transistor and the eighth transistor to be connected in series or in parallel, and

[0064] A signal may be output from the first terminal of the seventh transistor.

[0065] The second amplifier circuit may include:

[0066] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0067] an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0068] a seventh switch connected between the second end of the seventh transistor and a power supply voltage;

[0069] an eighth switch connected between the first terminal of the seventh transistor and the second terminal of the eighth transistor; and

[0070] a ninth switch connected between the second end of the eighth transistor and the power supply voltage, and

[0071] A signal may be output from the first terminal of the seventh transistor.

[0072] The control circuit may perform control of switching between the on state and the off state of the seventh switch and the eighth switch at the same timing, and may perform control of not turning on the eighth switch at the same timing as the seventh switch.

[0073] The control circuit may control the switch to be turned on based on an analog gain of the reference signal.

[0074] The control circuit may control the switch to be turned on based on an addition mode of the pixel signal.

[0075] The control circuit may control the switch to be turned on based on the conversion efficiency of the pixel signal.

[0076] The second amplifier circuit may include:

[0077] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0078] an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0079] a ninth transistor, a first end of which is connected to the second end of the eighth transistor, a second end of which is connected to a power supply voltage, and a control terminal of which is connected to the control terminal of the seventh transistor; and

[0080] a switch connected between the first end or the second end of the seventh transistor, the eighth transistor or the ninth transistor and a power supply voltage, the switch being configured to switch the seventh transistor, the eighth transistor and the ninth transistor to be connected in series or in parallel, and

[0081] A signal may be output from the first terminal of the seventh transistor.

[0082] The second amplifier circuit may include:

[0083] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0084] an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0085] a ninth transistor, a first end of which is connected to the second end of the eighth transistor, a second end of which is connected to a power supply voltage, and a control terminal of which is connected to the control terminal of the seventh transistor;

[0086] a seventh switch connected between the second terminal of the seventh transistor and a power supply voltage; and

[0087] an eighth switch connected between the first end of the seventh transistor and the second end of the eighth transistor, and

[0088] A signal may be output from the first terminal of the seventh transistor.

[0089] The active load in the first amplifier circuit and the amplifier transistor in the second amplifier circuit may be formed by p-type MOSFETs.

[0090] The active load in the first amplifier circuit and the amplifier transistor in the second amplifier circuit may be formed by n-type MOSFETs.

[0091] According to an embodiment, a comparator includes a first amplifier circuit, a second amplifier circuit, and a control circuit.

[0092] The first amplifier circuit amplifies and outputs a difference between a reference signal and an input signal.

[0093] The second amplifier circuit amplifies and outputs the first amplified signal output from the first amplifier circuit.

[0094] The control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifier transistor of the second amplifier circuit based on a reference signal.

[0095] According to an embodiment, an electronic device includes a light receiving element, a first amplifier circuit, a second amplifier circuit, and a control circuit, and

[0096] A digital signal obtained by performing analog-to-digital (AD) conversion on a signal output from the second amplifier circuit on the light receiving element is reconfigured to acquire image data.

[0097] The first amplifier circuit amplifies and outputs a difference between a reference signal and an input signal output from the light receiving element.

[0098] The second amplifier circuit amplifies and outputs the first amplified signal output from the first amplifier circuit.

[0099] The control circuit controls a transconductance of at least one of an active load in the first amplifier circuit or an amplifier transistor in the second amplifier circuit based on a reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] Figure 1 is a block diagram schematically showing a solid-state imaging device according to an embodiment.

[0101] Figure 2 : is a diagram schematically showing a semiconductor substrate on which the solid-state imaging device according to the present embodiment is mounted.

[0102] Figure 3 : is a diagram schematically showing a semiconductor substrate on which the solid-state imaging device according to the present embodiment is mounted.

[0103] Figure 4 is a circuit diagram illustrating an example of a comparator according to an embodiment.

[0104] Figure 5 is a circuit diagram showing an example of connection of a comparator according to an embodiment.

[0105] Figure 6 is a circuit diagram showing an example of connection of a comparator according to an embodiment.

[0106] Figure 7 is a circuit diagram showing an example of a comparator according to an embodiment.

[0107] Figure 8 is a circuit diagram showing an example of a comparator according to an embodiment.

[0108] Fig. 9 is a circuit diagram showing an example of a comparator according to an embodiment.

[0109] Fig.10 is a circuit diagram showing an example of a comparator according to an embodiment.

[0110] Fig.11 is a circuit diagram showing an example of a comparator according to an embodiment.

[0111] Fig.12 is a diagram illustrating an example of a pixel addition mode according to an embodiment.

[0112] Fig.13 It is shown Fig.12 FIG. 1 is a diagram of an embodiment of a pixel circuit in FIG.

[0113] Fig.14 It is shown Fig.12 Schematic diagram of an embodiment of a pixel circuit in.

[0114] Fig.15 is a diagram showing an example of a comparator according to an embodiment.

[0115] Fig.16 is a diagram showing an example of a comparator according to an embodiment.

[0116] Fig.17 is a diagram showing an example of a comparator according to an embodiment.

[0117] Fig.18 It is a block diagram showing an embodiment of a schematic structure of a vehicle control system.

[0118] Fig.19 It is an explanatory diagram showing an embodiment of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0119] Embodiments of the present disclosure are described below with reference to the accompanying drawings. The accompanying drawings are for explanation, and the shape and size of each component in an actual device, the ratio of the size to other components, etc. are not necessarily as shown in the drawings. In addition, because the drawings are shown in a simplified manner, configurations necessary for implementation other than those shown in the drawings are appropriately provided.

[0120] Figure 1 1 is a simplified diagram showing a part of a solid-state imaging device (image sensor) according to an embodiment. The solid-state imaging device 1 includes at least a horizontal drive circuit 10, a vertical drive circuit 12, a pixel array 14, an analog-to-digital conversion circuit (analog-to-digital converter, hereinafter referred to as ADC 16), and a logic circuit 18. The solid-state imaging device 1 may have a configuration in which some of these are omitted, or may selectively include other necessary configurations. For example, the solid-state imaging device 1 may include an input / output interface for inputting and outputting signals and a storage circuit for temporarily or non-temporarily storing data.

[0121] The horizontal driving circuit 10 is a circuit that selects which row of pixels 140 included in the pixel array 14 is to be driven.

[0122] The vertical drive circuit 12 is a circuit that controls which column of pixels 140 among the pixels 140 belonging to the row selected in the horizontal drive circuit 10 provided in the pixel array 14 performs output. The solid-state imaging device 1 outputs from the pixels 140 belonging to the column specified by the vertical drive circuit 12 in the row selected and driven by the horizontal drive circuit 10.

[0123] The pixel array 14 is a region in which pixels 140 are arranged. The pixels 140 are arranged in a two-dimensional array along row and column directions in the pixel array 14. The pixels 140 include light receiving elements, photoelectrically convert light incident on the pixels 140, and output analog signals based on the intensity of the incident light.

[0124] The ADC 16 is a circuit that converts an analog signal output from the pixel 140 into a digital signal and outputs the digital signal. For example, the ADC 16 compares a ramp signal as a reference signal with the analog signal output from the pixel 140, and counts from the time when the ramp signal starts to be output to the time when the comparison result signal is inverted, thereby converting the analog signal into a digital signal.

[0125] The digital signal generated by the ADC 16 is output to the logic circuit 18. The logic circuit 18 performs various processes on the digital signal and then outputs image data. The logic circuit 18 can also generate image data or perform recognition processing, for example, by performing color adjustment, signal processing, image processing, and optionally machine learning processing.

[0126] Figure 21 is a diagram showing an example of the arrangement of the pixel array 14 and the ADC 16 according to the embodiment. The solid-state imaging device 1 can be formed as a laminated semiconductor substrate 2. As an embodiment, the solid-state imaging device 1 is mounted on the semiconductor substrate 2, in which the first substrate 20 and the second substrate 22 are laminated. Note that a stacked structure of three or more layers is not excluded. For example, another layer may be laminated alone for a storage circuit.

[0127] These substrates can be laminated by any method, such as chip on chip (CoC), chip on wafer (CoW), or wafer on wafer (WoW). In addition, the related connections can be any method such as through-hole or micro-tip.

[0128] The first substrate 20 includes at least the pixel array 14. The pixel array 14 outputs a signal based on the intensity of the signal photoelectrically converted by the light receiving element to a signal line provided for each column, and the analog signal propagates to the second substrate 22 via the signal line provided for each column.

[0129] The second substrate 22 includes at least the ADC 16. The ADC 16 includes a column ADC 160 for each of the signal lines for each column in the pixel array 14. Note that one column ADC 160 may be provided for a plurality of columns, or a plurality of column ADCs 160 may be provided for one column.

[0130] The column ADC 160 converts analog signals output from the pixels 140 belonging to the column into digital signals and outputs the digital signals, and forms image data in a subsequent logic circuit.

[0131] Figure 3 1 is a diagram showing another example of the arrangement of the pixel array 14 and the ADC 16 according to the embodiment. The solid-state imaging device 1 is formed as a semiconductor substrate 2 in which a first substrate 20 and a second substrate 22 are connected to each other. Figure 2 are laminated similarly.

[0132] exist Figure 3 , the ADC 16 includes a pixel ADC 162 provided for each pixel 140. The pixel ADC 162 converts an analog signal output from the corresponding pixel 140 into a digital signal and outputs the digital signal.

[0133] Note that, in the above description, the case including the column ADC and the pixel ADC has been described as an example, but the mode of the solid-state imaging device 1 in the present disclosure is not limited thereto. For example, the solid-state imaging device 1 may have a mode in which the pixel array 14 is divided into a plurality of regions and each region includes a regional ADC, or may have a mode in which an ADC that processes outputs from an arbitrary number of pixels 140 is processed.

[0134] Next, a comparator implementing low noise in the present disclosure will be described through some non-limiting examples.

[0135] (First Embodiment)

[0136] Figure 4 is a circuit diagram showing an embodiment of a comparator provided inside the ADC 16 of the solid-state imaging device 1. The comparator 3 includes transistors Md1, Md2, Mb1, and Mb2, a first amplifier circuit 30, and a second amplifier circuit 32. In addition, capacitors C1, C2, and C3 that appropriately propagate a reference signal, an input signal, and an amplified signal may be provided.

[0137] It should be noted that in the following description, in a p-type MOSFET, the terminal (first end) on the lower side in the figure is described as a drain, and the terminal (second end) on the upper side in the figure is described as a source. However, this description is temporary, and the source and drain can be switched according to the connection state. Similarity applies to n-type MOSFET. Therefore, it is desirable to provide a transistor as an active load, specifically, a transistor in which the source and drain can be switched is a transistor in which the source and drain do not have corresponding characteristics, that is, a transistor in which the performance does not change even when the source and drain are switched to each other.

[0138] The transistor Md1 is, for example, an n-type MOSFET, and a ramp signal Vramp as a reference signal is applied to the gate of the transistor Md1 .

[0139] The transistor Md2 is, for example, an n-type MOSFET, and an input signal Vs1 which is an analog signal output from the pixel 140 is applied to a gate of the transistor Md2.

[0140] The transistor Md1 and the transistor Md2 are connected to the negative power supply voltage Vss via the transistor Mb1 that performs output control (bias current control). The transistor Md1 and the transistor Md2 form a differential input circuit that inputs an input signal and a ramp signal.

[0141] The first amplifier circuit 30 operates as a first-stage amplifier circuit that amplifies and outputs a differential voltage between an input signal input from a differential input circuit and a ramp signal.

[0142] The second amplifier circuit 32 operates as a second-stage amplifier circuit that amplifies and outputs a signal output from the first amplifier circuit 30. The second amplifier circuit 32 is connected to the negative power supply voltage Vss via the transistor Mb2. The second amplifier circuit 32 includes, for example, a transistor Ma7.

[0143] As a non-limiting example, the active load of the first amplifier circuit 30 and / or the second amplifier circuit 32 may be a p-type MOSFET. In this case, the transistor receiving the differential input may be an n-type MOSFET.

[0144] The transistor Ma7 is, for example, a p-type MOSFET, the output signal of the first amplifier circuit 30 is applied to its gate, its source is connected to the positive side power supply voltage Vdd, and its drain is connected to the drain of the transistor Mb2 which is an n-type MOSFET.

[0145] The solid-state imaging device 1 further includes a control circuit (not shown) that turns on and off a switch of the first amplifier circuit 30. The control circuit switches the switch and controls the active load of the first amplifier circuit 30.

[0146] The first amplifier circuit 30 includes a transistor and a switch, and controls an active load of the transistor by controlling the switch.

[0147] The first amplifier circuit 30 includes transistors Ma1, Ma2, Ma3, and Ma4 and switches Sw1, Sw2, Sw3, Sw4, Sw5, and Sw6.

[0148] The transistor Ma1 is, for example, a p-type MOSFET, and has a drain connected to the transistor Md1, and its gate and drain are connected. When the drain is connected to the transistor Md1, a current based on the ramp signal flows through the drain of the transistor Ma1.

[0149] The transistor Ma2 is, for example, a p-type MOSFET, and has a drain connected to the transistor Md2 and a gate connected to the gate of the transistor Ma1. When the drain is connected to the transistor Md2, a signal based on the input signal flows through the drain of the transistor Ma2. In addition, since a current mirror is formed by the transistor Ma1 and the transistor Ma2, a current obtained by subtracting a current based on the input voltage from a drain current of the transistor Ma1 (i.e., a current based on a difference between the ramp signal and the input signal) flows through the transistor Ma2.

[0150] That is, the first amplifier circuit 30 outputs a signal obtained by amplifying the difference between the ramp signal and the input signal from the drain of the transistor Ma2 .

[0151] The transistor Ma3 has a drain connected to the source of the transistor Ma1 and a gate connected to the gate of the transistor Ma1.

[0152] The transistor Ma4 has a drain connected to the source of the transistor Ma2 and a gate connected to the gate of the transistor Ma1.

[0153] The sources and drains of these transistors are connected via switches.

[0154] The switch Sw1 is connected between the source of the transistor Ma1 and the positive side power supply voltage Vdd.

[0155] The switch Sw2 is connected between the source of the transistor Ma2 and the positive-side power supply voltage Vdd.

[0156] The switch Sw3 is connected between the source of the transistor Ma3 and the drain of the transistor Ma1.

[0157] The switch Sw4 is connected between the source of the transistor Ma4 and the drain of the transistor Ma2.

[0158] The switch Sw5 is connected between the source of the transistor Ma3 and the positive-side power supply voltage Vdd.

[0159] The switch Sw6 is connected between the source of the transistor Ma4 and the positive-side power supply voltage Vdd.

[0160] As described above, the first amplifier circuit 30 includes a switch capable of switching the connection state of the transistors Ma1 and Ma3 to series or parallel and capable of switching the connection state of the transistors Ma2 and Ma4 to the same series or parallel state as the connection state of the transistors Ma1 and Ma3. That is, by providing a switch for switching the connection state between the appropriate drain or source of the drain or source of each transistor and the positive side power supply voltage Vdd, the series and parallel states of the transistors can be appropriately switched.

[0161] The control circuit controls the active load of the first amplifier circuit 30 by switching these switches. CM noise (common mode noise) in the circuit using the transistors in the above diagram is generally expressed by the following equation.

[0162] [Mathematical formula 1]

[0163]

[0164] Where NBW indicates the bandwidth of the noise.

[0165] exist Figure 4 In the first amplifier circuit 30, g in equation (1) mp_cm Controlled by the control circuit. In the case where two identical p-type MOSFETs are connected in parallel, the active load is the same as that in the case where one identical transistor is used, and the channel width is doubled, so that the overdrive voltage is reduced. On the other hand, in the case where two identical p-type MOSFETs are connected in series, the active load is halved and the channel length is doubled compared to the case where one identical transistor is used, so that the overdrive voltage is increased.

[0166] The transconductance g of the active load transistor in the amplifier circuit mp_cmMainly caused by the noise of the comparator. mp_cm When it is lower, the thermal noise can be made lower, but the overdrive voltage of the transistor becomes higher and the dynamic range of the comparator becomes smaller. As a result, the signal value is saturated in signals with large amplitude.

[0167] Therefore, in a state where a large amplitude signal is input and low noise is not required (for example, the analog gain of the ramp signal is low), transistors are connected in parallel to ensure the dynamic range, and in a state where a small amplitude signal is input and low noise is required (for example, the analog gain of the ramp signal is high), transistors are connected in series to achieve low noise.

[0168] When using Figure 4 When the connection in is performed, switches Sw1 and Sw3 are turned on and switch Sw5 is turned off, so that transistors Ma1 and Ma3 can be connected in parallel between the power supply voltage Vdd and the drain of transistor Ma1. In this case, the source and drain of transistor Ma3 are in a state opposite to the above state. Similarly, by turning on switches Sw2 and Sw4 and turning off switch Sw6, transistors Ma2 and Ma4 can be connected in parallel between the power supply voltage Vdd and the drain of transistor Ma2.

[0169] On the contrary, by turning off switches Sw1 and Sw3 and turning on switch Sw5, transistors Ma3 and Ma1 can be connected in series between the power supply voltage Vdd and the drain of transistor Ma1. Similarly, by turning off switches Sw2 and Sw4 and turning on switch Sw6, transistors Ma4 and Ma2 can be connected in series between the power supply voltage Vdd and the drain of transistor Ma2.

[0170] That is, the control circuit performs control so that switches Sw1, Sw2, Sw3 and Sw4 are turned on and off at the same time, switches Sw5 and Sw6 are turned on and off at the same time, and switches Sw5 and Sw6 are not turned on at the same time as switches Sw1, Sw2, Sw3 and Sw4.

[0171] Figure 5 is a diagram showing an embodiment of the state of the switches of the comparator 3. For example, when the analog gain of the ramp signal is low, the control circuit turns on the switches Sw1, Sw2, Sw3 and Sw4 and turns off the switches Sw5 and Sw6. Through this control, the comparator 3 can appropriately output a signal with a high dynamic range.

[0172] Figure 6 3 is a diagram showing an embodiment of the state of the switches of the comparator 3. For example, when the analog gain of the ramp signal is high, the control circuit turns off the switches Sw1, Sw2, Sw3 and Sw4 and turns on the switches Sw5 and Sw6. Through this control, the comparator 3 can appropriately output a low noise signal.

[0173] As described above, according to this embodiment, while realizing low noise of the signal when the analog gain is high, the output of the comparator, that is, the output of the image sensor, which ensures the dynamic range when the analog gain is low can be realized. In addition, since only a switch element as a switch for switching and requiring a small circuit area needs to be added, it can be realized without increasing the circuit area.

[0174] That is, according to the solid-state imaging device 1 of the present embodiment, in a case where a wide dynamic range is required due to a large amplitude but low noise is not required (for example, when the analog gain is low), an active load connected in parallel is used, and in a case where a wide dynamic range is not required but low noise is required due to a small amplitude (for example, when the analog gain is high), an active load connected in series can be used.

[0175] (Second Embodiment)

[0176] In the above-described first embodiment, a mode has been described in which two stages of transistors serving as active loads are stacked to switch between series connection and parallel connection, but three or more stages of transistors serving as active loads may be stacked.

[0177] Figure 7 : is a diagram showing a comparator 3 as an example of an embodiment. The first amplifier circuit 30 includes transistors Ma1, Ma2, Ma3, Ma4, Ma5, and Ma6, and switches Sw1, Sw2, Sw3, and Sw4.

[0178] The transistor Ma1 is, for example, a p-type MOSFET, and has a drain connected to the drain of the transistor Md1 and a gate connected to the drain.

[0179] The transistor Ma2 is, for example, a p-type MOSFET, and has a drain connected to the drain of the transistor Ma2 and a gate connected to the gate of the transistor Ma1. The first amplifier circuit 30 outputs an amplified signal from the drain of the transistor Ma2.

[0180] The transistor Ma3 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma1 and a gate connected to the gate of the transistor Ma1.

[0181] The transistor Ma4 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma2 and a gate connected to the gate of the transistor Ma1.

[0182] The transistor Ma5 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma3 , a source connected to the positive-side power supply voltage Vdd, and a gate connected to the gate of the transistor Ma1 .

[0183] The transistor Ma6 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma4 , a source connected to the positive-side power supply voltage Vdd, and a gate connected to the gate of the transistor Ma1 .

[0184] The switch Sw1 is connected between the source of the transistor Ma1 and the positive side power supply voltage Vdd.

[0185] The switch Sw2 is connected between the source of the transistor Ma1 and the positive-side power supply voltage Vdd.

[0186] The switch Sw3 is connected between the drain of the transistor Ma1 and the source of the transistor Ma3 .

[0187] The switch Sw4 is connected between the drain of the transistor Ma2 and the source of the transistor Ma4.

[0188] As described above, the first amplifier circuit 30 includes a switch capable of switching the connection state of the transistors Ma1, Ma3, and Ma5 in series or in parallel and capable of switching the connection state of the transistors Ma2, Ma4, and Ma6 to the same series or parallel state as the connection state of the transistors Ma1, Ma3, and Ma5. That is, by providing a switch for switching the connection state between the appropriate drain or source of the drain or source of each transistor and the positive side power supply voltage Vdd, the series and parallel states of the transistors can be appropriately switched.

[0189] For example, switches Sw1, Sw2, Sw3, and Sw4 are turned on when the analog gain is high, and turned off in other cases. When these switches are turned on, transistors Ma1, Ma3, and Ma5 are connected in parallel, and transistors Ma2, Ma4, and Ma6 are connected in parallel. In the off state of the switches, transistors Ma1, Ma3, and Ma5 are connected in series, and transistors Ma2, Ma4, and Ma6 are connected in series.

[0190] By means of such connection, the channel width of the transistor can be further increased when the analog gain is high, and the transconductance of the active load can be further reduced compared to the first embodiment, thereby further improving the effect of reducing thermal noise.

[0191] Note that four or more transistors can be stacked vertically by connecting similar transistors and switches. For example, in the case of vertically stacking an even number of transistors, the switches are connected similarly to the first embodiment, and in the case of vertically stacking an odd number of transistors, the switches are connected similarly to the second embodiment, so that the parallel state and the series state of the transistors can be appropriately switched.

[0192] (Third Embodiment)

[0193] In each of the above-described embodiments, the aspect in which the active load of the first amplifier circuit 30 is controlled has been described, but the aspect in which the amplification transistor of the second amplifier circuit 32 is controlled may be used.

[0194] Figure 8 is a circuit diagram showing an example of a comparator according to an embodiment. The first amplifier circuit 30 includes a current mirror formed by transistors Ma1 and Ma2. The second amplifier circuit 32 includes transistors Ma7 and Ma8 and switches Sw7, Sw8, and Sw9.

[0195] The transistor Ma7 is, for example, a p-type MOSFET, has the output of the first amplifier circuit 30 connected to a gate, and outputs an amplified signal from a drain.

[0196] The transistor Ma8 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma7 and a gate connected to the gate of the transistor Ma7.

[0197] The switch Sw7 is connected between the source of the transistor Ma7 and the positive-side power supply voltage Vdd.

[0198] The switch Sw8 is connected between the drain of the transistor Ma7 and the source of the transistor Ma8.

[0199] The switch Sw9 is connected between the source of the transistor Ma8 and the positive-side power supply voltage Vdd.

[0200] As described above, the second amplifier circuit 32 includes a switch capable of switching the connection state of the transistors Ma7 and Ma8 in series or in parallel. That is, by setting a switch for switching the connection state between the appropriate drain or source of the drain or source of each transistor and the positive side power supply voltage Vdd, the series and parallel states of the transistors can be appropriately switched.

[0201] By turning on the switches Sw7 and Sw8 and turning off the switch Sw9, the transistors Ma7 and Ma8 form a transistor that is arranged in parallel between the power supply voltage Vdd and the drain of the transistor Ma7. That is, it can be considered as a transistor with a long channel width. As a result, similar to the above-mentioned embodiment, the overdrive voltage can be reduced while keeping the amplification transistor of the second amplifier circuit 32 in the same state as one transistor.

[0202] On the other hand, by turning off switches Sw7 and Sw8 and turning on switch Sw9, transistors Ma7 and Ma8 form a transistor that is arranged in series between the power supply voltage Vdd and the drain of transistor Ma7. Since the gate is shared, it can be regarded as a transistor with a long channel length. Therefore, by increasing the threshold voltage Vth, the time until the comparator is reversed is extended, and by narrowing the NBW (i.e., noise bandwidth) in equation (1), as a result, thermal noise can be reduced.

[0203] By increasing the threshold voltage Vth, thermal noise can be reduced while reducing the dynamic range of the comparator. Therefore, for example, when the analog gain is low, the control circuit turns on switches Sw7 and Sw8 and turns off switch Sw9 to put transistors Ma7 and Ma8 into a parallel state and increase the dynamic range.

[0204] For example, in the case where the analog gain is high, the control circuit turns off the switches Sw7 and Sw8 and turns on the switch Sw9 to bring the transistors Ma7 and Ma8 into a series state and performs control to achieve low noise.

[0205] As described above, in the case where a wide dynamic range is required, the control circuit can ensure the wide dynamic range, and in the case where the amplitude of the signal is small and the dynamic range is narrow but low noise is desired, the control circuit can perform control to achieve low noise.

[0206] As described above, according to this embodiment, while realizing low noise of the signal when the analog gain is high, the output of the comparator, that is, the output of the image sensor, which ensures the dynamic range when the analog gain is low can be realized. In addition, since only a switch element as a switch for switching and requiring a small circuit area needs to be added, it can be realized without increasing the circuit area.

[0207] (Fourth Embodiment)

[0208] Furthermore, in the second amplifier circuit 32 , the number of stacked transistors is not limited to two, and may be three or more.

[0209] Fig. 9 is a circuit diagram showing an example of a comparator according to an embodiment. The first amplifier circuit 30 includes a current mirror formed by transistors Ma1 and Ma2. The second amplifier circuit 32 includes transistors Ma7, Ma8, and Ma9, and switches Sw7 and Sw8.

[0210] The transistor Ma7 is, for example, a p-type MOSFET, has the output of the first amplifier circuit 30 connected to a gate, and outputs an amplified signal from a drain.

[0211] The transistor Ma8 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma7 and a gate connected to the gate of the transistor Ma7.

[0212] The transistor Ma9 is, for example, a p-type MOSFET, and has a drain connected to the source of the transistor Ma8 and a source connected to the positive-side power supply voltage Vdd.

[0213] The switch Sw7 is connected between the source of the transistor Ma7 and the positive-side power supply voltage Vdd.

[0214] The switch Sw8 is connected between the drain of the transistor Ma7 and the source of the transistor Ma8.

[0215] As described above, the second amplifier circuit 32 includes a switch capable of switching the connection state of the transistors Ma7, Ma8, and Ma9 in series or in parallel. That is, by setting a switch for switching the connection state between the appropriate drain or source of the drain or source of each transistor and the positive side power supply voltage Vdd, the series and parallel states of the transistors can be appropriately switched.

[0216] By turning on the switches Sw7 and Sw8, the transistors Ma7, Ma8, and Ma9 are connected in parallel. On the other hand, when the switches Sw7 and Sw8 are turned off, the transistors Ma7, Ma8, and Ma9 are connected in series.

[0217] Therefore, similar to the above-described embodiment, the control circuit can switch between appropriately expanding the dynamic range and reducing noise through analog gain, rather than reducing the dynamic range.

[0218] (Fifth Embodiment)

[0219] In the third and fourth embodiments, the amplification transistor of the second amplifier circuit 32 is controlled, but this may be combined with the first and second embodiments.

[0220] Fig.10 : is a circuit diagram showing an example of the comparator 3 according to the embodiment. The comparator 3 has the configuration of the first amplifier circuit 30 in the first embodiment and the second amplifier circuit 32 in the third embodiment.

[0221] Fig.11 : is a circuit diagram showing an example of the comparator 3 according to the embodiment. The comparator 3 has the configuration of the first amplifier circuit 30 in the second embodiment and the second amplifier circuit 32 in the fourth embodiment.

[0222] With this configuration, the control circuit can control the mutual inductance g of the first amplifier circuit 30. mp And the threshold voltage Vth of the second amplifier circuit 32 can be controlled.

[0223] As a non-limiting example, the control circuit can control the mutual inductance of the first amplifier circuit and the threshold voltage of the second amplifier circuit through analog gain. Such control makes it possible to more effectively demonstrate the effect of reducing thermal noise under the condition of reduced noise. For example, according to Fig.11 For the comparator 3 in FIG. 3 , in experimental values, the noise bandwidth can be reduced to about 0.63 times, and the comparator noise can be reduced to about 0.72 times, compared with the case of not vertically stacking.

[0224] Note that although the number of parallel / serial transistors in the first amplifier circuit 30 and the number of parallel / serial transistors in the second amplifier circuit 32 are the same, the present invention is not limited thereto. For example, the first amplifier circuit 30 may include transistors stacked in three stages, and the second amplifier circuit 32 may include transistors stacked in two stages. As described above, the number of transistors to be vertically stacked does not need to match between the first amplifier circuit 30 and the second amplifier circuit 32.

[0225] (Sixth Embodiment)

[0226] In each of the above-described embodiments, the control circuit switches the switches of the first amplifier circuit 30 and / or the second amplifier circuit 32 based on the analog gain. The switching of the switches in the present disclosure is not limited thereto. In the present embodiment, as another non-limiting example, a configuration for switching the switches according to the pixel addition mode (merging mode) will be described.

[0227] Fig.12 is a diagram showing an example of an arrangement of the pixel 140 according to an embodiment. In the pixel 140, in the pixel array 14, a plurality of pixels may share the same floating diffusion area FD, or one pixel may include a plurality of light receiving elements and share the floating diffusion area FD.

[0228] The R, G, and B described in the pixel 140 means that a light receiving element receiving light in the red, green, and blue wavelength bands is provided. The color arrangement is exemplified by a quad-Bayer array, but is not limited thereto, and may be another array. For example, the pixel array 14 may include pixels 140 that receive a white (W) wavelength band, may include pixels 140 that receive a wavelength band of a complementary color system, or may have another arrangement even in the case of three colors of RGB.

[0229] The floating diffusion region FD is a region provided on the pixel circuit side of the pixel 140 and is provided for every four pixels or every four divided pixels, for example. However, the floating diffusion region FD is not limited to being shared by four regions and may be shared by more regions.

[0230] Fig.13 It is schematically shown Fig.12 1 is a circuit diagram of a pixel circuit of a pixel 140 in FIG. In the pixel 140, when a voltage Vtrg as an output trigger is applied to the transfer transistor, a signal obtained by photoelectric conversion of the light receiving element is transferred to the floating diffusion region FD.

[0231] For example, the solid-state imaging device 1 applies a voltage Vrst for turning on a reset transistor to reset the floating diffusion region FD, and then transfers a signal from the light receiving element to the floating diffusion region FD via a transfer transistor.

[0232] When the transistor is turned on by the voltage Vsel applied to each line selected by the horizontal driving circuit 10, a voltage corresponding to the voltage of the floating diffusion area FD is output via the signal line VSL. The signal Vsl output to the signal line VSL is an input signal Vsl of the comparator 3.

[0233] Here, the Pixel 140 shares Fig.12 In the case of the floating diffusion region FD shown, the output of the pixel 140 can be in a mode that selects a non-additive mode for performing output from a single pixel 140 (or a divided pixel, the same applies below) or an additive mode for obtaining the sum of outputs from multiple pixels 140.

[0234] For example, in the non-addition mode, any one of the voltages Vtrg0 , Vtrg1 , Vtrg2 , and Vtrg3 becomes an on voltage, and the output of any one of the pixels 140 is transferred to the floating diffusion region FD.

[0235] In the addition mode, a plurality of voltages (eg, all voltages) among the voltages Vtrg0 , Vtrg1 , Vtrg2 , and Vtrg3 become on voltages, and the sum of outputs from all pixels 140 is transferred to the floating diffusion region FD.

[0236] In the addition mode, for example, the saturation charge amount is four times the saturation charge amount Qs in the non-addition mode. For this reason, the ratio of the signal increases without reducing the noise, that is, the S / N ratio increases, but a wide dynamic range is required. Compared with the addition mode, in the non-addition mode, because the saturation charge amount Qs is small, even the same amount of noise as in the addition mode has a large influence on the signal, but because the saturation charge amount itself is small, the dynamic range can be reduced.

[0237] As a result, in the non-addition mode, a signal with a small amplitude as an output from one pixel 140 is input to the comparator 3, and the dynamic range may be narrow, but a low-noise output is desired. In the addition mode, a signal with a large amplitude as an output from the sum of a plurality of pixels 140 is input to the comparator 3, and there is no need to consider many small noises, but an output with a wide dynamic range is desired.

[0238] In view of the above situation, when the addition mode of the pixel is the non-addition mode, the control circuit performs control so that the transistors used as active loads are connected in series, and when the addition mode of the pixel is the addition mode, the control circuit performs control so that the transistors used as active loads are connected in parallel.

[0239] As described above, the solid-state imaging device 1 can ensure a suitable dynamic range and achieve low noise by the pixel addition mode instead of the active load of the analog gain switching comparator 3 .

[0240] (Seventh Embodiment)

[0241] The control circuit can also control the active load by setting the pixel conversion efficiency instead of the pixel addition mode. In this case as well, the arrangement of the floating diffusion region FD in the pixel 140 is similar to Fig.12 The arrangement of the case is similar.

[0242] Fig.14 1 is a diagram showing an example of a pixel circuit in the case of setting the pixel conversion efficiency. Compared with the case of the sixth embodiment described above, a transistor and a capacitor Cext for setting the pixel conversion efficiency are further provided.

[0243] When the pixel conversion efficiency is in the high efficiency conversion mode, the voltage Vcg applied to the gate of the conversion efficiency setting transistor becomes the cut-off voltage. In this mode, the capacity of the floating diffusion region FD is minimized to improve the conversion efficiency. By turning off the conversion efficiency setting transistor, the capacitor Cext is turned off, and the state of high conversion efficiency from charge to voltage is maintained.

[0244] In general, the high conversion efficiency mode is used when the saturation charge amount Qs is small. Therefore, in the high efficiency conversion mode, the dynamic range may be narrow, but low noise is desirable.

[0245] When the pixel conversion efficiency is in the low efficiency conversion mode, the voltage Vcg applied to the gate of the conversion efficiency setting transistor becomes the on voltage. In this mode, the capacitance of the floating diffusion region FD is connected to the capacitor Cext that charges the reset voltage. Therefore, the conversion efficiency from charging to voltage is reduced by the connection of the capacitor Cext.

[0246] In general, the low conversion efficiency mode is used when the saturation charge amount Qs is large. Therefore, in the low efficiency conversion mode, low noise is not necessary, but a wide dynamic range is desired.

[0247] In view of the above, the control circuit performs control so that the transistors as active loads are connected in series in the high conversion efficiency mode. In addition, in the low conversion efficiency mode, the control circuit performs control so that the transistors as active loads are connected in parallel.

[0248] As described above, by switching the active load of the comparator 3 in the pixel conversion efficiency mode, the solid-state imaging device 1 can ensure a suitable dynamic range and achieve low noise.

[0249] (Eighth Embodiment)

[0250] In each of the above-described embodiments, the aspect in which the differential input is an n-type MOSFET and the active load of the amplifier circuit is a p-type MOSFET has been described, but the mode of the comparator 3 in the present disclosure is not limited thereto.

[0251] Figures 15 to 17 are diagrams illustrating some non-limiting examples of comparators 3 according to embodiments. As shown by way of example in these figures, the differential input pair may comprise p-type MOSFETs and the active load transistors may comprise n-type MOSFETs.

[0252] [Mathematical formula 2]

[0253]

[0254] The thermal noise in this circuit is summarized in equation (2). In this case, the thermal noise can be reduced by controlling the transconductance g mn Therefore, similar to each of the above-described embodiments, by switching the series / parallel state of the n-type MOSFET used as an active load and the amplifier transistor, low noise can be achieved while ensuring a dynamic range.

[0255] Note that similar to the above embodiment, the number of vertically stacked n-type MOSFETs may be three or more. In addition, the control circuit may perform control to switch between series and parallel connection of active loads based on at least one of analog gain, pixel addition mode, or pixel conversion efficiency mode.

[0256] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can also be implemented as a device installed on any kind of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), etc.).

[0257] Fig.187000 is a block diagram showing an embodiment of a schematic configuration of a vehicle control system 7000, which is an embodiment of a mobile control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. Fig.18 In the illustrated embodiment, the vehicle control system 7000 includes a driving system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. For example, the communication network 7010 connecting the plurality of control units to each other may be an in-vehicle communication network conforming to any standard, such as a controller area network (CAN), a local interconnect network (LIN), a local area network (LAN), FlexRay (registered trademark), and the like.

[0258] Each control unit includes: a microcomputer that performs calculations according to various programs; a storage unit that stores programs executed by the microcomputer, parameters for various operations, etc.; and a drive circuit that drives various control object devices. Each control unit also includes: a network interface (I / F) for communicating with other control units via the communication network 7010; and a communication I / F for communicating with devices, sensors, etc. inside and outside the vehicle through wired communication or radio communication. Fig.18 , a microcomputer 7610, a general communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, a sound / image output unit 7670, an in-vehicle network I / F 7680, and a storage unit 7690 are shown as functional components of the integrated control unit 7600. Other control units similarly include a microcomputer, a communication I / F, a storage unit, and the like.

[0259] The driving system control unit 7100 controls the operation of devices related to the driving system of the vehicle according to various programs. For example, the driving system control unit 7100 is used as a control device for a driving force generating device (such as an internal combustion engine, a driving motor, etc.) for generating a driving force of the vehicle, a driving force transmitting mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc. The driving system control unit 7100 may have a function as a control device for an anti-lock braking system (ABS), an electronic stability control (ESC), etc.

[0260] The driving system control unit 7100 is connected to the vehicle state detection unit 7110. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor for detecting the acceleration of the vehicle, and at least one of a sensor for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the speed of the wheels. The driving system control unit 7100 performs calculation processing using the signal input from the vehicle state detection unit 7110 to control the internal combustion engine, the drive motor, the electric power steering device, the brake device, and the like.

[0261] The body system control unit 7200 controls the operation of various devices provided in the body according to various programs. For example, the body system control unit 7200 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave emitted from a mobile device may be input to the body system control unit 7200 as a substitute for a signal of a key or various switches. The body system control unit 7200 receives these input radio waves or signals, and controls a door lock device, a power window device, lights, etc. of the vehicle.

[0262] The battery control unit 7300 controls the secondary battery 7310 as a power source for driving the motor according to various programs. For example, information about the battery temperature, the battery output voltage, the amount of charge remaining in the battery, etc. is supplied to the battery control unit 7300 from the battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic operation processing using these signals, and performs control for adjusting the temperature of the secondary battery 7310 or controls a cooling device provided to the battery device, etc.

[0263] The vehicle exterior information detection unit 7400 detects information outside the vehicle including the vehicle control system 7000. For example, the vehicle exterior information detection unit 7400 is connected to at least one of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging unit 7410 includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. For example, the vehicle exterior information detection unit 7420 includes at least one of an environmental sensor for detecting current atmospheric conditions or weather conditions and a peripheral information detection sensor for detecting other vehicles, obstacles, pedestrians, etc., outside the vehicle including the vehicle control system 7000.

[0264] For example, the environmental sensor may be at least one of a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunlight sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The peripheral information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR device (a light detection and ranging device, or a laser imaging detection and ranging device). Each of the imaging portion 7410 and the vehicle exterior information detection unit 7420 may be provided as an independent sensor or device, or may be provided as a device in which a plurality of sensors or devices are integrated.

[0265] Here, Fig.19 An example of the installation position of the imaging unit 7410 and the vehicle exterior information detection unit 7420 is shown. The imaging units 7910, 7912, 7914, 7916 and 7918 are, for example, installed at least one of the positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 7900 and the position on the upper part of the windshield in the vehicle interior. The imaging unit 7910 installed at the front nose of the vehicle interior and the imaging unit 7918 installed at the upper part of the windshield mainly obtain images in front of the vehicle 7900. The imaging units 7912 and 7914 installed at the side mirrors mainly obtain images of the sides of the vehicle 7900. The imaging unit 7916 installed at the rear bumper or rear door mainly obtains images of the rear of the vehicle 7900. The imaging unit 7918 installed at the upper part of the windshield in the vehicle interior is mainly used to detect the front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0266] Notice, Fig.19 An example of the imaging range of each of the imaging units 7910, 7912, 7914, and 7916 is shown. Imaging range a represents the imaging range of the imaging unit 7910 set to the front nose. Imaging ranges b and c respectively represent the imaging ranges of the imaging units 7912 and 7914 provided to the side mirrors. Imaging range d represents the imaging range of the imaging unit 7916 set to the rear bumper or rear door. For example, by superimposing image data imaged by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0267] The vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, 7930 provided at the front, rear, side, corners, and upper portion of the windshield inside the vehicle 7900 may also be, for example, ultrasonic sensors or radar devices. The vehicle exterior information detection units 7920, 7926, 7930 provided at the front nose, rear bumper, rear door of the vehicle 7900, and upper portion of the windshield inside the vehicle may also be, for example, LIDAR devices. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, and the like.

[0268] Return to see Fig.18 , continue the description. The vehicle exterior information detection unit 7400 enables the imaging unit 7410 to capture an image outside the vehicle and receive the captured image data. In addition, the vehicle exterior information detection unit 7400 receives detection information from the vehicle exterior information detection unit 7420 connected to the vehicle exterior information detection unit 7400. In the case where the vehicle exterior information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the vehicle exterior information detection unit 7400 sends ultrasonic waves, electromagnetic waves, etc., and receives information of received reflected waves. Based on the received information, the vehicle exterior information detection unit 7400 can perform processing for detecting objects such as humans, vehicles, obstacles, signs, and text on the road surface, or processing for detecting the distance between objects. In addition, the vehicle exterior information detection unit 7400 can also perform environmental recognition processing for identifying rainfall, fog, road conditions, etc. based on the received information. The vehicle exterior information detection unit 7400 can calculate the distance to objects outside the vehicle based on the received information.

[0269] In addition, the vehicle exterior information detection unit 7400 can perform image recognition processing to identify humans, vehicles, obstacles, signs, text on the road surface, etc., or detect the distance thereto based on the received image data. The vehicle exterior information detection unit 7400 can perform processing such as distortion correction, alignment, etc. on the received image data, and combine the image data imaged by multiple different imaging units 7410 to generate a bird's-eye view image or a panoramic image. The vehicle exterior information detection unit 7400 can perform viewpoint transformation processing using the image data captured by the imaging unit 7410, which includes different imaging units.

[0270] The in-vehicle information detection unit 7500 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 7500 is connected to a driver state detection unit 7510 that detects the state of the driver. The driver state detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, a microphone that collects sounds inside the vehicle, and the like. The biosensor is, for example, arranged in a seat surface, a steering wheel, and the like, and detects biometric information of a passenger sitting on the seat or a driver holding the steering wheel. Based on the detection information input from the driver state detection unit 7510, the in-vehicle information detection unit 7500 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may subject the audio signal obtained by collecting the sound to processing such as noise elimination processing.

[0271] The integrated control unit 7600 controls the general operation within the vehicle control system 7000 according to various programs. The integrated control unit 7600 is connected to the input unit 7800. The input unit 7800 is implemented by a device such as a touch panel, a button, a microphone, a switch, a lever, etc. that can be input by the occupant. The integrated control unit 7600 can be supplied with data obtained by voice recognition of the voice input through the microphone. The input unit 7800 can be, for example, a remote control device using infrared or other radio waves, or an external connection device that supports the operation of the vehicle control system 7000, such as a mobile phone, a personal digital assistant (PDA), etc. The input unit 7800 can be, for example, a camera. In this case, the occupant can input information through gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant can be input. In addition, the input unit 7800 can include, for example, an input control circuit, etc., which generates an input signal based on the information input by the occupant using the above-mentioned input unit 7800, and outputs the generated input signal to the integrated control unit 7600. The occupants and the like input various data or instruct processing operations to the vehicle control system 7000 by operating the input unit 7800 .

[0272] The storage unit 7690 may include a read-only memory (ROM) storing various programs executed by the microcomputer and a random access memory (RAM) storing various parameters, operation results, sensor values, etc. In addition, the storage unit 7690 may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, etc.

[0273] The general communication I / F 7620 is a widely used communication I / F that mediates communication with various devices existing in the external environment 7750. The general communication I / F 7620 can implement a cellular communication protocol such as Global System for Mobile Communications (GSM (registered trademark)), Worldwide Interoperability for Microwave Access (WiMAX (registered trademark)), Long Term Evolution (LTE (registered trademark)), LTE-Advanced (LTE-A), etc., or another wireless communication protocol such as a wireless LAN (also known as Wireless Fidelity (Wi-Fi (registered trademark)), Bluetooth (registered trademark), etc. For example, the general communication I / F 7620 can be connected to a device (e.g., an application server or a control server) existing on an external network (e.g., the Internet, a cloud network, or a company-specific network) via a base station or an access point. In addition, for example, the general communication I / F 7620 can be connected to a terminal existing near the vehicle (the terminal is, for example, a driver's terminal, a pedestrian or a store, or a machine type communication (MTC) terminal) using a peer-to-peer (P2P) technology.

[0274] The dedicated communication I / F 7630 is a communication I / F that supports the development of a communication protocol for use in a vehicle. The dedicated communication I / F 7630 may implement a standard protocol such as Wireless Access in Vehicular Environments (WAVE) (which is a combination of Institute of Electrical and Electronics Engineers (IEEE) 802.11p as a lower layer and IEEE 1609 as a higher layer), Dedicated Short Range Communication (DSRC), or a cellular communication protocol. The dedicated communication I / F 7630 generally performs V2X communication as a concept including one or more of the following: communication between vehicles and vehicles (vehicle to vehicle), communication between roads and vehicles (vehicle to infrastructure), communication between vehicles and homes (vehicle to home), and communication between pedestrians and vehicles (vehicle to pedestrians).

[0275] The positioning unit 7640 performs positioning, for example, by receiving a global navigation satellite system (GNSS) signal (e.g., a GPS signal from a global positioning system (GPS) satellite) from a GNSS satellite, and generates position information including the latitude, longitude, and altitude of the vehicle. Incidentally, the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, a personal handyphone system (PHS), or a smart phone having a positioning function.

[0276] For example, the beacon receiving section 7650 receives radio waves or electromagnetic waves emitted from a radio station installed on a road or the like, and thereby obtains information on the current position, congestion, closed roads, necessary time, etc. Incidentally, the function of the beacon receiving section 7650 may be included in the above-mentioned dedicated communication I / F 7630.

[0277] The in-vehicle device I / F 7660 is a communication interface for mediating the connection between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 can establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or wireless universal serial bus (WUSB). In addition, the in-vehicle device I / F 7660 can establish a wired connection through a universal serial bus (USB), a high-definition multimedia interface (HDMI (registered trademark)), a mobile high-definition link (MHL), etc. via a connection terminal (and a cable, if necessary) not shown in the figure. The in-vehicle device 7760 may, for example, include at least one of a mobile device and a wearable device owned by an occupant and an information device carried or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a path to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0278] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals and the like according to a predetermined protocol supported by the communication network 7010.

[0279] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the vehicle network I / F 7680. For example, the microcomputer 7610 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information obtained about the inside and outside of the vehicle, and output a control command to the driving system control unit 7100. For example, the microcomputer 7610 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, vehicle speed maintenance for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc. In addition, microcomputer 7610 can perform cooperative control intended for autonomous driving by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information obtained about the vehicle's surroundings, thereby enabling the vehicle to travel automatically without depending on the driver's operation, etc.

[0280] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures, people, etc., based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the vehicle network I / F 7680, and generate local map information including information about the surroundings of the current position of the vehicle. In addition, the microcomputer 7610 may predict dangers such as collision of the vehicle, approach of pedestrians, etc., entering a closed road, etc., based on the obtained information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or lighting a warning lamp.

[0281] The sound / image output unit 7670 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.18In the example of, the audio speaker 7710, the display unit 7720 and the instrument panel 7730 are illustrated as output devices. For example, the display unit 7720 may include at least one of an onboard display and a head-up display. The display unit 7720 may have an augmented reality (AR) display function. The output device may be different from these devices, and may be another device such as headphones, a wearable device such as a glasses-type display worn by a passenger, a projector, a lamp, etc. In the case where the output device is a display device, the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or information received from another control unit in various forms such as text, images, tables, graphics, etc. In addition, in the case where the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced audio data or sound data, etc. into an analog signal, and outputs the analog signal audibly.

[0282] Note that Fig.18 In the illustrated embodiment, at least two control units connected to each other via the communication network 7010 may be integrated into one control unit. Alternatively, each individual control unit may include a plurality of control units. In addition, the vehicle control system 7000 may include another control unit not shown in the figure. In addition, part or all of the functions performed by one of the control units described above may be assigned to another control unit. In other words, as long as information is sent and received via the communication network 7010, predetermined arithmetic processing may be performed by any control unit. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and a plurality of control units may send and receive detection information to each other via the communication network 7010.

[0283] It should be noted that the reference Figure 1 The computer program for each function of the solid-state imaging device 1 according to the present embodiment described can be installed on any control unit or the like. In addition, a computer-readable recording medium in which such a computer program is stored can be provided. The recording medium is, for example, a magnetic disk, an optical disk, a magneto-optical disk, a flash memory, etc. In addition, the above-mentioned computer program can be distributed via, for example, a network without using a recording medium.

[0284] In the above vehicle control system 7000, see Figure 1 The solid-state imaging device 1 according to the present embodiment described can be applied to Fig.18 At least one of the imaging unit 7410, the vehicle exterior information detection unit 7420, or the driver state detection unit 7430 of the application example shown.

[0285] In addition, see Figure 1 At least some components of the solid-state imaging device 1 described may be used in Fig.18The integrated control unit 7600 shown in FIG. 7600 is implemented in a module (eg, an integrated circuit module including one die). Alternatively, see Figure 1 The solid-state imaging device 1 described above can be made of Fig.18 The vehicle control system 7000 shown in FIG. 7 is implemented by multiple control units.

[0286] The above-mentioned embodiment can have the following modes. (1)

[0288] A solid-state imaging device comprising:

[0289] A light receiving element;

[0290] a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal output from the light receiving element;

[0291] a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; and

[0292] The control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifying transistor of the second amplifier circuit based on a reference signal. (2)

[0294] The solid-state imaging device according to (1), wherein

[0295] The first amplifier circuit comprises:

[0296] a first transistor, wherein a current based on a reference signal flows to a first end and the first end is connected to a control terminal;

[0297] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0298] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0299] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor; and

[0300] a switch connected between a first terminal or a second terminal of any one of the first transistor, the second transistor, the third transistor, and the fourth transistor and a power supply voltage, the switch being configured to switch a connection state of the first transistor and the third transistor, and a series or parallel connection of the second transistor and the fourth transistor, and

[0301] A signal obtained by amplifying the input signal is output from the first terminal of the second transistor. (3)

[0303] The solid-state imaging device according to (1), wherein

[0304] The first amplifier circuit comprises:

[0305] a first transistor, wherein a current based on a reference signal flows to a first end and the first end is connected to a control terminal;

[0306] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0307] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0308] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0309] A first switch connected between the second end of the first transistor and a power supply voltage;

[0310] a second switch connected between the second end of the second transistor and a power supply voltage;

[0311] a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor;

[0312] a fourth switch connected between the first end of the second transistor and the second end of the fourth transistor;

[0313] a fifth switch connected between the second terminal of the third transistor and a power supply voltage; and

[0314] a sixth switch connected between the second terminal of the fourth transistor and the power supply voltage, and

[0315] A signal obtained by amplifying the input signal is output from the first terminal of the second transistor. (4)

[0317] The solid-state imaging device according to (3), wherein

[0318] Control Circuit

[0319] performing control to switch between an on state and an off state of the first switch, the second switch, the third switch, and the fourth switch at the same time, and

[0320] Control is performed to switch between the on state and the off state of the fifth switch and the sixth switch at the same timing, and not to turn on the fifth switch and the sixth switch at the same timing as the first switch. (5)

[0322] The solid-state imaging device according to (2) or (4), wherein

[0323] The control circuit controls the switch to be turned on based on the analog gain of the reference signal. (6)

[0325] The solid-state imaging device according to (2) or (4), wherein

[0326] The control circuit controls the switch to be turned on based on the addition mode of the pixel signal. (7)

[0328] The solid-state imaging device according to any one of (2) to (6), wherein

[0329] The control circuit controls the switch to be turned on based on the conversion efficiency of the pixel signal. (8)

[0331] The solid-state imaging device according to (1), wherein

[0332] The first amplifier circuit comprises:

[0333] a first transistor, wherein a current based on a reference signal flows to a first end and the first end is connected to a control terminal;

[0334] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0335] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0336] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0337] a fifth transistor, wherein a first end of the fifth transistor is connected to the second end of the third transistor, a second end of the fifth transistor is connected to a power supply voltage, and a control terminal of the fifth transistor is connected to the control terminal of the first transistor;

[0338] a sixth transistor, a first terminal of the sixth transistor being connected to the second terminal of the fourth transistor, a second terminal of the sixth transistor being connected to a power supply voltage, and a control terminal of the sixth transistor being connected to the control terminal of the first transistor; and

[0339] a switch connected between a first end or a second end of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and a power supply voltage, the switch being configured to switch a connection state of the first transistor, the third transistor, and the fifth transistor with the second transistor, the fourth transistor, and the sixth transistor to be connected in series or in parallel, and

[0340] A signal obtained by amplifying the input signal is output from the first terminal of the second transistor. (9)

[0342] The solid-state imaging device according to (1), wherein

[0343] The first amplifier circuit comprises:

[0344] a first transistor, wherein a current based on a reference signal flows to a first end and the first end is connected to a control terminal;

[0345] a second transistor, wherein a signal based on the input signal flows to the first end and a control terminal is connected to the control terminal of the first transistor;

[0346] a third transistor having a first terminal connected to the second terminal of the first transistor and a control terminal connected to the control terminal of the first transistor;

[0347] a fourth transistor having a first terminal connected to the second terminal of the second transistor and a control terminal connected to the control terminal of the first transistor;

[0348] a fifth transistor, wherein a first end of the fifth transistor is connected to the second end of the third transistor, a second end of the fifth transistor is connected to a power supply voltage, and a control terminal of the fifth transistor is connected to the control terminal of the first transistor;

[0349] a sixth transistor, wherein a first end of the sixth transistor is connected to the second end of the fourth transistor, a second end of the sixth transistor is connected to a power supply voltage, and a control terminal of the sixth transistor is connected to the control terminal of the first transistor;

[0350] A first switch connected between the second end of the first transistor and a power supply voltage;

[0351] a second switch connected between the second end of the second transistor and a power supply voltage;

[0352] a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor; and

[0353] a fourth switch connected between the first terminal of the second transistor and the second terminal of the fourth transistor, and

[0354] A signal obtained by amplifying the input signal is output from the first terminal of the second transistor. (10)

[0356] The solid-state imaging device according to (8) or (9), wherein

[0357] The control circuit performs control to turn on and off the first switch, the second switch, the third switch, and the fourth switch at the same timing. (11)

[0359] The solid-state imaging device according to any one of (1) to (10), wherein

[0360] The second amplifier circuit comprises:

[0361] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0362] an eighth transistor, a first end of the eighth transistor being connected to the second end of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor; and

[0363] a switch connected between the first terminal or the second terminal of the seventh transistor or the eighth transistor and the power supply voltage, the switch being configured to switch the seventh transistor and the eighth transistor to be connected in series or in parallel, and

[0364] A signal is output from the first terminal of the seventh transistor. (12)

[0366] The solid-state imaging device according to any one of (1) to (10), wherein

[0367] The second amplifier circuit comprises:

[0368] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0369] an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0370] a seventh switch connected between the second end of the seventh transistor and a power supply voltage;

[0371] an eighth switch connected between the first terminal of the seventh transistor and the second terminal of the eighth transistor; and

[0372] a ninth switch connected between the second terminal of the eighth transistor and the power supply voltage, and

[0373] A signal is output from the first terminal of the seventh transistor. (13)

[0375] The solid-state imaging device according to (12), wherein

[0376] Control Circuit

[0377] performing control to switch between an on state and an off state of the seventh switch and the eighth switch at the same time, and

[0378] Control is performed not to turn on the eighth switch at the same timing as the seventh switch. (14)

[0380] The solid-state imaging device according to any one of (11) to (13), wherein

[0381] The control circuit controls the switch to be turned on based on the analog gain of the reference signal. (15)

[0383] The solid-state imaging device according to any one of (11) to (14), wherein

[0384] The control circuit controls the switch to be turned on based on the addition mode of the pixel signal. (16)

[0386] The solid-state imaging device according to any one of (11) to (14), wherein

[0387] The control circuit controls the switch to be turned on based on the conversion efficiency of the pixel signal. (17)

[0389] The solid-state imaging device according to any one of (1) to (10), wherein

[0390] The second amplifier circuit comprises:

[0391] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0392] an eighth transistor, a first end of the eighth transistor being connected to the second end of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0393] a ninth transistor, a first end of which is connected to the second end of the eighth transistor, a second end of which is connected to a power supply voltage, and a control terminal of which is connected to the control terminal of the seventh transistor; and

[0394] a switch connected between the first terminal or the second terminal of the seventh transistor, the eighth transistor or the ninth transistor and the power supply voltage, the switch being configured to switch the seventh transistor, the eighth transistor and the ninth transistor to be connected in series or in parallel, and

[0395] A signal is output from the first terminal of the seventh transistor. (18)

[0397] The solid-state imaging device according to any one of (1) to (10), wherein

[0398] The second amplifier circuit comprises:

[0399] a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected;

[0400] an eighth transistor, a first end of the eighth transistor being connected to the second end of the seventh transistor, and a control terminal of the eighth transistor being connected to the control terminal of the seventh transistor;

[0401] a ninth transistor, a first end of which is connected to the second end of the eighth transistor, a second end of which is connected to a power supply voltage, and a control terminal of which is connected to the control terminal of the seventh transistor;

[0402] a seventh switch connected between the second terminal of the seventh transistor and a power supply voltage; and

[0403] an eighth switch connected between the first terminal of the seventh transistor and the second terminal of the eighth transistor, and

[0404] A signal is output from the first terminal of the seventh transistor. (19)

[0406] The solid-state imaging device according to any one of (1) to (18), wherein the active load in the first amplifier circuit and the amplifier transistor in the second amplifier circuit are formed of p-type MOSFETs. (20)

[0408] The solid-state imaging device according to any one of (1) to (18), wherein the active load in the first amplifier circuit and the amplifier transistor in the second amplifier circuit are formed of n-type MOSFETs. (twenty one)

[0410] A comparator, comprising:

[0411] a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal;

[0412] a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; and

[0413] The control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifying transistor of the second amplifier circuit based on a reference signal. (twenty two)

[0415] An electronic device, comprising:

[0416] A light receiving element;

[0417] a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal, the input signal being an output of the light receiving element;

[0418] a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; and

[0419] a control circuit that controls the transconductance of at least one of the active load in the first amplifier circuit or the amplifying transistor in the second amplifier circuit based on the reference signal; wherein

[0420] A digital signal obtained by analog-to-digital conversion of a signal output from the second amplifier circuit is reconfigured by the light receiving element to acquire image data.

[0421] Aspects of the present disclosure are not limited to the above-described embodiments, and include various conceivable modifications. The effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. That is, various additions, modifications, and partial deletions may be made without departing from the conceptual concept and gist of the present disclosure obtained from the contents defined in the claims and their equivalents, etc.

[0422] Reference Symbols List

[0423] 1 Solid-state imaging device

[0424] 10 Horizontal drive circuit

[0425] 12 Vertical drive circuit

[0426] 14-pixel array

[0427] 140 pixels

[0428] 16ADC

[0429] 160 columns ADC

[0430] 162-pixel ADC

[0431] 18 Logic Circuit

[0432] 2 Semiconductor substrate

[0433] 20 First substrate

[0434] 22. Second substrate

[0435] 3 Comparator

[0436] 30 First amplifier circuit

[0437] 32 Second amplifier circuit

[0438] Md1, Md2 input stage transistors

[0439] Ma1, Ma2, Ma3, Ma4, Ma5, Ma6, Ma7, Ma8, Ma9 amplifier stage transistors

[0440] Mb1, Mb2 bias stage transistors

[0441] C1, C2, C3 capacitors.

Claims

1. A solid-state imaging device, comprising: A light receiving element; a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal output from the light receiving element; a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; as well as A control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifying transistor of the second amplifier circuit based on the reference signal.

2. The solid-state imaging device according to claim 1, wherein The first amplifier circuit comprises: a first transistor in which a current based on the reference signal flows to a first end, and the first end is connected to a control terminal; a second transistor in which a signal based on the input signal flows to a first end and a control terminal is connected to the control terminal of the first transistor; a third transistor in which a first terminal is connected to the second terminal of the first transistor and a control terminal is connected to the control terminal of the first transistor; a fourth transistor in which a first terminal is connected to the second terminal of the second transistor and a control terminal is connected to the control terminal of the first transistor; and a switch connected between a first end or a second end of any one of the first transistor, the second transistor, the third transistor, and the fourth transistor and a power supply voltage, the switch being configured to switch a connection state of the first transistor and the third transistor, and a connection state of the second transistor and the fourth transistor to a series connection or a parallel connection, and A signal obtained by amplifying the input signal is output from the first terminal of the second transistor.

3. The solid-state imaging device according to claim 1, wherein The first amplifier circuit comprises: a first transistor in which a current based on the reference signal flows to a first end, and the first end is connected to a control terminal; a second transistor in which a signal based on the input signal flows to a first end and a control terminal is connected to the control terminal of the first transistor; a third transistor in which a first terminal is connected to the second terminal of the first transistor and a control terminal is connected to the control terminal of the first transistor; a fourth transistor in which a first terminal is connected to the second terminal of the second transistor and a control terminal is connected to the control terminal of the first transistor; A first switch connected between the second end of the first transistor and a power supply voltage; a second switch connected between the second end of the second transistor and the power supply voltage; a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor; a fourth switch connected between the first end of the second transistor and the second end of the fourth transistor; a fifth switch connected between the second terminal of the third transistor and the power supply voltage; and a sixth switch connected between the second terminal of the fourth transistor and the power supply voltage, and A signal obtained by amplifying the input signal is output from the first terminal of the second transistor.

4. The solid-state imaging device according to claim 3, wherein The control circuit Control is performed to switch between the on state and the off state of the first switch, the second switch, the third switch and the fourth switch at the same time, and control is performed to switch between the on state and the off state of the fifth switch and the sixth switch at the same time, and the fifth switch and the sixth switch are not turned on at the same time as the first switch.

5. The solid-state imaging device according to claim 2, wherein: The control circuit controls the switch to be turned on based on an analog gain of the reference signal.

6. The solid-state imaging device according to claim 2, wherein: The control circuit controls the switch to be turned on based on an addition pattern of the pixel signal.

7. The solid-state imaging device according to claim 2, wherein: The control circuit controls the switch to be turned on based on a conversion efficiency of a pixel signal.

8. The solid-state imaging device according to claim 1, wherein The first amplifier circuit comprises: a first transistor in which a current based on the reference signal flows to a first end, and the first end is connected to a control terminal; a second transistor in which a signal based on the input signal flows to a first end and a control terminal is connected to the control terminal of the first transistor; a third transistor in which a first terminal is connected to the second terminal of the first transistor and a control terminal is connected to the control terminal of the first transistor; a fourth transistor in which a first terminal is connected to the second terminal of the second transistor and a control terminal is connected to the control terminal of the first transistor; a fifth transistor in which a first terminal is connected to the second terminal of the third transistor, a second terminal is connected to a power supply voltage, and a control terminal is connected to the control terminal of the first transistor; a sixth transistor in which a first terminal is connected to the second terminal of the fourth transistor, a second terminal is connected to the power supply voltage, and a control terminal is connected to the control terminal of the first transistor; and a switch connected between a first end or a second end of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and the power supply voltage, the switch being configured to switch a connection state of the first transistor, the third transistor, and the fifth transistor and the second transistor, the fourth transistor, and the sixth transistor to a series connection or a parallel connection, and A signal obtained by amplifying the input signal is output from the first terminal of the second transistor.

9. The solid-state imaging device according to claim 1, wherein The first amplifier circuit comprises: a first transistor in which a current based on the reference signal flows to a first end, and the first end is connected to a control terminal; a second transistor in which a signal based on the input signal flows to a first end and a control terminal is connected to the control terminal of the first transistor; a third transistor in which a first terminal is connected to the second terminal of the first transistor and a control terminal is connected to the control terminal of the first transistor; a fourth transistor in which a first terminal is connected to the second terminal of the second transistor and a control terminal is connected to the control terminal of the first transistor; a fifth transistor in which a first terminal is connected to the second terminal of the third transistor, a second terminal is connected to a power supply voltage, and a control terminal is connected to the control terminal of the first transistor; a sixth transistor in which a first terminal is connected to the second terminal of the fourth transistor, the second terminal is connected to the power supply voltage, and a control terminal is connected to the control terminal of the first transistor; A first switch connected between the second end of the first transistor and the power supply voltage; a second switch connected between the second end of the second transistor and the power supply voltage; a third switch connected between the first terminal of the first transistor and the second terminal of the third transistor; and a fourth switch connected between the first terminal of the second transistor and the second terminal of the fourth transistor, and A signal obtained by amplifying the input signal is output from the first terminal of the second transistor.

10. The solid-state imaging device according to claim 8, wherein The control circuit performs control to turn on and off the first switch, the second switch, the third switch, and the fourth switch at the same timing.

11. The solid-state imaging device according to claim 1, wherein The second amplifier circuit comprises: a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected; an eighth transistor in which a first terminal is connected to the second terminal of the seventh transistor and a control terminal is connected to the control terminal of the seventh transistor; and a switch connected between the first end or the second end of the seventh transistor or the eighth transistor and a power supply voltage, the switch being configured to switch the seventh transistor and the eighth transistor to be connected in series or in parallel, and A signal is output from the first terminal of the seventh transistor.

12. The solid-state imaging device according to claim 1, wherein The second amplifier circuit comprises: a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected; an eighth transistor in which a first terminal is connected to the second terminal of the seventh transistor and a control terminal is connected to the control terminal of the seventh transistor; a seventh switch connected between the second end of the seventh transistor and a power supply voltage; an eighth switch connected between the first end of the seventh transistor and the second end of the eighth transistor; and a ninth switch connected between the second terminal of the eighth transistor and the power supply voltage, and A signal is output from the first terminal of the seventh transistor.

13. The solid-state imaging device according to claim 12, wherein: The control circuit performing control to switch between an on state and an off state of the seventh switch and the eighth switch at the same time, and Control is performed so as not to turn on the eighth switch at the same timing as the seventh switch.

14. The solid-state imaging device according to claim 11, wherein The control circuit controls the switch to be turned on based on an analog gain of the reference signal.

15. The solid-state imaging device according to claim 11, wherein The control circuit controls the switch to be turned on based on an addition pattern of the pixel signal.

16. The solid-state imaging device according to claim 11, wherein The control circuit controls the switch to be turned on based on a conversion efficiency of a pixel signal.

17. The solid-state imaging device according to claim 1, wherein The second amplifier circuit comprises: a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected; an eighth transistor in which a first terminal is connected to the second terminal of the seventh transistor and a control terminal is connected to the control terminal of the seventh transistor; a ninth transistor in which a first terminal is connected to the second terminal of the eighth transistor, a second terminal is connected to a power supply voltage, and a control terminal is connected to the control terminal of the seventh transistor; and a switch connected between the first end or the second end of the seventh transistor, the eighth transistor or the ninth transistor and the power supply voltage, the switch being configured to switch the seventh transistor, the eighth transistor and the ninth transistor to be connected in series or in parallel, and A signal is output from the first terminal of the seventh transistor.

18. The solid-state imaging device according to claim 1, wherein The second amplifier circuit comprises: a seventh transistor having a control terminal to which the output of the first amplifier circuit is connected; an eighth transistor in which a first terminal is connected to the second terminal of the seventh transistor and a control terminal is connected to the control terminal of the seventh transistor; a ninth transistor in which a first terminal is connected to the second terminal of the eighth transistor, a second terminal is connected to a power supply voltage, and a control terminal is connected to the control terminal of the seventh transistor; a seventh switch connected between the second terminal of the seventh transistor and the power supply voltage; and an eighth switch connected between the first terminal of the seventh transistor and the second terminal of the eighth transistor, and A signal is output from the first terminal of the seventh transistor.

19. A comparator comprising: a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal; a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; as well as A control circuit controls a transconductance of at least one of an active load of the first amplifier circuit or an amplifying transistor of the second amplifier circuit based on the reference signal.

20. An electronic device comprising: A light receiving element; a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal, the input signal being an output of the light receiving element; a second amplifier circuit that amplifies and outputs the first amplified signal output from the first amplifier circuit; as well as a control circuit that controls a transconductance of at least one of an active load in the first amplifier circuit or an amplifying transistor in the second amplifier circuit based on the reference signal; A digital signal obtained by analog-to-digital conversion AD of a signal output from the second amplifier circuit is reconfigured by the light receiving element to acquire image data.

Images