Display substrate, display panel and display device

Abstract

A display substrate includes: a plurality of sub-pixels, an n-th sub-pixel (PX) including: a transmissive region (TS) and a reflective region (FS); a storage capacitor (C) and a switching transistor (T2) provided in the reflection region (FS); the storage capacitor (C) comprises a first polar plate (C11), a second polar plate (C12) and a third polar plate (C13), the first polar plate (C11) is electrically connected with the third polar plate (C13), the second polar plate (C12) is electrically connected with the switching transistor (T2), and each of the first polar plate (C11) and the second polar plate (C12) is insulated from the second polar plate (C12) at an interval; the switching transistor (T2) includes an active portion (A); wherein the orthographic projection of the first polar plate (C11) on the substrate (200) is overlapped with the orthographic projection of the second polar plate (C12) on the substrate (200), and the orthographic projection of the second polar plate (C12) on the substrate (200) is overlapped with the orthographic projection of the third polar plate (C13) on the substrate (200); the orthographic projection of the active part (A) on the substrate (200) and the orthographic projection of the third polar plate (C13) on the substrate (200) are arranged at intervals, and the thickness of the active part (A) is roughly the same as that of the third polar plate (C13). The invention further provides a display panel and a display device.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] Currently, display screens mainly include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. A liquid crystal display typically includes a display substrate, an opposing substrate disposed opposite the display substrate, and a liquid crystal layer located between the display substrate and the opposing substrate. A liquid crystal display can generate an electric field through pixel electrodes in the display substrate to change the rotational orientation of liquid crystal molecules in the liquid crystal layer, and can be used in conjunction with polarizers to achieve display. An organic light-emitting diode display includes an anode, a cathode, and an organic light-emitting layer disposed between the anode and cathode. An organic light-emitting diode can generate current through the anode and cathode to drive the organic light-emitting layer for light-emitting display.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, a display panel, and a display device.

[0005] According to a first aspect of the present disclosure, a display substrate is provided, comprising: a base substrate, a semiconductor layer, a first conductive layer, and a second conductive layer, wherein the second conductive layer is located on a side of the first conductive layer away from the base substrate;

[0006] The display substrate further comprises a plurality of sub-pixels, wherein the nth sub-pixel comprises: a transmission area and a reflection area outside the transmission area;

[0007] The nth sub-pixel further includes: a storage capacitor and a switch transistor arranged in the reflective area;

[0008] The storage capacitor includes: a first plate, a second plate, and a third plate, wherein the first plate is located in the first conductive layer, the second plate is located in the second conductive layer, and the third plate is located on a side of the second conductive layer away from the substrate, the first plate is electrically connected to the third plate, the second plate is electrically connected to the switching transistor, and each of the first plate and the second plate is insulated and spaced apart from the second plate;

[0009] The switching transistor includes an active portion, wherein the active portion is disposed in the semiconductor layer;

[0010] The orthographic projection of the first electrode plate on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate, and the orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the third electrode plate on the base substrate;

[0011] The orthographic projection of the active portion on the base substrate is spaced apart from the orthographic projection of the third electrode plate on the base substrate, and the thickness of the active portion is substantially the same as the thickness of the third electrode plate;

[0012] Said n is a positive integer.

[0013] According to an embodiment of the present disclosure, the display substrate further includes a transparent conductive layer and a first insulating layer, wherein the transparent conductive layer is located on a side of the second conductive layer facing away from the base substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer;

[0014] The third electrode is located in the transparent conductive layer, and the nth sub-pixel further includes a transparent conductive portion, which is located in the transparent conductive layer and is insulated from the third electrode.

[0015] The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected;

[0016] A first via hole is provided on the first insulating layer and penetrates the first insulating layer. The first sub-portion is located in the transmissive region, the second sub-portion is located in the reflective region, an orthographic projection of the second sub-portion on the base substrate overlaps with an orthographic projection of the second electrode plate on the base substrate, and in the overlapping region, the second sub-portion and the second electrode plate are electrically connected through the first via hole.

[0017] The first electrode plate includes a third sub-portion, the orthographic projection of the third sub-portion on the base substrate at least partially surrounds the orthographic projection of the first via on the base substrate, and a part of the orthographic projection of the third sub-portion on the base substrate overlaps with the orthographic projection of the second sub-portion on the base substrate, and another part overlaps with the orthographic projection of the second sub-portion on the base substrate and is arranged at an interval.

[0018] According to an embodiment of the present disclosure, the third subsection includes: a first structure and a second structure;

[0019] The orthographic projections of the first sub-portion, the second sub-portion, and the active portion on the base substrate are arranged along a first direction, and in a second direction, the orthographic projections of the first structure and the second structure on the base substrate are respectively located on opposite sides of the orthographic projection of the first via on the base substrate;

[0020] The orthographic projection of a portion of the first structure close to the second structure on the substrate overlaps with the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of a portion of the first structure away from the second structure on the substrate is spaced apart from the orthographic projection of the second sub-portion on the substrate; and / or,

[0021] The orthographic projection of a portion of the second structure close to the first structure on the substrate overlaps with the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of a portion of the second structure away from the first structure on the substrate is spaced apart from the orthographic projection of the second sub-portion on the substrate;

[0022] The second direction intersects the first direction.

[0023] According to an embodiment of the present disclosure, in the first direction, an orthographic projection of any one of the first structure and the second structure on the base substrate has a first distance from an orthographic projection of the first sub-portion on the base substrate, and an orthographic projection of the first via on the base substrate has a second distance from an orthographic projection of the first sub-portion on the base substrate.

[0024] The first interval is smaller than the second interval.

[0025] According to an embodiment of the present disclosure, the transparent conductive portion further includes a connecting sub-portion located between the first sub-portion and the second sub-portion;

[0026] The orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the connecting sub-portion on the base substrate.

[0027] According to an embodiment of the present disclosure, the first electrode plate further includes a fourth sub-portion, wherein in the first direction, an orthographic projection of the fourth sub-portion on the substrate is located between an orthographic projection of the second sub-portion on the substrate and an orthographic projection of the active portion on the substrate, and an orthographic projection of the third sub-portion on the substrate is located on a side of the orthographic projection of the fourth sub-portion on the substrate that is closer to the orthographic projection of the second sub-portion on the substrate.

[0028] An orthographic projection of the third electrode plate on the base substrate overlaps with an orthographic projection of the fourth sub-portion on the base substrate.

[0029] According to an embodiment of the present disclosure, the display substrate further comprises a plurality of data lines, the plurality of data lines are arranged along the second direction, and the xth data line is electrically connected to the nth sub-pixel;

[0030] In the nth sub-pixel, in the second direction, an orthographic projection of the third electrode on the substrate and an orthographic projection of the xth data line on the substrate have a third spacing, an orthographic projection of the third electrode on the substrate and an orthographic projection of the x+1th data line on the substrate have a fourth spacing, an orthographic projection of the second electrode on the substrate and an orthographic projection of the xth data line on the substrate have a fifth spacing, and an orthographic projection of the second electrode on the substrate and an orthographic projection of the x+1th data line on the substrate have a sixth spacing;

[0031] The third spacing is smaller than the fifth spacing, and the fourth spacing is smaller than the sixth spacing;

[0032] Both x and y are positive integers.

[0033] According to an embodiment of the present disclosure, in the nth sub-pixel, in the second direction, an orthographic projection of the first electrode on the base substrate and an orthographic projection of the xth data line on the base substrate have a seventh spacing, and an orthographic projection of the first electrode on the base substrate and an orthographic projection of the x+1th data line on the base substrate have an eighth spacing;

[0034] The fifth interval is greater than the seventh interval, and the sixth interval is greater than the eighth interval.

[0035] According to an embodiment of the present disclosure, the orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate are arranged along a first direction, and in the first direction, there is a ninth distance between the orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate;

[0036] The orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate are arranged along the first direction, and in the first direction, there is a tenth distance between the orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate;

[0037] The first direction intersects the second direction, and the ninth interval is greater than the tenth interval.

[0038] According to an embodiment of the present disclosure, the orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate are arranged along the first direction, and in the first direction, there is an eleventh spacing between the orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate, and the ninth spacing is smaller than the eleventh spacing.

[0039] According to an embodiment of the present disclosure, the display substrate further includes a second reflective conductive layer, which is located on a side of the transparent conductive layer facing away from the base substrate;

[0040] The nth sub-pixel further includes a reflective portion, the reflective portion is located in the second reflective conductive layer, and a fourth opening is provided on the reflective portion;

[0041] The orthographic projection of the reflective portion on the base substrate at least covers the orthographic projections of the active portion and the third electrode plate on the base substrate, and the orthographic projection of the fourth opening on the base substrate covers the orthographic projection of the first sub-portion on the base substrate.

[0042] According to an embodiment of the present disclosure, the display substrate further includes a first reflective conductive layer, the first reflective conductive layer is located on a side of the second conductive layer away from the base substrate, and the third electrode is located in the first reflective conductive layer;

[0043] The display substrate further comprises a plurality of data lines and a plurality of gate lines, wherein the plurality of data lines are arranged along a second direction, and the plurality of gate lines are arranged along a first direction, wherein the first direction intersects the second direction;

[0044] The xth data line is electrically connected to the nth sub-pixel, and the yth gate line is electrically connected to the nth sub-pixel;

[0045] The orthographic projection of at least one of the x-th data line, the x+1-th data line, the y-1-th gate line, and the y-th gate line on the base substrate overlaps with the orthographic projection of the third electrode in the n-th sub-pixel on the base substrate;

[0046] Both x and y are positive integers.

[0047] According to an embodiment of the present disclosure, the display substrate further includes a transparent conductive layer and a first insulating layer, wherein the transparent conductive layer is located on a side of the first reflective conductive layer facing away from the base substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer;

[0048] The nth sub-pixel further includes a transparent conductive portion, and the transparent conductive portion is located in the transparent conductive layer;

[0049] The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected;

[0050] A first via hole is provided on the first insulating layer and penetrates the first insulating layer. The first sub-portion is located in the transmissive region, the second sub-portion is located in the reflective region, an orthographic projection of the second sub-portion on the base substrate overlaps with an orthographic projection of the second electrode plate on the base substrate, and in the overlapping region, the second sub-portion and the second electrode plate are electrically connected through the first via hole.

[0051] A first opening and a second opening are provided on the third electrode plate, wherein the orthographic projection of the first opening on the base substrate covers the orthographic projection of the transmission area on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first via on the base substrate.

[0052] According to an embodiment of the present disclosure, a third opening is further provided on the third electrode plate, and the orthographic projection of the third opening on the base substrate covers the orthographic projection of the active portion on the base substrate;

[0053] In the second direction, the first opening has a first size, the second opening has a second size, and the third opening has a third size;

[0054] The third size is smaller than the first size and larger than the second size.

[0055] According to an embodiment of the present disclosure, the orthographic projection of the first electrode plate on the base substrate overlaps with the orthographic projection of the second sub-portion on the base substrate, and the orthographic projection of the first electrode plate on the base substrate is located on a side of the orthographic projection of the first via on the base substrate away from the first sub-portion.

[0056] According to an embodiment of the present disclosure, the first sub-portion and the second sub-portion have substantially the same size in the second direction.

[0057] According to an embodiment of the present disclosure, the display substrate further includes a second reflective conductive layer, and the second reflective conductive layer is located on a side of the first reflective conductive layer away from the base substrate;

[0058] The nth sub-pixel further includes a reflective portion, the reflective portion is located in the second reflective conductive layer, an orthographic projection of the reflective portion on the base substrate covers the second opening and an orthographic projection of the third opening on the base substrate, and a fourth opening is further provided on the reflective portion, an orthographic projection of the fourth opening on the base substrate covers the transmissive area;

[0059] In an edge region of the fourth opening, the reflective portion is electrically connected to the first sub-portion.

[0060] According to an embodiment of the present disclosure, a size of the fourth opening in the second direction is greater than or equal to a size of the fourth opening in the first direction.

[0061] According to an embodiment of the present disclosure, the display substrate further includes a display area and the peripheral area at least partially surrounding the display area, and the plurality of sub-pixels are located in the display area;

[0062] The display substrate further includes a plurality of first connection lines, a plurality of second connection lines, and at least one common signal line, wherein the plurality of first connection lines are arranged along a first direction, and the plurality of second connection lines are arranged along the first direction;

[0063] In the nth sub-pixel, the third electrode is electrically connected to the i-th first connecting line, the first electrode is electrically connected to the j-th second connecting line, and the i-th first connecting line and the j-th second connecting line are electrically connected to the common signal line in the peripheral area;

[0064] Both i and j are positive integers.

[0065] According to an embodiment of the present disclosure, in the reflective region, an orthographic projection of the active portion on the base substrate and an orthographic projection of the third electrode plate on the base substrate form a complementary pattern.

[0066] According to a second aspect of the present disclosure, a display panel is provided, comprising a display substrate and an opposing substrate, wherein the display substrate comprises the above-mentioned display substrate, and the opposing substrate comprises a plurality of color resists, wherein the mth color resist is arranged corresponding to the nth sub-pixel;

[0067] The m-th color resist includes a first region, a second region, and a third region, wherein an orthographic projection of the first region on the base substrate covers an orthographic projection of the transmission region of the n-th sub-pixel on the base substrate, and an orthographic projection of the third region on the base substrate covers an orthographic projection of the active portion of the n-th sub-pixel on the base substrate, and in a first direction, the second region is located between the first region and the third region;

[0068] In a second direction, a size of the second area is smaller than or equal to a size of the third area, and the second direction intersects the first direction;

[0069] The m is a positive integer.

[0070] According to an embodiment of the present disclosure, the plurality of color resists include a first color resist, a second color resist, and a third color resist, the first color resist, the second color resist, and the third color resist have different colors, and the orthographic projection of the first color resist on the base substrate, the orthographic projection of the second color resist on the base substrate, and the orthographic projection of the third color resist on the base substrate are spaced apart from each other;

[0071] In the second direction, the second area of ​​the first color resist has a fourth size, the second area of ​​the second color resist has a fifth size, and the second area of ​​the third color resist has a sixth size. The fifth size is larger than the fourth size and smaller than the sixth size.

[0072] According to an embodiment of the present disclosure, the display panel further includes a liquid crystal layer, the liquid crystal layer includes a plurality of dimming areas, and the zth dimming area is arranged corresponding to the nth sub-pixel;

[0073] The zth dimming area includes a first dimming sub-area and a second dimming sub-area, the orthographic projection of the first dimming sub-area on the substrate covers the orthographic projection of the transmission area of ​​the nth sub-pixel on the substrate, the orthographic projection of the second dimming sub-area on the substrate covers the orthographic projection of the reflection area of ​​the nth sub-pixel on the substrate, and the box thickness of the first dimming sub-area is greater than the box thickness of the second dimming sub-area.

[0074] According to a third aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0076] 1A to 1E schematically illustrate plan views of sub-pixels of a display substrate in one example;

[0077] FIG2 schematically shows a plan view of a display substrate in an embodiment of the present disclosure;

[0078] FIG3 schematically shows a plan view of a first conductive layer in some embodiments of the present disclosure;

[0079] FIG4 schematically shows a plan view of a semiconductor layer in some embodiments of the present disclosure;

[0080] FIG5 schematically shows a plan view of the second conductive layer in some embodiments of the present disclosure;

[0081] FIG6 schematically shows a plan view of a transparent conductive layer in some embodiments of the present disclosure;

[0082] FIG7 schematically shows a plan view of a first insulating layer in some embodiments of the present disclosure;

[0083] FIG8 schematically shows a plan view of a second reflective conductive layer in some embodiments of the present disclosure;

[0084] FIG9 schematically shows a plan view of a first conductive layer and a semiconductor layer in some embodiments of the present disclosure;

[0085] FIG10 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, and a first insulating layer in some embodiments of the present disclosure;

[0086] FIG11 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a transparent conductive layer in some embodiments of the present disclosure;

[0087] FIG12 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a transparent conductive layer, and a second reflective conductive layer in some embodiments of the present disclosure;

[0088] FIG13 schematically shows a cross-sectional view of a sub-pixel in some embodiments of the present disclosure;

[0089] FIG14 schematically shows the spacing between the first structure, the second structure, the first via hole, and the first sub-section in an embodiment of the present disclosure;

[0090] FIG15 schematically shows the spacing between the first electrode plate, the second electrode plate, the third electrode plate and the data line in an embodiment of the present disclosure;

[0091] FIG16 schematically shows the distances between the first electrode plate, the second electrode plate, the third electrode plate and the active portion in an embodiment of the present disclosure;

[0092] FIG17 schematically shows a plan view of the first conductive layer in some other embodiments of the present disclosure;

[0093] FIG18 schematically shows a plan view of a semiconductor layer in some other embodiments of the present disclosure;

[0094] FIG19 schematically shows a plan view of the second conductive layer in some other embodiments of the present disclosure;

[0095] FIG20 schematically shows a plan view of the first insulating layer in some other embodiments of the present disclosure;

[0096] FIG21 schematically shows a plan view of a transparent conductive layer in some other embodiments of the present disclosure;

[0097] FIG22 schematically shows a plan view of the first reflective conductive layer in some other embodiments of the present disclosure;

[0098] FIG23 schematically shows a plan view of the second reflective conductive layer in some other embodiments of the present disclosure;

[0099] FIG24 schematically shows a plan view of a first conductive layer and a semiconductor layer in some other embodiments of the present disclosure;

[0100] FIG25 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, and a first insulating layer in some other embodiments of the present disclosure;

[0101] FIG26 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a first reflective conductive layer in some other embodiments of the present disclosure;

[0102] FIG27 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, and a transparent conductive layer in some other embodiments of the present disclosure;

[0103] FIG28 schematically shows a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, a transparent conductive layer, and a second reflective conductive layer in some other embodiments of the present disclosure;

[0104] FIG29 schematically shows a cross-sectional view of a sub-pixel in some other embodiments of the present disclosure;

[0105] 30 and 31 schematically illustrate cross-sectional views of a display panel according to an embodiment of the present disclosure;

[0106] FIG32 schematically shows a plan view of a color resist in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0108] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0109] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0110] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0111] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0112] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0113] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0114] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0115] At present, LCD screens can be divided into transmissive LCD screens, reflective LCD screens and semi-transmissive and semi-reflective LCD screens. Transmissive LCD screens use a backlight module as a light source. The light emitted by the backlight module passes through the liquid crystal layer and the polarizer to display the image. Transmissive LCD screens can display images in dark environments, but the display is not clear in bright environments. Reflective LCD screens use external ambient light as a light source. After the external ambient light enters the reflective LCD screen, it is reflected to display the image. Reflective LCD screens can achieve clear display in bright environments, but they cannot display images in dark environments. Semi-transmissive and semi-reflective LCD screens have the characteristics of both transmissive and reflective LCD screens. Transmissive and reflective areas are set in the screen at the same time. They can be used in both bright and dark environments.

[0116] In one example, a transflective liquid crystal display is provided. The transflective liquid crystal display in this example can switch between reflective display and transmissive display, using ambient light as a light source in reflective display and a backlight module as a light source in transmissive display.

[0117] The semi-transmissive and semi-reflective liquid crystal display screen in this example includes a display substrate and an opposing substrate. Figures 1A to 1E schematically show plan views of sub-pixels of the display substrate in an example, wherein Figure 1A schematically shows a plan view of the first conductive layer in an example, Figure 1B schematically shows a plan view of the second conductive layer in an example, Figure 1C schematically shows a plan view of the reflective layer in an example, Figure 1D schematically shows a plan view of the first conductive layer and the second conductive layer in an example, and Figure 1E schematically shows a plan view of the first conductive layer, the second conductive layer and the reflective layer in an example.

[0118] With reference to Figures 1A to 1E , the display substrate includes a plurality of sub-pixels, at least one of which includes a reflective portion 110. The reflective portion 110 is located in the reflective layer. The reflective portion 110 is used to: reflect ambient light during reflective display, and prevent light leakage during transmissive display. In this example, at least part of the black matrix in the opposing substrate is removed. At the same time, the width of the data lines 120 and the gate lines 130 in the display substrate is thickened. The data lines 120 and the gate lines 130 can also reflect light, which can increase the reflection area during reflective display, thereby improving the aperture ratio during reflective display. In addition, the data lines 120 and the gate lines 130 can overlap with the reflective portion 110 in the display substrate, thereby replacing the cancelled black matrix to achieve a light shielding effect during transmissive display, thereby preventing light leakage during transmissive display.

[0119] In this example, at least one subpixel includes a switching transistor T1 and a storage capacitor Cst. Due to the subpixel's pixel structure, a transition voltage ΔVp inevitably exists due to coupling capacitance and the gate voltage switching from a high potential to a low potential. The theoretical formula for this transition voltage ΔVp is as follows: ΔVp = Cgs*(Vgh - Vgl) / (Cgs + Cst + Clc);

[0120] Where: ΔVp is the trip voltage, Vgh is the gate high voltage of the switching transistor T1, Vgl is the gate low voltage of the switching transistor T1, and Clc is the liquid crystal capacitance. Typically, Cgs is the capacitance formed by the gate and source of the switching transistor T1, and the gate insulation layer therebetween. Cst is the storage capacitance Cst formed by the pixel electrode and common electrode, and the insulation layer therebetween.

[0121] Due to the influence of liquid crystal characteristics, the maximum liquid crystal capacitance Clcmax and the minimum liquid crystal capacitance Clcmin are quite different, which makes the difference Ω between the maximum jump voltage Vpmax and the minimum jump voltage ΔVpmin larger. When the difference Ω is greater than 0.5, unacceptable flicker (fliker) will appear on the screen.

[0122] In order to reduce the difference Ω, the capacitance of the storage capacitor Cst can be increased. However, in order to meet the high-resolution requirements, the size of the sub-pixels in the display substrate is getting smaller and smaller, and accordingly, the area of ​​the storage capacitor Cst in the sub-pixel is also getting smaller and smaller. In the above example, due to the thickening of the data line 120 and the gate line 130, the area of ​​the storage capacitor Cst is further limited. The area of ​​the storage capacitor Cst is positively correlated with the capacitance of the storage capacitor Cst. The reduction in the area of ​​the storage capacitor Cst directly leads to a decrease in the capacitance of the storage capacitor Cst. In this example, since the area of ​​the storage capacitor Cst is limited to a large extent, the capacitance of the storage capacitor Cst is difficult to meet the demand for reducing the difference Ω.

[0123] In view of this, embodiments of the present disclosure provide a display substrate comprising: a base substrate, a semiconductor layer, a first conductive layer, and a second conductive layer, the second conductive layer being located along a side of the first conductive layer away from the base substrate. The display substrate further comprises a plurality of sub-pixels, wherein the nth sub-pixel comprises a transmissive region and a reflective region located outside the transmissive region. n is a positive integer. The nth sub-pixel further comprises a storage capacitor disposed in the reflective region and a switching transistor. The storage capacitor comprises a first plate, a second plate, and a third plate, the first plate being located in the first conductive layer, the second plate being located in the second conductive layer, and the third plate being located on a side of the second conductive layer facing away from the base substrate. The first plate is electrically connected to the third plate, and the second plate is electrically connected to the switching transistor. Each of the first and second plates is insulated and spaced apart from the second plate. The switching transistor comprises an active portion disposed in the semiconductor layer. The orthographic projection of the first plate on the base substrate overlaps with the orthographic projection of the second plate on the base substrate, and the orthographic projection of the second plate on the base substrate overlaps with the orthographic projection of the third plate on the base substrate. The orthographic projection of the active portion on the base substrate is spaced apart from the orthographic projection of the third electrode plate on the base substrate, and the thickness of the active portion is substantially the same as that of the third electrode plate.

[0124] In this way, the capacitance of the storage capacitor can be increased, effectively reducing the aforementioned difference Ω. At the same time, the horizontal dimensions of the storage capacitor only change slightly, or even remain unchanged, facilitating the design of small sub-pixels. Furthermore, the third electrode plate is spaced apart from the active portion and has approximately the same thickness, thereby reducing or evening the step difference in the film layer caused by the active portion. This, in turn, helps to make the reflective surface in the reflective area flatter, thereby improving the reflective efficiency of the reflective area.

[0125] FIG2 schematically shows a plan view of a display substrate in an embodiment of the present disclosure.

[0126] 2 , the display substrate in the embodiment of the present disclosure includes a display area AA and a peripheral area NA located on at least one side of the display area AA.

[0127] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a polygon (e.g., a rectangle) with straight edges, a circle or an ellipse with curved edges, or a semicircle or a semiellipse with both straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as a region having a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0128] The display substrate may further include a base substrate 200 and a plurality of pixel units P disposed on the base substrate 200 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a first direction Y and a second direction X. Each pixel unit P may include a plurality of sub-pixels PX. For example, the pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the embodiments of the present disclosure are not limited thereto.

[0129] The display substrate further includes a plurality of gate lines GL and a plurality of data lines DL disposed on the base substrate 200 and located at least in the display area AA. The plurality of gate lines GL extend along the second direction X, and the plurality of data lines DL extend along the first direction Y. Exemplarily, one sub-pixel PX is connected to one data line DL and one gate line GL, sub-pixels PX in the same row are connected to the same gate line GL, sub-pixels PX in different rows are connected to different gate lines GL, sub-pixels PX in the same column are connected to the same data line DL, and sub-pixels PX in different columns are connected to different data lines DL.

[0130] The peripheral area NA may be disposed on at least one side of the display area AA. For example, the peripheral area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the peripheral area NA may include a vertical portion extending in the first direction Y and a horizontal portion extending in the second direction X.

[0131] The display substrate may further include a gate drive circuit 21 and a drive chip 22 arranged on the base substrate 200 and located in the peripheral area NA. For example, the gate drive circuit 21 may be located on at least one side of the display area AA. In the embodiment shown in Figure 2, the gate drive circuit 21 is respectively located on the left and right sides of the display area AA. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) viewed by the human eye during display. For example, the drive chip 22 may be located on at least one side of the display area AA. In the embodiment shown in Figure 2, the drive chip 22 is located on the lower side of the display area AA. It should be noted that the lower side may be the lower side of the display substrate (screen) viewed by the human eye during display.

[0132] The driver chip 22 includes a data driver circuit that sequentially latches input data according to a clock signal, converts the latched data into analog signals, and then inputs them to the data lines DL of the display substrate. The gate driver circuit 21 is typically implemented by a shift register, which converts the clock signal into on / off voltages and outputs them to the gate lines GL of the display substrate.

[0133] It should be noted that although Figure 2 shows that the gate drive circuit 21 is located on the left and right sides of the display area AA and the drive chip 22 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate drive circuit 21 and the drive chip 22 can be located at any suitable position in the peripheral area NA.

[0134] For example, the gate driver circuit 21 can adopt GOA technology, i.e., Gate Driver on Array. In GOA technology, the gate driver circuit 21 is directly set on the array substrate to replace the external chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a gate line GL. The shift registers at each level output scanning signals in sequence to achieve row-by-row scanning of the pixel unit. In some embodiments, each level of shift register can also be connected to multiple gate lines GL. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrates. The driver chip 22 can be folded to the back side of the display substrate through a structure such as a cover chip film.

[0135] The display substrate according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 2 to FIG. 29 .

[0136] Figures 3 to 12 schematically illustrate plan views of sub-pixels in some embodiments of the present disclosure, and Figure 13 schematically illustrates a cross-sectional view of a sub-pixel in some embodiments of the present disclosure. Figure 3 schematically illustrates a plan view of a first conductive layer in some embodiments of the present disclosure, Figure 4 schematically illustrates a plan view of a semiconductor layer in some embodiments of the present disclosure, Figure 5 schematically illustrates a plan view of a second conductive layer in some embodiments of the present disclosure, Figure 6 schematically illustrates a plan view of a transparent conductive layer in some embodiments of the present disclosure, Figure 7 schematically illustrates a plan view of a first insulating layer in some embodiments of the present disclosure, Figure 8 schematically illustrates a plan view of a second reflective conductive layer in some embodiments of the present disclosure, Figure 9 schematically illustrates a plan view of a first conductive layer and a semiconductor layer in some embodiments of the present disclosure, Figure 10 schematically illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, and a first insulating layer in some embodiments of the present disclosure, Figure 11 schematically illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a transparent conductive layer in some embodiments of the present disclosure, and Figure 12 schematically illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a transparent conductive layer, and a second reflective conductive layer in some embodiments of the present disclosure.

[0137] 2 to 13 , the display substrate of the embodiment of the present disclosure further includes: a semiconductor layer 210 , a first conductive layer 220 and a second conductive layer 230 . The second conductive layer 230 is located on a side of the first conductive layer 220 away from the base substrate 200 .

[0138] The semiconductor layer 210 may be made of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The first conductive layer 220 may be made of a metal. For example, the first conductive layer 220 may be made of a metal such as Mo, Al, Cu, or alloys thereof, or a material such as Ti / Al / Ti. Optionally, a plurality of gate lines GL may be located in the first conductive layer 220. The second conductive layer 230 may be made of a metal. For example, the second conductive layer 230 may be made of a metal such as Mo, Al, Cu, or alloys thereof, or a material such as Ti / Al / Ti. Optionally, a plurality of data lines DL may be located in the second conductive layer 230.

[0139] The display substrate of the present disclosure is used in a transflective display screen. The nth subpixel PX among a plurality of subpixels PX includes a transmissive region TS and a reflective region FS located outside the transmissive region TS. The nth subpixel PX also includes a storage capacitor C and a switching transistor T2 disposed in the reflective region FS. n is a positive integer.

[0140] The nth sub-pixel PX may refer to any one of a plurality of sub-pixels PX. That is, in the embodiments of the present disclosure, any one of the plurality of sub-pixels PX may include a reflective region FS, a transmissive region TS, a storage capacitor C located in the reflective region FS, and a switching transistor T2. The reflective region FS is used to reflect ambient light during reflective display, while the transmissive region TS is used to allow light emitted by the backlight module to pass through during transmissive display.

[0141] The transmissive area TS and the reflective area FS can have various shapes. For example, the transmissive area TS and the reflective area FS can be provided in various shapes, such as a closed polygon with straight edges (e.g., a rectangle), a circle with curved edges, an ellipse, and the like, as well as a semicircle with straight and curved edges, a semi-ellipse, and the like. In the embodiment of the present disclosure, the transmissive area TS and the reflective area FS are provided as a single area with a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. For example, alternatively, the reflective area FS may at least partially surround the transmissive area TS.

[0142] Optionally, the transmissive region TS and the reflective region FS are arranged along a first direction Y, the n-th sub-pixel PX is electrically connected to the y-th gate line GL, and in the n-th sub-pixel PX, the orthographic projection of the transmissive region TS on the base substrate 200 is located on a side of the orthographic projection of the reflective region FS on the base substrate 200 that is away from the y-th gate line GL. In other words, the reflective region FS is closer to the y-th gate line GL than the transmissive region TS. Alternatively, the reflective region FS may be disposed around the transmissive region TS, and the specific arrangement may be determined based on actual needs, and the embodiments of the present disclosure are not limited thereto.

[0143] For clarity, unless otherwise specified, the following description will be made by taking one sub-pixel PX (ie, the nth sub-pixel PX) and a signal line electrically connected to the sub-pixel PX as an example.

[0144] In the nth subpixel PX, the storage capacitor C includes a first plate C11, a second plate C12, and a third plate C13. The first plate C11 is located in the first conductive layer 220, the second plate C12 is located in the second conductive layer 230, and the third plate C13 is located on a side of the second conductive layer 230 facing away from the base substrate 200. The first plate C11 is electrically connected to the third plate C13, and the second plate C12 is electrically connected to the switching transistor T2. Each of the first plate C11 and the second plate C12 is insulated and spaced apart from the second plate C12. The switching transistor T2 includes an active portion A disposed in the semiconductor layer 210. The orthographic projection of the first plate C11 on the base substrate 200 overlaps with the orthographic projection of the second plate C12 on the base substrate 200, and the orthographic projection of the second plate C12 on the base substrate 200 overlaps with the orthographic projection of the third plate C13 on the base substrate 200.

[0145] The first plate C11 is closer to the base substrate 200 than the second plate C12, and the second plate C12 is closer to the base substrate 200 than the third plate C13. In other words, in the thickness direction of the display substrate, the first plate C11 and the third plate C13 are disposed on either side of the second plate C12. The first plate C11 and the third plate C13 are electrically connected to each other, thereby collectively forming a first end of the storage capacitor C. For example, the first plate C11 and the third plate C13 are both electrically connected to a common signal line VCOM located in the peripheral area NA via a connecting line. Furthermore, the common signal line VCOM provides a constant voltage signal (e.g., a common voltage signal) to the first plate C11 and the third plate C13.

[0146] The second electrode plate C12 forms the second end of the storage capacitor C. The gate G of the switching transistor T2 is electrically connected to the gate line GL. The first electrode TS of the switching transistor T2 is electrically connected to the data line DL. The second electrode TD of the switching transistor T2 is electrically connected to the second end of the storage capacitor C. The switching transistor T2 is turned on in response to an active level signal provided by the gate line GL. At this time, the data voltage signal on the data line DL can be written into the storage capacitor C through the switching transistor T2.

[0147] In the example shown in FIG1 , the storage capacitor C includes two plates, for example, a first plate C1 located in the first conductive layer and a second plate C2 located in the second conductive layer. In the thickness direction of the display substrate, the first plate C1 and the second plate C2 overlap and are insulated and spaced apart. Compared to the example shown in FIG1 , the storage capacitor C of the embodiment of the present disclosure is further provided with a third plate C13, which overlaps with the first plate C11 and the second plate C12. This significantly increases the capacitance of the storage capacitor C while allowing only minor changes, or even no changes, to the horizontal dimensions of the storage capacitor C, facilitating the design of a small sub-pixel PX.

[0148] The switching transistor T2 may include a top gate structure or a bottom gate structure. For example, in the embodiment of the present disclosure, the switching transistor T2 adopts a bottom gate structure. For example, the semiconductor layer 210 is located between the first conductive layer 220 and the second conductive layer 230, the gate G of the switching transistor T2 is located in the first conductive layer 220, and the orthographic projection of the gate G of the switching transistor T2 on the substrate 200 overlaps the orthographic projection of the active portion A on the substrate 200. The active portion A includes a first pole connection portion, a second pole connection portion, and a channel portion located between the first pole connection portion and the second pole connection portion. The first pole connection portion is electrically connected to the first pole TS of the switching transistor T2, and the second pole connection portion is electrically connected to the second pole TD of the switching transistor T2.

[0149] In the reflective region FS, the active portion A is only provided in the switching transistor T2. This active portion A causes a step difference in the film layer in the reflective region FS, thereby affecting the uniformity of the film thickness in the reflective region FS. In view of this, in the embodiments of the present disclosure, the orthographic projection of the third electrode plate C13 on the base substrate 200 is spaced apart from the orthographic projection of the active portion A on the base substrate 200, and the thickness of the third electrode plate C13 is substantially the same as that of the active portion A.

[0150] For example, the ratio of the thickness of the active portion A to the thickness of the third electrode plate C13 can be set to 8:11 to 11:8. For example, the ratio of the thickness of the active portion A to the thickness of the third electrode plate C13 can be set to 9:11 to 11:9. Preferably, the ratio of the thickness of the active portion A to the thickness of the third electrode plate C13 can be set to 10:11 to 11:10. Ideally, the ratio of the thickness of the active portion A to the thickness of the third electrode plate C13 can be set to 1:1, in which case the film thickness step difference can be further improved.

[0151] The thickness of the active portion A can be set to 0.12 μm to 0.24 μm, for example, 0.14 μm, 0.16 μm, 0.18 μm, 0.2 μm, or 0.22 μm. The thickness of the third electrode plate C13 can be set to 0.14 μm to 0.26 μm, for example, 0.16 μm, 0.18 μm, 0.2 μm, 0.22 μm, or 0.24 μm. In an embodiment of the present disclosure, the thickness of the active portion A can be set to 0.18 μm, and the thickness of the third electrode plate C13 can be set to 0.2 μm.

[0152] It should be noted that the ratio and specific value between the thickness of the active part A and the third electrode plate C13 are not limited to the above examples and can be selected according to actual needs, as long as the difference between the thickness of the active part A and the thickness of the third electrode plate C13 does not exceed 30%.

[0153] In this way, the film layer step difference caused by the active portion A can be reduced or filled by the third electrode plate C13, which is beneficial to improving the uniformity of the film thickness of the reflective region FS.

[0154] Therefore, the third electrode plate C13 can not only increase the capacitance of the storage capacitor C, but also reduce or fill the film step caused by the active portion A, thereby making the reflection surface in the reflection area FS flatter and improving the reflection efficiency of the reflection area FS.

[0155] The following further describes the embodiments of the present disclosure.

[0156] In some specific embodiments, the display substrate further includes a transparent conductive layer 240 and a first insulating layer 250 . The transparent conductive layer 240 is located on the side of the second conductive layer 230 facing away from the base substrate 200 . The first insulating layer 250 is located between the second conductive layer 230 and the transparent conductive layer 240 .

[0157] In an embodiment of the present disclosure, the material of the transparent conductive layer 240 may include a transparent conductive material. For example, the material of the transparent conductive layer 240 may include indium tin oxide (ITO). The first insulating layer 250 may include an inorganic insulating material, an organic insulating material, or any combination thereof. For example, the inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic insulating material may include polyimide, polyamide, acrylic resin, phenol resin, benzocyclobutene, etc.

[0158] In the embodiment of the present disclosure, the third electrode plate C13 can be located in the transparent conductive layer 240, or the third electrode plate C13 can be located in the first reflective conductive layer described below. The following first describes the embodiment of the present disclosure in which the third electrode plate C13 is located in the transparent conductive layer 240, with reference to Figures 3 to 16.

[0159] The third electrode plate C13 is located in the transparent conductive layer 240, and the third electrode plate C13 can have various shapes. For example, the third electrode plate C13 can be provided in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or an ellipse with curved edges, and a semicircle or a semi-ellipse with straight and curved edges. In the embodiment of the present disclosure, the third electrode plate C13 is provided as a region having a quadrilateral shape including straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and not a limitation of the present disclosure. For example, in other embodiments, the third electrode plate C13 may also include a shape that can form a complementary pattern with the active portion A. The specific details will be described in detail below, so it will not be repeated here.

[0160] The nth subpixel PX further includes a transparent conductive portion 241, which is located in the transparent conductive layer 240 and is insulated and spaced apart from the third electrode C13. The transparent conductive portion 241 includes a first sub-portion 2411 and a second sub-portion 2412, which are electrically connected. A first via V1 is provided on the first insulating layer 250, penetrating the first insulating layer 250. The first sub-portion 2411 is located in the transmissive region TS, and the second sub-portion 2412 is located in the reflective region FS. The orthographic projection of the second sub-portion 2412 on the base substrate 200 overlaps with the orthographic projection of the second electrode C12 on the base substrate 200. In the overlapping region, the second sub-portion 2412 and the second electrode C12 are electrically connected via the first via V1.

[0161] In an embodiment of the present disclosure, the first sub-portion 2411 may be a pixel electrode in the transmissive region TS. For example, after the display substrate and the counter substrate 300 are aligned, the liquid crystal layer is located on the side of the first sub-portion 2411 facing away from the base substrate 200. Because the transparent conductive layer 240 comprises a transparent conductive material, the first sub-portion 2411 allows light to pass through. In other words, light emitted by the backlight module can pass through the first sub-portion 2411 and enter the liquid crystal layer. One end of the second electrode C12 is electrically connected to the second electrode TD of the switching transistor T2, and the other end of the second electrode C12 is electrically connected to the second sub-portion 2412 via a first via V1. Thus, when the switching transistor T2 is turned on, the data voltage signal on the data line DL can be transmitted to the first sub-portion 2411 via the switching transistor T2, the second electrode C12, and the second sub-portion 2412. This generates a first electric field between the first sub-portion 2411 and the corresponding common electrode. This first electric field can drive the liquid crystals in the liquid crystal layer to change their rotational orientation, thereby achieving a display function.

[0162] In some specific embodiments, the display substrate further includes a second reflective conductive layer 260, which is located on a side of the transparent conductive layer 240 facing away from the base substrate 200. The nth sub-pixel PX further includes a reflective portion 261, which is located in the second reflective conductive layer 260 and has a fourth opening K4 defined therein. The orthographic projection of the reflective portion 261 on the base substrate 200 covers at least the orthographic projections of the active portion A and the third electrode plate C13 on the base substrate 200. The orthographic projection of the fourth opening K4 on the base substrate 200 covers the orthographic projection of the first sub-portion 2411 on the base substrate 200.

[0163] The second reflective conductive layer 260 is made of a light-reflecting conductive material, enabling the reflective portion 261 to reflect light. This allows the reflective portion 261 to reflect ambient light during reflective display and prevent light leakage during transmissive display. The fourth opening K4 exposes the reflective area FS of the sub-pixel PX, allowing light emitted by the backlight module to escape therethrough during transmissive display. At the edge of the fourth opening K4, the reflective portion 261 is electrically connected to the first sub-portion 2411, enabling the reflective portion 261 to function as a pixel electrode in the reflective area FS.

[0164] For example, after the display substrate and the counter substrate 300 are aligned, the liquid crystal layer is located on the side of the reflective portion 261 facing away from the base substrate 200. Thus, during reflective display, ambient light can be reflected back into the liquid crystal layer via the reflective portion 261. Simultaneously, when the switch transistor T2 is turned on, the data voltage signal on the data line DL can be transmitted to the reflective portion 261 via the switch transistor T2, the second electrode C12, the second sub-portion 2412, and the first sub-portion 2411. This allows a second electric field to be formed between the reflective portion 261 and the corresponding common electrode. This second electric field can drive the liquid crystals in the liquid crystal layer to change their rotational orientation, thereby achieving a display function.

[0165] 13 , the reflective portion 261 covers the active portion A and the third electrode plate C13. Through the third electrode plate C13, the portion of the reflective portion 261 covering the active portion A and the portion covering the third electrode plate C11 are approximately located in the same horizontal plane, thereby making the reflective surface in the reflective region FS as flat as possible.

[0166] In addition to covering the active portion A and the third electrode plate C13, the orthographic projection of the reflective portion 261 on the base substrate 200 can also cover the orthographic projection of the entire reflective area FS on the base substrate 200. Furthermore, the orthographic projection of the reflective portion 261 on the base substrate 200 can also overlap with adjacent gate lines and data lines. For example, the reflective portion 261 in the nth sub-pixel PX can overlap with the xth data line DL, the x+1th data line DL, the y-1th gate line GL, and the yth gate line GL. In this way, on the one hand, the reflection area during reflective display can be increased. On the other hand, during transmissive display, the reflective portion 261, the data line GL, and the gate line DL can replace the black matrix in the color filter substrate to block light. As a result, the black matrix in the color filter substrate can be eliminated, which can increase the amount of light entering during reflective display.

[0167] In some specific embodiments, the first electrode plate C11 includes a third sub-portion 211 and a fourth sub-portion 212, the orthographic projection of the fourth sub-portion 212 on the base substrate 200 is located on a side of the orthographic projection of the second sub-portion 2412 on the base substrate 200 that is away from the orthographic projection of the first sub-portion 2411 on the base substrate 200, the orthographic projection of the third sub-portion 211 on the base substrate 200 is located on a side of the orthographic projection of the fourth sub-portion 212 on the base substrate 200 that is close to the second sub-portion 2412, and the orthographic projection of the third sub-portion 211 on the base substrate 200 at least partially surrounds the orthographic projection of the first via V1 on the base substrate 200. Moreover, a portion of the orthographic projection of the third sub-portion 211 on the base substrate 200 overlaps with the orthographic projection of the second sub-portion 2412 on the base substrate 200, and another portion is arranged to overlap with the orthographic projection of the second sub-portion 2412 on the base substrate 200. In the thickness direction of the display substrate, the third sub-portion 211 is arranged to overlap with the second sub-portion 2412, and at the same time, it extends from the overlapping position to the periphery of the second sub-portion 2412.

[0168] The first via V1 is closer to the first sub-portion 2411 than the fourth sub-portion 212. The orthographic projection of the third sub-portion 211 on the base substrate 200 is generally U-shaped. In the thickness direction of the display substrate, the inner side of the U-shape overlaps with the second sub-portion 2412, while the outer side is spaced apart from the second sub-portion 2412. This allows the third sub-portion 211 to surround the periphery of the first via V1 and maintain a certain distance from the first via V1. This prevents electrostatic discharge from occurring near the location of the first via V1 and potentially damaging nearby devices. For example, when forming the first via V1 through a dry etching process (e.g., plasma bombardment), charge accumulation may form on the second electrode plate C12 exposed by the first via V1. In the embodiments of the present disclosure, by surrounding the third sub-portion 211 around the periphery of the first via V1 and maintaining a certain distance from the first via V1, an electrostatic discharge path can be prevented from forming between the charge accumulation location on the second electrode plate C12 and the third sub-portion 211, thereby preventing electrostatic discharge.

[0169] Moreover, the third sub-section 211 extends to the periphery of the second sub-section 2412, specifically to the periphery of the overlapping area of ​​the extended second electrode plate C12 and the second sub-section 2412. The third sub-section 211 can reduce the film layer step difference caused by the overlap of the second sub-section 2412 and the second electrode plate C12, thereby being beneficial to the uniformity of the film thickness in the overlapping area of ​​the second electrode plate C12 and the second sub-section 2412 and its periphery, thereby improving the flatness of the reflecting surface of the reflecting area FS.

[0170] Optionally, the orthographic projection of the third sub-portion 211 on the base substrate 200 may overlap with the orthographic projection of the second electrode plate C12 on the base substrate 200 , thereby further increasing the capacitance of the storage capacitor C.

[0171] In some specific embodiments, the third sub-section 211 includes a first structure 2111 and a second structure 2112 .

[0172] In an embodiment of the present disclosure, the first structure 2111 and the second structure 2112 may include a strip structure, and the dimensions of the first structure 2111 and the second structure 2112 in the first direction Y are larger than the dimensions in the second direction X. For example, referring to Figure 3, the first structure 2111 and the second structure 2112 are vertically extending strip structures.

[0173] The first sub-portion 2411, the second sub-portion 2412, and the orthographic projection of the active portion A on the base substrate 200 are arranged along the first direction Y. The orthographic projection of the first via V1 on the base substrate 200 is located on a side of the orthographic projection of the first sub-portion 2411 on the base substrate 200 that is close to the orthographic projection of the active portion A on the base substrate 200. In the second direction X, the orthographic projections of the first structure 2111 and the second structure 2112 on the base substrate 200 are located on opposite sides of the orthographic projection of the first via V1 on the base substrate 200.

[0174] The orthographic projection of a portion of the first structure 2111 close to the second structure 2112 on the base substrate 200 overlaps with the orthographic projection of the second electrode plate C12 on the base substrate 200, and the orthographic projection of a portion of the second structure 2112 facing away from the second structure 2112 on the base substrate 200 is spaced apart from the orthographic projection of the second electrode plate C12 on the base substrate 200. And / or, the orthographic projection of a portion of the second structure 2112 close to the first structure 2111 on the base substrate 200 overlaps with the orthographic projection of the second electrode plate C12 on the base substrate 200, and the orthographic projection of a portion of the second structure 2112 facing away from the first structure 2111 on the base substrate 200 is spaced apart from the orthographic projection of the second electrode plate C12 on the base substrate 200, and the second direction X intersects the first direction Y.

[0175] In an embodiment of the present disclosure, a plurality of gate lines GL are arranged along a first direction Y, and the nth subpixel PX is electrically connected to the yth gate line GL. In a direction from the y-1th gate line GL to the yth gate line GL, the first sub-portion 2411, the second sub-portion 2412, and the active portion A are arranged in sequence. A plurality of data lines DL are arranged along a second direction X, and the nth subpixel PX is electrically connected to the xth data line DL. In a direction from the xth data line DL to the x+1th data line DL, the first structure 2111, the first via V1, and the second structure 2112 are arranged in sequence.

[0176] In the embodiment of the present disclosure, for either the first structure 2111 or the second structure 2112, its orthographic projection on the base substrate 200 partially overlaps with the orthographic projection of the second sub-section 2412 on the base substrate 200. For example, in the thickness direction of the display substrate, the right side of the first structure 2111 overlaps with the second sub-section 2412, and the left side is spaced apart from the second sub-section 2412. The left side of the second structure 2112 overlaps with the second sub-section 2412, and the right side is spaced apart from the second sub-section 2412. In this way, the third sub-section 211 reduces the film step difference between the overlapping area of ​​the second electrode plate C12 and the second sub-section 2412 and the left and right sides thereof.

[0177] FIG14 schematically illustrates the spacing between the first structure, the second structure, the first via hole, and the first sub-section in an embodiment of the present disclosure.

[0178] 14 , in some specific embodiments, in the first direction Y, an orthographic projection of either the first structure 2111 or the second structure 2112 on the base substrate 200 has a first distance d1 from an orthographic projection of the first sub-portion 2411 on the base substrate 200, and an orthographic projection of the first via V1 on the base substrate 200 has a second distance d2 from the orthographic projection of the first sub-portion 2411 on the base substrate 200.

[0179] In the embodiment of the present disclosure, the first distance d1 may refer to the average distance between the orthographic projection of the first structure 2111 (the second structure 2112) on the base substrate 200 and the orthographic projection of the first sub-portion 2411 on the base substrate 200, and the second distance d2 may refer to the average distance between the orthographic projection of the first via V1 on the base substrate 200 and the orthographic projection of the first sub-portion 2411 on the base substrate 200. The first distance d1 is smaller than the second distance d2, so that the first structure 2111 (the second structure 2112) extends as far as possible toward the first sub-portion 2411, thereby increasing the coverage area of ​​the first structure 2111 (the second structure 2112), which helps to further improve film thickness uniformity.

[0180] 6 and 11 , in some embodiments, the transparent conductive portion 241 further includes a connecting sub-portion 2413 located between the first sub-portion 2411 and the second sub-portion 2412. The orthographic projection of the second electrode plate C12 on the base substrate 200 overlaps with the orthographic projection of the connecting sub-portion 2413 on the base substrate 200.

[0181] Optionally, the connecting sub-portion 2413 may be disposed around the first sub-portion 2411, and the orthographic projection of either the first structure 2111 or the second structure 2112 on the base substrate 200 is spaced apart from the orthographic projection of the connecting sub-portion 2413 on the base substrate 200. The second electrode plate C12 is closer to the first sub-portion 2411 than the first structure 2111 (the second structure 2112), and the second electrode plate C12 is close to the transmissive region TS. This facilitates alignment based on the second electrode plate C12 in subsequent steps.

[0182] 9 and 11 , in some specific embodiments, the orthographic projection of the third electrode plate C13 on the base substrate 200 overlaps with the orthographic projection of the fourth sub-portion 212 on the base substrate 200. This allows the first electrode plate C11, the second electrode plate C12, and the third electrode plate C13 to overlap, thereby reducing the space occupied by the three electrodes in the horizontal direction.

[0183] Optionally, in the first direction Y, the orthographic projection of the third electrode plate C13 on the base substrate 200 is located between the orthographic projection of the third sub-portion 2412 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200. In this way, the third electrode plate C13 is farther away from the second sub-portion 2412 than the third sub-portion 211, thereby maintaining a certain distance between the third electrode plate C13 and the second sub-portion 2412 to prevent a short circuit between the third electrode plate C13 and the second sub-portion 2412.

[0184] FIG15 schematically shows the spacing between the first electrode plate, the second electrode plate, the third electrode plate and the data line in an embodiment of the present disclosure.

[0185] 11 and 15 , in some specific embodiments, the display substrate further includes a plurality of data lines DL, the plurality of data lines DL being arranged along the second direction X, and the x-th data line DL being electrically connected to the n-th sub-pixel PX. In the n-th sub-pixel PX, in the second direction X, an orthographic projection of the third plate C13 on the substrate 200 and an orthographic projection of the x-th data line DL on the substrate 200 have a third spacing d3 therebetween, an orthographic projection of the third plate C13 on the substrate 200 and an orthographic projection of the x+1-th data line DL on the substrate 200 have a fourth spacing d4 therebetween, an orthographic projection of the second plate C12 on the substrate 200 and an orthographic projection of the x-th data line DL on the substrate 200 have a fifth spacing d5 therebetween, and a sixth spacing d6 therebetween, an orthographic projection of the second plate C12 on the substrate 200 and an orthographic projection of the x+1-th data line DL on the substrate 200 have a sixth spacing d6 therebetween.

[0186] It should be noted that the spacing mentioned above may refer to the average spacing or the minimum spacing between two structures. In the embodiments of the present disclosure, unless otherwise specified, the spacing is taken as an example to refer to the average spacing between two structures.

[0187] In the embodiment of the present disclosure, the third spacing d3 is smaller than the fifth spacing d5, and the fourth spacing d4 is smaller than the sixth spacing d6. In this way, the second plate C12 can maintain a safe distance from the xth data line DL and the x+1th data line DL to prevent the second plate C12 from shorting with the xth data line DL and the x+1th data line DL. In the second direction X, the left side of the third plate C13 is closer to the xth data line DL than the left side of the second plate C12, and the right side of the third plate C13 is closer to the x+1th data line DL than the right side of the second plate C12. This prevents the overlapping position of the second plate C12 and the third plate C13 from changing due to process fluctuations (the portion that should have overlapped becomes non-overlapping due to misalignment), which helps to ensure the uniformity of the storage capacitor C.

[0188] In some specific embodiments, in the nth sub-pixel PX, in the second direction X, there is a seventh distance d7 between the orthographic projection of the first electrode plate C11 on the substrate substrate 200 and the orthographic projection of the xth data line DL on the substrate substrate 200, and there is an eighth distance d8 between the orthographic projection of the first electrode plate C11 on the substrate substrate 200 and the orthographic projection of the x+1th data line DL on the substrate substrate 200.

[0189] In the embodiment of the present disclosure, the fifth spacing d5 is greater than the seventh spacing d7, and the sixth spacing d6 is greater than the eighth spacing d8. In the second direction X, the left side of the first electrode plate C11 is closer to the xth data line DL than the left side of the second electrode plate C12, and the right side of the first electrode plate C11 is closer to the x+1th data line DL than the right side of the second electrode plate C12. This prevents process fluctuations from causing the overlapping position of the first electrode plate C11 and the third electrode plate C13 to change (the portion that should have overlapped becomes non-overlapping due to misalignment), which helps to ensure the uniformity of the storage capacitor C.

[0190] Optionally, in the embodiments of the present disclosure, there is no restriction on the size relationship between the third spacing d3 and the seventh spacing d7, and the size relationship between the fourth spacing d4 and the eighth spacing d8. For example, the third spacing d3 can be less than or equal to the seventh spacing d7, and the fourth spacing d4 can be less than or equal to the eighth spacing d8, as long as these spacings can ensure that the parasitic capacitance generated by the first electrode C11 (third electrode C13) and the data line DL is within an acceptable range.

[0191] FIG16 schematically illustrates the spacing between the first electrode plate, the second electrode plate, the third electrode plate, and the active portion in an embodiment of the present disclosure.

[0192] 11 and 16 , in some specific embodiments, the orthographic projection of the third electrode plate C13 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200 are aligned along a first direction Y, and a ninth distance d9 is defined between the orthographic projection of the third electrode plate C13 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200 in the first direction Y. The orthographic projection of the second electrode plate C12 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200 are aligned along the first direction Y, and a tenth distance d10 is defined between the orthographic projection of the second electrode plate C12 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200 in the first direction Y. The first direction Y intersects the second direction X.

[0193] In the embodiment of the present disclosure, the ninth distance d9 is greater than the tenth distance d10. In the first direction Y, the lower side of the second electrode plate C12 is closer to the active portion A than the lower side of the third electrode plate C13. This prevents the area of ​​the third electrode plate C13 from being too large, thereby maintaining a safe distance between the third electrode plate C13 and the active portion A, thereby preventing the common voltage signal on the third electrode plate C13 from interfering with the characteristics of the switching transistor T2.

[0194] In some specific embodiments, the orthographic projection of the first electrode plate C11 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200 are arranged along the first direction Y, and in the first direction Y, there is an eleventh distance d11 between the orthographic projection of the first electrode plate C11 on the base substrate 200 and the orthographic projection of the active portion A on the base substrate 200.

[0195] In the embodiment of the present disclosure, the ninth distance d9 is smaller than the eleventh distance d11. In the first direction Y, the lower side of the second electrode plate C12 is closer to the active portion A than the lower side of the first plate. This prevents the area of ​​the first electrode plate C11 from being too large, facilitating sufficient spacing between the first electrode plate C11 and the active portion A to prevent the first electrode plate C11 from interfering with the characteristics of the switching transistor T2.

[0196] Optionally, the orthographic projection of the gate G of the switching transistor T2 on the base substrate 200 overlaps the orthographic projection of the active portion A on the base substrate 200, the orthographic projection of the first electrode plate C11 on the base substrate 200 and the orthographic projection of the gate G of the switching transistor T2 on the base substrate 200 are aligned along the first direction Y, and in the first direction Y, there is a twelfth distance between the orthographic projection of the first electrode plate C11 on the base substrate 200 and the orthographic projection of the gate G of the switching transistor T2 on the base substrate 200. The orthographic projection of the second electrode plate C12 on the base substrate 200 and the orthographic projection of the gate G of the switching transistor T2 on the base substrate 200 are aligned along the first direction Y, and in the first direction Y, there is a thirteenth distance between the orthographic projection of the second electrode plate C12 on the base substrate 200 and the orthographic projection of the gate G of the switching transistor T2 on the base substrate 200. The thirteenth distance is smaller than the twelfth distance, so that the first electrode plate C11 and the gate G of the switching transistor T2 can maintain a sufficient distance to prevent the first electrode plate C11 and the gate G of the switching transistor T2 from being short-circuited.

[0197] Referring to Figure 13 , in some specific embodiments, in addition to the aforementioned first insulating layer 250, a corresponding insulating layer may be provided between any two adjacent conductive layers. For example, a second insulating layer 280, also referred to as a gate insulating layer, may be provided between the first conductive layer 220 and the semiconductor layer 210. A planarizing layer 290 may be provided between the transparent conductive layer 240 and the second reflective conductive layer 260. Planarizing layer 290 may comprise an organic material and is used to reduce the step difference between the layers, thereby maintaining the second reflective conductive layer 260 as flat as possible.

[0198] The preparation process in the embodiments of the present disclosure is briefly described below.

[0199] First, a first conductive layer 220 is formed on a base substrate 200. The first conductive layer 220 includes a first electrode C11, the gate of the switching transistor T2, and a gate line GL. A second insulating layer 280 is then formed on the first conductive layer 220. A semiconductor layer 210 is then formed on the second insulating layer 280. The semiconductor layer 210 includes an active portion A. Furthermore, a second conductive layer 230 is formed on the semiconductor layer 210. The second conductive layer 230 includes a second electrode C12, the source and drain electrodes of the switching transistor T2, and a data line DL. Furthermore, a first insulating layer 250 is formed on the second conductive layer 230, and a first via V1 is formed therein. Subsequently, a transparent conductive layer 240 is formed on the first insulating layer 250. The transparent conductive layer 240 includes a third electrode C13 and a transparent conductive portion 241. The transparent conductive portion 241 is electrically connected to the second electrode C12 via the first via V1. Finally, a flat layer 290 and a second reflective conductive layer 260 are formed on the transparent conductive layer 240 . A large hole V2 is dug in the flat layer 290 corresponding to the transmission region TS. The large hole V2 of the second reflective conductive layer 260 overlaps the transparent conductive portion 241 .

[0200] According to the above embodiment, by adding the third electrode C13 in the transparent conductive layer 240 , the capacitance of the storage capacitor C can be increased without increasing the process steps, and the film step difference caused by the active portion A can be improved at the same time.

[0201] Figures 17 to 28 schematically illustrate plan views of sub-pixels in other embodiments of the present disclosure, and Figure 29 schematically illustrates cross-sectional views of sub-pixels in other embodiments of the present disclosure. Figure 17 schematically illustrates a plan view of a first conductive layer in other embodiments of the present disclosure, Figure 18 schematically illustrates a plan view of a semiconductor layer in other embodiments of the present disclosure, Figure 19 schematically illustrates a plan view of a second conductive layer in other embodiments of the present disclosure, Figure 20 schematically illustrates a plan view of a first insulating layer in other embodiments of the present disclosure, Figure 21 schematically illustrates a plan view of a transparent conductive layer in other embodiments of the present disclosure, Figure 22 schematically illustrates a plan view of a first reflective conductive layer in other embodiments of the present disclosure, Figure 23 schematically illustrates a plan view of a second reflective conductive layer in other embodiments of the present disclosure, and Figure 24 schematically illustrates a plan view of a first conductive layer and a semiconductor layer in other embodiments of the present disclosure. FIG25 schematically shows a plan view of the first conductive layer, the semiconductor layer, the second conductive layer and the first insulating layer in other embodiments of the present disclosure, FIG26 schematically shows a plan view of the first conductive layer, the semiconductor layer, the second conductive layer, the first insulating layer and the first reflective conductive layer in other embodiments of the present disclosure, FIG27 schematically shows a plan view of the first conductive layer, the semiconductor layer, the second conductive layer, the first insulating layer, the first reflective conductive layer and the transparent conductive layer in other embodiments of the present disclosure, and FIG28 schematically shows a plan view of the first conductive layer, the semiconductor layer, the second conductive layer, the first insulating layer, the first reflective conductive layer, the transparent conductive layer and the second reflective conductive layer in other embodiments of the present disclosure.

[0202] 17 to 29 , the following describes a solution in which the third electrode plate C13 is located in the first reflective conductive layer in an embodiment of the present disclosure.

[0203] In some specific embodiments, the display substrate further includes a first reflective conductive layer 270, which is located on a side of the second conductive layer 230 facing away from the base substrate 200. The third electrode C13 is located in the first reflective conductive layer 270. The display substrate further includes a plurality of data lines DL and a plurality of gate lines GL. The plurality of data lines DL are arranged along a second direction X, and the plurality of gate lines GL are arranged along a first direction Y, with the first direction Y intersecting the second direction X. The xth data line DL is electrically connected to the nth sub-pixel PX, and the yth gate line GL is electrically connected to the nth sub-pixel PX. The orthographic projection of at least one of the xth data line DL, the x+1th data line DL, the y-1th gate line GL, and the yth gate line GL on the base substrate 200 overlaps with the orthographic projection of the third electrode C13 in the nth sub-pixel PX on the base substrate 200. x and y are both positive integers.

[0204] In an embodiment of the present disclosure, the first reflective conductive layer 270 comprises a light-reflecting metal material, such as silver, copper, aluminum, or alloys thereof. Because the first reflective conductive layer 270 comprises a light-reflecting metal material, the third electrode C13 disposed within the first reflective conductive layer 270 is capable of reflecting light. Consequently, in an embodiment of the present disclosure, the third electrode C13 can overlap with at least one of the xth data line DL, the x+1th data line DL, the y-1th gate line GL, and the yth gate line GL, thereby replacing the black matrix originally provided in the color filter substrate to provide light shielding, thereby preventing light leakage during transmissive display. Furthermore, using the third electrode C13, the data lines DL, and the gate lines GL in place of the black matrix can increase the amount of light entering during reflective display, while also increasing the reflective area, thereby enhancing the display quality during reflective display. For example, in the thickness direction of the display substrate, the third electrode C13 overlaps each of the xth data line DL, the x+1th data line DL, the y-1th gate line GL, and the yth gate line GL, thereby covering as much of the reflective area FS as possible.

[0205] Furthermore, because the third electrode plate C13 can reflect light, the line widths of the gate lines GL and data lines DL can be reduced in the embodiment of the present disclosure compared to the aforementioned embodiment, thereby reducing the space occupied by the gate lines GL and data lines DL. This facilitates increasing the size of each structure in the sub-pixel PX. For example, in the embodiment of the present disclosure, the line width of the gate lines GL can be set to 3-6 μm, and the line width of the data lines DL can be set to 2-4 μm. After reducing the line widths of the gate lines GL and data lines DL, the size of the third electrode plate C13 in the first direction Y and the second direction X can be increased, thereby ensuring that the third electrode plate C13 in the nth sub-pixel PX always overlaps with each of the xth data line DL, the x+1th data line DL, the y-1th gate line GL, and the yth gate line GL in the thickness direction of the display substrate, thereby ensuring that no light leakage occurs during transmissive display.

[0206] Optionally, the third plates C13 in adjacent sub-pixels PX may be formed as an integral structure.

[0207] In some specific embodiments, the display substrate further includes a transparent conductive layer 240 and a first insulating layer 250. The transparent conductive layer 240 is located on a side of the second conductive layer 230 facing away from the base substrate 200, and the first insulating layer 250 is located between the second conductive layer 230 and the transparent conductive layer 240. The nth sub-pixel PX further includes a transparent conductive portion 241, which is located in the transparent conductive layer 240. The transparent conductive portion 241 includes a first sub-portion 2411 and a second sub-portion 2412, and the first sub-portion 2411 and the second sub-portion 2412 are electrically connected. A first via hole V1 is provided on the first insulating layer 250 and passes through the first insulating layer 250. The first sub-portion 2411 is located in the transmission area TS, and the second sub-portion 2412 is located in the reflection area FS. The orthographic projection of the second sub-portion 2412 on the base substrate 200 overlaps with the orthographic projection of the second electrode plate C12 on the base substrate 200, and in the overlapping area, the second sub-portion 2412 and the second electrode plate C12 are electrically connected through the first via hole V1.

[0208] Unlike the previous embodiment, in this embodiment, the third electrode C13 is no longer provided in the transparent conductive layer 240. However, the transparent conductive layer 240 still has a transparent conductive portion 241, which serves as the pixel electrode in the transmissive region TS. The transparent conductive portion 241 can have the same morphology design as the previous embodiment, or a different morphology design.

[0209] For example, in this embodiment, due to the reduced width of the data lines DL, the morphology design of the transmissive region TS is more flexible. For example, the transmissive region TS can be a vertically extending strip, as in the aforementioned embodiment. Alternatively, without changing the area of ​​the transmissive region TS, the transmissive region TS can be a horizontally extending strip. Alternatively, without changing the area of ​​the transmissive region TS, the transmissive region TS can be a square. Accordingly, in this embodiment, the first sub-portion 2411 can be a vertical strip, a horizontal strip, a square, or the like.

[0210] In some specific embodiments, the second sub-portion 2412 may have the same morphology design as the aforementioned embodiment, or may have a different morphology design.

[0211] For example, the first sub-portion 2411 adopts the same morphological design as the aforementioned embodiment. At the same time, the first electrode C11 adopts the design of the aforementioned embodiment, that is, the first electrode C11 includes the aforementioned third sub-portion 211, and the third sub-portion 211 extends to the periphery of the overlapping area between the second electrode C12 and the transparent conductive portion 241 to improve the film thickness step difference between the overlapping area and its periphery.

[0212] Alternatively, the first sub-portion 2411 and the second sub-portion 2412 can be made substantially the same size in the second direction X. In this case, the third sub-portion 211 on the first electrode plate C11 can be eliminated, and the second sub-portion 2412 can be extended to the periphery of the overlapping region between the second electrode plate C12 and the transparent conductive portion 241 to improve the thickness step difference between the overlapping region and its periphery. Optionally, the third electrode plate C13 can cover the portion of the second sub-portion 2412 extending to the periphery of the overlapping region to prevent parasitic capacitance from being generated between the second sub-portion 2412 and the data line DL.

[0213] The third electrode plate C13 is provided with a first opening K1 and a second opening K2. The orthographic projection of the first opening K1 on the base substrate 200 overlaps the orthographic projection of the transmissive region TS on the base substrate 200, while the orthographic projection of the second opening K2 on the base substrate 200 overlaps the orthographic projection of the first via V1 on the base substrate 200. Thus, the first opening K1 allows the third electrode plate C13 to avoid the transmissive region TS of the sub-pixel PX. The second opening K2 exposes the first via V1, allowing the subsequently formed transparent conductive portion 241 to be electrically connected to the second electrode plate C12 through the second opening K2 and the first via V1.

[0214] Optionally, the first opening K1 and the second opening K2 are formed into an integral structure. In addition to exposing the first via hole V1, the second opening K2 can also expose the second electrode plate C12 around the first via hole V1, thereby maintaining a certain safe distance between the third electrode plate C13 and the first via hole V1 to avoid accidental damage to the third electrode plate C13 when etching the first via hole V1.

[0215] Optionally, the corners of the first opening K1 and the second opening K2 may be non-right angle corners, for example, arc-shaped corner areas, etc., so as to reduce stress concentration at the corners.

[0216] Optionally, the orthographic projection of the second electrode plate C12 on the base substrate 200 covers the orthographic projection of the second opening K2 on the base substrate 200. For example, the left side of the second opening K2 is located to the right of the left side of the second electrode plate C12, and the right side of the second opening K2 is located to the left of the right side of the second electrode plate C12.

[0217] In some specific embodiments, the third electrode plate C13 is further provided with a third opening K3. The orthographic projection of the third opening K3 on the base substrate 200 overlaps the orthographic projection of the active portion A on the base substrate 200. In the second direction X, the first opening K1 has a first dimension d21, the second opening K2 has a second dimension d22, and the third opening K3 has a third dimension d23. The third dimension d23 is smaller than the first dimension d21 and larger than the second dimension d22.

[0218] In an embodiment of the present disclosure, the pattern of the third openings K3 may be substantially the same as the pattern of the active portion A.

[0219] Optionally, the orthographic projection of the gate of the switching transistor T2 on the base substrate 200 covers the orthographic projection of the third opening K3 on the base substrate 200. In this way, the third electrode plate C13 can avoid the active portion A through the third opening K3 to prevent the third electrode plate C13 from affecting the characteristics of the switching transistor T2. At the same time, the area of ​​the third opening K3 is not too large, so that the third electrode plate C13 covers as much of the reflection area FS as possible, thereby improving the film layer step difference caused by the active portion A as much as possible.

[0220] In some specific embodiments, the orthographic projection of the first electrode plate C11 on the base substrate 200 overlaps with the orthographic projection of the second sub-portion 2412 on the base substrate 200 , and the orthographic projection of the first electrode plate C11 on the base substrate 200 is located on a side of the orthographic projection of the first via V1 on the base substrate 200 away from the first sub-portion 2411 .

[0221] In the disclosed embodiment, the first electrode plate C11 is closer to the active portion A than the first via V1, and is located below the first via V1. Unlike the previous embodiment, this embodiment eliminates the third sub-portion 211 on the first electrode plate C11. The second sub-portion 2412 is used to improve the aforementioned film thickness step difference. The entire first electrode plate C11 is located on the side of the first via V1 closest to the active portion A.

[0222] In some specific embodiments, the display substrate further includes a second reflective conductive layer 260, which is located on a side of the first reflective conductive layer 270 facing away from the base substrate 200. The nth sub-pixel PX further includes a reflective portion 261, which is located in the second reflective conductive layer 260. The orthographic projection of the reflective portion 261 on the base substrate 200 covers the orthographic projection of the second opening K2 and the third opening K3 on the base substrate 200. The reflective portion 261 is further provided with a fourth opening K4, whose orthographic projection on the base substrate 200 covers the transmissive region TS. The reflective portion 261 is electrically connected to the first sub-portion 2411 at the edge of the fourth opening K4.

[0223] In the embodiment of the present disclosure, the second reflective conductive layer 260 includes a reflective metal material. The reflective portion 261 and the third electrode C13 can form complementary patterns. That is, in the reflective region FS, the portion exposed by the third electrode C13 can be covered by the reflective portion 261, while the portion exposed by the third electrode C13 is covered by the reflective portion 261, thereby increasing the reflective area.

[0224] In the embodiment of the present disclosure, the orthographic projection of the first opening K1 on the base substrate 200 covers the orthographic projection of the fourth opening K4 on the base substrate 200 , so that the range of the transmission region TS can be defined by the fourth opening K4 .

[0225] In some specific embodiments, the dimension of the fourth opening K4 in the second direction X is greater than or equal to the dimension of the fourth opening K4 in the first direction Y. The fourth opening K4 is a horizontal strip structure. Alternatively, the fourth opening K4 is a square. Compared to a strip structure, a square-shaped fourth opening K4 can better improve light leakage during transmissive display.

[0226] Referring to Figure 29 , in some specific embodiments, in addition to the aforementioned first insulating layer 250, a corresponding insulating layer may be provided between two adjacent conductive layers. For example, a second insulating layer 280, also referred to as a gate insulating layer, may be provided between the first conductive layer 220 and the semiconductor layer 210. A planarizing layer 290 may be provided between the transparent conductive layer 240 and the second reflective conductive layer 260. The planarizing layer 290 may comprise an organic material and is used to reduce the step difference between the film layers, thereby maintaining the second reflective conductive layer 260 as flat as possible.

[0227] The first insulating layer 250 may include a composite structure of two insulating film layers. For example, the first insulating layer 250 includes a first spacer layer 251 and a second spacer layer 252. The first spacer layer 251 is located between the first reflective conductive layer 270 and the second conductive layer 230. The second spacer layer 252 is located between the first reflective conductive layer 270 and the transparent conductive layer 240. The first via V1 passes through the first spacer layer 251 and the second spacer layer 252.

[0228] The preparation process in the embodiments of the present disclosure is briefly described below.

[0229] First, a first conductive layer 220 is formed on a base substrate 200. The first conductive layer 220 includes a first electrode C11, the gate electrode of the switching transistor T2, and a gate line GL. Compared to the previous embodiment, the width of the gate line GL is reduced. Next, a second insulating layer 280 is formed on the first conductive layer 220. A semiconductor layer 210 is formed on the second insulating layer 280. The semiconductor layer 210 includes an active portion A. Furthermore, a second conductive layer 230 is formed on the semiconductor layer 210. The second conductive layer 230 includes a second electrode C12, the source and drain electrodes of the switching transistor T2, and a data line DL. Compared to the previous embodiment, the width of the data line DL is reduced. Furthermore, a first spacer layer 251 is formed on the second conductive layer 230. Subsequently, a first reflective conductive layer 270 is formed on the first spacer layer 251. The first reflective conductive layer 270 includes a third electrode C13. Next, a second spacer layer 252 is formed on the first reflective conductive layer 270, and a first via hole V1 is formed through the first and second spacer layers 251 and 252. Subsequently, a transparent conductive layer 240 is formed on the second spacer layer 252. The transparent conductive layer 240 includes a transparent conductive portion 241, which is electrically connected to the second electrode plate C12 via the first via hole V1. Finally, a planarizing layer 290 and a second reflective conductive layer 260 are formed on the transparent conductive layer 240. A large hole V2 is formed in the planarizing layer 290 corresponding to the transmissive region TS. The second reflective conductive layer 260 overlaps the transparent conductive portion 241 at the location of the large hole V2.

[0230] In the embodiment of the present disclosure, the third electrode C13 is arranged in the first reflective conductive layer 270. Compared with the solution of setting it in the transparent conductive layer 240, the size of the third electrode C13 is not limited by the transparent conductive part 241. Therefore, the design is more flexible and the coverage area can be larger. In addition to increasing the capacitance of the storage capacitor C and improving the film thickness step difference, the reflection area can also be increased to improve the reflection effect.

[0231] The following describes a general design in the embodiments of the present disclosure that can be applied to each of the above embodiments.

[0232] With reference to FIG. 2 and FIG. 11 , in some specific embodiments, the display substrate further includes a display area and a peripheral area NA at least partially surrounding the display area, with multiple sub-pixels PX located in the display area. The display substrate further includes a plurality of first connection lines L1, a plurality of second connection lines L2, and at least one common signal line VCOM. The plurality of first connection lines L1 are arranged along a first direction Y, and the plurality of second connection lines L2 are arranged along the first direction Y. In the nth sub-pixel PX, the third electrode C13 is electrically connected to the i-th first connection line L1, the first electrode C11 is electrically connected to the j-th second connection line L2, and the i-th first connection line L1 and the j-th second connection line L2 are electrically connected to the common signal line VCOM in the peripheral area NA. Wherein, i and j are both positive integers.

[0233] In an embodiment of the present disclosure, the common signal line VCOM is located in the peripheral area NA. For example, the common signal line VCOM is at least partially disposed around the display area AA. Optionally, the common signal line VCOM is located in the first conductive layer 220 .

[0234] Optionally, a gate driving circuit 21 is provided in the peripheral area NA, and the orthographic projection of the common signal line VCOM on the base substrate 200 is located between the orthographic projection of the display area AA on the base substrate 200 and the orthographic projection of the gate driving circuit 21 on the base substrate 200 .

[0235] The first connection line L1 and the second connection line L2 extend along the second direction X, and the common signal line VCOM intersects the first connection line L1 (or the second connection line L2) in the peripheral area NA. At the intersection, the common signal line VCOM and the first connection line L1 (or the second connection line L2) can be connected through the connection hole.

[0236] Optionally, when the third electrode plate C13 is located in the first reflective conductive layer 270, the third electrode plates C13 in the plurality of sub-pixels PX can be formed into an integrated structure. In addition to being electrically connected to the common signal line VCOM through the first connection line L1 extending along the second direction X, the third electrode plate C13 can also be electrically connected to the common signal line VCOM through a third connection line extending along the first direction Y.

[0237] In some specific embodiments, in the reflective region FS, the orthographic projection of the active portion A on the base substrate 200 and the orthographic projection of the third electrode plate C13 on the base substrate 200 form a complementary pattern.

[0238] In the embodiment of the present disclosure, the orthographic projections of the active portion A and the third electrode plate C13 on the base substrate 200 form complementary patterns in the reflection area FS, which may mean that except for the area where the reflection area FS must be exposed (such as the first via V1 and its surroundings and the surroundings of the active portion A), the orthographic projections of the active portion A and the third electrode plate C13 on the base substrate 200 can fill the entire reflection area FS, thereby maximizing the coverage area of ​​the third electrode plate C13, so as to better improve the film thickness step difference problem caused by the active portion A.

[0239] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above, having a display area AA and a peripheral area NA and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0240] Figures 30 and 31 schematically illustrate cross-sectional views of a display panel according to an embodiment of the present disclosure. Figure 30 illustrates a display panel with the third electrode plate located in the transparent conductive layer, while Figure 31 illustrates a display panel with the third electrode plate located in the first reflective conductive layer. Figure 32 schematically illustrates a plan view of a color resist according to an embodiment of the present disclosure.

[0241] With reference to Figures 30 to 32 , the display panel in the embodiment of the present disclosure includes a display substrate 400 and an opposing substrate 300. The display substrate 400 includes the display substrate 400 described in the aforementioned embodiment. The opposing substrate 300 includes a plurality of color resists SR, with the mth color resist SR being provided corresponding to the nth subpixel PX. The mth color resist SR includes a first region Q1, a second region Q2, and a third region Q3. The orthographic projection of the first region Q1 on the base substrate 200 overlaps the orthographic projection of the transmissive region TS of the nth subpixel PX on the base substrate 200. The orthographic projection of the third region Q3 on the base substrate 200 overlaps the orthographic projection of the active portion A of the nth subpixel PX on the base substrate 200. In a first direction Y, the second region Q2 is located between the first region Q1 and the third region Q3. In a second direction X, the size of the second region Q2 is smaller than or equal to the size of the third region Q3, and the second direction X intersects the first direction Y.

[0242] Optionally, the first direction Y may include an extension direction of the data line DL on the display substrate, and the second direction X includes an extension direction of the gate line GL on the display substrate. For example, referring to FIG. 2 , the first direction Y may be a vertical direction in FIG. 2 , and the second direction X may be a horizontal direction in FIG. 2 , that is, the first direction and the second direction intersect.

[0243] In the embodiments of the present disclosure, each color resist SR allows light of one color to pass through, and different color resists SR allow different light to pass through. For example, multiple color resists SR allow red light, green light, and blue light to pass through, respectively. Multiple color resists SR can be set in a one-to-one correspondence with multiple sub-pixels PX, that is, each color resist SR is set corresponding to a sub-pixel PX, and different sub-pixels PX are set corresponding to different color resists SR. The nth sub-pixel PX can refer to any sub-pixel PX among the multiple sub-pixels PX, and the mth color resist SR is the color resist SR set corresponding to the sub-pixel PX.

[0244] Referring to Figure 32, the first area Q1 covers the transmission area TS, the third area Q3 covers the switching transistor T2, and the second area Q2 is between the first area Q1 and the third area Q3. The second area Q2 is narrower than the third area Q3, thereby increasing the amount of ambient light entering during reflective display, thereby improving the reflective display effect.

[0245] In some specific embodiments, the plurality of color resists SR include a first color resist SR1, a second color resist SR2, and a third color resist SR3. The first color resist SR1, the second color resist SR2, and the third color resist SR3 have different colors. Furthermore, the orthographic projections of the first color resist SR1, the second color resist SR2, and the third color resist SR3 on the base substrate 200 are spaced apart from each other to prevent optical crosstalk between the plurality of color resists SR. For example, the first color resist SR1 is a red color resist, the second color resist SR2 is a green color resist, and the third color resist SR3 is a blue color resist.

[0246] In the second direction X, the second area Q2 of the first color resist SR1 has a fourth dimension d31, the second area Q2 of the second color resist has a fifth dimension d32, and the second area Q2 of the third color resist has a sixth dimension d33. The fifth dimension d32 is greater than the fourth dimension d31 and smaller than the sixth dimension d33. For example, the second area Q2 of the first color resist SR1 is narrower than the second area Q2 of the second color resist SR2, and the second area Q2 of the second color resist is narrower than the second area Q2 of the third color resist SR3.

[0247] In the embodiment of the present disclosure, the sizes of the second regions Q2 of different color resists SR are different, so as to meet the requirements of the amount of light entering different colors.

[0248] It should be noted that, in the embodiment of the present disclosure, the size relationship of the second region Q2 between the plurality of color resists SR is not limited to the above example, and can be determined according to actual needs, which will not be listed here one by one.

[0249] In some specific embodiments, the display panel further includes a liquid crystal layer LC, the liquid crystal layer LC includes a plurality of dimming zones TG, and the zth dimming zone TG is disposed corresponding to the nth sub-pixel PX.

[0250] The zth dimming area TG includes a first dimming sub-area TG1 and a second dimming sub-area TG2. The orthographic projection of the first dimming sub-area TG1 on the substrate 200 covers the orthographic projection of the transmission area TS of the nth sub-pixel PX on the substrate 200. The orthographic projection of the second dimming sub-area TG2 on the substrate 200 covers the orthographic projection of the reflection area FS of the nth sub-pixel PX on the substrate 200. The box thickness h1 of the first dimming sub-area TG1 is greater than the box thickness h2 of the second dimming sub-area TG2.

[0251] In the embodiment of the present disclosure, the ratio of the cell thickness h1 of the first dimming sub-zone TG1 to the cell thickness h2 of the second dimming sub-zone TG2 can be set to 2:1. Thus, during reflective display, the optical path of ambient light in the second dimming sub-zone TG2 is the first optical path, while during transmissive display, the optical path of light emitted by the backlight module in the first dimming sub-zone TG1 is the second optical path. The first optical path and the second optical path are equal, thereby achieving optimal transmissive and reflective display effects.

[0252] In the embodiment of the present disclosure, the color filter substrate no longer has a black matrix, and the black matrix is ​​replaced by the reflective portion 261, the third electrode C13, the data line DL and the gate line GL in the display substrate 400 to achieve the light shielding effect. For details, please refer to the above embodiment and will not be repeated here.

[0253] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0254] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate and display panel. For details, please refer to the above description and will not be repeated here.

Claims

1. A display substrate, wherein: include: A substrate, a semiconductor layer, a first conductive layer and a second conductive layer, wherein the second conductive layer is located on a side of the first conductive layer away from the substrate; The display substrate further comprises a plurality of sub-pixels, wherein the nth sub-pixel comprises: a transmission area and a reflection area outside the transmission area; The nth sub-pixel further includes: a storage capacitor and a switch transistor arranged in the reflective area; The storage capacitor comprises: a first plate, a second plate and a third plate, wherein the first plate is located in the first conductive layer, the second plate is located in the second conductive layer, the third plate is located on a side of the second conductive layer away from the substrate, the first plate is electrically connected to the third plate, the second plate is electrically connected to the switch transistor, and each of the first plate and the second plate is insulated and spaced apart from the second plate; The switch transistor includes an active portion, wherein the active portion is disposed in the semiconductor layer; The orthographic projection of the first electrode plate on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate, and the orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the third electrode plate on the base substrate; The orthographic projection of the active portion on the base substrate is spaced apart from the orthographic projection of the third electrode plate on the base substrate, and the thickness of the active portion is substantially the same as the thickness of the third electrode plate; Said n is a positive integer.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a transparent conductive layer and a first insulating layer, wherein the transparent conductive layer is located on a side of the second conductive layer away from the base substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer; The third electrode is located in the transparent conductive layer, and the nth sub-pixel further includes a transparent conductive portion, which is located in the transparent conductive layer and is insulated from the third electrode; Wherein, the transparent conductive part includes a first sub-part and a second sub-part, and the first sub-part and the second sub-part are electrically connected; A first via hole penetrating through the first insulating layer is provided on the first insulating layer, the first sub-portion is located in the transmission area, the second sub-portion is located in the reflection area, an orthographic projection of the second sub-portion on the base substrate overlaps with an orthographic projection of the second electrode plate on the base substrate, and in the overlapping area, the second sub-portion and the second electrode plate are electrically connected through the first via hole; The first electrode plate includes a third sub-portion, the orthographic projection of the third sub-portion on the substrate at least partially surrounds the orthographic projection of the first via on the substrate, and a part of the orthographic projection of the third sub-portion on the substrate overlaps with the orthographic projection of the second sub-portion on the substrate, and another part overlaps with the orthographic projection of the second sub-portion on the substrate and is arranged at an interval.

3. The display substrate according to claim 2, wherein: The third subsection includes: a first structure and a second structure; The orthographic projections of the first sub-portion, the second sub-portion and the active portion on the base substrate are arranged along a first direction, and in a second direction, the orthographic projections of the first structure and the second structure on the base substrate are respectively located on two opposite sides of the orthographic projection of the first via hole on the base substrate; The orthographic projection of a portion of the first structure close to the second structure on the substrate overlaps with the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of a portion of the first structure away from the second structure on the substrate is spaced from the orthographic projection of the second sub-portion on the substrate; and / or, The orthographic projection of a portion of the second structure close to the first structure on the substrate overlaps with the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of a portion of the second structure away from the first structure on the substrate is spaced from the orthographic projection of the second sub-portion on the substrate; The second direction intersects with the first direction.

4. The display substrate according to claim 3, wherein: In the first direction, an orthographic projection of any one of the first structure and the second structure on the substrate has a first distance from an orthographic projection of the first sub-portion on the substrate, and an orthographic projection of the first via hole on the substrate has a second distance from an orthographic projection of the first sub-portion on the substrate; The first spacing is smaller than the second spacing.

5. The display substrate according to claim 2, wherein: The transparent conductive portion further includes a connecting sub-portion located between the first sub-portion and the second sub-portion; The orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the connecting sub-portion on the base substrate.

6. The display substrate according to claim 3, wherein: The first electrode plate further includes a fourth sub-portion, wherein in the first direction, an orthographic projection of the fourth sub-portion on the substrate substrate is located between an orthographic projection of the second sub-portion on the substrate substrate and an orthographic projection of the active portion on the substrate substrate, and an orthographic projection of the third sub-portion on the substrate substrate is located on a side of the orthographic projection of the fourth sub-portion on the substrate substrate close to the orthographic projection of the second sub-portion on the substrate substrate; An orthographic projection of the third electrode plate on the base substrate overlaps with an orthographic projection of the fourth sub-portion on the base substrate.

7. The display substrate according to claim 1, wherein: The display substrate further comprises a plurality of data lines, the plurality of data lines are arranged along the second direction, and the xth data line is electrically connected to the nth sub-pixel; In the nth sub-pixel, in the second direction, the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the xth data line on the substrate have a third spacing, the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the x+1th data line on the substrate have a fourth spacing, the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the xth data line on the substrate have a fifth spacing, and the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the x+1th data line on the substrate have a sixth spacing; The third interval is smaller than the fifth interval, and the fourth interval is smaller than the sixth interval; Both x and y are positive integers.

8. The display substrate according to claim 7, wherein: In the nth sub-pixel, in the second direction, there is a seventh spacing between the orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the xth data line on the base substrate, and there is an eighth spacing between the orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the x+1th data line on the base substrate; The fifth interval is greater than the seventh interval, and the sixth interval is greater than the eighth interval.

9. The display substrate according to claim 7 or 8, wherein: The orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate are arranged along a first direction, and in the first direction, there is a ninth spacing between the orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate; The orthographic projection of the second electrode plate on the base substrate is parallel to the projection of the active portion on the base substrate. The orthographic projections of the second electrode plate and the active portion are arranged along the first direction, and in the first direction, there is a tenth distance between the orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate; The first direction intersects with the second direction, and the ninth interval is greater than the tenth interval.

10. The display substrate according to claim 9, wherein: The orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate are arranged along the first direction, and in the first direction, there is an eleventh spacing between the orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the active portion on the base substrate, and the ninth spacing is smaller than the eleventh spacing.

11. The display substrate according to claim 2, wherein: The display substrate further comprises a second reflective conductive layer, and the second reflective conductive layer is located on a side of the transparent conductive layer away from the base substrate; The nth sub-pixel further includes a reflective portion, the reflective portion is located in the second reflective conductive layer, and a fourth opening is provided on the reflective portion; The orthographic projection of the reflective portion on the base substrate at least covers the orthographic projections of the active portion and the third electrode plate on the base substrate, and the orthographic projection of the fourth opening on the base substrate covers the orthographic projection of the first sub-portion on the base substrate.

12. The display substrate according to claim 1, wherein: The display substrate further comprises a first reflective conductive layer, the first reflective conductive layer is located on a side of the second conductive layer away from the base substrate, and the third electrode plate is located in the first reflective conductive layer; The display substrate further comprises a plurality of data lines and a plurality of gate lines, wherein the plurality of data lines are arranged along a second direction, and the plurality of gate lines are arranged along a first direction, wherein the first direction intersects with the second direction; The xth data line is electrically connected to the nth sub-pixel, and the yth gate line is electrically connected to the nth sub-pixel; The orthographic projection of at least one of the x-th data line, the x+1-th data line, the y-1-th gate line and the y-th gate line on the base substrate overlaps with the orthographic projection of the third electrode in the n-th sub-pixel on the base substrate; Both x and y are positive integers.

13. The display substrate according to claim 12, wherein: The display substrate further comprises a transparent conductive layer and a first insulating layer, wherein the transparent conductive layer is located on a side of the first reflective conductive layer away from the base substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer; The nth sub-pixel further includes a transparent conductive portion, and the transparent conductive portion is located in the transparent conductive layer; Wherein, the transparent conductive part includes a first sub-part and a second sub-part, and the first sub-part and the second sub-part are electrically connected; A first via hole penetrating through the first insulating layer is provided on the first insulating layer, the first sub-portion is located in the transmission area, the second sub-portion is located in the reflection area, an orthographic projection of the second sub-portion on the base substrate overlaps with an orthographic projection of the second electrode plate on the base substrate, and in the overlapping area, the second sub-portion and the second electrode plate are electrically connected through the first via hole; The third electrode plate is provided with a first opening and a second opening, wherein the orthographic projection of the first opening on the base substrate covers the orthographic projection of the transmission area on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first via hole on the base substrate.

14. The display substrate according to claim 13, wherein: The third electrode plate is further provided with a third opening, and the orthographic projection of the third opening on the base substrate covers the orthographic projection of the active portion on the base substrate; In the second direction, the first opening has a first size, the second opening has a second size, and the third opening has a third size; The third size is smaller than the first size and larger than the second size.

15. The display substrate according to claim 13, wherein: The orthographic projection of the first electrode plate on the base substrate overlaps with the orthographic projection of the second sub-portion on the base substrate, and the orthographic projection of the first electrode plate on the base substrate is located on a side of the orthographic projection of the first via on the base substrate away from the first sub-portion.

16. The display substrate according to claim 13, wherein: The first sub-portion and the second sub-portion have substantially the same size in the second direction.

17. The display substrate according to claim 14, wherein: The display substrate further comprises a second reflective conductive layer, wherein the second reflective conductive layer is located on a side of the first reflective conductive layer away from the base substrate; The nth sub-pixel further includes a reflective portion, the reflective portion is located in the second reflective conductive layer, the orthographic projection of the reflective portion on the base substrate covers the second opening and the orthographic projection of the third opening on the base substrate, and a fourth opening is further provided on the reflective portion, the orthographic projection of the fourth opening on the base substrate covers the transmission area; The reflective portion is electrically connected to the first sub-portion in an edge region of the fourth opening.

18. The display substrate according to claim 17, wherein: A size of the fourth opening in the second direction is greater than or equal to a size of the fourth opening in the first direction.

19. The display substrate according to any one of claims 1 to 18, wherein: The display substrate further comprises a display area and the peripheral area at least partially surrounding the display area, and the plurality of sub-pixels are located in the display area; The display substrate further includes a plurality of first connection lines, a plurality of second connection lines and at least one common signal line, the plurality of first connection lines are arranged along a first direction, and the plurality of second connection lines are arranged along the first direction; In the nth sub-pixel, the third electrode plate is electrically connected to the i-th first connecting line, the first electrode plate is electrically connected to the j-th second connecting line, and the i-th first connecting line and the j-th second connecting line are electrically connected to the common signal line in the peripheral area; The i and the j are both positive integers.

20. The display substrate according to any one of claims 1 to 18, wherein: In the reflective region, an orthographic projection of the active portion on the base substrate and an orthographic projection of the third electrode plate on the base substrate form a complementary pattern.

21. A display panel, wherein: A display substrate and an opposing substrate are included, wherein the display substrate includes the display substrate according to any one of claims 1 to 20, and the opposing substrate includes a plurality of color resists, wherein the mth color resist is arranged corresponding to the nth sub-pixel; The m-th color resist includes a first area, a second area and a third area, wherein the first area is The orthographic projection on the substrate covers the orthographic projection of the transmission area of ​​the nth sub-pixel on the substrate, the orthographic projection of the third area on the substrate covers the orthographic projection of the active part of the nth sub-pixel on the substrate, and in the first direction, the second area is located between the first area and the third area; In a second direction, the size of the second area is smaller than or equal to the size of the third area, and the second direction intersects the first direction; The m is a positive integer.

22. The display panel according to claim 21, wherein: The plurality of color resists include a first color resist, a second color resist and a third color resist, the first color resist, the second color resist and the third color resist have different colors, and the orthographic projection of the first color resist on the base substrate, the orthographic projection of the second color resist on the base substrate and the orthographic projection of the third color resist on the base substrate are arranged spaced from each other; In the second direction, the second area of ​​the first color resist has a fourth size, the second area of ​​the second color resist has a fifth size, and the second area of ​​the third color resist has a sixth size, and the fifth size is larger than the fourth size and smaller than the sixth size.

23. The display panel according to claim 21, wherein: The display panel further includes a liquid crystal layer, the liquid crystal layer includes a plurality of dimming areas, and the zth dimming area is arranged corresponding to the nth sub-pixel; The zth dimming area includes a first dimming sub-area and a second dimming sub-area, the orthographic projection of the first dimming sub-area on the substrate covers the orthographic projection of the transmission area of ​​the nth sub-pixel on the substrate, the orthographic projection of the second dimming sub-area on the substrate covers the orthographic projection of the reflection area of ​​the nth sub-pixel on the substrate, and the box thickness of the first dimming sub-area is greater than the box thickness of the second dimming sub-area.

24. A display device, wherein: Comprising the display panel as claimed in any one of claims 21 to 23.

Images