Display device

Abstract

There is provided a display device including: a first electrode and a second electrode disposed on a substrate so as to be spaced apart from each other; a first insulating layer disposed on the substrate and overlapping the first electrode and the second electrode; a third electrode disposed on the first insulating layer and overlapping the first electrode and the second electrode; a second insulating layer disposed on the first insulating layer and overlapping the third electrode; a fourth electrode disposed on the second insulating layer, the fourth electrode overlapping the third electrode, and the fourth electrode being electrically connected to the first electrode; a third insulating layer disposed on the second insulating layer and overlapping the fourth electrode; and a fifth electrode disposed on the third insulating layer, the fifth electrode overlapping the fourth electrode, and the fifth electrode being electrically connected to the third electrode.

Description

Technical Field

[0001] One or more embodiments relate to a display device. Background Art

[0002] The display device visually displays data. The display device can be used as a display unit of a small product such as a mobile phone, and can also be used as a display unit of a large product such as a television.

[0003] The display device includes pixels that receive electrical signals and emit light to display an image to the outside. Each pixel may include a display element. As an example, an organic light emitting display device may include an organic light emitting diode (OLED) as a display element. Typically, an organic light emitting display device includes a thin film transistor and an organic light emitting diode above a substrate, and operates while the organic light emitting diode spontaneously emits light.

[0004] Recently, as uses of display devices have diversified, various designs for improving the quality of display devices have been attempted. Summary of the invention

[0005] Technical issues

[0006] One or more embodiments include a display device including a capacitor having increased (or guaranteed) capacitance.The capacitor may be placed in a pixel circuit configured to drive a display element.

[0007] The technical aspects are not limited to those mentioned above, and other technical aspects not mentioned will be clearly understood by those of ordinary skill in the art from the description of the present disclosure.

[0008] Technical Solution

[0009] According to one or more embodiments, a display device may include: a first electrode and a second electrode, which are arranged separately from each other on a substrate; a first insulating layer, which is arranged on the substrate and overlaps with the first electrode and the second electrode; a third electrode, which is arranged on the first insulating layer and overlaps with the first electrode and the second electrode; a second insulating layer, which is arranged on the first insulating layer and overlaps with the third electrode; a fourth electrode, which is arranged on the second insulating layer, overlaps with the third electrode, and is electrically connected to the first electrode; a third insulating layer, which is arranged on the second insulating layer and overlaps with the fourth electrode; and a fifth electrode, which is arranged on the third insulating layer, overlaps with the fourth electrode, and is electrically connected to the third electrode.

[0010] In a plan view, the second electrode may extend substantially in a first direction and have a protrusion protruding in a second direction intersecting the first direction, and the first electrode may be provided adjacent to the protrusion of the second electrode in the first direction.

[0011] The display device may further include: a first display element configured to emit light of a first color; and a first pixel circuit electrically connected to the first display element and electrically connected to a power line. The first pixel circuit may include: a first transistor configured to control the magnitude of a first drive current flowing through the first display element; a first storage capacitor electrically connected between a gate of the first transistor and a source of the first transistor; and a first holding capacitor electrically connected between the power line and the source of the first transistor. The first storage capacitance of the first storage capacitor may be the sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fourth electrode, and a third capacitance between the fourth electrode and the fifth electrode. The first holding capacitance of the first holding capacitor may be a fourth capacitance between the second electrode and the third electrode.

[0012] The display device may further include: a second display element configured to emit light of a second color different from the first color; and a second pixel circuit electrically connected to the second display element and electrically connected to the power line. The second pixel circuit may include: a second transistor configured to control the magnitude of a second drive current flowing through the second display element; a second storage capacitor electrically connected between a gate of the second transistor and a source of the second transistor; and a second holding capacitor electrically connected between the power line and the source of the second transistor. The first storage capacitance of the first storage capacitor may be greater than the second storage capacitance of the second storage capacitor, and the first holding capacitance of the first holding capacitor may be less than the second holding capacitance of the second holding capacitor.

[0013] The first color may be green, and the second color may be blue.

[0014] The display device may further include: a display element; and a pixel circuit electrically connected to the display element and electrically connected to a power line. The pixel circuit may include: a first transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to a gate of the first transistor, and the second storage electrode being electrically connected to a source of the first transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the first transistor. The first storage electrode of the storage capacitor may include the first electrode and the fourth electrode, the second storage electrode of the storage capacitor may include a portion of the third electrode overlapping with the first electrode, and the fifth electrode, the first holding electrode of the holding capacitor may include the second electrode, and the second holding electrode of the holding capacitor may include another portion of the third electrode overlapping with the second electrode.

[0015] The display element may include an anode and a cathode, the pixel circuit may be electrically connected to a data line, a first voltage line and a second voltage line, and the pixel circuit may further include: a second transistor, configured to electrically connect the data line to the gate of the first transistor in response to a first scan signal; a third transistor, configured to electrically connect the first voltage line to the gate of the first transistor in response to a second scan signal; a fourth transistor, configured to electrically connect the second voltage line to the anode of the display element in response to the third scan signal; a fifth transistor, configured to electrically connect the power line to the drain of the first transistor in response to a first emission control signal; and a sixth transistor, configured to electrically connect the source of the first transistor to the anode of the display element in response to a second emission control signal.

[0016] The display device may further include: a semiconductor layer provided between the third electrode and the fourth electrode and including an oxide semiconductor material.

[0017] The third electrode may include an opening exposing at least a portion of the first insulating layer, and the first electrode may be electrically connected to the fourth electrode through a contact hole passing through the opening of the third electrode.

[0018] In a plan view, the opening of the third electrode may overlap with a central portion of the first electrode.

[0019] The fourth electrode may include an opening exposing at least a portion of the second insulating layer, and the third electrode may be electrically connected to the fifth electrode through a contact hole passing through the opening of the fourth electrode.

[0020] According to one or more embodiments, a display device may include: a first electrode and a second electrode, which are arranged separately from each other on a substrate; a first insulating layer, which is arranged on the substrate and overlaps with the first electrode and the second electrode; a third electrode, which is arranged on the first insulating layer and overlaps with the first electrode and the second electrode; a second insulating layer, which is arranged on the first insulating layer and overlaps with the third electrode; a fourth electrode, which is arranged on the second insulating layer, overlaps with the third electrode, and is electrically connected to the second electrode; a third insulating layer, which is arranged on the second insulating layer and overlaps with the fourth electrode; a fifth electrode, which is arranged on the third insulating layer, overlaps with the third electrode, and is electrically connected to the first electrode; a fourth insulating layer, which is arranged on the third insulating layer and overlaps with the fifth electrode; and a sixth electrode, which is arranged on the fourth insulating layer, overlaps with the fifth electrode, and is electrically connected to the third electrode.

[0021] The fourth electrode may include an oxide semiconductor material.

[0022] In a plan view, the second electrode may extend substantially in a first direction and have a protrusion protruding in a second direction intersecting the first direction, and the first electrode may be provided adjacent to the protrusion of the second electrode in the first direction.

[0023] The display device may further include: a display element; and a pixel circuit electrically connected to the display element and electrically connected to a power line. The pixel circuit may include: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to a gate of the transistor, and the second storage electrode being electrically connected to a source of the transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the transistor. The first storage electrode of the storage capacitor may include the first electrode and the fifth electrode, the second storage electrode of the storage capacitor may include a portion of the third electrode overlapping with the first electrode, and the sixth electrode, the first holding electrode of the holding capacitor may include the second electrode and the fourth electrode, and the second holding electrode of the holding capacitor may include another portion of the third electrode overlapping with the second electrode.

[0024] The display device may further include: a first display element configured to emit light of a first color; and a first pixel circuit electrically connected to the first display element and electrically connected to a power line. The first pixel circuit may include: a first transistor configured to control the magnitude of a first drive current flowing through the first display element; a first storage capacitor electrically connected between a gate of the first transistor and a source of the first transistor; and a first holding capacitor electrically connected between the power line and the source of the first transistor. The first storage capacitance of the first storage capacitor may be the sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fifth electrode, and a third capacitance between the fifth electrode and the sixth electrode. The first holding capacitance of the first holding capacitor may be the sum of a fourth capacitance between the second electrode and the third electrode, and a fifth capacitance between the third electrode and the fourth electrode.

[0025] The display device may further include: a second display element configured to emit light of a second color different from the first color; and a second pixel circuit electrically connected to the second display element and electrically connected to the power line. The second pixel circuit may include: a second transistor configured to control the magnitude of a second drive current flowing through the second display element; a second storage capacitor electrically connected between a gate of the second transistor and a source of the second transistor; and a second holding capacitor electrically connected between the power line and the source of the second transistor. The first storage capacitance of the first storage capacitor may be greater than the second storage capacitance of the second storage capacitor. The first holding capacitance of the first holding capacitor may be less than the second holding capacitance of the second holding capacitor.

[0026] The first color may be green, and the second color may be blue.

[0027] The third electrode may include a first opening exposing at least a portion of the first insulating layer, the fifth electrode may include a second opening exposing at least a portion of the third insulating layer, the first electrode may be electrically connected to the fifth electrode via a first contact hole passing through the first opening of the third electrode, and the third electrode may be electrically connected to the sixth electrode via a second contact hole passing through the second opening of the fifth electrode.

[0028] According to one or more embodiments, a display device may include: a first electrode and a second electrode, which are arranged separately from each other on a substrate; a first insulating layer, which is arranged on the substrate and overlaps with the first electrode and the second electrode; a third electrode, which is arranged on the first insulating layer and overlaps with the first electrode; a fourth electrode, which is arranged on the first insulating layer and is separated from the third electrode and overlaps with the second electrode; a second insulating layer, which is arranged on the first insulating layer and overlaps with the third electrode and the fourth electrode; a fifth electrode, which is arranged on the second insulating layer, overlaps with the third electrode, and is electrically connected to the first electrode; a third insulating layer, which is arranged on the second insulating layer and overlaps with the fifth electrode; and a sixth electrode, which is arranged on the third insulating layer, overlaps with the fifth electrode, and is electrically connected to the second electrode and the third electrode.

[0029] In a plan view, the fourth electrode may extend substantially in a first direction and have a protrusion protruding in a second direction intersecting the first direction, and the third electrode may be provided adjacent to the protrusion of the fourth electrode in the first direction.

[0030] The display device may further include: a semiconductor layer provided between the third electrode and the fifth electrode and including an oxide semiconductor material.

[0031] The fourth electrode may be in a state where a preset voltage is applied to the fourth electrode.

[0032] The display device may further include: a display element; and a pixel circuit electrically connected to the display element and electrically connected to a power line. The pixel circuit may further include: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor electrically connected between a gate of the transistor and a source of the transistor; and a holding capacitor electrically connected between the power line and the source of the transistor. The storage capacitance of the storage capacitor may be the sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fifth electrode, and a third capacitance between the fifth electrode and the sixth electrode. The holding capacitance of the holding capacitor may be a fourth capacitance between the second electrode and the fourth electrode.

[0033] The display device may further include: a display element; and a pixel circuit electrically connected to the display element and electrically connected to a power line. The pixel circuit may further include: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to a gate of the transistor, and the second storage electrode being electrically connected to a source of the transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the transistor. The first storage electrode of the storage capacitor may include the first electrode and the fifth electrode, the second storage electrode of the storage capacitor may include the third electrode and the sixth electrode, the first holding electrode of the holding capacitor may include the fourth electrode, and the second holding electrode of the holding capacitor may include the second electrode.

[0034] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, the drawings and the claims.

[0035] These general and specific aspects may be implemented using systems, methods, computer programs, or a combination of specific systems, methods, and computer programs.

[0036] Beneficial Effects

[0037] According to the above-described embodiment, a display device including a capacitor having increased (or ensured) capacitance can be provided. The capacitor can be placed in a pixel circuit configured to drive a display element. However, the scope of the present disclosure is not limited thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic cross-sectional view of a display device according to an embodiment;

[0039] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment;

[0041] Figure 4 is a schematic plan view of a display device according to an embodiment;

[0042] Figure 5 is included in Figure 4 A schematic diagram of an equivalent circuit of a pixel in a display device;

[0043] Figure 6 is included in Figure 4 A schematic configuration diagram of positions of transistors, capacitors, etc. in a pixel circuit in a display device of FIG. 1 ;

[0044] Figures 7 to 11 is used for Figure 6 Schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in ;

[0045] Fig.12 It is along Figure 6 The line I-I' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG.

[0046] Fig.13 It is along Figure 6 The line II-II' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG.

[0047] Fig.14 It is along Figure 6 The line III-III' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG.

[0048] Fig.15 is included in Figure 4 A schematic configuration diagram of positions of transistors, capacitors, etc. in a pixel circuit in a display device of FIG. 1 ;

[0049] Figures 16 to 20 is used for Fig.15 Schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in ;

[0050] Fig.21 It is along Fig.15 The line IV-IV' in Fig.15 A cross-sectional view of an example of a portion of a display device in FIG.

[0051] Fig. 22 is included in Figure 4 A schematic configuration diagram of positions of transistors, capacitors, etc. in a pixel circuit in a display device of FIG. 1 ;

[0052] Figure 23 to Figure 27 is used for Fig. 22 A schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in FIG. 1 ; and

[0053] Fig.28 are respectively along Fig. 22 The line V-V' and line VI-VI' in Fig. 22 A cross-sectional view of an example of a portion of a display device. DETAILED DESCRIPTION

[0054] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments will be described hereinafter only by reference to the accompanying drawings to illustrate various aspects of the description.

[0055] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same or corresponding elements in the drawings may be given the same reference numerals, and redundant descriptions thereof may be omitted.

[0056] Although terms such as "first" and "second" may be used to describe various elements, these elements must not be limited to the above terms. The above terms are used to distinguish one element from another element.

[0057] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0058] It will be understood that the terms “comprising,” “having,” and / or “including” as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0059] It will be further understood that when a layer, region or element is referred to as being “on” another layer, region or element, it can be directly or indirectly on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0060] For convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. As an example, for convenience of description, the size and thickness of each element shown in the drawings may be arbitrarily represented, and therefore, the present disclosure is not necessarily limited thereto.

[0061] Where a particular embodiment may be implemented differently, a particular process sequence may be performed in a different order than that described. As an example, two processes described in succession may be performed substantially simultaneously or in a reverse order.

[0062] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean any combination including "A, B, or A and B".

[0063] The phrase "at least one of A and B" may be interpreted as A only, B only, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z.

[0064] It will be understood that when an element (or region, layer or portion, etc.) is referred to in the specification as being "on" another element, "connected to" or "coupled to" another element, the element (or region, layer or portion, etc.) can be directly set on the other element mentioned above, directly connected or coupled to the other element mentioned above, or intervening elements can be set between them.

[0065] It will be understood that the term “connected to” or “coupled to” may include a physical connection or physical coupling and / or an electrical connection or electrical coupling.

[0066] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0067] An element extending "substantially" in one direction may refer to an element extending in a zigzag or other shape in the direction, as well as an element extending straight in the direction. That is, the element may extend only in the indicated direction, or may extend in directions other than the indicated direction as well as in the indicated direction.

[0068] The term "overlap" means that the first object may be partially or completely above or below the second object or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0069] Figure 1 is a schematic cross-sectional view of a display device according to an embodiment.

[0070] refer to Figure 1 , the display device may include a first capacitor C11 and a second capacitor C12.

[0071] The first capacitor C11 may include a first electrode E11, a third electrode E13, a fourth electrode E14, and a fifth electrode E15. The third electrode E13 may be disposed on the first electrode E11 and may at least partially overlap with the first electrode E11. The first electrode E11 and the third electrode E13 may constitute a first capacitor Cpa1. The fourth electrode E14 may be disposed on the third electrode E13 and may at least partially overlap with the third electrode E13. The third electrode E13 and the fourth electrode E14 may constitute a second capacitor Cpa2. The fourth electrode E14 may be electrically connected to the first electrode E11. The fifth electrode E15 may be disposed on the fourth electrode E14 and may at least partially overlap with the fourth electrode E14. The fourth electrode E14 and the fifth electrode E15 may constitute a third capacitor Cpa3. The fourth electrode E14 may be electrically connected to the first electrode E11. The fifth electrode E15 may be electrically connected to the third electrode E13.

[0072] The first capacitor C11 may have a capacitance based on the first capacitor Cpa1, the second capacitor Cpa2, and the third capacitor Cpa3. As an example, the capacitance (or capacitance value) of the first capacitor C11 may be the sum of the first capacitor Cpa1, the second capacitor Cpa2, and the third capacitor Cpa3.

[0073] The second capacitor C12 may include a second electrode E12 and a third electrode E13. The third electrode E13 may be disposed on the second electrode E12 and may at least partially overlap the second electrode E12. The second electrode E12 and the third electrode E13 may constitute a fourth capacitor Cpa4.

[0074] The second capacitor C12 may have a capacitance based on the fourth capacitor Cpa4. As an example, the capacitance of the second capacitor C12 may be the fourth capacitor Cpa4.

[0075] In the case of “the first capacitor C11 may include the third electrode E13”, it may mean “the first capacitor C11 may include a portion of the third electrode E13 overlapping the first electrode E11”. In the case of “the second capacitor C12 may include the third electrode E13”, it may mean “the second capacitor C12 may include another portion of the third electrode E13 overlapping the second electrode E12”.

[0076] As in the embodiment, when at least some of the electrodes constituting the first capacitor C11 are disposed on the second capacitor C12, the area in which the electrodes constituting the second capacitor C12 can be arranged can be increased (or ensured). When at least some of the electrodes constituting the first capacitor C11 are stacked on the second capacitor C12, the capacitance of the second capacitor C12 can be increased (or ensured).

[0077] In the following, reference Figure 1 The configuration of the display device is described more specifically according to the stacked structure.

[0078] The substrate 100 may include a glass material, a ceramic material and / or a metal material. The substrate 100 may include a flexible material or a bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin including polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate and / or cellulose acetate propionate.

[0079] The substrate 100 may have a single layer structure or a multilayer structure of the above materials, and may further include an inorganic layer in the case of a multilayer structure. In an embodiment, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0080] The first electrode E11 and the second electrode E12 may be disposed on the substrate 100. The first electrode E11 may be separated from the second electrode E12. The first electrode E11 and the second electrode E12 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the first electrode E11 and the second electrode E12 may be a single Mo layer.

[0081] In an embodiment, a preset voltage may be applied to the second electrode E12. As an example, the following description Figure 5 The first driving voltage ELVDD may be applied to the second electrode E12.

[0082] The barrier layer 110 may be disposed on the substrate 100 to cover the first electrode E11 and the second electrode E12. The barrier layer 110 may prevent or reduce the penetration of impurities from the substrate 100, etc. The barrier layer 110 may include an inorganic material, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material, the inorganic material including an oxide or a nitride.

[0083] The third electrode E13 may be disposed on the barrier layer 110. The third electrode E13 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the third electrode E13 may include a single Mo layer.

[0084] The first electrode E11 and the third electrode E13 may overlap each other (the barrier layer 110 is between the first electrode E11 and the third electrode E13) and form a first capacitor Cpa1. The second electrode E12 and the third electrode E13 may overlap each other (the barrier layer 110 is between the second electrode E12 and the third electrode E13) and form a fourth capacitor Cpa4. The barrier layer 110 may be used as a dielectric layer of a capacitor.

[0085] The buffer layer 111 may be disposed on the barrier layer 110 to cover the third electrode E13. The buffer layer 111 may be configured to reduce or block penetration of foreign matter, moisture, or external air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material, the inorganic material including an oxide or a nitride.

[0086] The first insulating layer 113 and the second insulating layer 115 may be stacked on the buffer layer 111. The first insulating layer 113 and the second insulating layer 115 may each include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0087] The fourth electrode E14 may be disposed between the first insulating layer 113 and the second insulating layer 115. The fourth electrode E14 may be electrically connected to the first electrode E11. The fourth electrode E14 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc. and include a single layer or multiple layers. As an example, the fourth electrode E14 may include a single Mo layer.

[0088] The third electrode E13 and the fourth electrode E14 may overlap each other (with the buffer layer 111 and the first insulating layer 113 between them) and form the second capacitor Cpa2. The buffer layer 111 and the first insulating layer 113 may function as dielectric layers of the capacitor.

[0089] The fifth electrode E15 may be disposed on the second insulating layer 115. The fifth electrode E15 may be electrically connected to the third electrode E13. The fifth electrode E15 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti) and have a single-layer structure or a multi-layer structure including the above materials. As an example, the fifth electrode E15 may have a multi-layer structure of Ti / Al / Ti.

[0090] The fourth electrode E14 and the fifth electrode E15 may overlap each other (the second insulating layer 115 is between the fourth electrode E14 and the fifth electrode E15) and constitute the third capacitor Cpa3. The second insulating layer 115 may function as a dielectric layer of the capacitor.

[0091] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment. Figure 2 In, with Figure 1 The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0092] refer to Figure 2 , the display device may include a first capacitor C21 and a second capacitor C22.

[0093] The first capacitor C21 may include a first electrode E21, a third electrode E23, a fifth electrode E25, and a sixth electrode E26. The first electrode E21, the third electrode E23, the fifth electrode E25, and the sixth electrode E26 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc., and may include a single layer or multiple layers. As an example, the first electrode E21, the third electrode E23, and the fifth electrode E25 may each be a single Mo layer. The sixth electrode E26 may have a multilayer structure of Ti / Al / Ti.

[0094] The first electrode E21 may be disposed between the substrate 100 and the barrier layer 110, the third electrode E23 may be disposed between the barrier layer 110 and the buffer layer 111, the fifth electrode E25 may be disposed between the first insulating layer 113 and the second insulating layer 115, and the sixth electrode E26 may be disposed on the second insulating layer 115. The first electrode E21 and the third electrode E23 may overlap with each other (the barrier layer 110 is between the first electrode E21 and the third electrode E23) and constitute a first capacitor Cpb1. The third electrode E23 and the fifth electrode E25 may overlap with each other (the buffer layer 111 and the first insulating layer 113 are between the third electrode E23 and the fifth electrode E25) and constitute a second capacitor Cpb2. The fifth electrode E25 and the sixth electrode E26 may overlap with each other (the second insulating layer 115 is between the fifth electrode E25 and the sixth electrode E26) and constitute a third capacitor Cpb3. The barrier layer 110, the buffer layer 111, the first insulating layer 113, and the second insulating layer 115 may function as dielectric layers. The first electrode E21 may be electrically connected to the fifth electrode E25. The third electrode E23 may be electrically connected to the sixth electrode E26.

[0095] The first capacitor C21 may have a capacitance based on the first capacitor Cpb1, the second capacitor Cpb2, and the third capacitor Cpb3. As an example, the capacitance (or capacitance value) of the first capacitor C21 may be the sum of the first capacitor Cpb1, the second capacitor Cpb2, and the third capacitor Cpb3.

[0096] The second capacitor C22 may include a second electrode E22, a third electrode E23, and a fourth electrode E24. The second electrode E22 and the third electrode E23 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc., and include a single layer or multiple layers. As an example, the second electrode E22 and the third electrode E23 may be a single Mo layer. The fourth electrode E24 may include an oxide semiconductor material. The fourth electrode E24 may include, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The fourth electrode E24 may be conductorized (or conductive) by plasma treatment, etc.

[0097] The second electrode E22 may be disposed between the substrate 100 and the barrier layer 110, the third electrode E23 may be disposed between the barrier layer 110 and the buffer layer 111, and the fourth electrode E24 may be disposed between the buffer layer 111 and the first insulating layer 113. The second electrode E22 may be separated from the first electrode E21. The second electrode E22 and the third electrode E23 may overlap with each other (the barrier layer 110 is between the second electrode E22 and the third electrode E23) and constitute a fourth capacitor Cpb4. The third electrode E23 and the fourth electrode E24 may overlap with each other (the buffer layer 111 is between the third electrode E23 and the fourth electrode E24) and constitute a fifth capacitor Cpb5. The barrier layer 110 and the buffer layer 111 may serve as dielectric layers of a capacitor. The second electrode E22 may be electrically connected to the fourth electrode E24.

[0098] The second capacitor C22 may have a capacitance based on the fourth capacitor Cpb4 and the fifth capacitor Cpb5. As an example, the capacitance of the second capacitor C22 may be the sum of the fourth capacitor Cpb4 and the fifth capacitor Cpb5.

[0099] In an embodiment, a preset voltage may be applied to the second electrode E22 and the fourth electrode E24. As an example, the following description Figure 5 The first driving voltage ELVDD may be applied to the second electrode E22 and the fourth electrode E24.

[0100] In the case of “the first capacitor C21 may include the third electrode E23”, it may mean “the first capacitor C21 may include a portion of the third electrode E23 overlapping the first electrode E21 and the fifth electrode E25”. In the case of “the second capacitor C22 may include the third electrode E23”, it may mean “the second capacitor C22 may include another portion of the third electrode E23 overlapping the second electrode E22 and the fourth electrode E24”.

[0101] As in the embodiment, in the case where at least some of the electrodes constituting the first capacitor C21 are disposed on the second capacitor C22, the area in which the electrodes constituting the second capacitor C22 can be arranged can be increased (or ensured). In the case where at least some of the electrodes constituting the first capacitor C21 are stacked on the second capacitor C22, the capacitance of the second capacitor C22 can be increased (or ensured). In the case where the electrodes constituting the second capacitor C22 are stacked in a multi-layer structure, the capacitance of the second capacitor C22 can be further increased (or ensured).

[0102] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment. Figure 3 In, with Figure 1The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0103] refer to Figure 3 , the display device may include a first capacitor C31 and a second capacitor C32.

[0104] The first capacitor C31 may include a first electrode E31, a third electrode E33, a fifth electrode E35, and a sixth electrode E36. The first electrode E31, the third electrode E33, the fifth electrode E35, and the sixth electrode E36 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc., and may include a single layer or multiple layers. As an example, the first electrode E31, the third electrode E33, and the fifth electrode E35 may each be a single Mo layer. The sixth electrode E36 may have a multilayer structure of Ti / Al / Ti.

[0105] The first electrode E31 may be disposed between the substrate 100 and the barrier layer 110, the third electrode E33 may be disposed between the barrier layer 110 and the buffer layer 111, the fifth electrode E35 may be disposed between the first insulating layer 113 and the second insulating layer 115, and the sixth electrode E36 may be disposed on the second insulating layer 115. The first electrode E31 and the third electrode E33 may overlap with each other (the barrier layer 110 is between the first electrode E31 and the third electrode E33) and constitute a first capacitor Cpc1. The third electrode E33 and the fifth electrode E35 may overlap with each other (the buffer layer 111 and the first insulating layer 113 are between the third electrode E33 and the fifth electrode E35) and constitute a second capacitor Cpc2. The fifth electrode E35 and the sixth electrode E36 may overlap with each other (the second insulating layer 115 is between the fifth electrode E35 and the sixth electrode E36) and constitute a third capacitor Cpc3. The barrier layer 110, the buffer layer 111, the first insulating layer 113, and the second insulating layer 115 may function as dielectric layers. The first electrode E31 may be electrically connected to the fifth electrode E35. The third electrode E33 may be electrically connected to the sixth electrode E36.

[0106] The first capacitor C31 may have a capacitance based on the first capacitance Cpc1, the second capacitance Cpc2, and the third capacitance Cpc3. As an example, the capacitance of the first capacitor C31 may be the sum of the first capacitance Cpc1, the second capacitance Cpc2, and the third capacitance Cpc3.

[0107] The second capacitor C32 may include a second electrode E32 and a fourth electrode E34. The second electrode E32 and the fourth electrode E34 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the second electrode E32 and the fourth electrode E34 may each be a single Mo layer.

[0108] The second electrode E32 may be disposed between the substrate 100 and the barrier layer 110, and the fourth electrode E34 may be disposed between the barrier layer 110 and the buffer layer 111. The second electrode E32 may be separated from the first electrode E31, and the fourth electrode E34 may be separated from the third electrode E33. The second electrode E32 and the fourth electrode E34 may overlap each other (the barrier layer 110 is between the second electrode E32 and the fourth electrode E34) and constitute a fourth capacitor Cpb4. The barrier layer 110 may serve as a dielectric layer of the capacitor. The second electrode E32 may be electrically connected to the sixth electrode E36.

[0109] The second capacitor C32 may have a capacitance based on the fourth capacitor Cpb4. As an example, the capacitance of the second capacitor C32 may be the fourth capacitor Cpb4.

[0110] In an embodiment, a preset voltage may be applied to the fourth electrode E34. As an example, the voltage described below Figure 5 The first driving voltage ELVDD may be applied to the fourth electrode E34.

[0111] As in the embodiment, when at least some of the electrodes constituting the first capacitor C31 are disposed on the second capacitor C32, the area in which the electrodes constituting the second capacitor C32 can be arranged can be increased (or ensured). When at least some of the electrodes constituting the first capacitor C31 are stacked on the second capacitor C32, the capacitance of the second capacitor C32 can be increased (or ensured).

[0112] Figure 4 is a schematic plan view of a display device according to an embodiment.

[0113] refer to Figure 4 , the display device 1 may include a display area DA and a peripheral area PA. The display area DA may be configured to display an image, and the peripheral area PA may surround at least a portion of the display area DA. The display device 1 may display an image to the outside by using light emitted from the display area DA. Since the display device 1 includes the substrate 100, it can be understood that the substrate 100 includes the display area DA and the peripheral area PA. In other words, it can be understood that the display area DA and the peripheral area PA are defined in the substrate 100.

[0114] The substrate 100 may include various materials, such as glass, metal and / or plastic. In an embodiment, the substrate 100 may include a flexible material. Here, the flexible material refers to a material that is easy to warp, bendable, foldable and / or rollable. The substrate 100 of the flexible material may include ultra-thin glass, metal and / or plastic.

[0115] like Figure 4As shown in , the display area DA may be rectangular. In another embodiment, the display area DA may be provided in a polygonal shape such as a triangle, a pentagon, and a hexagon, a circular shape, an elliptical shape, or an irregular shape.

[0116] Pixels PX including various display elements such as organic light emitting diodes OLED may be arranged in the display area DA of the substrate 100. The pixels PX may be arranged in a stripe configuration, a PenTile TM Various configurations such as a red sub-pixel, a green sub-pixel, or a blue sub-pixel may be arranged to display an image. Hereinafter, in the specification, each pixel PX indicates a sub-pixel configured to emit light of a different color. Each pixel PX may be, for example, a red sub-pixel, a green sub-pixel, or a blue sub-pixel.

[0117] Although an organic light-emitting display device is described as an example of a display device according to an embodiment, the display device according to the embodiment is not limited thereto. In another embodiment, the display device according to the embodiment may be an inorganic light-emitting display device or a quantum dot light-emitting display device. As an example, the emission layer of the display element of the display device may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, an inorganic material and a quantum dot, or an organic material, an inorganic material and a quantum dot.

[0118] The peripheral area PA of the substrate 100 is an area arranged around the display area DA and may be an area where no image is displayed. The pads may be arranged in the peripheral area PA. Various wirings, printed circuit boards, or driver integrated circuit (IC) chips configured to transmit electrical signals to the display area DA may be attached to the pads.

[0119] Figure 5 is included in Figure 4 Schematic diagram of the equivalent circuit of a pixel in a display device.

[0120] refer to Figure 5 , the pixel PX may include a pixel circuit PC and a display element electrically connected to the pixel circuit PC. The display element may be an organic light emitting diode OLED including an anode (or pixel electrode) and a cathode (opposite electrode).

[0121] As an example, Figure 5As shown in , the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a storage capacitor Cst, and a holding capacitor Chd. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chd may be connected to the first scan line GWL, the second scan line GRL, and the third scan line GIL, the data line DL, the first emission control line EML, and the second emission control line EMBL, the power line PL, the first voltage line VL1, the second voltage line VL2, and the common electrode. The 1st scan line GWL, the 2nd scan line GRL and the 3rd scan line GIL can be configured to transmit the 1st scan signal GW, the 2nd scan signal GR and the 3rd scan signal GI, respectively, the data line DL can be configured to transmit the data voltage Vdata, the 1st emission control line EML and the 2nd emission control line EMBL can be configured to transmit the 1st emission control signal EM and the 2nd emission control signal EMB, respectively, the power line PL can be configured to transmit the 1st driving voltage ELVDD, the 1st voltage line VL1 can be configured to transmit the reference voltage VREF, the 2nd voltage line VL2 can be configured to transmit the initialization voltage Vint, and the 2nd driving voltage ELVSS can be applied to the common electrode.

[0122] The first transistor T1 may be a driving transistor in which the magnitude of its drain current may be determined according to its (upper) gate-source voltage, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be switching transistors that are turned on / off according to the gate-source voltage (substantially the gate voltage). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be formed as thin film transistors.

[0123] In an embodiment, Figure 5As shown in , the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be provided as n-channel metal oxide semiconductor field effect transistors (MOSFETs). In another embodiment, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be n-channel metal oxide semiconductor (NMOS) field effect transistors (n-channel MOSFETs), and the remaining transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be p-channel metal oxide semiconductor (PMOS) field effect transistors (p-channel MOSFETs). In another embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be p-channel metal oxide semiconductor (PMOS) field effect transistors (p-channel MOSFETs).

[0124] In an embodiment, the semiconductor layer of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the semiconductor layer may be an ITZO (InSnZnO) semiconductor layer and an IGZO (InGaZnO) semiconductor layer, etc.

[0125] As another example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include a semiconductor layer including silicon. As an example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include a semiconductor layer including low temperature polysilicon (LTPS). Because polysilicon material has a high electron mobility (100cm 2 / Vs or greater), so the energy consumption can be low and the reliability can be excellent.

[0126] As another example, some semiconductor layers among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include low-temperature polycrystalline silicon (LTPS), and other semiconductor layers among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include oxide semiconductors (e.g., IGZO, etc.).

[0127] The storage capacitor Cst may include a first storage electrode CEs1 and a second storage electrode CEs2. The holding capacitor Chd may include a first holding electrode CEh1 and a second holding electrode CEh2. The first holding electrode CEh1 may be connected to the power line PL, and the second holding electrode CEh2 may be connected to the second storage electrode CEs2 of the storage capacitor Cst.

[0128] The first transistor T1 may be configured to control the magnitude of the driving current Id flowing from the power line PL through the organic light emitting diode OLED according to the (upper) gate-source voltage. The first transistor T1 may include an upper gate Ga, a drain D, a source S, and a lower gate Gb. The upper gate Ga may be connected to the first storage electrode CEs1 of the storage capacitor Cst, the drain D may be connected to the power line PL through the fifth transistor T5, the source S may be connected to the organic light emitting diode OLED through the sixth transistor T6, and the lower gate Gb may be connected to the second holding electrode CEh2 of the holding capacitor Chd. The lower gate Gb of the first transistor T1 may be connected to the source S of the first transistor T1.

[0129] The first transistor T1 may be configured to output a driving current Id to the organic light emitting diode OLED according to a gate-source voltage. The magnitude of the driving current Id may be determined based on a difference between the gate-source voltage of the first transistor T1 and a threshold voltage. The organic light emitting diode OLED may be configured to receive the driving current Id from the first transistor T1 and emit light at a brightness corresponding to the magnitude of the driving current Id.

[0130] The second transistor T2 may be configured to connect the data line DL to the first storage electrode CEs1 of the storage capacitor Cst (or the upper gate Ga of the first transistor T1) in response to the first scan signal GW. The second transistor T2 may be configured to connect the data line DL and the first storage electrode CEs1 of the storage capacitor Cst (or the upper gate Ga of the first transistor T1) to each other in response to the first scan signal GW. The second transistor T2 may be configured to transmit the data voltage Vdata to the first storage electrode CEs1 of the storage capacitor Cst (or the upper gate Ga of the first transistor T1) in response to the first scan signal GW.

[0131] The third transistor T3 may be configured to connect the first voltage line VL1 to the upper gate Ga of the first transistor T1 in response to the second scan signal GR. The third transistor T3 may be configured to connect the first voltage line VL1 and the upper gate Ga of the first transistor T1 to each other in response to the second scan signal GR. The third transistor T3 may be configured to apply the reference voltage VREF to the upper gate Ga of the first transistor T1 in response to the second scan signal GR.

[0132] The fourth transistor T4 may be configured to connect the second voltage line VL2 to the anode of the organic light emitting diode OLED in response to the third scan signal GI. The fourth transistor T4 may be configured to connect the second voltage line VL2 and the anode of the organic light emitting diode OLED to each other in response to the third scan signal GI. The fourth transistor T4 may be configured to apply the initialization voltage Vint to the anode of the organic light emitting diode OLED in response to the third scan signal GI.

[0133] The fifth transistor T5 may be configured to connect the power line PL to the drain D of the first transistor T1 in response to the first emission control signal EM. The fifth transistor T5 may be configured to connect the power line PL and the drain D of the first transistor T1 to each other in response to the first emission control signal EM. The fifth transistor T5 may be configured to apply the first driving voltage ELVDD to the drain D of the first transistor T1 in response to the first emission control signal EM.

[0134] The sixth transistor T6 may be configured to connect the source S of the first transistor T1 to the anode of the organic light emitting diode OLED in response to the second emission control signal EMB. The sixth transistor T6 may be configured to connect the source S of the first transistor T1 and the anode of the organic light emitting diode OLED to each other in response to the second emission control signal EMB.

[0135] Despite Figure 5 , the fifth transistor T5 and the sixth transistor T6 are shown to be configured to operate in response to different emission control signals EM and EMB, respectively, but in another embodiment, the fifth transistor T5 and the sixth transistor T6 may be configured to operate in response to the same emission control signal.

[0136] In an embodiment, the second scanning signal GR may be substantially synchronized with the first scanning signal GW in the previous row. The third scanning signal GI may be substantially synchronized with the first scanning signal GW. According to another example, the third scanning signal GI may be substantially synchronized with the first scanning signal GW in the next row or the second scanning signal GR in the next row.

[0137] Despite Figure 5, the pixel circuit PC is shown to include six transistors and two capacitors, but in another embodiment, the pixel circuit PC may include five transistors and two capacitors. In another embodiment, the pixel circuit PC may include seven transistors and two capacitors.

[0138] Figure 6 is included in Figure 4 A schematic configuration diagram of positions of transistors and capacitors, etc. in a pixel circuit in a display device of Figures 7 to 11 is used for Figure 6 Schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in FIG. Figures 7 to 11 Describes Figure 6 The first pixel circuit PC11 is described above, but the description is also applicable to the second pixel circuit PC12 and the third pixel circuit PC13.

[0139] First, refer to Figure 6 , the display device may include a first pixel circuit PC11, a second pixel circuit PC12, and a third pixel circuit PC13. The first pixel circuit PC11, the second pixel circuit PC12, and the third pixel circuit PC13 may be arranged in a first direction (eg, ±x direction).

[0140] The first pixel circuit PC11, the second pixel circuit PC12, and the third pixel circuit PC13 may each correspond to Figure 5 As an example, the first pixel circuit PC11 may include a first transistor T11, a second transistor T12, a third transistor T13, a fourth transistor T14, a fifth transistor T15, and a sixth transistor T16, a first storage capacitor Cst11, and a first holding capacitor Chd11. The first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14, the fifth transistor T15, and the sixth transistor T16 may correspond to Figure 5 The first storage capacitor Cst11 may correspond to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6. Figure 5 The storage capacitor Cst, and the first holding capacitor Chd11 may correspond to Figure 5Although the first pixel circuit PC11 has been described, the description is also applicable to the second pixel circuit PC12 and the third pixel circuit PC13. As an example, the second pixel circuit PC12 may include a second storage capacitor Cst12 and a second holding capacitor Chd12, and the third pixel circuit PC13 may include a third storage capacitor Cst13 and a third holding capacitor Chd13. The second storage capacitor Cst12 and the third storage capacitor Cst13 may each correspond to Figure 5 The storage capacitor Cst of the second storage capacitor Chd12 and the third storage capacitor Chd13 may each correspond to Figure 5 The holding capacitor Chd.

[0141] In an embodiment, the 1st pixel circuit PC11, the 2nd pixel circuit PC12 and the 3rd pixel circuit PC13 may be electrically connected to display elements configured to emit light of different colors, respectively. The 1st pixel circuit PC11, the 2nd pixel circuit PC12 and the 3rd pixel circuit PC13 may be configured to drive display elements configured to emit light of different colors, respectively. As an example, the display element electrically connected to the 1st pixel circuit PC11 may be configured to emit red light. The 1st pixel circuit PC11 may be configured to drive a display element configured to emit red light. The display element electrically connected to the 2nd pixel circuit PC12 may be configured to emit green light. The 2nd pixel circuit PC12 may be configured to drive a display element configured to emit green light. The display element electrically connected to the 3rd pixel circuit PC13 may be configured to emit blue light. The 3rd pixel circuit PC13 may be configured to drive a display element configured to emit blue light.

[0142] The first storage capacitor Cst11 of the first pixel circuit PC11 may have a first storage capacitor Cpt11, and the first retention capacitor Chd11 of the first pixel circuit PC11 may have a first retention capacitor Cpd11. The second storage capacitor Cst12 of the second pixel circuit PC12 may have a second storage capacitor Cpt12, and the second retention capacitor Chd12 of the second pixel circuit PC12 may have a second retention capacitor Cpd12. The third storage capacitor Cst13 of the third pixel circuit PC13 may have a third storage capacitor Cpt13, and the third retention capacitor Chd13 of the third pixel circuit PC13 may have a third retention capacitor Cpd13.

[0143] In an embodiment, the first storage capacitance Cpt11 of the first storage capacitor Cst11, the second storage capacitance Cpt12 of the second storage capacitor Cst12, and the third storage capacitance Cpt13 of the third storage capacitor Cst13 may be substantially equal to each other. The first holding capacitance Cpd11 of the first holding capacitor Chd11, the second holding capacitance Cpd12 of the second holding capacitor Chd12, and the third holding capacitance Cpd13 of the third holding capacitor Chd13 may be substantially equal to each other.

[0144] In another embodiment, the first storage capacitance Cpt11 of the first storage capacitor Cst11, the second storage capacitance Cpt12 of the second storage capacitor Cst12, and the third storage capacitance Cpt13 of the third storage capacitor Cst13 may be different from each other. The first holding capacitance Cpd11 of the first holding capacitor Chd11, the second holding capacitance Cpd12 of the second holding capacitor Chd12, and the third holding capacitance Cpd13 of the third holding capacitor Chd13 may be substantially different from each other. As an example, the second storage capacitance Cpt12 of the second storage capacitor Cst12 may be greater than the first storage capacitance Cpt11 of the first storage capacitor Cst11 and the third storage capacitance Cpt13 of the third storage capacitor Cst13. The third holding capacitance Cpd13 of the third holding capacitor Chd13 may be greater than the first holding capacitance Cpd11 of the first holding capacitor Chd11 and the second holding capacitance Cpd12 of the second holding capacitor Chd12.

[0145] refer to Figures 7 to 11 More specific description Figure 6 Elements such as transistors and capacitors of the display device shown in .

[0146] Figure 7 The first conductive layer 1000 shown in FIG. 1 may be disposed on the substrate 100 (see Figure 4 ). The first conductive layer 1000 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the first conductive layer 1000 may include a single Mo layer.

[0147] The first conductive layer 1000 may include a first conductive pattern 1001, a second conductive pattern 1002, a third conductive pattern 1003, and a fourth conductive pattern 1004. The first conductive pattern 1001, the third conductive pattern 1003, and the fourth conductive pattern 1004 may extend substantially in a first direction (eg, ±x direction). The third conductive pattern 1003 may be in a state where a preset voltage is applied. As an example, Figure 5The first driving voltage ELVDD may be applied to the third conductive pattern 1003. The fourth conductive pattern 1004 may be a repair line. The first conductive pattern 1001 may correspond to Figure 5 The first scanning line GWL, the second conductive pattern 1002 may correspond to Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, and the third conductive pattern 1003 may correspond to Figure 5 The first holding electrode CEh1 of the holding capacitor Chd.

[0148] In an embodiment, the third conductive pattern 1003 may have a protrusion 1003p protruding in the second direction (e.g., ±y direction). The second conductive pattern 1002 may be arranged adjacent to the protrusion 1003p of the third conductive pattern 1003 in the first direction (e.g., ±x direction). The second conductive pattern 1002 may be arranged between the protrusions 1003p of the third conductive pattern 1003.

[0149] The areas of the second conductive pattern 1002 and the third conductive pattern 1003 may be changed by moving the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). As an example, in the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the +x direction, the area of ​​the second conductive pattern 1002 may be reduced, and the area of ​​the third conductive pattern 1003 may be increased. In the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the -x direction, the area of ​​the second conductive pattern 1002 may be increased, and the area of ​​the third conductive pattern 1003 may be reduced. In the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the +y direction, the area of ​​the second conductive pattern 1002 can be reduced, and the area of ​​the third conductive pattern 1003 can be increased. In the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the -y direction, the area of ​​the second conductive pattern 1002 can be increased, and the area of ​​the third conductive pattern 1003 can be reduced.

[0150] Figure 8The second conductive layer 1100 shown in FIG. 1 may be disposed on the first conductive layer 1000. The second conductive layer 1100 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the second conductive layer 1100 may include a single Mo layer.

[0151] The second conductive layer 1100 may include a fifth conductive pattern 1101, a sixth conductive pattern 1102, and a seventh conductive pattern 1103. The fifth conductive pattern 1101 and the seventh conductive pattern 1103 may extend substantially in the first direction (eg, ±x direction). The fifth conductive pattern 1101 and the seventh conductive pattern 1103 may be in a state where a preset voltage is applied. As an example, Figure 5 A reference voltage VREF may be applied to the fifth conductive pattern 1101, and Figure 5 The initialization voltage Vint may be applied to the seventh conductive pattern 1103. A first opening 1102op may be formed in the sixth conductive pattern 1102. A conductive pattern disposed on the sixth conductive pattern 1102 may be connected to a conductive pattern disposed below the sixth conductive pattern 1102 through the first opening 1102op of the sixth conductive pattern 1102. The fifth conductive pattern 1101 may correspond to Figure 5 The sixth conductive pattern 1102 may correspond to the first voltage line VL1. Figure 5 The 7th conductive pattern 1103 may correspond to the 2nd storage electrode CEs2 of the storage capacitor Cst and the 2nd holding electrode CEh2 of the holding capacitor Chd. Figure 5 The second voltage line VL2.

[0152] Fig. 9 The semiconductor layer 1200 shown in the figure may be disposed on the second conductive layer 1100. The semiconductor layer 1200 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the semiconductor layer 1200 may be an ITZO (InSnZnO) semiconductor layer and an IGZO (InGaZnO) semiconductor layer, etc. If necessary, a process of being conductorized (or conductive) by plasma treatment, etc. may be performed on at least a portion of the semiconductor layer 1200. The semiconductor layer 1200 may include a first semiconductor pattern 1201, a second semiconductor pattern 1202, and a third semiconductor pattern 1203.

[0153] Fig. 9The third conductive layer 1300 shown in FIG. 1 may be disposed on the semiconductor layer 1200. The third conductive layer 1300 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the third conductive layer 1300 may include a single Mo layer.

[0154] The third conductive layer 1300 may include an eighth conductive pattern 1301, a ninth conductive pattern 1302, a tenth conductive pattern 1303, an eleventh conductive pattern 1304, a twelfth conductive pattern 1305, a thirteenth conductive pattern 1306, a fourteenth conductive pattern 1307, a fifteenth conductive pattern 1308, and a sixteenth conductive pattern 1309. The eighth conductive pattern 1301, the ninth conductive pattern 1302, the twelfth conductive pattern 1305, the fourteenth conductive pattern 1307, the fifteenth conductive pattern 1308, and the sixteenth conductive pattern 1309 may extend substantially in the first direction (e.g., ±x direction). A second opening 1304op may be formed in the eleventh conductive pattern 1304. A conductive pattern disposed on the eleventh conductive pattern 1304 may be connected to a semiconductor pattern and / or a conductive pattern disposed below the eleventh conductive pattern 1304 through the second opening 1304op of the eleventh conductive pattern 1304. The eighth conductive pattern 1301 may correspond to Figure 5 The 9th conductive pattern 1302 may correspond to the 1st scanning line GWL. Figure 5 The 11th conductive pattern 1304 may correspond to the 2nd scanning line GRL. Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, the twelfth conductive pattern 1305 may correspond to Figure 5 The 14th conductive pattern 1307 may correspond to the 1st emission control line EML. Figure 5 The 2nd emission control line EMBL, the 15th conductive pattern 1308 may correspond to Figure 5 The 3rd scanning line GIL, and the 16th conductive pattern 1309 may correspond to Figure 5 The second voltage line VL2.

[0155] Figure 8 The 7th conductive pattern 1103 and the 16th conductive pattern 1309 may each correspond to Figure 5 The 7th conductive pattern 1103 can be connected to the 1st pixel circuit PC11 and the 3rd pixel circuit PC13, and is configured to connect the 2nd voltage line VL2 of the 1st pixel circuit PC11 and the 3rd pixel circuit PC13. Figure 5 The initialization voltage Vint is transmitted to the first pixel circuit PC11 and the third pixel circuit PC13. The 16th conductive pattern 1309 may be connected to the second pixel circuit PC12, and is configured to transmit the initialization voltage Vint to the second pixel circuit PC12.

[0156] The portion of the 10th conductive pattern 1303 overlapping with the 1st semiconductor pattern 1201 may correspond to the gate of the 2nd transistor T12. The portion of the 9th conductive pattern 1302 overlapping with the 1st semiconductor pattern 1201 may correspond to the gate of the 3rd transistor T13. The portion of the 11th conductive pattern 1304 overlapping with the 2nd semiconductor pattern 1202 may correspond to the (upper) gate of the 1st transistor T11. The portion of the 12th conductive pattern 1305 overlapping with the 2nd semiconductor pattern 1202 may correspond to the gate of the 5th transistor T15. The portion of the 14th conductive pattern 1307 overlapping with the 3rd semiconductor pattern 1203 may correspond to the gate of the 6th transistor T16. The portion of the 15th conductive pattern 1308 overlapping with the 3rd semiconductor pattern 1203 may correspond to the gate of the 4th transistor T14.

[0157] The eighth conductive pattern 1301 may be connected to the first conductive pattern 1001 through the first contact hole cnta1. The first conductive pattern 1001 and the eighth conductive pattern 1301 may constitute a double scanning line. The eleventh conductive pattern 1304 may be connected to the second conductive pattern 1002 through the second contact hole cnta2. The second conductive pattern 1002 and the eleventh conductive pattern 1304 may constitute a Figure 5 The 13th conductive pattern 1306 may be connected to the 3rd conductive pattern 1003 through the 3rd contact hole cnta3.

[0158] Fig.10 The fourth conductive layer 1400 shown in the figure may be disposed on the third conductive layer 1300. The fourth conductive layer 1400 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single layer structure or a multilayer structure including the above materials. As an example, the fourth conductive layer 1400 may have a multilayer structure of Ti / Al / Ti.

[0159] The fourth conductive layer 1400 may include a 17th conductive pattern 1401, an 18th conductive pattern 1402, a 19th conductive pattern 1403, a 20th conductive pattern 1404, a 21st conductive pattern 1405, a 22nd conductive pattern 1406, a 23rd conductive pattern 1407, and a 24th conductive pattern 1408. The 17th conductive pattern 1401 may extend substantially in the second direction (eg, ±y direction). The 17th conductive pattern 1401 may correspond to Figure 5 The 21st conductive pattern 1405 may correspond to the data line DL. Figure 5 The second storage electrode CEs2 of the storage capacitor Cst.

[0160] The 17th conductive pattern 1401 may be connected to the 1st semiconductor pattern 1201 through the 4th contact hole cnta4. The 18th conductive pattern 1402 may be connected to the 8th conductive pattern 1301 through the (5-1)th contact hole cnta5-1, and connected to the 10th conductive pattern 1303 through the (5-2)th contact hole cnta5-2. The 19th conductive pattern 1403 may be connected to the 1st semiconductor pattern 1201 through the (6-1)th contact hole cnta6-1, and connected to the 5th conductive pattern 1101 through the (6-2)th contact hole cnta6-2. The 20th conductive pattern 1404 may be connected to the 1st semiconductor pattern 1201 through the (7-1)th contact hole cnta7-1, and connected to the 11th conductive pattern 1304 through the (7-2)th contact hole cnta7-2. The 21st conductive pattern 1405 may be connected to the 6th conductive pattern 1102 through the (8-1)th contact hole cnta8-1, connected to the 2nd semiconductor pattern 1202 through the (8-2)th contact hole cnta8-2, and connected to the 3rd semiconductor pattern 1203 through the (8-3)th contact hole cnta8-3. The 22nd conductive pattern 1406 may be connected to the 2nd semiconductor pattern 1202 through the (9-1)th contact hole cnta9-1, and connected to the 13th conductive pattern 1306 through the (9-2)th contact hole cnta9-2. The 23rd conductive pattern 1407 may be connected to the 3rd semiconductor pattern 1203 through the 10th contact hole cnta10. The 24th conductive pattern 1408 may be connected to the 7th conductive pattern 1103 through the (11-1)th contact hole cnta11-1, and connected to the 3rd semiconductor pattern 1203 through the (11-2)th contact hole cnta11-2.

[0161] Fig.11 The fifth conductive layer 1500 shown in the figure may be disposed on the fourth conductive layer 1400. The fifth conductive layer 1500 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single layer structure or a multilayer structure including the above materials. As an example, the fifth conductive layer 1500 may have a multilayer structure of Ti / Al / Ti.

[0162] The fifth conductive layer 1500 may include a 25th conductive pattern 1501, a 26th conductive pattern 1502, a 27th conductive pattern 1503, a 28th conductive pattern 1504, and a 29th conductive pattern 1505. The 25th conductive pattern 1501, the 27th conductive pattern 1503, the 28th conductive pattern 1504, and the 29th conductive pattern 1505 may extend substantially in the second direction (eg, ±y direction). The 25th conductive pattern 1501 may correspond to Figure 5 The 27th conductive pattern 1503 may correspond to the electric line PL Figure 5The 28th conductive pattern 1504 may correspond to the 2nd voltage line VL2. Figure 5 The common electrode, and the 29th conductive pattern 1505 may correspond to Figure 5 The first voltage line VL1.

[0163] The 25th conductive pattern 1501 can be connected to the 22nd conductive pattern 1406 through the 12th contact hole cnta12. The 26th conductive pattern 1502 can be connected to the anode of the display element through the (13-1)th contact hole cnta13-1, and connected to the 23rd conductive pattern 1407 through the (13-2)th contact hole cnta13-2. The 27th conductive pattern 1503 can be connected to the 24th conductive pattern 1408 through the 14th contact hole cnta14. The 29th conductive pattern 1505 can be connected to the 19th conductive pattern 1403 of the 3rd pixel circuit PC13 through the 15th contact hole cnta15.

[0164] Fig.12 It is along Figure 6 The line I-I' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG. Fig.12 Describes Figure 6 The first pixel circuit PC11 is described above, but the description is also applicable to the second pixel circuit PC12 and the third pixel circuit PC13.

[0165] refer to Fig.12 , the first pixel circuit PC11 may include a first storage capacitor Cst11 and a first holding capacitor Chd11.

[0166] The first storage capacitor Cst11 may include a second conductive pattern 1002 (or a first electrode), a sixth conductive pattern 1102 (or a third electrode), an eleventh conductive pattern 1304 (or a fourth electrode), and a twenty-first conductive pattern 1405 (or a fifth electrode). The first storage capacitor Cst11 may include a first storage electrode and a second storage electrode. The first storage electrode may be connected to the (upper) gate of the first transistor T11, and the second storage electrode may be connected to the source of the first transistor T11. The first storage electrode of the first storage capacitor Cst11 may include the second conductive pattern 1002 and the eleventh conductive pattern 1304, and the second storage electrode of the first storage capacitor Cst11 may include the sixth conductive pattern 1102 and the twenty-first conductive pattern 1405.

[0167] The 6th conductive pattern 1102 may be disposed on the 2nd conductive pattern 1002 and may at least partially overlap with the 2nd conductive pattern 1002. The 2nd conductive pattern 1002 and the 6th conductive pattern 1102 may constitute the (1-1)th storage capacitor Cpt11-1. The 11th conductive pattern 1304 may be disposed on the 6th conductive pattern 1102 and may partially overlap with the 6th conductive pattern 1102. The 6th conductive pattern 1102 and the 11th conductive pattern 1304 may constitute the (1-2)th storage capacitor Cpt11-2. The 21st conductive pattern 1405 may be disposed on the 11th conductive pattern 1304 and may at least partially overlap with the 11th conductive pattern 1304. The 11th conductive pattern 1304 and the 21st conductive pattern 1405 may constitute the (1-3)th storage capacitor Cpt11-3. As described later with reference to Fig.13 As described above, the 11th conductive pattern 1304 can be electrically connected to the 2nd conductive pattern 1002. Fig.14 As described, the 21st conductive pattern 1405 may be electrically connected to the 6th conductive pattern 1102 .

[0168] The first storage capacitor Cst11 may include a first storage capacitor Cpt11 based on a (1-1)th storage capacitor Cpt11-1, a (1-2)th storage capacitor Cpt11-2, and a (1-3)th storage capacitor Cpt11-3. As an example, the first storage capacitor Cpt11 of the first storage capacitor Cst11 may be the sum of the (1-1)th storage capacitor Cpt11-1, the (1-2)th storage capacitor Cpt11-2, and the (1-3)th storage capacitor Cpt11-3.

[0169] The first holding capacitor Chd11 may include a third conductive pattern 1003 (or a second electrode) and a sixth conductive pattern 1102. The first holding capacitor Chd11 may include a first holding electrode and a second holding electrode. The first holding electrode may be connected to Figure 5 The first holding electrode of the first holding capacitor Chd11 may include a third conductive pattern 1003 , and the second holding electrode of the first holding capacitor Chd11 may include a sixth conductive pattern 1102 .

[0170] The sixth conductive pattern 1102 may be provided on the third conductive pattern 1003, and may partially overlap the third conductive pattern 1003. The third conductive pattern 1003 and the sixth conductive pattern 1102 may constitute a first holding capacitor Cpd11 of the first holding capacitor Chd11.

[0171] In the case where “the first storage capacitor Cst11 may include the sixth conductive pattern 1102”, it may mean “the first storage capacitor Cst11 may include a portion of the sixth conductive pattern 1102 overlapping the second conductive pattern 1002”. In the case where “the first holding capacitor Chd11 may include the sixth conductive pattern 1102”, it may mean “the first holding capacitor Chd11 may include another portion of the sixth conductive pattern 1102 overlapping the third conductive pattern 1003”.

[0172] As referenced above Figure 7 As described, the areas of the second conductive pattern 1002 and the third conductive pattern 1003 can be changed by moving the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). In the case where the areas of the second conductive pattern 1002 and the third conductive pattern 1003 are changed, the area of ​​each of the second conductive pattern 1002 and the third conductive pattern 1003 overlapping the sixth conductive pattern 1102 can be changed. The first storage capacitance Cpt11 of the first storage capacitor Cst11 and the first holding capacitance Cpd11 of the first holding capacitor Chd11 can be changed.

[0173] As an example, in the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the +x direction, the area of ​​the second conductive pattern 1002 can be reduced, and the area of ​​the third conductive pattern 1003 can be increased. The first storage capacitance Cpt11 of the first storage capacitor Cst11 can be reduced, and the first retention capacitance Cpd11 of the first retention capacitor Chd11 can be increased. In the case where the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other are moved in the -x direction, the area of ​​the second conductive pattern 1002 can be increased, and the area of ​​the third conductive pattern 1003 can be reduced. The first storage capacitance Cpt11 of the first storage capacitor Cst11 can be increased, and the first retention capacitance Cpd11 of the first retention capacitor Chd11 can be reduced.

[0174] As described above, the capacitor of the first pixel circuit PC11, the capacitor of the second pixel circuit PC12, and the capacitor of the third pixel circuit PC13 can be formed differently by moving the positions of the edge 1002e of the second conductive pattern 1002 and the edge 1003e of the third conductive pattern 1003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). As an example, the second storage capacitance Cpt12 of the second storage capacitor Cst12 can be greater than the first storage capacitance Cpt11 of the first storage capacitor Cst11 and the third storage capacitance Cpt13 of the third storage capacitor Cst13. The third storage capacitance Cpd13 of the third storage capacitor Chd13 can be greater than the first storage capacitance Cpd11 of the first storage capacitor Chd11 and the second storage capacitance Cpd12 of the second storage capacitor Chd12.

[0175] As in the embodiment, in the case where at least some of the electrodes constituting the first storage capacitor Cst11 are disposed on the first holding capacitor Chd11, the area in which the electrodes constituting the first holding capacitor Chd11 can be arranged can be increased (or ensured). In the case where at least some of the electrodes constituting the first storage capacitor Cst11 are stacked on the first holding capacitor Chd11, the first holding capacitance Cpd11 of the first holding capacitor Chd11 can be increased (or ensured). As the first holding capacitance Cpd11 of the first holding capacitor Chd11 is increased (or ensured), the variation of the source of the first transistor T11 can be reduced. As the variation of the source of the first transistor T11 is reduced, an advantage can be achieved by reducing the data swing range while driving the pixel circuit.

[0176] In the following, reference Fig.12 The configuration of the display device is described more specifically according to the stacked structure.

[0177] The substrate 100 may include a glass material, a ceramic material and / or a metal material. The substrate 100 may include a flexible material and / or a bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin, and the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate and / or cellulose acetate propionate.

[0178] The substrate 100 may have a single layer structure or a multilayer structure of the above materials, and may further include an inorganic layer in the case of a multilayer structure. In an embodiment, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0179] The second conductive pattern 1002 and the third conductive pattern 1003 may be disposed on the substrate 100. The second conductive pattern 1002 may be separated from the third conductive pattern 1003. The second conductive pattern 1002 and the third conductive pattern 1003 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the second conductive pattern 1002 and the third conductive pattern 1003 may be a single Mo layer.

[0180] In an embodiment, a preset voltage may be applied to the third conductive pattern 1003. As an example, Figure 5 The first driving voltage ELVDD may be applied to the third conductive pattern 1003 .

[0181] The barrier layer 110 may be disposed on the substrate 100 to cover the second conductive pattern 1002 and the third conductive pattern 1003. The barrier layer 110 may prevent or reduce the penetration of impurities from the substrate 100, etc. The barrier layer 110 may include an inorganic material, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material, the inorganic material including an oxide or a nitride.

[0182] The sixth conductive pattern 1102 may be disposed on the barrier layer 110. The sixth conductive pattern 1102 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the sixth conductive pattern 1102 may include a single Mo layer.

[0183] The second conductive pattern 1002 and the sixth conductive pattern 1102 may overlap each other (the barrier layer 110 is between the second conductive pattern 1002 and the sixth conductive pattern 1102) and constitute the (1-1) storage capacitor Cpt11-1. The third conductive pattern 1003 and the sixth conductive pattern 1102 may overlap each other (the barrier layer 110 is between the third conductive pattern 1003 and the sixth conductive pattern 1102) and constitute the first holding capacitor Cpd11. The barrier layer 110 may be used as a dielectric layer of a capacitor.

[0184] The buffer layer 111 may be disposed on the barrier layer 110 to cover the sixth conductive pattern 1102. The buffer layer 111 may be configured to reduce or block penetration of foreign matter, moisture, or external air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material, an organic material, or an organic / inorganic composite material, and include a single layer or multiple layers including an inorganic material and an organic material, the inorganic material including an oxide or a nitride.

[0185] The first insulating layer 113 and the second insulating layer 115 may be stacked on the buffer layer 111. The first insulating layer 113 and the second insulating layer 115 may each include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0186] The 11th conductive pattern 1304 may be disposed between the first insulating layer 113 and the second insulating layer 115. The 11th conductive pattern 1304 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the 11th conductive pattern 1304 may include a single Mo layer.

[0187] The sixth conductive pattern 1102 and the eleventh conductive pattern 1304 may overlap each other (with the buffer layer 111 and the first insulating layer 113 between them) and constitute the (1-2)th storage capacitor Cpt11-2. The buffer layer 111 and the first insulating layer 113 may serve as dielectric layers of the capacitor.

[0188] The 21st conductive pattern 1405 may be disposed on the second insulating layer 115. The 21st conductive pattern 1405 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and have a single-layer structure or a multi-layer structure including the above materials. As an example, the 21st conductive pattern 1405 may have a multi-layer structure of Ti / Al / Ti.

[0189] The 11th conductive pattern 1304 and the 21st conductive pattern 1405 may overlap each other (with the second insulating layer 115 between the 11th conductive pattern 1304 and the 21st conductive pattern 1405) and constitute the (1-3)th storage capacitor Cpt11-3. The second insulating layer 115 may function as a dielectric layer of the capacitor.

[0190] The third insulating layer 117 and the fourth insulating layer 119 may be stacked on the second insulating layer 115 to cover the 21st conductive pattern 1405. The third insulating layer 117 and the fourth insulating layer 119 may include a single layer or a multilayer including an organic material and provide a flat upper surface. The third insulating layer 117 and the fourth insulating layer 119 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0191] The 27th conductive pattern 1503 and the 28th conductive pattern 1504 may be disposed between the third insulating layer 117 and the fourth insulating layer 119. The 27th conductive pattern 1503 and the 28th conductive pattern 1504 may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and have a single-layer structure or a multi-layer structure including the above materials. As an example, the 27th conductive pattern 1503 and the 28th conductive pattern 1504 may each have a multi-layer structure of Ti / Al / Ti.

[0192] The display element 300 may be disposed on the fourth insulating layer 119. The display element 300 may be an organic light emitting diode OLED, and may include a pixel electrode 310, an intermediate layer 320 having an organic emission layer, and an opposite electrode 330.

[0193] The pixel electrode 310 may be a (semi) light-transmitting electrode or a reflective electrode. In an embodiment, the pixel electrode 310 may include a reflective layer and a transparent electrode layer or a semi-transparent electrode layer on the reflective layer. The reflective layer may include at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and compounds thereof. The transparent electrode layer or the semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 310 may include ITO / Ag / ITO.

[0194] In the display area of ​​the substrate 100, a pixel defining layer 121 may be disposed on the fourth insulating layer 119. The pixel defining layer 121 may cover the edge of the pixel electrode 310 and include an opening exposing a central portion of the pixel electrode 310. The emission area of ​​the display element 300 may be defined by the opening.

[0195] The pixel defining layer 121 may prevent arcing or the like from occurring at the edge of each pixel electrode 310 by increasing the distance between the edge of each pixel electrode 310 and the opposing electrode 330 above the pixel electrode 310 .

[0196] The pixel defining layer 121 may include an organic insulating material such as polyimide, acrylic resin, benzocyclobutene and phenolic resin, and may be formed by using spin coating, etc. The pixel defining layer 121 may include an organic insulating material. In other embodiments, the pixel defining layer 121 may include an inorganic insulating material such as silicon nitride, silicon oxynitride and / or silicon oxide. In other embodiments, the pixel defining layer 121 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 121 may include a light blocking material and be provided in black. The light blocking material may include carbon black, carbon nanotubes, a resin or paste including a black dye, particles of a metal (e.g., nickel, aluminum, molybdenum and their alloys), particles of a metal oxide (e.g., chromium oxide) or particles of a metal nitride (e.g., chromium nitride). In the case where the pixel defining layer 121 includes a light blocking material, external light reflection of a metal structure arranged below the pixel defining layer 121 may be reduced.

[0197] The intermediate layer 320 may be disposed inside the opening formed in the pixel defining layer 121 and may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue, or white light. The organic emission layer may include a high molecular weight organic material or a low molecular weight organic material. Functional layers may be selectively further arranged below and above the organic emission layer, including a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL).

[0198] The counter electrode 330 may be a light-transmitting electrode or a reflective electrode. In an embodiment, the counter electrode 330 may be a transparent electrode or a semi-transparent electrode, and may include a metal thin film containing Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof and having a small work function. Such as ITO, IZO, ZnO and / or In 2 O 3 A layer of a transparent conductive oxide (TCO) may be further disposed on the metal film. The opposing electrode 330 may be disposed throughout the display area and disposed on the intermediate layer 320 and the pixel defining layer 121. The opposing electrode 330 may be formed as one body over the display element 300 to correspond to the pixel electrode 310.

[0199] Because the display element 300 may be easily damaged by external moisture or oxygen, etc., an encapsulation layer (not shown) may protect the display element 300 by covering the display element 300. The encapsulation layer may cover the display area and extend to at least a portion of the peripheral area. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0200] Fig.13 It is along Figure 6 The line II-II' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG. Fig.13 In, with Fig.12 The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0201] refer to Fig.13 , the sixth conductive pattern 1102 may include a first opening 1102op exposing at least a portion of the barrier layer 110. The 11th conductive pattern 1304 may be connected to the second conductive pattern 1002 through a second contact hole cnta2 formed in the barrier layer 110, the buffer layer 111, and the first insulating layer 113. The second contact hole cnta2 may pass through the first opening 1102op of the sixth conductive pattern 1102.

[0202] In the embodiment, as above Figure 6 As shown in FIG. 1 , in a plan view, the first opening 1102op of the sixth conductive pattern 1102 may overlap the central portion of the second conductive pattern 1002. A connection defect between the second conductive pattern 1002 and the eleventh conductive pattern 1304 may be prevented.

[0203] Fig.14 It is along Figure 6 The line III-III' in Figure 6 A cross-sectional view of an example of a portion of a display device in FIG. Fig.14 In, with Fig.12 The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0204] refer to Fig.14 The second semiconductor pattern 1202 may be disposed between the buffer layer 111 and the first insulating layer 113 . The twenty-fifth conductive pattern 1501 may be disposed between the third insulating layer 117 and the fourth insulating layer 119 .

[0205] The 11th conductive pattern 1304 may have a second opening 1304op exposing at least a portion of the first insulating layer 113. The 21st conductive pattern 1405 may be connected to the 6th conductive pattern 1102 through the (8-1)th contact hole cnta8-1 formed in the buffer layer 111, the first insulating layer 113, and the second insulating layer 115. The 21st conductive pattern 1405 may be connected to the second semiconductor pattern 1202 through the (8-2)th contact hole cnta8-2 formed in the first insulating layer 113 and the second insulating layer 115. The (8-1)th contact hole cnta8-1 and the (8-2)th contact hole cnta8-2 may pass through the second opening 1304op of the 11th conductive pattern 1304.

[0206] Fig.15 is included in Figure 4 A schematic configuration diagram of positions of transistors and capacitors, etc. in a pixel circuit in a display device of Figures 16 to 20 is used for Fig.15 Schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in FIG. Figures 16 to 20 Describes Fig.15 The first pixel circuit PC21 is described above, but the description is also applicable to the second pixel circuit PC22 and the third pixel circuit PC23.

[0207] First, refer to Fig.15 The display device may include a first pixel circuit PC21, a second pixel circuit PC22, and a third pixel circuit PC23. The first pixel circuit PC21, the second pixel circuit PC22, and the third pixel circuit PC23 may be arranged in a first direction (eg, ±x direction).

[0208] The first pixel circuit PC21, the second pixel circuit PC22, and the third pixel circuit PC23 may each correspond to Figure 5 As an example, the first pixel circuit PC21 may include a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, and a sixth transistor T26, a first storage capacitor Cst21, and a first holding capacitor Chd21. The first transistor T21, the second transistor T22, the third transistor T23, the fourth transistor T24, the fifth transistor T25, and the sixth transistor T26 may correspond to Figure 5 The first storage capacitor Cst21 may correspond to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6. Figure 5 The storage capacitor Cst, and the first holding capacitor Chd21 may correspond to Figure 5Although the first pixel circuit PC21 has been described, the description is also applicable to the second pixel circuit PC22 and the third pixel circuit PC23. As an example, the second pixel circuit PC22 may include a second storage capacitor Cst22 and a second holding capacitor Chd22, and the third pixel circuit PC23 may include a third storage capacitor Cst23 and a third holding capacitor Chd23. The second storage capacitor Cst22 and the third storage capacitor Cst23 may each correspond to Figure 5 The storage capacitor Cst of the second storage capacitor Chd22 and the third storage capacitor Chd23 may each correspond to Figure 5 The holding capacitor Chd.

[0209] In an embodiment, the 1st pixel circuit PC21, the 2nd pixel circuit PC22 and the 3rd pixel circuit PC23 can be electrically connected to display elements configured to emit light of different colors, respectively. The 1st pixel circuit PC21, the 2nd pixel circuit PC22 and the 3rd pixel circuit PC23 can be configured to drive display elements configured to emit light of different colors, respectively. As an example, the display element electrically connected to the 1st pixel circuit PC21 can be configured to emit red light. The 1st pixel circuit PC21 can be configured to drive a display element configured to emit red light. The display element electrically connected to the 2nd pixel circuit PC22 can be configured to emit green light. The 2nd pixel circuit PC22 can be configured to drive a display element configured to emit green light. The display element electrically connected to the 3rd pixel circuit PC23 can be configured to emit blue light. The 3rd pixel circuit PC23 can be configured to drive a display element configured to emit blue light.

[0210] The first storage capacitor Cst21 of the first pixel circuit PC21 may have a first storage capacitance Cpt21, and the first holding capacitor Chd21 of the first pixel circuit PC21 may have a first holding capacitance Cpd21. The second storage capacitor Cst22 of the second pixel circuit PC22 may have a second storage capacitance Cpt22, and the second holding capacitor Chd22 of the second pixel circuit PC22 may have a second holding capacitance Cpd22. The third storage capacitor Cst23 of the third pixel circuit PC23 may have a third storage capacitance Cpt23, and the third holding capacitor Chd23 of the third pixel circuit PC23 may have a third holding capacitance Cpd23.

[0211] In an embodiment, the first storage capacitance Cpt21 of the first storage capacitor Cst21, the second storage capacitance Cpt22 of the second storage capacitor Cst22, and the third storage capacitance Cpt23 of the third storage capacitor Cst23 may be substantially equal to each other. The first holding capacitance Cpd21 of the first holding capacitor Chd21, the second holding capacitance Cpd22 of the second holding capacitor Chd22, and the third holding capacitance Cpd23 of the third holding capacitor Chd23 may be substantially equal to each other.

[0212] In another embodiment, the first storage capacitance Cpt21 of the first storage capacitor Cst21, the second storage capacitance Cpt22 of the second storage capacitor Cst22, and the third storage capacitance Cpt23 of the third storage capacitor Cst23 may be different from each other. The first holding capacitance Cpd21 of the first holding capacitor Chd21, the second holding capacitance Cpd22 of the second holding capacitor Chd22, and the third holding capacitance Cpd23 of the third holding capacitor Chd23 may be different from each other. As an example, the second storage capacitance Cpt22 of the second storage capacitor Cst22 may be greater than the first storage capacitance Cpt21 of the first storage capacitor Cst21 and the third storage capacitance Cpt23 of the third storage capacitor Cst23. The third holding capacitance Cpd23 of the third holding capacitor Chd23 may be greater than the first holding capacitance Cpd21 of the first holding capacitor Chd21 and the second holding capacitance Cpd22 of the second holding capacitor Chd22.

[0213] refer to Figures 16 to 20 More specific description Fig.15 Elements such as transistors and capacitors of the display device shown in .

[0214] Fig.16 The first conductive layer 2000 shown in FIG. 1 may be disposed on the substrate 100 (see Figure 4 ). The first conductive layer 2000 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the first conductive layer 2000 may include a single Mo layer.

[0215] The first conductive layer 2000 may include a first conductive pattern 2001, a second conductive pattern 2002, a third conductive pattern 2003, and a fourth conductive pattern 2004. The first conductive pattern 2001, the third conductive pattern 2003, and the fourth conductive pattern 2004 may extend substantially in a first direction (eg, ±x direction). The third conductive pattern 2003 may be in a state where a preset voltage is applied. As an example, Figure 5The first driving voltage ELVDD may be applied to the third conductive pattern 2003. The fourth conductive pattern 2004 may be a repair line. The first conductive pattern 2001 may correspond to Figure 5 The first scanning line GWL, the second conductive pattern 2002 may correspond to Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, and the third conductive pattern 2003 may correspond to Figure 5 The first holding electrode CEh1 of the holding capacitor Chd.

[0216] In an embodiment, the third conductive pattern 2003 may have a protrusion 2003p protruding in the second direction (e.g., ±y direction). The second conductive pattern 2002 may be arranged adjacent to the protrusion 2003p of the third conductive pattern 2003 in the first direction (e.g., ±x direction). The second conductive pattern 2002 may be arranged between the protrusions 2003p of the third conductive pattern 2003.

[0217] The areas of the second conductive pattern 2002 and the third conductive pattern 2003 may be changed by moving the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). As an example, in the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other are moved in the +x direction, the area of ​​the second conductive pattern 2002 may be reduced, and the area of ​​the third conductive pattern 2003 may be increased. In the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other are moved in the -x direction, the area of ​​the second conductive pattern 2002 may be increased, and the area of ​​the third conductive pattern 2003 may be reduced. In the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other are moved in the +y direction, the area of ​​the second conductive pattern 2002 can be reduced, and the area of ​​the third conductive pattern 2003 can be increased. In the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other are moved in the -y direction, the area of ​​the second conductive pattern 2002 can be increased, and the area of ​​the third conductive pattern 2003 can be reduced.

[0218] Fig.17The second conductive layer 2100 shown in FIG. 2 may be disposed on the first conductive layer 2000. The second conductive layer 2100 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the second conductive layer 2100 may include a single Mo layer.

[0219] The second conductive layer 2100 may include a fifth conductive pattern 2101, a sixth conductive pattern 2102, and a seventh conductive pattern 2103. The fifth conductive pattern 2101 and the seventh conductive pattern 2103 may extend substantially in the first direction (eg, ±x direction). The fifth conductive pattern 2101 and the seventh conductive pattern 2103 may be in a state of applying a preset voltage. As an example, Figure 5 A reference voltage VREF may be applied to the fifth conductive pattern 2101, and Figure 5 The initialization voltage Vint may be applied to the seventh conductive pattern 2103. A first opening 2102op may be formed in the sixth conductive pattern 2102. A conductive pattern disposed on the sixth conductive pattern 2102 may be connected to a conductive pattern disposed below the sixth conductive pattern 2102 through the first opening 2102op of the sixth conductive pattern 2102. The fifth conductive pattern 2101 may correspond to Figure 5 The sixth conductive pattern 2102 may correspond to the first voltage line VL1 of Figure 5 The 7th conductive pattern 2103 may correspond to the 2nd storage electrode CEs2 of the storage capacitor Cst and the 2nd holding electrode CEh2 of the holding capacitor Chd. Figure 5 The second voltage line VL2.

[0220] Fig.18 The semiconductor layer 2200 shown in the figure may be disposed on the second conductive layer 2100. The semiconductor layer 2200 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the semiconductor layer 2200 may be an ITZO (InSnZnO) semiconductor layer and an IGZO (InGaZnO) semiconductor layer, etc. The semiconductor layer 2200 may include a first semiconductor pattern 2201, a second semiconductor pattern 2202, a third semiconductor pattern 2203, and a fourth semiconductor pattern 2204.

[0221] If necessary, at least a portion of the semiconductor layer 2200 may be subjected to a process of being conductorized (or conductive) by plasma treatment or the like. As an example, the fourth semiconductor pattern 2204 may be conductorized (or conductive) by plasma treatment or the like. The fourth semiconductor pattern 2204 may correspond to Figure 5 The first holding electrode CEh1 of the holding capacitor Chd.

[0222] Fig.18 The third conductive layer 2300 shown in FIG. 2 may be disposed on the semiconductor layer 2200. The third conductive layer 2300 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the third conductive layer 2300 may include a single Mo layer.

[0223] The third conductive layer 2300 may include an eighth conductive pattern 2301, a ninth conductive pattern 2302, a tenth conductive pattern 2303, an eleventh conductive pattern 2304, a twelfth conductive pattern 2305, a thirteenth conductive pattern 2306, a fourteenth conductive pattern 2307, a fifteenth conductive pattern 2308, and a sixteenth conductive pattern 2309. The eighth conductive pattern 2301, the ninth conductive pattern 2302, the twelfth conductive pattern 2305, the fourteenth conductive pattern 2307, the fifteenth conductive pattern 2308, and the sixteenth conductive pattern 2309 may extend substantially in the first direction (e.g., ±x direction). A second opening 2304op may be formed in the eleventh conductive pattern 2304. A conductive pattern disposed on the eleventh conductive pattern 2304 may be connected to a semiconductor pattern and / or a conductive pattern disposed below the eleventh conductive pattern 2304 through the second opening 2304op of the eleventh conductive pattern 2304. The eighth conductive pattern 2301 may correspond to Figure 5 The 9th conductive pattern 2302 may correspond to the 1st scanning line GWL. Figure 5 The 11th conductive pattern 2304 may correspond to the 2nd scanning line GRL. Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, the twelfth conductive pattern 2305 may correspond to Figure 5 The 14th conductive pattern 2307 may correspond to the 1st emission control line EML. Figure 5 The 2nd emission control line EMBL, the 15th conductive pattern 2308 may correspond to Figure 5 The 3rd scanning line GIL, and the 16th conductive pattern 2309 may correspond to Figure 5 The second voltage line VL2.

[0224] Figure 8 The 7th conductive pattern 2103 and the 16th conductive pattern 2309 may each correspond to Figure 5 The 7th conductive pattern 2103 can be connected to the 1st pixel circuit PC21 and the 3rd pixel circuit PC23, and is configured to connect the 2nd voltage line VL2 of the pixel circuit PC21 to the 3rd pixel circuit PC23. Figure 5The initialization voltage Vint is transmitted to the first pixel circuit PC21 and the third pixel circuit PC23. The 16th conductive pattern 2309 may be connected to the second pixel circuit PC22 and configured to transmit the initialization voltage Vint to the second pixel circuit PC22.

[0225] The portion of the 10th conductive pattern 2303 overlapping with the 1st semiconductor pattern 2201 may correspond to the gate of the 2nd transistor T22. The portion of the 9th conductive pattern 2302 overlapping with the 1st semiconductor pattern 2201 may correspond to the gate of the 3rd transistor T23. The portion of the 11th conductive pattern 2304 overlapping with the 2nd semiconductor pattern 2202 may correspond to the (upper) gate of the 1st transistor T21. The portion of the 12th conductive pattern 2305 overlapping with the 2nd semiconductor pattern 2202 may correspond to the gate of the 5th transistor T25. The portion of the 14th conductive pattern 2307 overlapping with the 3rd semiconductor pattern 2203 may correspond to the gate of the 6th transistor T26. The portion of the 15th conductive pattern 2308 overlapping with the 3rd semiconductor pattern 2203 may correspond to the gate of the 4th transistor T24.

[0226] The eighth conductive pattern 2301 may be connected to the first conductive pattern 2001 through the first contact hole cntb1. The first conductive pattern 2001 and the eighth conductive pattern 2301 may constitute a double scanning line. The eleventh conductive pattern 2304 may be connected to the second conductive pattern 2002 through the second contact hole cntb2. The second conductive pattern 2002 and the eleventh conductive pattern 2304 may constitute a Figure 5 The 13th conductive pattern 2306 may be connected to the 3rd conductive pattern 2003 through the 3rd contact hole cntb3.

[0227] Fig.19 The fourth conductive layer 2400 shown in the figure may be disposed on the third conductive layer 2300. The fourth conductive layer 2400 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti) and may have a single layer structure or a multilayer structure including the above materials. As an example, the fourth conductive layer 2400 may have a multilayer structure of Ti / Al / Ti.

[0228] The fourth conductive layer 2400 may include a 17th conductive pattern 2401, an 18th conductive pattern 2402, a 19th conductive pattern 2403, a 20th conductive pattern 2404, a 21st conductive pattern 2405, a 22nd conductive pattern 2406, a 23rd conductive pattern 2407, and a 24th conductive pattern 2408. The 17th conductive pattern 2401 may extend substantially in the second direction (eg, ±y direction). The 17th conductive pattern 2401 may correspond to Figure 5The 21st conductive pattern 2405 may correspond to the data line DL. Figure 5 The second storage electrode CEs2 of the storage capacitor Cst.

[0229] The 17th conductive pattern 2401 may be connected to the 1st semiconductor pattern 2201 through the 4th contact hole cntb4. The 18th conductive pattern 2402 may be connected to the 8th conductive pattern 2301 through the (5-1)th contact hole cntb5-1, and connected to the 10th conductive pattern 2303 through the (5-2)th contact hole cntb5-2. The 19th conductive pattern 2403 may be connected to the 1st semiconductor pattern 2201 through the (6-1)th contact hole cntb6-1, and connected to the 5th conductive pattern 2101 through the (6-2)th contact hole cntb6-2. The 20th conductive pattern 2404 may be connected to the 1st semiconductor pattern 2201 through the (7-1)th contact hole cntb7-1, and connected to the 11th conductive pattern 2304 through the (7-2)th contact hole cntb7-2. The 21st conductive pattern 2405 may be connected to the 6th conductive pattern 2102 through the (8-1)th contact hole cntb8-1, connected to the 2nd semiconductor pattern 2202 through the (8-2)th contact hole cntb8-2, and connected to the 3rd semiconductor pattern 3203 through the (8-3)th contact hole cntb8-3. The 22nd conductive pattern 2406 may be connected to the 4th semiconductor pattern 2204 through the (9-1)th contact hole cntb9-1, connected to the 13th conductive pattern 2306 through the (9-2)th contact hole cntb9-2, and connected to the 2nd semiconductor pattern 3202 through the (9-3)th contact hole cntb9-3. The 23rd conductive pattern 2407 may be connected to the 3rd semiconductor pattern 2203 through the 10th contact hole cntb10. The 24th conductive pattern 2408 may be connected to the 7th conductive pattern 2103 through the (11-1)th contact hole cntb11-1, and connected to the 3rd semiconductor pattern 2203 through the (11-2)th contact hole cntb11-2.

[0230] Fig. 20 The fifth conductive layer 2500 shown in the figure may be disposed on the fourth conductive layer 2400. The fifth conductive layer 2500 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti) and may have a single layer structure or a multilayer structure including the above materials. As an example, the fifth conductive layer 2500 may have a multilayer structure of Ti / Al / Ti.

[0231] The fifth conductive layer 2500 may include a 25th conductive pattern 2501, a 26th conductive pattern 2502, a 27th conductive pattern 2503, a 28th conductive pattern 2504, and a 29th conductive pattern 2505. The 25th conductive pattern 2501, the 27th conductive pattern 2503, the 28th conductive pattern 2504, and the 29th conductive pattern 2505 may extend substantially in the second direction (eg, ±y direction). The 25th conductive pattern 2501 may correspond to Figure 5 The 27th conductive pattern 2503 may correspond to the electric line PL Figure 5 The 28th conductive pattern 2504 may correspond to the 2nd voltage line VL2. Figure 5 The common electrode, and the 29th conductive pattern 2505 may correspond to Figure 5 The first voltage line VL1.

[0232] The 25th conductive pattern 2501 can be connected to the 22nd conductive pattern 2406 through the 12th contact hole cntb12. The 26th conductive pattern 2502 can be connected to the 23rd conductive pattern 2407 through the (13-1)th contact hole cnta13-1, and connected to the anode of the display element through the (13-2)th contact hole cntb13-2.

[0233] Fig.21 It is along Fig.15 The line IV-IV' in Fig.15 A cross-sectional view of an example of a portion of a display device in FIG. Fig.21 Describes Fig.15 The first pixel circuit PC21 is shown in FIG. 1 , but the description is also applicable to the second pixel circuit PC22 and the third pixel circuit PC23. Fig.21 In, with Fig.12 The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0234] refer to Fig.21 , the first pixel circuit PC21 may include a first storage capacitor Cst21 and a first holding capacitor Chd21.

[0235] The first storage capacitor Cst21 may include a second conductive pattern 2002 (or a first electrode), a sixth conductive pattern 2102 (or a third electrode), an eleventh conductive pattern 2304 (or a fifth electrode), and a twenty-first conductive pattern 2405 (or a sixth electrode). The first storage capacitor Cst21 may include a first storage electrode and a second storage electrode. The first storage electrode may be connected to the (upper) gate of the first transistor T21, and the second storage electrode may be connected to the source of the first transistor T21. The first storage electrode of the first storage capacitor Cst21 may include the second conductive pattern 2002 and the eleventh conductive pattern 2304, and the second storage electrode of the first storage capacitor Cst21 may include the sixth conductive pattern 2102 and the twenty-first conductive pattern 2405.

[0236] The second conductive pattern 2002, the sixth conductive pattern 2102, the eleventh conductive pattern 2304, and the twenty-first conductive pattern 2405 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti) and have a single layer or multiple layers. As an example, the second conductive pattern 2002, the sixth conductive pattern 2102, and the eleventh conductive pattern 2304 may each be a single Mo layer. The twenty-first conductive pattern 2405 may have a multilayer structure of Ti / Al / Ti.

[0237] The second conductive pattern 2002 may be disposed between the substrate 100 and the barrier layer 110, the sixth conductive pattern 2102 may be disposed between the barrier layer 110 and the buffer layer 111, the eleventh conductive pattern 2304 may be disposed between the first insulating layer 113 and the second insulating layer 115, and the twenty-first conductive pattern 2405 may be disposed between the second insulating layer 115 and the third insulating layer 117. The second conductive pattern 2002 and the sixth conductive pattern 2102 may overlap with each other (the barrier layer 110 is between the second conductive pattern 2002 and the sixth conductive pattern 2102) and constitute the (1-1)th storage capacitor Cpt21-1. The sixth conductive pattern 2102 and the eleventh conductive pattern 2304 may overlap with each other (the buffer layer 111 and the first insulating layer 113 are between the sixth conductive pattern 2102 and the eleventh conductive pattern 2304) and constitute the (1-2)th storage capacitor Cpt21-2. The 11th conductive pattern 2304 and the 21st conductive pattern 2405 may overlap each other (with the second insulating layer 115 between the 11th conductive pattern 2304 and the 21st conductive pattern 2405) and constitute the (1-3)th storage capacitor Cpt21-3. The barrier layer 110, the buffer layer 111, the first insulating layer 113 and the second insulating layer 115 may serve as dielectric layers.

[0238] The second conductive pattern 2002 may be connected to the 11th conductive pattern 2304 through the second contact hole cntb2 formed in the barrier layer 110, the buffer layer 111, and the first insulating layer 113. The second contact hole cntb2 may pass through the first opening 2102op of the sixth conductive pattern 2102. The sixth conductive pattern 2102 may be connected to the 21st conductive pattern 2405 through the (8-1)th contact hole cntb8-1 formed in the buffer layer 111, the first insulating layer 113, and the second insulating layer 115. The (8-1)th contact hole cntb8-1 may pass through the second opening 2304op of the 11th conductive pattern 2304.

[0239] The first storage capacitor Cst21 may include a first storage capacitor Cpt21 based on a (1-1)th storage capacitor Cpt21-1, a (1-2)th storage capacitor Cpt21-2, and a (1-3)th storage capacitor Cpt21-3. As an example, the first storage capacitor Cpt21 of the first storage capacitor Cst21 may be the sum of the (1-1)th storage capacitor Cpt21-1, the (1-2)th storage capacitor Cpt21-2, and the (1-3)th storage capacitor Cpt21-3.

[0240] The first holding capacitor Chd21 may include a third conductive pattern 2003 (or a second electrode), a sixth conductive pattern 2102, and a fourth semiconductor pattern 2204 (or a fourth electrode). The first holding capacitor Chd21 may include a first holding electrode and a second holding electrode. The first holding electrode may be connected to Figure 5 The first holding electrode of the first holding capacitor Chd21 may include the third conductive pattern 2003 and the fourth semiconductor pattern 2204, and the second holding electrode of the first holding capacitor Chd21 may include the sixth conductive pattern 2102.

[0241] The third conductive pattern 2003 and the sixth conductive pattern 2102 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the third conductive pattern 2003 and the sixth conductive pattern 2102 may be a single Mo layer. The fourth semiconductor pattern 2204 may include an oxide semiconductor material. The fourth semiconductor pattern 2204 may include, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The fourth semiconductor pattern 2204 may be conductorized (or conductive) by plasma treatment, etc.

[0242] The third conductive pattern 2003 may be disposed between the substrate 100 and the barrier layer 110, the sixth conductive pattern 2102 may be disposed between the barrier layer 110 and the buffer layer 111, and the fourth semiconductor pattern 2204 may be disposed between the buffer layer 111 and the first insulating layer 113. The third conductive pattern 2003 may be separated from the second conductive pattern 2002. The third conductive pattern 2003 and the sixth conductive pattern 2102 may overlap with each other (the barrier layer 110 is between the third conductive pattern 2003 and the sixth conductive pattern 2102) and constitute the (1-1)th holding capacitor Cpd21-1. The sixth conductive pattern 2102 and the fourth semiconductor pattern 2204 may overlap with each other (the buffer layer 111 is between the sixth conductive pattern 2102 and the fourth semiconductor pattern 2204) and constitute the (1-2)th holding capacitor Cpd21-2. The barrier layer 110 and the buffer layer 111 may serve as dielectric layers of a capacitor.

[0243] A preset voltage may be applied to the third conductive pattern 2003 and the fourth semiconductor pattern 2204. As an example, Figure 5 The first driving voltage ELVDD may be applied to the third conductive pattern 2003 and the fourth semiconductor pattern 2204 .

[0244] The third conductive pattern 2003 may be electrically connected to the fourth semiconductor pattern 2204. As an example, the third conductive pattern 2003 may be connected to the 13th conductive pattern 2306 through the third contact hole cntb3 formed in the barrier layer 110, the buffer layer 111, and the first insulating layer 113. The fourth semiconductor pattern 2204 may be connected to the 22nd conductive pattern 2406 through the (9-1)th contact hole cntb9-1 formed in the first insulating layer 113 and the second insulating layer 115. The 13th conductive pattern 2306 may be connected to the 22nd conductive pattern 2406 through the (9-2)th contact hole cntb9-2 formed in the second insulating layer 115. The 22nd conductive pattern 2406 may be connected to the 25th conductive pattern 2501 through the 12th contact hole cntb12 formed in the third insulating layer 117.

[0245] The first holding capacitor Chd21 may have a first holding capacitor Cpd21 based on the (1-1)th holding capacitor Cpd21-1 and the (1-2)th holding capacitor Cpd21-2. As an example, the first holding capacitor Chd21 may be the sum of the (1-1)th holding capacitor Cpd21-1 and the (1-2)th holding capacitor Cpd21-2.

[0246] In the case where “the first storage capacitor Cst21 may include the sixth conductive pattern 2102”, it may mean “the first storage capacitor Cst21 may include a portion of the sixth conductive pattern 2102 overlapping the second conductive pattern 2002 and the eleventh conductive pattern 2304”. In the case where “the first holding capacitor Chd21 may include the sixth conductive pattern 2102”, it may mean “the first holding capacitor Chd21 may include another portion of the sixth conductive pattern 2102 overlapping the third conductive pattern 2003 and the fourth semiconductor pattern 2204”.

[0247] As referenced above Fig.16 As described above, the areas of the second conductive pattern 2002 and the third conductive pattern 2003 can be changed by moving the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). In the case where the areas of the second conductive pattern 2002 and the third conductive pattern 2003 are changed, the area of ​​each of the second conductive pattern 2002 and the third conductive pattern 2003 overlapping the sixth conductive pattern 2102 can be changed. The first storage capacitance Cpt21 of the first storage capacitor Cst21 and the first holding capacitance Cpd21 of the first holding capacitor Chd21 can be changed.

[0248] As an example, in the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other move in the +x direction, the area of ​​the second conductive pattern 2002 can be reduced, and the area of ​​the third conductive pattern 2003 can be increased. The first storage capacitance Cpt21 of the first storage capacitor Cst21 can be reduced, and the first retention capacitance Cpd21 of the first retention capacitor Chd21 can be increased. In the case where the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other move in the -x direction, the area of ​​the second conductive pattern 2002 can be increased, and the area of ​​the third conductive pattern 2003 can be reduced. The first storage capacitance Cpt21 of the first storage capacitor Cst21 can be increased, and the first retention capacitance Cpd21 of the first retention capacitor Chd21 can be reduced.

[0249] As described above, the capacitor of the first pixel circuit PC21, the capacitor of the second pixel circuit PC22, and the capacitor of the third pixel circuit PC23 can be formed differently by moving the positions of the edge 2002e of the second conductive pattern 2002 and the edge 2003e of the third conductive pattern 2003 facing each other in the first direction (e.g., ±x direction) and / or the second direction (e.g., ±y direction). As an example, the second storage capacitance Cpt22 of the second storage capacitor Cst22 can be greater than the first storage capacitance Cpt21 of the first storage capacitor Cst21 and the third storage capacitance Cpt23 of the third storage capacitor Cst23. The third storage capacitance Cpd23 of the third storage capacitor Chd23 can be greater than the first storage capacitance Cpd21 of the first storage capacitor Chd21 and the second storage capacitance Cpd22 of the second storage capacitor Chd22.

[0250] As in the embodiment, in the case where at least some of the electrodes constituting the first storage capacitor Cst21 are disposed on the first holding capacitor Chd21, the area in which the electrodes constituting the first holding capacitor Chd21 can be arranged can be increased (or ensured). In the case where at least some of the electrodes constituting the first storage capacitor Cst21 are stacked on the first holding capacitor Chd21, the first holding capacitance Cpd21 of the first holding capacitor Chd21 can be increased (or ensured). In the case where the electrodes constituting the first holding capacitor Chd21 are stacked in a multilayer structure, the first holding capacitance Cpd21 of the first holding capacitor Chd21 can be further increased (or ensured). As the first holding capacitance Cpd21 of the first holding capacitor Chd21 is increased (or ensured), the variation of the source of the first transistor T21 can be reduced. As the variation of the source of the first transistor T21 is reduced, an advantage can be achieved by reducing the data swing range while driving the pixel circuit.

[0251] Fig. 22 is included in Figure 4 A schematic configuration diagram of positions of transistors and capacitors, etc. in a pixel circuit in a display device of Figure 23 to Figure 27 is used for Fig. 22 Schematic configuration diagram of elements such as transistors and capacitors of layers of a display device shown in FIG. Figure 23 to Figure 27 Describes Fig. 22 The first pixel circuit PC31 is described above, but the description is also applicable to the second pixel circuit PC32 and the third pixel circuit PC33.

[0252] First, refer to Fig. 22, the display device may include a first pixel circuit PC31, a second pixel circuit PC32, and a third pixel circuit PC33. The first pixel circuit PC31, the second pixel circuit PC32, and the third pixel circuit PC33 may be arranged in a first direction (eg, ±x direction).

[0253] The first pixel circuit PC31, the second pixel circuit PC32, and the third pixel circuit PC33 may each correspond to Figure 5 As an example, the first pixel circuit PC31 may include a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, a fifth transistor T35, and a sixth transistor T36, a first storage capacitor Cst31, and a first holding capacitor Chd31. The first transistor T31, the second transistor T32, the third transistor T33, the fourth transistor T34, the fifth transistor T35, and the sixth transistor T36 may correspond to Figure 5 The first storage capacitor Cst31 may correspond to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6. Figure 5 The storage capacitor Cst, and the first holding capacitor Chd31 may correspond to Figure 5 Although the first pixel circuit PC31 has been described, the description is also applicable to the second pixel circuit PC32 and the third pixel circuit PC33. As an example, the second pixel circuit PC32 may include a second storage capacitor Cst32 and a second holding capacitor Chd32, and the third pixel circuit PC33 may include a third storage capacitor Cst33 and a third holding capacitor Chd33. The second storage capacitor Cst32 and the third storage capacitor Cst33 may each correspond to Figure 5 The storage capacitor Cst of the second storage capacitor Chd32 and the third storage capacitor Chd33 may each correspond to Figure 5 The holding capacitor Chd.

[0254] In an embodiment, the 1st pixel circuit PC31, the 2nd pixel circuit PC32 and the 3rd pixel circuit PC33 can be electrically connected to display elements configured to emit light of different colors, respectively. The 1st pixel circuit PC31, the 2nd pixel circuit PC32 and the 3rd pixel circuit PC33 can be configured to drive display elements configured to emit light of different colors, respectively. As an example, the display element electrically connected to the 1st pixel circuit PC31 can be configured to emit red light. The 1st pixel circuit PC31 can be configured to drive a display element configured to emit red light. The display element electrically connected to the 2nd pixel circuit PC32 can be configured to emit green light. The 2nd pixel circuit PC32 can be configured to drive a display element configured to emit green light. The display element electrically connected to the 3rd pixel circuit PC33 can be configured to emit blue light. The 3rd pixel circuit PC33 can be configured to drive a display element configured to emit blue light.

[0255] The first storage capacitor Cst31 of the first pixel circuit PC31 may have a first storage capacitance Cpt31, and the first retention capacitor Chd31 of the first pixel circuit PC31 may have a first retention capacitance Cpd31. The second storage capacitor Cst32 of the second pixel circuit PC32 may have a second storage capacitance Cpt32, and the second retention capacitor Chd32 of the second pixel circuit PC32 may have a second retention capacitance Cpd32. The third storage capacitor Cst33 of the third pixel circuit PC33 may have a third storage capacitance Cpt33, and the third retention capacitor Chd33 of the third pixel circuit PC33 may have a third retention capacitance Cpd33.

[0256] In an embodiment, the first storage capacitance Cpt31 of the first storage capacitor Cst31, the second storage capacitance Cpt32 of the second storage capacitor Cst32, and the third storage capacitance Cpt33 of the third storage capacitor Cst33 may be substantially equal to each other. The first holding capacitance Cpd31 of the first holding capacitor Chd31, the second holding capacitance Cpd32 of the second holding capacitor Chd32, and the third holding capacitance Cpd33 of the third holding capacitor Chd33 may be substantially equal to each other.

[0257] In another embodiment, the first storage capacitance Cpt31 of the first storage capacitor Cst31, the second storage capacitance Cpt32 of the second storage capacitor Cst32, and the third storage capacitance Cpt33 of the third storage capacitor Cst33 may be different from each other. The first holding capacitance Cpd31 of the first holding capacitor Chd31, the second holding capacitance Cpd32 of the second holding capacitor Chd32, and the third holding capacitance Cpd33 of the third holding capacitor Chd33 may be different from each other. As an example, the second storage capacitance Cpt32 of the second storage capacitor Cst32 may be greater than the first storage capacitance Cpt31 of the first storage capacitor Cst31 and the third storage capacitance Cpt33 of the third storage capacitor Cst33. The third holding capacitance Cpd33 of the third holding capacitor Chd33 may be greater than the first holding capacitance Cpd31 of the first holding capacitor Chd31 and the second holding capacitance Cpd32 of the second holding capacitor Chd32.

[0258] refer to Figure 23 to Figure 27 More specific description Fig. 22 Elements such as transistors and capacitors of the display device shown in .

[0259] Fig.23 The first conductive layer 3000 shown in FIG. 1 may be disposed on the substrate 100 (see Figure 4 ). The first conductive layer 3000 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the first conductive layer 3000 may include a single Mo layer.

[0260] The first conductive layer 3000 may include a first conductive pattern 3001, a second conductive pattern 3002, a third conductive pattern 3003, and a fourth conductive pattern 3004. The first conductive pattern 3001 and the fourth conductive pattern 3004 may extend substantially in a first direction (eg, ±x direction). The fourth conductive pattern 3004 may be a repair line. The first conductive pattern 3001 may correspond to Figure 5 The first scanning line GWL, the second conductive pattern 3002 may correspond to Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, and the third conductive pattern 3003 may correspond to Figure 5 The second holding electrode CEh2 of the holding capacitor Chd.

[0261] Fig.24 The second conductive layer 3100 shown in FIG. 3 may be disposed on the first conductive layer 3000. The second conductive layer 3100 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the second conductive layer 3100 may include a single Mo layer.

[0262] The second conductive layer 3100 may include a fifth conductive pattern 3101, a sixth conductive pattern 3102, a seventh conductive pattern 3103, an eighth conductive pattern 3104, and a ninth conductive pattern 3105. The fifth conductive pattern 3101, the seventh conductive pattern 3103, the eighth conductive pattern 3104, and the ninth conductive pattern 3105 may extend substantially in the first direction (e.g., ±x direction). The fifth conductive pattern 3101, the seventh conductive pattern 3103, the eighth conductive pattern 3104, and the ninth conductive pattern 3105 may be in a state where a preset voltage is applied. As an example, Figure 5 The reference voltage VREF can be applied to the fifth conductive pattern 3101, Figure 5 The first driving voltage ELVDD may be applied to the seventh conductive pattern 3103, and Figure 5 The initialization voltage Vint may be applied to the 8th conductive pattern 3104 and the 9th conductive pattern 3105. The 5th conductive pattern 3101 may correspond to Figure 5 The first voltage line VL1, the sixth conductive pattern 3102 may correspond to Figure 5 The 7th conductive pattern 3103 may correspond to the 2nd storage electrode CEs2 of the storage capacitor Cst. Figure 5 The first holding electrode CEh1 of the holding capacitor Chd, and the eighth conductive pattern 3104 and the ninth conductive pattern 3105 may correspond to Figure 5 The second voltage line VL2.

[0263] In an embodiment, the seventh conductive pattern 3103 may have a protrusion 3103p protruding in the second direction (e.g., ±y direction). The sixth conductive pattern 3102 may be arranged adjacent to the protrusion 3103p of the seventh conductive pattern 3103 in the first direction (e.g., ±x direction). The sixth conductive pattern 3102 may be arranged between the protrusions 3103p of the seventh conductive pattern 3103.

[0264] The eighth conductive pattern 3104 and the ninth conductive pattern 3105 may each correspond to Figure 5 The 8th conductive pattern 3104 can be connected to the 1st pixel circuit PC31 and the 3rd pixel circuit PC33, and is configured to connect the 2nd voltage line VL2 of the 8th conductive pattern 3104 to different pixel circuits. Figure 5 The initialization voltage Vint is transmitted to the first pixel circuit PC31 and the third pixel circuit PC33. The ninth conductive pattern 3105 may be connected to the second pixel circuit PC32 and is configured to transmit the initialization voltage Vint to the second pixel circuit PC32.

[0265] Fig.25The semiconductor layer 3200 shown in the figure may be disposed on the second conductive layer 2100. The semiconductor layer 3200 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the semiconductor layer 3200 may be an ITZO (InSnZnO) semiconductor layer and an IGZO (InGaZnO) semiconductor layer, etc. If necessary, a process of being conductorized (or conductive) by plasma treatment, etc. may be performed on at least a portion of the semiconductor layer 3200. The semiconductor layer 3200 may include a first semiconductor pattern 3201, a second semiconductor pattern 3202, and a third semiconductor pattern 3203.

[0266] Fig.25 The third conductive layer 3300 shown in FIG. 3 may be disposed on the semiconductor layer 3200. The third conductive layer 3300 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may include a single layer or multiple layers. As an example, the third conductive layer 3300 may include a single Mo layer.

[0267] The third conductive layer 3300 may include a 10th conductive pattern 3301, an 11th conductive pattern 3302, a 12th conductive pattern 3303, a 13th conductive pattern 3304, a 14th conductive pattern 3305, a 15th conductive pattern 3306, a 16th conductive pattern 3307, a 17th conductive pattern 3308, and an 18th conductive pattern 3309. The 10th conductive pattern 3301, the 11th conductive pattern 3302, the 15th conductive pattern 3306, the 16th conductive pattern 3307, and the 17th conductive pattern 3308 may extend substantially in the first direction (e.g., ±x direction). The 10th conductive pattern 3301 may correspond to Figure 5 The 11th conductive pattern 3302 may correspond to the 1st scanning line GWL. Figure 5 The 2nd scanning line GRL, the 14th conductive pattern 3305 may correspond to Figure 5 The first storage electrode CEs1 of the storage capacitor Cst, the fifteenth conductive pattern 3306 may correspond to Figure 5 The 1st emission control line EML, the 16th conductive pattern 3307 may correspond to Figure 5 The 2nd emission control line EMBL, and the 17th conductive pattern 3308 may correspond to Figure 5 The 3rd scan line GIL.

[0268] The portion of the 12th conductive pattern 3303 overlapping with the first semiconductor pattern 3201 may correspond to the gate of the second transistor T32. The portion of the 11th conductive pattern 3302 overlapping with the first semiconductor pattern 3201 may correspond to the gate of the third transistor T33. The portion of the 14th conductive pattern 3305 overlapping with the second semiconductor pattern 3202 may correspond to the gate of the first transistor T31. The portion of the 15th conductive pattern 3306 overlapping with the second semiconductor pattern 3202 may correspond to the gate of the fifth transistor T35. The portion of the 16th conductive pattern 3307 overlapping with the third semiconductor pattern 3203 may correspond to the gate of the sixth transistor T36. The portion of the 17th conductive pattern 3308 overlapping with the third semiconductor pattern 3203 may correspond to the gate of the fourth transistor T34.

[0269] The tenth conductive pattern 3301 may be connected to the first conductive pattern 3001 through the first contact hole cntc1. The thirteenth conductive pattern 3304 may be connected to the third conductive pattern 3003 through the second contact hole cntc2. The fourteenth conductive pattern 3305 may be connected to the second conductive pattern 3002 through the third contact hole cntc3. The second conductive pattern 3002 and the fourteenth conductive pattern 3305 may constitute Figure 5 The first storage electrode CEs1 of the storage capacitor Cst.

[0270] Fig.26 The fourth conductive layer 3400 shown in the figure may be disposed on the third conductive layer 3300. The fourth conductive layer 3400 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti) and may have a single layer structure or a multilayer structure including the above materials. As an example, the fourth conductive layer 3400 may have a multilayer structure of Ti / Al / Ti.

[0271] The fourth conductive layer 3400 may include a 19th conductive pattern 3401, a 20th conductive pattern 3402, a 21st conductive pattern 3403, a 22nd conductive pattern 3404, a 23rd conductive pattern 3405, a 24th conductive pattern 3406, a 25th conductive pattern 3407, and a 26th conductive pattern 3408. The 19th conductive pattern 3401 may extend substantially in the second direction (eg, ±y direction). The 19th conductive pattern 3401 may correspond to Figure 5 The 23rd conductive pattern 3405 may correspond to the data line DL. Figure 5 The second storage electrode CEs2 of the storage capacitor Cst.

[0272] The 19th conductive pattern 3401 may be connected to the 1st semiconductor pattern 3201 through the 4th contact hole cntc4. The 20th conductive pattern 3402 may be connected to the 10th conductive pattern 3301 through the (5-1)th contact hole cntc5-1, and connected to the 12th conductive pattern 3303 through the (5-2)th contact hole cntc5-2. The 21st conductive pattern 3403 may be connected to the 1st semiconductor pattern 3201 through the (6-1)th contact hole cntc6-1, and connected to the 5th conductive pattern 3101 through the (6-2)th contact hole cntc6-2. The 22nd conductive pattern 3404 may be connected to the 1st semiconductor pattern 3201 through the (7-1)th contact hole cntc7-1, and connected to the 14th conductive pattern 3305 through the (7-2)th contact hole cntc7-2. The 23rd conductive pattern 3405 may be connected to the 13th conductive pattern 3304 through the (8-1)th contact hole cntc8-1, connected to the 6th conductive pattern 3102 through the (8-2)th contact hole cntc8-2, connected to the 2nd semiconductor pattern 3202 through the (8-3)th contact hole cntc8-3, and connected to the 3rd semiconductor pattern 3203 through the (8-4)th contact hole cntc8-4. The 24th conductive pattern 3406 may be connected to the 7th conductive pattern 3103 through the (9-1)th contact hole cntc9-1, and connected to the 2nd semiconductor pattern 3202 through the (9-2)th contact hole cntc9-2. The 25th conductive pattern 3407 may be connected to the 3rd semiconductor pattern 3203 through the 10th contact hole cntc10. The 26th conductive pattern 3408 may be connected to the 8th conductive pattern 3104 through the (11-1)th contact hole cntc11-1, and connected to the 3rd semiconductor pattern 3203 through the (11-2)th contact hole cntc11-2.

[0273] Fig. 27 The fifth conductive layer 3500 shown in the figure may be disposed on the fourth conductive layer 3400. The fifth conductive layer 3500 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti) and have a single layer structure or a multilayer structure including the above materials. As an example, the fifth conductive layer 3500 may have a multilayer structure of Ti / Al / Ti.

[0274] The fifth conductive layer 3500 may include a 27th conductive pattern 3501, a 28th conductive pattern 3502, a 29th conductive pattern 3503, a 30th conductive pattern 3504, and a 31st conductive pattern 3505. The 27th conductive pattern 3501, the 29th conductive pattern 3503, the 30th conductive pattern 3504, and the 31st conductive pattern 3505 may extend substantially in the second direction (eg, ±y direction). The 27th conductive pattern 3501 may correspond to Figure 5The 29th conductive pattern 3503 may correspond to the electric line PL Figure 5 The 30th conductive pattern 3504 may correspond to the second voltage line VL2. Figure 5 The common electrode, and the 31st conductive pattern 3505 may correspond to Figure 5 The first voltage line VL1.

[0275] The 27th conductive pattern 3501 can be connected to the 24th conductive pattern 3406 through the 12th contact hole cntc12. The 28th conductive pattern 3502 can be connected to the anode of the display element through the (13-1)th contact hole cntc13-1, and connected to the 25th conductive pattern 3407 through the (13-2)th contact hole cntc13-2. The 29th conductive pattern 3503 can be connected to the 26th conductive pattern 3408 through the 14th contact hole cntc14. The 31st conductive pattern 3505 can be connected to the 21st conductive pattern 3403 of the 3rd pixel circuit PC33 through the 15th contact hole cntc15.

[0276] Fig.28 are respectively along Fig. 22 The line V-V' and line VI-VI' in Fig. 22 A cross-sectional view of an example of a portion of a display device. Fig.28 Describes Fig. 22 The first pixel circuit PC31 is shown in FIG. 1 , but the description is also applicable to the second pixel circuit PC32 and the third pixel circuit PC33. Fig.28 In, with Fig.12 The same reference numerals as in the drawings denote the same components, and thus, repeated descriptions thereof are omitted.

[0277] refer to Fig.28 , the first pixel circuit PC31 may include a first storage capacitor Cst31 and a first holding capacitor Chd31.

[0278] The first storage capacitor Cst31 may include a second conductive pattern 3002 (or a first electrode), a sixth conductive pattern 3102 (or a third electrode), a fourteenth conductive pattern 3305 (or a fifth electrode), and a twenty-third conductive pattern 3405 (or a sixth electrode). The first storage capacitor Cst31 may include a first storage electrode and a second storage electrode. The first storage electrode may be connected to the (upper) gate of the first transistor T31, and the second storage electrode may be connected to the source of the first transistor T31. The first storage electrode of the first storage capacitor Cst31 may include the second conductive pattern 3002 and the fourteenth conductive pattern 3305, and the second storage electrode of the first storage capacitor Cst31 may include the sixth conductive pattern 3102 and the twenty-third conductive pattern 3405.

[0279] The second conductive pattern 3002, the sixth conductive pattern 3102, the fourteenth conductive pattern 3305, and the twenty-third conductive pattern 3405 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti) and have a single layer or multiple layers. As an example, the second conductive pattern 3002, the sixth conductive pattern 3102, and the fourteenth conductive pattern 3305 may each be a single Mo layer. The twenty-third conductive pattern 3405 may have a multilayer structure of Ti / Al / Ti.

[0280] The second conductive pattern 3002 may be disposed between the substrate 100 and the barrier layer 110, the sixth conductive pattern 3102 may be disposed between the barrier layer 110 and the buffer layer 111, the fourteenth conductive pattern 3305 may be disposed between the first insulating layer 113 and the second insulating layer 115, and the twenty-third conductive pattern 3405 may be disposed between the second insulating layer 115 and the third insulating layer 117. The second conductive pattern 3002 and the sixth conductive pattern 3102 may overlap with each other (the barrier layer 110 is between the second conductive pattern 3002 and the sixth conductive pattern 3102) and constitute the (1-1) storage capacitor Cpt31-1. The sixth conductive pattern 3102 and the fourteenth conductive pattern 3305 may overlap with each other (the buffer layer 111 and the first insulating layer 113 are between the sixth conductive pattern 3102 and the fourteenth conductive pattern 3305) and constitute the (1-2) storage capacitor Cpt31-2. The 14th conductive pattern 3305 and the 23rd conductive pattern 3405 may overlap each other (the second insulating layer 115 is between the 14th conductive pattern 3305 and the 23rd conductive pattern 3405) and constitute the (1-3)th storage capacitor Cpt31-3. The barrier layer 110, the buffer layer 111, the first insulating layer 113 and the second insulating layer 115 may serve as dielectric layers.

[0281] The second conductive pattern 3002 can be connected to the 14th conductive pattern 3305 through the third contact hole cntc3 formed in the barrier layer 110, the buffer layer 111 and the first insulating layer 113. The sixth conductive pattern 3102 can be connected to the 23rd conductive pattern 3405 through the (8-2)th contact hole cntc8-2 formed in the buffer layer 111, the first insulating layer 113 and the second insulating layer 115.

[0282] The first storage capacitor Cst31 may include a first storage capacitor Cpt31 based on a (1-1)th storage capacitor Cpt31-1, a (1-2)th storage capacitor Cpt31-2, and a (1-3)th storage capacitor Cpt31-3. As an example, the first storage capacitor Cpt31 of the first storage capacitor Cst31 may be the sum of the (1-1)th storage capacitor Cpt31-1, the (1-2)th storage capacitor Cpt31-2, and the (1-3)th storage capacitor Cpt31-3.

[0283] The first holding capacitor Chd31 may include a third conductive pattern 3003 (or a second electrode) and a seventh conductive pattern 3103 (or a fourth electrode). The first holding capacitor Chd31 may include a first holding electrode and a second holding electrode. The first holding electrode may be connected to Figure 5 The first holding electrode of the first holding capacitor Chd31 may include a third conductive pattern 3003 , and the second holding electrode of the first holding capacitor Chd31 may include a seventh conductive pattern 3103 .

[0284] The third conductive pattern 3003 and the seventh conductive pattern 3103 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and include a single layer or multiple layers. As an example, the third conductive pattern 3003 and the seventh conductive pattern 3103 may be a single Mo layer.

[0285] The third conductive pattern 3003 may be disposed between the substrate 100 and the barrier layer 110, and the seventh conductive pattern 3103 may be disposed between the barrier layer 110 and the buffer layer 111. The third conductive pattern 3003 may be separated from the second conductive pattern 3002, and the seventh conductive pattern 3103 may be separated from the sixth conductive pattern 3102. The third conductive pattern 3003 may overlap with the seventh conductive pattern 3103 (the barrier layer 110 is between the third conductive pattern 3003 and the seventh conductive pattern 3103). The third conductive pattern 3003 and the seventh conductive pattern 3103 may constitute the first holding capacitor Cpd31 of the first holding capacitor Chd31. The barrier layer 110 may function as a dielectric layer of the capacitor.

[0286] In an embodiment, a preset voltage may be applied to the seventh conductive pattern 3103. As an example, Figure 5 The first driving voltage ELVDD may be applied to the seventh conductive pattern 3103. The seventh conductive pattern 3103 may be connected to the 24th conductive pattern 3406 through the (9-1)th contact hole cntc9-1 formed in the buffer layer 111, the first insulating layer 113, and the second insulating layer 115. The 24th conductive pattern 3406 may be connected to the 27th conductive pattern 3501 through the 12th contact hole cntc12 formed in the third insulating layer 117.

[0287] The third conductive pattern 3003 may be electrically connected to the 23rd conductive pattern 3405. As an example, the third conductive pattern 3003 may be connected to the 13th conductive pattern 3304 through the second contact hole cntc2 formed in the barrier layer 110, the buffer layer 111, and the first insulating layer 113. The 13th conductive pattern 3304 may be electrically connected to the 23rd conductive pattern 3405 through the (8-1)th contact hole cntc8-1 formed in the second insulating layer 115.

[0288] As in the embodiment, in the case where at least some of the electrodes constituting the first storage capacitor Cst31 are disposed on the first holding capacitor Chd31, the area in which the electrodes constituting the first holding capacitor Chd31 can be arranged can be increased (or ensured). In the case where at least some of the electrodes constituting the first storage capacitor Cst31 are stacked on the first holding capacitor Chd31, the first holding capacitance Cpd31 of the first holding capacitor Chd31 can be increased (or ensured). As the first holding capacitance Cpd31 of the first holding capacitor Chd31 is increased (or ensured), the variation of the source of the first transistor T31 can be reduced. As the variation of the source of the first transistor T31 is reduced, an advantage can be achieved by reducing the data swing range while driving the pixel circuit.

[0289] Although the description has been made with respect to a display device, the description is not limited thereto. As an example, a method of manufacturing such a display device also falls within the scope of the present disclosure.

[0290] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: The first electrode and the second electrode are disposed separately from each other on the substrate; a first insulating layer, disposed on the substrate and overlapping the first electrode and the second electrode; a third electrode disposed on the first insulating layer and overlapping the first electrode and the second electrode; a second insulating layer, disposed on the first insulating layer and overlapping the third electrode; a fourth electrode disposed on the second insulating layer, the fourth electrode overlapping the third electrode, and the fourth electrode being electrically connected to the first electrode; a third insulating layer, disposed on the second insulating layer and overlapping the fourth electrode; as well as A fifth electrode is provided on the third insulating layer, the fifth electrode overlaps with the fourth electrode, and the fifth electrode is electrically connected to the third electrode.

2. The display device according to claim 1, wherein: In a plan view, the second electrode extends substantially in a first direction and has a protruding portion protruding in a second direction intersecting the first direction, and The first electrode is provided adjacent to the protruding portion of the second electrode in the first direction.

3. The display device according to claim 1, further comprising: a first display element configured to emit light of a first color; as well as A first pixel circuit is electrically connected to the first display element and to the power line, wherein: The first pixel circuit comprises: a first transistor configured to control the magnitude of a first driving current flowing through the first display element; a first storage capacitor electrically connected between the gate of the first transistor and the source of the first transistor; and a first holding capacitor electrically connected between the power line and the source of the first transistor, The first storage capacitance of the first storage capacitor is the sum of the first capacitance between the first electrode and the third electrode, the second capacitance between the third electrode and the fourth electrode, and the third capacitance between the fourth electrode and the fifth electrode, and A first holding capacitance of the first holding capacitor is a fourth capacitance between the second electrode and the third electrode.

4. The display device according to claim 3, further comprising: a second display element configured to emit light of a second color different from the first color; as well as a second pixel circuit electrically connected to the second display element and electrically connected to the power line, wherein: The second pixel circuit comprises: a second transistor configured to control the magnitude of a second driving current flowing through the second display element; a second storage capacitor electrically connected between the gate of the second transistor and the source of the second transistor; and a second holding capacitor electrically connected between the power line and the source of the second transistor, The first storage capacitance of the first storage capacitor is greater than the second storage capacitance of the second storage capacitor, and The first holding capacitance of the first holding capacitor is smaller than the second holding capacitance of the second holding capacitor.

5. The display device according to claim 4, wherein: The first color is green, and The second color is blue.

6. The display device according to claim 1, further comprising: Display components; as well as a pixel circuit electrically connected to the display element and electrically connected to a power line, wherein The pixel circuit comprises: a first transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to the gate of the first transistor, and the second storage electrode being electrically connected to the source of the first transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the first transistor, The first storage electrode of the storage capacitor includes the first electrode and the fourth electrode, The second storage electrode of the storage capacitor includes a portion of the third electrode overlapping with the first electrode and the fifth electrode, The first holding electrode of the holding capacitor includes the second electrode, and The second holding electrode of the holding capacitor includes another portion of the third electrode that overlaps with the second electrode.

7. The display device according to claim 6, wherein: The display element comprises an anode and a cathode, The pixel circuit is electrically connected to the data line, the first voltage line and the second voltage line, and The pixel circuit further includes: a second transistor configured to electrically connect the data line to the gate of the first transistor in response to a first scanning signal; a third transistor configured to electrically connect the first voltage line to the gate of the first transistor in response to a second scan signal; a fourth transistor configured to electrically connect the second voltage line to the anode of the display element in response to a third scan signal; a fifth transistor configured to electrically connect the power line to a drain of the first transistor in response to a first emission control signal; and The sixth transistor is configured to electrically connect the source of the first transistor to the anode of the display element in response to a second emission control signal.

8. The display device according to claim 1, further comprising: The semiconductor layer is provided between the third electrode and the fourth electrode and includes an oxide semiconductor material.

9. The display device according to claim 1, wherein: The third electrode includes an opening exposing at least a portion of the first insulating layer, and The first electrode is electrically connected to the fourth electrode via a contact hole passing through the opening of the third electrode.

10. The display device according to claim 9, wherein: In a plan view, the opening of the third electrode overlaps with a central portion of the first electrode.

11. The display device according to claim 1, wherein: The fourth electrode includes an opening exposing at least a portion of the second insulating layer, and The third electrode is electrically connected to the fifth electrode via a contact hole passing through the opening of the fourth electrode.

12. A display device comprising: The first electrode and the second electrode are disposed separately from each other on the substrate; a first insulating layer, disposed on the substrate and overlapping the first electrode and the second electrode; a third electrode disposed on the first insulating layer and overlapping the first electrode and the second electrode; a second insulating layer, disposed on the first insulating layer and overlapping the third electrode; a fourth electrode disposed on the second insulating layer, the fourth electrode overlapping the third electrode, and the fourth electrode being electrically connected to the second electrode; a third insulating layer, disposed on the second insulating layer and overlapping the fourth electrode; a fifth electrode disposed on the third insulating layer, the fifth electrode overlapping the third electrode, and the fifth electrode being electrically connected to the first electrode; a fourth insulating layer, disposed on the third insulating layer and overlapping the fifth electrode; as well as A sixth electrode is provided on the fourth insulating layer, the sixth electrode overlaps with the fifth electrode, and the sixth electrode is electrically connected to the third electrode.

13. The display device according to claim 12, wherein: The fourth electrode includes an oxide semiconductor material.

14. The display device according to claim 12, wherein: In a plan view, the second electrode extends substantially in a first direction and has a protruding portion protruding in a second direction intersecting the first direction, and The first electrode is provided adjacent to the protruding portion of the second electrode in the first direction.

15. The display device according to claim 12, further comprising: Display components; as well as a pixel circuit electrically connected to the display element and electrically connected to a power line, wherein The pixel circuit comprises: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to the gate of the transistor, and the second storage electrode being electrically connected to the source of the transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the transistor, The first storage electrode of the storage capacitor includes the first electrode and the fifth electrode, The second storage electrode of the storage capacitor includes a portion of the third electrode overlapping with the first electrode and the sixth electrode, The first holding electrode of the holding capacitor includes the second electrode and the fourth electrode, and The second holding electrode of the holding capacitor includes another portion of the third electrode that overlaps with the second electrode.

16. The display device according to claim 12, further comprising: a first display element configured to emit light of a first color; as well as The first pixel circuit is electrically connected to the first display element and to the power line, wherein: The first pixel circuit comprises: a first transistor configured to control the magnitude of a first driving current flowing through the first display element; a first storage capacitor electrically connected between the gate of the first transistor and the source of the first transistor; and a first holding capacitor electrically connected between the power line and the source of the first transistor, The first storage capacitance of the first storage capacitor is the sum of the first capacitance between the first electrode and the third electrode, the second capacitance between the third electrode and the fifth electrode, and the third capacitance between the fifth electrode and the sixth electrode, and A first holding capacitance of the first holding capacitor is a sum of a fourth capacitance between the second electrode and the third electrode and a fifth capacitance between the third electrode and the fourth electrode.

17. The display device according to claim 16, further comprising: a second display element configured to emit light of a second color different from the first color; as well as a second pixel circuit electrically connected to the second display element and electrically connected to the power line, wherein: The second pixel circuit comprises: a second transistor configured to control the magnitude of a second driving current flowing through the second display element; a second storage capacitor electrically connected between the gate of the second transistor and the source of the second transistor; and a second holding capacitor electrically connected between the power line and the source of the second transistor, The first storage capacitance of the first storage capacitor is greater than the second storage capacitance of the second storage capacitor, and The first holding capacitance of the first holding capacitor is smaller than the second holding capacitance of the second holding capacitor.

18. The display device according to claim 17, wherein: The first color is green, and The second color is blue.

19. The display device according to claim 12, wherein: The third electrode includes a first opening exposing at least a portion of the first insulating layer. The fifth electrode includes a second opening exposing at least a portion of the third insulating layer, The first electrode is electrically connected to the fifth electrode through a first contact hole passing through the first opening of the third electrode, and The third electrode is electrically connected to the sixth electrode via a second contact hole passing through the second opening of the fifth electrode.

20. A display device comprising: The first electrode and the second electrode are disposed separately from each other on the substrate; a first insulating layer, disposed on the substrate and overlapping the first electrode and the second electrode; a third electrode, disposed on the first insulating layer and overlapping the first electrode; a fourth electrode, disposed on the first insulating layer, separate from the third electrode and overlapping the second electrode; a second insulating layer, disposed on the first insulating layer and overlapping the third electrode and the fourth electrode; a fifth electrode disposed on the second insulating layer, the fifth electrode overlapping the third electrode, and the fifth electrode being electrically connected to the first electrode; a third insulating layer, disposed on the second insulating layer and overlapping the fifth electrode; as well as A sixth electrode is provided on the third insulating layer, the sixth electrode overlaps with the fifth electrode, and the sixth electrode is electrically connected to the second electrode and the third electrode.

21. The display device according to claim 20, wherein: In a plan view, the fourth electrode extends substantially in a first direction and has a protruding portion protruding in a second direction intersecting the first direction, and The third electrode is provided adjacent to the protruding portion of the fourth electrode in the first direction.

22. The display device according to claim 20, further comprising: The semiconductor layer is provided between the third electrode and the fifth electrode and includes an oxide semiconductor material.

23. The display device according to claim 20, wherein: The fourth electrode is in a state where a preset voltage is applied to the fourth electrode.

24. The display device according to claim 20, further comprising: Display components; as well as a pixel circuit electrically connected to the display element and electrically connected to a power line, wherein The pixel circuit further comprises: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor electrically connected between the gate of the transistor and the source of the transistor; and a holding capacitor electrically connected between the power line and the source of the transistor, The storage capacitance of the storage capacitor is the sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fifth electrode, and a third capacitance between the fifth electrode and the sixth electrode, and The retention capacitance of the retention capacitor is a fourth capacitance between the second electrode and the fourth electrode.

25. The display device according to claim 20, further comprising: Display components; as well as a pixel circuit electrically connected to the display element and electrically connected to a power line, wherein The pixel circuit further comprises: a transistor configured to control the magnitude of a driving current flowing through the display element; a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to the gate of the transistor, and the second storage electrode being electrically connected to the source of the transistor; and a holding capacitor including a first holding electrode and a second holding electrode, the first holding electrode being electrically connected to the power line, and the second holding electrode being electrically connected to the source of the transistor, and The first storage electrode of the storage capacitor includes the first electrode and the fifth electrode, The second storage electrode of the storage capacitor includes the third electrode and the sixth electrode, The first holding electrode of the holding capacitor includes the fourth electrode, and The second holding electrode of the holding capacitor includes the second electrode.

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