Photodetector with notched light absorbing layer

Abstract

The invention relates to a photodetector having a notched light absorbing layer. A structure for a photonic chip including a photodetector and a method of forming such a structure. The structure includes a photodetector disposed on a substrate and including a light absorbing layer. The light absorbing layer includes a sidewall and a recess in the sidewall. The structure also includes a waveguide core including a portion adjacent to the recess in the sidewall of the light absorbing layer.

Description

Technical Field

[0001] The present disclosure relates to photonic chips, and more particularly to structures for photonic chips including photodetectors and methods of forming such structures. Background Art

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips include photonic integrated circuits composed of photonic components (such as modulators, polarizers, and optical couplers) that are used to manipulate light received from a light source (such as an optical fiber or a laser). Photodetectors can be used in photonic integrated circuits to convert light that can be modulated into an optical signal into an electrical signal.

[0003] The photodetector may include a light absorbing layer and a waveguide core, the waveguide core being configured to transmit light to the light absorbing layer. Back reflections reaching the waveguide core may affect the photodetector, resulting in poor responsivity and quantum efficiency. The back reflections may be due at least in part to a refractive index mismatch between the light absorbing layer material and the waveguide core material of the photodetector.

[0004] There is a need for improved structures for photonic chips including photodetectors and methods of forming such structures. Summary of the invention

[0005] In an embodiment of the present invention, a structure for a photonic chip is provided. The structure includes a photodetector located on a substrate. The photodetector includes a light absorbing layer, the light absorbing layer includes a sidewall and a notch located in the sidewall. The structure also includes a waveguide core, which includes a portion adjacent to the notch in the sidewall of the light absorbing layer.

[0006] In an embodiment of the present invention, a method for forming a structure for a photonic chip is provided. The method includes forming a photodetector on a substrate. The photodetector includes a light absorbing layer, the light absorbing layer includes a sidewall and a recess in the sidewall. The method also includes forming a waveguide core, the waveguide core includes a portion adjacent to the recess in the sidewall of the light absorbing layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain embodiments of the present invention. In the accompanying drawings, the same reference numerals represent the same features in each view.

[0008] Figure 1 is a top view of a structure at an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0009] Figure 2 It is roughly along Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0010] Figure 2A It is roughly along Figure 1 A cross-sectional view taken along line 2A-2A in FIG.

[0011] Figure 3 is Figure 1 , 2 , a top view of the structure in the manufacturing stage of the processing method after 2A.

[0012] Figure 4 It is roughly along Figure 3 A cross-sectional view taken along line 4-4 in FIG.

[0013] Figure 4A It is roughly along Figure 3 A cross-sectional view taken along line 4A-4A in FIG.

[0014] Figure 5 , 5A is Figure 3 , 4 , a top view of the structure in the manufacturing stage of the processing method after 4A.

[0015] Figure 6 , 6A is a cross-sectional view of a structure according to an alternative embodiment of the present invention.

[0016] Figure 7 , 7A is a top view of a structure according to an alternative embodiment of the present invention.

[0017] Figure 8 is a top view of a structure according to an alternative embodiment of the present invention.

[0018] Fig. 9 is a top view of a structure according to an alternative embodiment of the present invention.

[0019] Fig.10 is a top view of a structure according to an alternative embodiment of the present invention.

[0020] Fig.11 is a top view of a structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0021] refer to Figure 1 , 22A, according to an embodiment of the present invention, structure 10 includes a waveguide core 12 and a photodetector 14, which are located on and above a dielectric layer 16 and a semiconductor substrate 18. In an embodiment, dielectric layer 16 can be composed of a dielectric material such as silicon dioxide, and semiconductor substrate 18 can be composed of a semiconductor material such as single crystal silicon. In an embodiment, dielectric layer 16 can be a buried oxide layer of a silicon-on-insulator substrate, and dielectric layer 16 can provide a low refractive index cladding between waveguide core 12 and photodetector 14 from semiconductor substrate 18.

[0022] The waveguide core 12 includes a tapered portion 20 positioned adjacent to the photodetector 14. The tapered portion 20 extending longitudinally along the longitudinal axis 21 has a side wall 17 and a side wall 19 opposite the side wall 17. The photodetector 14 includes a pad 24 having side edges 23, 25, 27, 29 and a semiconductor layer 26 providing a light absorbing layer disposed inside the side edges 23, 25, 27, 29 of the pad 24. In an embodiment, the tapered portion 20 may be connected to the side edge 23 of the pad 24 such that the side walls 17, 19 directly abut the side edge 23. In an embodiment, the tapered portion 20 may be disposed equidistantly relative to the side edge 27 and the side edge 29. In an embodiment, the semiconductor layer 26 may be disposed equidistantly relative to the side edge 27 and the side edge 29.

[0023] The width dimension of the tapered portion 20 may increase as the distance from the side edge 23 of the pad 24 along the longitudinal axis 21 decreases. In an embodiment, the width dimension of the tapered portion 20 may increase linearly as the distance from the side edge 23 decreases. In an alternative embodiment, the width dimension of the tapered portion 20 may vary based on a non-linear function, such as a quadratic function, a cubic function, a parabolic function, a sine function, a cosine function, a Bessel function, or an exponential function. In an embodiment, the tapered portion 20 may include a single stage of tapering characterized by a taper angle. In an alternative embodiment, the tapered portion 20 may taper in multiple stages, each stage characterized by a different taper angle.

[0024] In alternative embodiments, the tapered portion 20 of the waveguide core 12 may taper in a height dimension and taper in a width dimension. For example, the height dimension of the tapered portion 20 may increase as the distance from the side edge 23 of the pad 24 decreases. In alternative embodiments, the semiconductor substrate 18 may include a cavity or undercut located below all or part of the tapered portion 20 of the waveguide core 12.

[0025] In an embodiment, the liner 24 of the waveguide core 12 and the photodetector 14 may be composed of a material having a refractive index greater than the refractive index of silicon dioxide. In an embodiment, the liner 24 of the waveguide core 12 and the photodetector 14 may be composed of a semiconductor material. In an embodiment, the liner 24 of the waveguide core 12 and the photodetector 14 may be composed of single crystal silicon. The liner 24 of the waveguide core 12 and the photodetector 14 may be formed by patterning a layer composed of its constituent materials using photolithography and etching processes. In an embodiment, the liner 24 of the waveguide core 12 and the photodetector 14 may be formed by patterning a semiconductor material (e.g., single crystal silicon) of a device layer of a silicon-on-insulator substrate. In an embodiment, the tapered portion 20 of the waveguide core 12 may be included in a stacked waveguide, which, for example, includes a tapered portion of another waveguide core composed of a different material (e.g., polysilicon or silicon nitride) disposed at a level higher than the tapered portion 20.

[0026] The semiconductor layer 26 of the photodetector 14 may be composed of a light absorbing material that generates charge carriers from absorbed photons of light by photoelectric conversion. In an embodiment, the semiconductor layer 26 may be composed of an intrinsic semiconductor material. In an embodiment, the semiconductor layer 26 may be composed of intrinsic germanium. In an embodiment, the semiconductor layer 26 may be composed of an intrinsic semiconductor material having a component including germanium. In alternative embodiments, the semiconductor layer 26 may be composed of a different type of semiconductor material, such as a III-V compound semiconductor material or silicon.

[0027] The semiconductor layer 26 may be formed by an epitaxial growth process. In an embodiment, the semiconductor layer 26 may be epitaxially grown in the trench 22 patterned in the liner 24, so that the semiconductor layer 26 includes a lower portion located below the top surface 28 of the liner 24 and an upper portion located above the top surface 28 of the liner 24. A hard mask composed of a dielectric material may be disposed on the top surface 28 of the liner 24 and surround the trench 22 during the epitaxial growth process, and may be removed after the epitaxial growth process. From a vertical perspective, the shape of the upper portion of the semiconductor layer 26 may follow the contour of the trench 22 patterned in the liner 24.

[0028] The semiconductor layer 26 has an end that includes a notch 30, which represents an indentation that extends into a sidewall 34 of the semiconductor layer 26. The notch 30 is disposed adjacent to the tapered portion 20 of the waveguide core 12 and the side edge 23 of the pad 24, and the notch 30 opens toward the tapered portion 20 of the waveguide core 12. The notch 30 is disposed on an area of ​​the pad 24 that is free of light absorbing material of the semiconductor layer 26. The end of the semiconductor layer 26 includes sidewalls 31, 32, 33 that surround the notch 30 and the area of ​​the pad 24 within the boundaries of the notch 30 on multiple sides. In an embodiment, the sidewalls 31, 32, 33 may intersect at a sharp corner. In an embodiment, the sidewalls 31, 32, 33 may intersect at a rounded or radiused corner. In an embodiment, the sidewalls 31, 32, 33 may be planar and may intersect at a sharp corner. In an embodiment, the side walls 31 , 32 , 33 may be planar and may intersect at rounded or radiused corners.

[0029] Semiconductor layer 26 extends longitudinally on liner 24 along longitudinal axis 36. Sidewall 31 is inclined at an acute angle relative to longitudinal axis 36 of semiconductor layer 26. Sidewall 32 is also inclined at an acute angle relative to longitudinal axis 36 of semiconductor layer 26. In an embodiment, the acute angles of sidewalls 31, 32 may be equal. Sidewall 33 may connect sidewall 31 to sidewall 32. In an embodiment, sidewall 33 may be oriented transverse to longitudinal axis 36.

[0030] Semiconductor layer 26 may also have sidewall 37 positioned adjacent to side edge 27 of pad 24, sidewall 38 positioned adjacent to side edge 25 of pad 24, and sidewall 39 positioned adjacent to side edge 29 of pad 24. Semiconductor layer 26 includes a prong disposed between adjacent portions of sidewall 31 and sidewall 37 and terminating at a portion of sidewall 34 adjacent to tapered portion 20 of waveguide core 12. Semiconductor layer 26 also includes another prong disposed between adjacent portions of sidewall 32 and sidewall 39 and terminating at another portion of sidewall 34 adjacent to tapered portion 20 of waveguide core 12. In an embodiment, sidewall 34 may be bifurcated to provide portions terminating the prong separated by notches 30. In an embodiment, the portion of sidewall 34 terminating the prong may be planar. In an alternative embodiment, the portion of sidewall 34 terminating the prong may be rounded or chamfered. In an alternative embodiment, sidewall 31 may intersect sidewall 37 at a point, and sidewall 32 may intersect sidewall 39 at a point, such that the prong is triangular rather than trapezoidal, and sidewall 34 is absent.

[0031] The sidewalls 31, 32, 33 adjacent to the notch 30 and the portion of the sidewall 34 at the tip or end of the fork can be considered to define a facet of the semiconductor layer 26 of the photodetector 14. The facet is configured to receive light from the tapered portion 20 of the waveguide core 12. In an embodiment, the longitudinal axis 36 of the semiconductor layer 26 can be aligned parallel to the longitudinal axis 21 of the tapered portion 20. In an alternative embodiment, the longitudinal axis 21 of the tapered portion 20 can be angled relative to the longitudinal axis 36 of the semiconductor layer 26. In an embodiment, the notch 30 can be symmetrical or centered about the longitudinal axis 36 so that the notch 30 has a symmetrical placement in the semiconductor layer 26.

[0032] In an embodiment, the recess 30 may extend through the entire thickness T of the semiconductor layer 26. In an alternative embodiment, the semiconductor layer 26 may be formed on the top surface 28 of the liner 24, rather than being formed within the trench 22, such that the entire thickness T of the semiconductor layer 26 is disposed above the top surface 28. In this regard, the semiconductor layer 26 may be epitaxially grown on the top surface 28 of the liner 24 and then patterned by photolithography and etching processes to shape and form the recess 30.

[0033] refer to Figure 3 , 4 , 4A, wherein the same reference numerals denote Figure 1 , 2 , 2A, and at a subsequent manufacturing stage, structure 10 may include a doped region 40 formed in a portion of liner 24 adjacent to sidewall 37 of semiconductor layer 26 and a doped region 42 formed in a portion of liner 24 adjacent to side 39 of semiconductor layer 26. Semiconductor layer 26 is laterally located between doped region 40 and doped region 42. Doped regions 40, 42 of different conductivity types may extend completely through the entire thickness of liner 24 to an underlying dielectric layer 16. Doped region 40 and doped region 42 may define an anode and a cathode, respectively, of photodetector 14.

[0034] Doped regions 40 may be formed, for example, by ion implantation, wherein an implantation mask has openings defining implantation regions of pads 24. The implantation mask may include a photoresist layer applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define openings above the regions of pads 24 to be implanted. Implantation conditions, such as ion species, dose, and kinetic energy, may be selected to adjust the electrical and physical properties of doped regions 40. After forming doped regions 40, the implantation mask may be stripped. In an embodiment, the semiconductor material of doped regions 40 may include a p-type dopant, such as boron, that provides p-type conductivity. In an alternative embodiment, due to the overlap of the openings in the implantation mask, portions of semiconductor layer 26 immediately adjacent to doped regions 40 and underlying portions of pads 24 may be implanted with p-type dopants.

[0035] Doped regions 42 may be formed, for example, by ion implantation, wherein an implantation mask has openings defining implantation regions for pads 24. The implantation mask may include a photoresist layer applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define openings above the regions of pads 24 to be implanted. Implantation conditions, such as ion species, dose, and kinetic energy, may be selected to adjust the electrical and physical properties of doped regions 42. After forming doped regions 42, the implantation mask may be stripped. In an embodiment, the semiconductor material of doped regions 42 may include an n-type dopant, such as phosphorus or arsenic, that provides n-type conductivity. In an alternative embodiment, due to the overlap of the openings in the implantation mask, portions of semiconductor layer 26 adjacent to doped regions 42 and underlying portions of pads 24 may be implanted with n-type dopants.

[0036] The portion of the liner 24 below the semiconductor layer 26 may be composed of an intrinsic semiconductor material, such as intrinsic silicon, which has not been doped by the ion implantation that forms the doped regions 40, 42. The longitudinal axis 21 of the tapered portion 20 may intersect the intrinsic portion of the liner 24. In an embodiment, the intrinsic portion of the liner 24 may extend from a side edge 23 of the liner 24 to a side edge 25 of the liner 24. The doped region 40, the intrinsic semiconductor material of the semiconductor layer 26 and the portion of the liner 24 below the semiconductor layer 26, and the doped region 42 may define a lateral pin diode structure that can implement the functionality of the photodetector 14.

[0037] The heavily doped region 41 may be formed by performing masked ion implantation in a portion of the doped region 40 adjacent to the side edge 27, and the heavily doped region 43 may be formed by performing masked ion implantation in a portion of the doped region 42 adjacent to the side edge 29. The heavily doped region 41 may be doped with the same conductivity type as the doped region 40, but with a higher dopant concentration. The heavily doped region 43 may be doped with the same conductivity type as the doped region 42, but with a higher dopant concentration.

[0038] refer to Figure 5 , 5A , wherein the same reference numerals denote Figure 3 , 4 4A, and in a subsequent manufacturing stage, a conformal dielectric layer 45 may be formed that extends across the liner 24 and the semiconductor layer 26 and follows the topography created by the semiconductor layer 26. The conformal dielectric layer 45 may be composed of a dielectric material such as silicon nitride. An additional conformal dielectric layer (not shown) composed of a dielectric material such as silicon dioxide may be disposed between the semiconductor layer 26 and the conformal dielectric layer 45.

[0039] Dielectric layers 46, 47 are formed on the waveguide core 12 and the photodetector 14. In an embodiment, the dielectric layers 46, 47 may be composed of a dielectric material (e.g., silicon dioxide) having a lower refractive index than the material of the waveguide core 12. The dielectric layer 46 may be deposited and planarized, and the dielectric layer 47 may be deposited on the planarized dielectric layer 46.

[0040] A contact 48 may be formed that completely penetrates the conformal dielectric layer 45 and the dielectric layers 46, 47 to land on the heavily doped region 41, and a contact 49 may be formed that completely penetrates the conformal dielectric layer 45 and the dielectric layers 46, 47 to land on the heavily doped region 43. The heavily doped region 41 electrically couples the contact 48 to the doped region 40 with reduced contact resistance. The heavily doped region 43 electrically couples the contact 49 to the doped region 42 with reduced contact resistance. The contacts 48, 49 may be composed of a metal such as tungsten. The doped regions 40, 42 may be biased by the contacts 48, 49, which may be coupled to an interconnect (not shown) formed in a dielectric layer above the dielectric layer 47.

[0041] In use, light, such as laser light, propagates in the waveguide core 12 toward the photodetector 14 and is coupled from the tapered portion 20 of the waveguide core 12 to the semiconductor layer 26 of the photodetector 14. The waveguide core 12 can support the propagation of light having transverse electric polarization, transverse magnetic polarization, or a combination of both polarizations. In an embodiment, the light received by the photodetector 14 can be modulated into an optical signal. The semiconductor layer 26 absorbs photons of light and converts the absorbed photons into charge carriers by photoelectric conversion. The biasing of the doped regions 40, 42 causes the charge carriers to be collected and output to provide a measurable photocurrent that varies over time.

[0042] The notches 30 formed in the semiconductor layer 26 can be used to significantly reduce optical reflection losses and insertion losses while maintaining high coupling efficiency and without introducing responsiveness loss to the embodiments of the photodetector 14. The advantages associated with the embodiments of the photodetector 14 are particularly advantageous for optical transceivers used for optical interconnects, which transmit modulated light as data over significant distances between different locations through optical fibers. For example, such optical transceivers can be deployed in data communication systems or data computing systems.

[0043] refer to Figure 6 , 6A According to an alternative embodiment, the structure 10 may be modified so that the photodetector 14 has a vertical arrangement rather than a horizontal arrangement. Figure 6 As shown, the doped region 40 may extend across the entire pad 24, the heavily doped region 41 may be disposed in the pad 24 on both sides of the semiconductor layer 26, and the doped region 42 and the heavily doped region 43 may be disposed in the upper portion of the conductor layer 26. In an alternative embodiment, as shown in FIG. Fig. 6A As shown, structure 10 may be configured with a heavily doped region 41 disposed in liner 24 adjacent only one side of semiconductor layer 26 .

[0044] In an alternative embodiment, semiconductor layer 26 may be disposed entirely on and above top surface 28 of pad 24. In an alternative embodiment, photodetector 14 may be configured as an avalanche photodetector including a region of intrinsic semiconductor material in pad 24 defining a multiplication region and an additional doped region in pad 24 defining a charge control region.

[0045] refer to Figure 7 , 7A According to an alternative embodiment, the longitudinal axis 21 of the tapered portion 20 can be tilted relative to the side edge 23 of the liner 24 and the longitudinal axis 36 of the semiconductor layer 26 to further reduce the optical return loss. In an embodiment, the longitudinal axis 36 of the semiconductor layer 26 can be oriented at an acute angle relative to the longitudinal axis 21 of the tapered portion 20. In an embodiment, as Figure 7As shown, the longitudinal axis 21 of the tapered portion 20 can be oriented to form a positive angular difference between the longitudinal axis 21 and the longitudinal axis 36. Fig. 7A As shown, the tapered portion 20 may be oriented to form a negative angular difference between the longitudinal axis 21 and the longitudinal axis 36 .

[0046] refer to Figure 8 According to an alternative embodiment, the semiconductor layer 26 can be modified to include a notch 50 in the end portion, which is longitudinally disposed at the end of the semiconductor layer 26 opposite the end portion including the notch 30. The notch 50 can be surrounded on multiple sides by sidewalls 57, 58, 59 similar to the sidewalls 31, 32, 33. The notch 50 is located adjacent to the side edge 25 of the pad 24 and is inset into the sidewall 38 ( Figure 7 In an embodiment, sidewall 38 may be bifurcated to provide portions of respective prongs terminating semiconductor layer 26 separated by notches 50 .

[0047] The structure 10 may also include a waveguide core 52 having a tapered portion 54 positioned adjacent to the side edge 25 of the pad 24, opposite the tapered portion 20 of the waveguide core 12 adjacent to the side edge 23. The tapered portion 54 of the waveguide core 52 is positioned adjacent to the notch 50 in the semiconductor layer 26. In an embodiment, the side edge 25 of the pad 24 may be located between the tapered portion 54 of the waveguide core 52 and the notch 50 in the semiconductor layer 26. The tapered portion 54 of the waveguide core 52 may be similar or identical to the tapered portion 20 of the waveguide core 12. In an embodiment, the waveguide core 52 may be composed of the same material as the waveguide core 12 and the pad 24. The sidewalls 57, 58, 59 and the remainder of the sidewall 38 surrounding the notch 50 define a facet of the semiconductor layer 26 of the photodetector 14, the facet being configured to receive light from the tapered portion 54 of the waveguide core 52. In alternative embodiments, the longitudinal axis 21 of the tapered portion 20 of the waveguide core 12 and / or the longitudinal axis 53 of the tapered portion 54 of the waveguide core 52 may be tilted, such as Figure 7 or Fig. 7A shown.

[0048] In addition to the input provided by the tapered portion 20 of the waveguide core 12, the tapered portion 54 of the waveguide core 52 can provide another input to the photodetector 14. The total optical power delivered to the photodetector 14 can be divided between the input provided by the tapered portion 20 and the input provided by the tapered portion 54. The notch 50 in the semiconductor layer 26 can significantly reduce optical reflection losses while maintaining high coupling efficiency and without introducing responsiveness loss to the photodetector 14.

[0049] refer to Fig. 9According to an embodiment of the present invention, the recess 30 may be configured as a concavity surrounded by a curved sidewall 60 rather than a concavity surrounded by planar sidewalls 31, 32, 33 ( Figure 1 The curved sidewall 60 may be characterized by a concave shape that curves inwardly and opens toward the tapered portion 20 of the waveguide core 12.

[0050] refer to Fig.10 According to an embodiment of the present invention, the recess 30 may be configured as a cusped shape surrounded by curved side walls 62, 64, rather than a flat side wall 31, 32, 33 ( Figure 1 The curved sidewalls 62, 64 may be characterized by respective convex shapes that curve outward and meet at a point to form a pointed shape that opens toward the tapered portion 20 of the waveguide core 12.

[0051] refer to Fig.11 According to an embodiment of the present invention, the recess 30 can be laterally offset relative to the longitudinal axis 36 of the semiconductor layer 26 so that the recess 30 is asymmetrically disposed in the semiconductor layer 26. Due to the lateral offset, the width dimensions of the portion of the sidewall 34 terminating the prong of the semiconductor layer 26 adjacent to the recess 30 can be different.

[0052] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0053] References herein to terms modified by approximate language such as "approximately," "about," "substantially" are not limited to the exact value specified. Approximate language may correspond to the precision of the instrument used to measure the value, and, unless instrument precision is relied upon, may indicate a range of + / - 10% of the stated value(s).

[0054] References to terms such as "vertical", "horizontal", etc. herein are by way of example and not limitation to establish a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to directions perpendicular to the horizontal direction just defined. The term "lateral" refers to a direction within a horizontal plane.

[0055] A feature that is "connected" or "coupled" to or "connected to" or "coupled to" another feature may be directly connected or coupled to or to the other features, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to or "directly connected to" or "directly coupled to" another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to or "indirectly connected to" or "indirectly coupled to" another feature if there is at least one intermediate feature. A feature that is "on" or "contacting" another feature may be directly on or in direct contact with the other features, or one or more intermediate features may be present. A feature may be "directly on" or "directly in contact with" another feature if there are no intermediate features. A feature may be "indirectly on" or "indirectly in contact with" another feature if there is at least one intermediate feature. Different features may "overlap" if one feature extends over another feature and covers a portion of another feature.

[0056] The description of various embodiments of the present invention is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are intended to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photonic chip, the structure comprising: substrate; a photodetector on the substrate, the photodetector comprising a light absorbing layer, the light absorbing layer comprising a first sidewall and a first recess in the first sidewall; as well as A first waveguide core includes a portion adjacent to the first recess in the first sidewall of the light absorbing layer.

2. The structure according to claim 1, wherein: The portion of the first waveguide core is tapered with a width dimension that increases as the distance from the first sidewall of the light absorbing layer decreases.

3. The structure according to claim 1, wherein: The light absorbing layer includes a longitudinal axis, and the first notch is centered along the first sidewall relative to the longitudinal axis.

4. The structure according to claim 1, wherein: The light absorbing layer includes a longitudinal axis, and the portion of the first waveguide core includes a longitudinal axis aligned with the longitudinal axis of the light receiving layer.

5. The structure according to claim 1, wherein: The light absorbing layer includes a longitudinal axis, and the portion of the first waveguide core includes a longitudinal axis aligned at an acute angle relative to the longitudinal axis of the light receiving layer.

6. The structure according to claim 1, wherein: The light absorbing layer includes a longitudinal axis, a second sidewall, and a third sidewall, and the first notch is located between the second sidewall and the third sidewall.

7. The structure according to claim 6, wherein: The second side wall and the third side wall are inclined at respective acute angles relative to the longitudinal axis.

8. The structure according to claim 7, wherein: The second side wall and the third side wall are bent outwardly.

9. The structure according to claim 8, wherein: The second side wall intersects the third side wall at a point.

10. The structure according to claim 7, wherein: The second side wall and the third side wall are bent inwardly.

11. The structure according to claim 1, wherein: The light absorbing layer comprises a longitudinal axis, a second sidewall, and a second recess in the second sidewall, the second recess being spaced apart from the first recess along the longitudinal axis, and the structure further comprises: A second waveguide core includes a portion adjacent to the second recess in the second sidewall of the light absorbing layer.

12. The structure according to claim 11, wherein: The portion of the first waveguide core has a longitudinal axis aligned with the longitudinal axis of the light absorbing layer, and the portion of the second waveguide core has a longitudinal axis aligned with the longitudinal axis of the light absorbing layer.

13. The structure according to claim 11, wherein: The portion of the first waveguide core has a longitudinal axis aligned at an acute angle relative to the longitudinal axis of the light absorbing layer, and the portion of the second waveguide core has a longitudinal axis aligned at an acute angle relative to the longitudinal axis of the light absorbing layer.

14. The structure according to claim 1, further comprising: a gasket connected to the portion of the first waveguide core; a first doped region in the pad, the first doped region having a first conductivity type; as well as a second doped region in the pad, the second doped region having a second conductivity type opposite to the first conductivity type, The light absorbing layer is disposed on a portion of the pad between the first doping region and the second doping region, and the portion of the pad includes an intrinsic semiconductor material.

15. The structure of claim 1, wherein: The first notch is a recess having a curved second sidewall.

16. The structure of claim 1, wherein: The first notch penetrates the entire thickness of the light absorbing layer.

17. The structure of claim 1, wherein: The first recess opens toward the portion of the first waveguide core.

18. The structure of claim 1, wherein: The light absorbing layer includes a second sidewall and a third sidewall, the first sidewall includes a first portion located between the first notch and the second sidewall, and the first sidewall includes a second portion located between the first notch and the third sidewall.

19. The structure of claim 18, wherein: The light absorbing layer includes a first fork located between the first notch and the second sidewall, and the light receiving layer includes a second fork located between the first notch and the third sidewall.

20. A method of forming a structure for a photonic chip, the method comprising: forming a photodetector on a substrate, wherein the photodetector comprises a light absorbing layer, and the light absorbing layer comprises a sidewall and a recess in the sidewall; and A waveguide core is formed, the waveguide core including a portion adjacent to the recess in the sidewall of the light absorbing layer.

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