Memory, control method thereof and electronic equipment

Abstract

The invention relates to a memory, a control method thereof and electronic equipment, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional packaging technology, the memory further comprises an interface circuit, the interface circuit is used for realizing communication between the memory and an external system, and the interface circuit is used for realizing communication between the memory and the external system. The interface circuit is arranged on the storage chip. Compared with an implementation mode that an interface circuit is generally arranged in a logic chip in the prior art, the memory provided by the invention has the advantages that the interface circuit is arranged in the memory chip, and the interface circuit is a standard memory interface, so that the design based on the memory chip does not need process migration; the design complexity and design difficulty caused by interface circuit process migration can be avoided, and the architecture iteration speed is greatly increased.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a memory and a control method thereof, and an electronic device. Background Art

[0002] A complete storage device can be divided into two main parts: interface circuits and other circuits that implement non-interface functions such as control, storage, and computing. In traditional two-dimensional memories, since the interface circuits and other circuits are integrated on the same chip, the same manufacturing process is usually used. However, with the growing demand for storage performance in computing systems, traditional two-dimensional memories have gradually encountered bottlenecks in terms of storage density, data bandwidth and other performance. In order to improve these problems, three-dimensional stacked memory technology has emerged. This technology realizes the integration of chips or structures with different functions by stacking multiple chips or structures in the vertical direction, improves the integration of memory, and significantly improves storage performance.

[0003] According to the functional composition of the chip, there are two architectures of 3D stacked memory: one is a 3D stacked memory that is entirely composed of memory chips, such as 3D NAND Flash memory; the other is a hybrid stack of memory chips and logic chips, such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM). These hybrid stacked memories use advanced packaging technology to vertically connect memory chips and logic chips, shortening the data transmission distance and achieving higher internal bandwidth and lower latency for memory chips.

[0004] Although 3D stacked memory technology has brought significant performance improvements, it faces new challenges in the design of interface circuits. In existing solutions, the number of memory chips using a hybrid stacking architecture may be single or multiple, which are vertically connected through advanced packaging technology and communicate with the outside through interface circuits located on the logic chip. However, memory chips and logic chips usually use different manufacturing processes, among which the logic chip process is often more advanced. Therefore, in order to adapt to the functional requirements of 3D stacked memory, the 3D stacked memory with a hybrid stacking architecture needs to migrate the interface circuits originally located on the memory chip in the traditional memory. This means that the interface circuit needs to be redesigned and customized under the manufacturing process framework of the logic chip to ensure the performance and compatibility of the entire 3D stacked memory system. This greatly increases the design complexity of such 3D stacked memory ( Figure 1 )

[0005] In order to achieve effective chip management, these memory chips are usually stacked vertically using advanced packaging technology, and ultimately communicate with external systems through interface circuits on logic chips. Since memory chips and logic chips are often based on different manufacturing processes, this requires us to migrate the process of the interface circuits originally integrated on the memory chips in the design of three-dimensional stacked memory.

[0006] The interface circuit is responsible for handling high-speed communication between the memory and the external system. In order to ensure signal integrity and transmission efficiency, it usually contains complex analog circuits. Therefore, the circuit process migration of the interface is not similar to the code migration or simple circuit replication in the digital circuit design process, but requires redesigning and customizing the circuit with the same function within the manufacturing process framework of the logic chip according to the interface circuit characteristics under the original memory chip process. This significantly increases the design difficulty and complexity, and also limits the development speed of iterative updates of three-dimensional stacked memory ( Figure 2 ).

[0007] Therefore, it is necessary to improve the existing memory. Summary of the invention

[0008] In response to the above problems, the present invention provides a memory, including a memory chip and a logic chip, wherein the memory chip and the logic chip are packaged using a three-dimensional packaging process, and the memory also includes an interface circuit, which is used to realize communication between the memory and an external system, and the interface circuit is arranged on the memory chip.

[0009] Optionally, the logic chip includes a memory chip control circuit, and the memory chip control circuit is connected to the interface circuit and can send corresponding operation instructions based on control instructions of an external system to control the operation of the memory chip.

[0010] Optionally, the storage chip includes multiple storage circuits and a control circuit corresponding to each of the storage circuits; the storage chip control circuit includes a control logic circuit and multiple storage controllers corresponding to the storage circuits, the control logic circuit is configured to connect to the interface circuit, receive control instructions sent by an external system, and convert them into operation instructions for the storage chip, and send them to each of the storage controllers; multiple storage controllers are connected in series and connected to the control logic circuit, each of the storage controllers is connected to the corresponding control circuit through an IO interface, and can send operation instructions to the corresponding control circuit, and the control circuit can drive the corresponding storage circuit based on the operation instructions.

[0011] Optionally, the memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

[0012] Optionally, the memory chip control circuit portion is disposed in the logic chip.

[0013] Optionally, the memory chip control circuit includes a first control circuit and a second control circuit, the first control circuit can be implemented through digital circuit design and arranged in the logic chip, and the second control circuit is arranged in the memory chip.

[0014] Optionally, the first control circuit includes: a command parser and an address decoder.

[0015] Optionally, the second control circuit includes: a refresh controller and an error correction and checker.

[0016] Compared with the existing three-dimensional stacked memory that sets the interface circuit on the logic chip, the present invention sets the interface circuit on the memory chip, which occupies part of the memory chip area. In order to eliminate the impact of storage density caused by this area occupation, the present invention migrates part of the control circuit set on the memory chip in the existing solution and sets it on the logic chip using a digital process. Therefore, although the memory chip has added an interface circuit, part of the control circuit has also been removed simultaneously, so that indicators such as the memory chip area and storage density will not be greatly affected.

[0017] In order to achieve the above-mentioned invention object, the present application provides a method for controlling a memory, wherein the memory includes a logic chip and a storage chip, and comprises the following steps:

[0018] Receiving control instructions from an external system through an interface circuit provided in the memory chip;

[0019] converting the control instruction into an operation instruction of the memory chip through a memory chip control circuit provided in the logic chip; and

[0020] The storage chip executes the operation instruction.

[0021] In order to achieve the above-mentioned purpose of the invention, the present application provides an electronic device using the memory described above.

[0022] To sum up, compared with the implementation method of the prior art in which the interface circuit is usually set on the logic chip, the memory provided in the present application sets the interface circuit on the memory chip. Since the interface circuit is a standard memory interface, its design based on the memory chip does not require process migration, which can avoid the design complexity and difficulty caused by the process migration of the interface circuit, and greatly improve the speed of architecture iteration. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of a three-dimensional packaged memory architecture in the prior art.

[0024] Figure 2 It is a schematic diagram of the architecture of the memory from two-dimensional packaging to three-dimensional packaging interface circuit process migration in the prior art.

[0025] Figure 3 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0026] Figure 4 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0027] Figure 5 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0028] Figure 6 It is a schematic diagram of the data reading and writing process of the memory provided in the embodiment of the present invention.

[0029] Figure 7 It is a schematic diagram of the steps of a memory control method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] like Figure 3 As shown, this embodiment provides a memory, which includes a memory chip 100 and a logic chip 200 packaged by a three-dimensional packaging process. The memory also includes an interface circuit 300 for communication between the memory and an external system. The interface circuit 300 is arranged on the memory chip 100.

[0032] Compared with the conventional implementation method of setting the interface circuit in the logic chip 200, the interface circuit 300 is set in the memory chip 100. Since the interface circuit 300 is a standard memory interface, its design based on the memory chip 100 does not require process migration, thus avoiding the design complexity and difficulty caused by the process migration of the interface circuit 300 and greatly improving the architecture iteration speed.

[0033] Specifically, the interface circuit is generally a SerDes (Serialization / Deserialization) circuit, which is a high-speed serial-to-parallel / parallel-to-serial data conversion interface circuit. Its implementation requires the use of analog circuit processes, including circuit design, circuit netlist simulation, layout design, parasitic parameter extraction and post-imitation, chip return test and other complex design and testing processes to ensure the correctness of the function; this means that if the interface circuit is migrated from one process to another, the above process needs to be re-performed, which brings a huge and complex workload, and the reliability cannot be guaranteed. The memory architecture provided in this embodiment sets the interface circuit on the memory chip, and does not need to migrate the interface circuit from the memory chip process to the logic chip process, thereby greatly reducing the design complexity and difficulty of the three-dimensional stacked memory, and greatly improving the architecture iteration speed of such memory.

[0034] Optionally, the logic chip 200 includes a memory chip control circuit 210 , which is connected to the interface circuit 300 and can issue corresponding operation instructions based on control instructions sent by an external system to control the operation of the memory chip 100 .

[0035] Alternatively, if Figure 4 As shown, the memory chip 100 includes a plurality of memory circuits 110 and a control circuit 120 corresponding to each memory circuit 110; the memory chip control circuit 210 includes a control logic circuit 211 and a plurality of memory controllers 212 corresponding to the memory circuits 110, the control logic circuit 211 is configured to be connected to the interface circuit 300, receive control instructions sent by an external system, and convert them into operation instructions of the memory chip 100, and send them to each memory controller 212; the plurality of memory controllers 212 are connected in series and connected to the control logic circuit 211, and each memory controller 212 is connected to the corresponding control circuit 120 through an IO package formed by IO interfaces respectively provided on the memory chip 100 and the logic chip 200 and connecting lines between the interfaces, and can send operation instructions to the corresponding control circuit 120, and the control circuit 120 can drive the corresponding memory circuit 110 based on the operation instructions.

[0036] Optionally, the logic chip 200 further includes a functional circuit 220 , which may be a logic operation circuit that can perform calculations such as addition and multiplication.

[0037] Optionally, when there are multiple memory chips 100, they are stacked in the form of a three-dimensional package on top of the logic circuit 200, and the upper memory chip 100 and the bottom memory chip 100 are connected through the IO of the advanced packaging interface and are jointly controlled by the memory controller 212 of the logic chip 200. For example, when a certain memory controller 212 on the logic chip 200 is working, it simultaneously accesses the memory circuit 110 corresponding to the memory controller 212 on each memory chip 100.

[0038] Optionally, when there are multiple memory chips 100 , all or at least some of the memory chips 100 are provided with an interface circuit 300 to communicate with an external system.

[0039] Alternatively, if Figure 5 As shown, in the present embodiment, the memory chip control circuit 210 is further defined as a first control circuit 213 and a second control circuit 214, wherein the first control circuit 213 is a control circuit that can be realized by digital circuit design, and the second control circuit 214 is a control circuit other than the first control circuit 213. Furthermore, the first control circuit 213 is arranged on the logic chip 200, and the second control circuit 214 is arranged on the memory chip 100, thereby achieving the matching of circuit configuration and process, and further effectively alleviating or even eliminating the influence of the interface circuit being changed from being arranged on the logic chip to being arranged on the memory chip on indicators such as the memory chip area and storage density.

[0040] The following is a detailed description of the principle of the memory provided in this embodiment to achieve the above technical effects: Taking a DRAM memory chip as an example, its control circuit generally includes a command parser, an address decoder, a refresh controller, an error correction and checker and other circuits. In this embodiment, if the memory chip is implemented as a DRAM, its command parser, address decoder and other control circuits can be implemented on a logic chip with a more advanced process through a digital design process. Compared with the control circuits implemented by the storage process, these control circuits implemented on the logic chip have higher performance and faster decoding speed, and can be integrated into the first control circuit 213 described above. The refresh controller, error correction and checker are closely connected with the memory circuit, so they are still set on the memory chip, which can be integrated into the second control circuit 214 described above. When the memory chip is implemented as other memory devices, its control circuit can also be set on the logic chip or the memory chip according to the feasibility of the digital implementation process, the degree of connection with the memory circuit and other considerations.

[0041] Compared with the existing three-dimensional stacked memory that sets the interface circuit on the logic chip, this embodiment sets the interface circuit on the memory chip, which occupies part of the memory chip area. In order to eliminate the impact of storage density caused by this area occupation, this embodiment migrates part of the control circuit set on the memory chip in the existing solution and sets it on the logic chip using a digital process. Therefore, although the memory chip has added an interface circuit, part of the control circuit has also been removed simultaneously, so that indicators such as the memory chip area and storage density will not be greatly affected.

[0042] Alternatively, if Figure 6 As shown, the workflow of the three-dimensional stacked memory architecture provided by this embodiment is:

[0043] When the external input read data operation signal is sent to the interface circuit of the memory chip, the interface circuit receives the relevant data and transmits the signal to the memory chip control circuit located in the logic chip. The memory chip control circuit parses and translates the signal into a memory chip read operation instruction and sends it to the memory chip. Subsequently, the memory chip performs the operation according to the input instruction and operation information, reads the data to the interface circuit and outputs it.

[0044] Optionally, in this implementation, the three-dimensional packaging of the memory uses TSV technology or Hybrid bonding technology for wiring.

[0045] Optionally, the interface circuit 300 provided in the memory chip 100 is configured to receive any signal or a combination of address input signals, data input / output signals, word or byte selection input signals, hardware reset / sector protection unlock signals, output enable signals, command lane signals, address lane signals, Ready / Busy indication signals, differential clock signals, clock enable signals, chip select signals, row address select signals, column address select signals, write enable signals, data read and write clock signals, BANK address signals, data mask signals, termination resistor signals, calibration signals, command address signals, and data bus signals.

[0046] Optionally, the memory chip 100 is a Flash memory chip, a DRAM memory chip, a SRAM memory chip, an MRAM memory chip or a RRAM memory chip.

[0047] Alternatively, if Figure 7 As shown, this embodiment provides a control method for a memory, the memory includes a logic chip and a storage chip, and the control method includes the steps of:

[0048] Receiving control instructions from an external system through an interface circuit disposed in the memory chip;

[0049] The control instruction is converted into an operation instruction of the memory chip by a memory chip control circuit arranged in the logic chip; and

[0050] The memory chip executes the operation instructions.

[0051] Optionally, this embodiment further provides an electronic device, using the memory provided by this embodiment, specifically, the electronic device may be a computer.

[0052] So far, the technical solution of the present invention has been described in conjunction with the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to the above-mentioned specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A memory, characterized in that: It includes a memory chip and a logic chip. The memory chip and the logic chip are packaged using a three-dimensional packaging process. The memory also includes an interface circuit. The interface circuit is used to realize communication between the memory and an external system. The interface circuit is arranged on the memory chip.

2. The memory according to claim 1, characterized in that: The logic chip includes a memory chip control circuit, which is connected to the interface circuit and can send corresponding operation instructions based on control instructions from an external system to control the operation of the memory chip.

3. The memory according to claim 2, characterized in that: The storage chip includes multiple storage circuits and control circuits corresponding to each of the storage circuits; the storage chip control circuit includes a control logic circuit and multiple storage controllers corresponding to the storage circuits, the control logic circuit is configured to connect to the interface circuit, receive control instructions sent by an external system, and convert them into operation instructions for the storage chip, and send them to each of the storage controllers; multiple storage controllers are connected in series and connected to the control logic circuit, each of the storage controllers is connected to the corresponding control circuit through an IO interface, and can send operation instructions to the corresponding control circuit, and the control circuit can drive the corresponding storage circuit based on the operation instructions.

4. The memory according to any one of claims 1 to 3, characterized in that: The memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

5. The memory according to claim 2 or 3, characterized in that: The control circuit part is arranged on the logic chip.

6. The memory according to claim 5, characterized in that: The control circuit includes a first control circuit and a second control circuit. The first control circuit can be implemented through digital circuit design and is arranged in the logic chip, and the second control circuit is arranged in the memory chip.

7. The memory according to claim 6, characterized in that: The first control circuit includes: a command parser and an address decoder.

8. The memory according to claim 6, characterized in that: The second control circuit includes a refresh controller and an error correction and checker.

9. A method for controlling a memory, wherein the memory comprises a logic chip and a storage chip, wherein: Includes steps: Receiving control instructions from an external system through an interface circuit provided in the memory chip; converting the control instruction into an operation instruction of the memory chip through a memory chip control circuit arranged in the logic circuit; and The storage chip executes the operation instruction.

10. An electronic device, characterized in that: A memory according to any one of claims 1 to 8 is used.

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