Memory, control method thereof and electronic equipment

Abstract

The invention relates to a memory and a control method thereof, and an electronic device, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional stacked packaging technology, the memory chip comprises a plurality of memory groups and interfaces corresponding to at least part of the memory groups, and the interfaces are connected with the memory groups. And the at least part of the memory groups are in data interaction with the logic chip through the independent interfaces. Through an advanced packaging mode and a distributed architecture design, the number of external communication interfaces of the memory chip is increased, the access mode of the memory to an internal memory group and a memory block is fundamentally changed, and an original centralized working mode is changed into a distributed working mode; therefore, the memory bank and the memory block are supported to execute related operations at the same time, the resource utilization rate of the memory is improved, a larger data bandwidth is provided for efficient calculation, and the bottleneck of a'storage wall 'faced by the memory is effectively relieved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a memory and a control method thereof, and an electronic device. Background Art

[0002] like Figure 1 As shown, traditional memory chips usually contain one or more memory groups, and each memory group contains one or more memory blocks. These memory blocks communicate with the outside through a standard interface that conforms to a specific memory protocol, and external control instructions and data transmission are carried out through the signal lines of the interface. Under this storage architecture, when a memory group or memory block occupies the interface, the remaining memory groups or memory blocks will not be able to interact with the outside world. In addition, since the address of the external input usually points to a specific storage location, which corresponds to the storage circuit of a specific memory block in a memory group, each operation is only performed by the memory block pointed to by the address, while other memory blocks and other memory groups in the memory group will not participate in the operation. This centralized working mode has gradually developed with the iteration of memory chips and has become a more common memory working mode.

[0003] However, in recent years, the computing needs and data volume of computing systems have continued to grow, while the bandwidth provided by storage devices has failed to match it, resulting in the working mode of traditional memory chips gradually failing to meet the needs of modern computing systems. This mismatch exacerbates the "storage wall" problem faced by computing systems and limits the overall performance and efficiency of the system. Therefore, there is an urgent need to explore new storage architectures and working modes to cope with the growing computing and data transmission needs.

[0004] In order to alleviate the storage bandwidth bottleneck problem, there are usually two options. The first option is to increase the number of storage devices working in parallel and increase the bandwidth by increasing the number of data channels ( Figure 2 ). However, as the computing power of the computing system increases, the area occupied by the computing circuit gradually increases, and increasing the number of storage devices also requires more area resources. In addition, the controllers that control these storage devices also occupy valuable area space, and the increase in data paths also increases the complexity of the system. In the end, the overall performance of the system using this solution is limited. As area resources are gradually exhausted, the optimization and development of the system face greater bottlenecks.

[0005] The second solution is to use high-performance storage devices, such as high-bandwidth memory (HBM), to increase the bandwidth by increasing the density of a single memory and the number of interface signals ( Figure 3). This solution alleviates the bandwidth bottleneck and area problem of the previous solution to a certain extent. However, high-bandwidth memory such as HBM still needs to be connected to circuits such as CPU / GPU / NPU through a unique interface, so its working mode is similar to the traditional centralized working mode. Specifically, the external can only communicate data through this memory interface and locate a memory block or multiple memory blocks with the same address according to the input address. Therefore, although this solution increases the number of memory blocks that can perform operations simultaneously, only some of the memory blocks pointed to by the external address perform operations, while other memory blocks do not participate. This still wastes storage resources and limits the further improvement of memory performance.

[0006] Therefore, it is necessary to improve the existing memory. Summary of the invention

[0007] In response to the above problems, the present invention provides a memory, including a memory chip and a logic chip, wherein the memory chip and the logic chip are packaged using a three-dimensional stacking packaging process, and the memory chip includes multiple memory groups and an interface corresponding to each memory group, and each of the memory groups interacts with the logic chip for data through an independent interface.

[0008] Optionally, the memory further includes a memory group controller, which corresponds one-to-one to the memory group and can control the corresponding memory group in response to a control instruction of the logic chip.

[0009] Optionally, the memory group controller is disposed in the memory chip, and the memory group controller is connected between the corresponding memory group and the interface.

[0010] Optionally, the memory group controller is arranged in the logic chip, and the memory group controller is connected to the corresponding memory group through the corresponding interface.

[0011] Optionally, different memory group controllers are configured to control corresponding memory groups to execute completely different, partially identical or completely identical operation instructions at the same time.

[0012] Optionally, along the direction of three-dimensional stacking of the logic chip and the memory chip, corresponding to the position of the first interface, the logic chip is provided with a second interface, and the first interface and the second interface are connected along the direction of three-dimensional stacking of the logic chip and the memory chip by a Hybrid bonding process and / or a TSV process.

[0013] Optionally, the memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

[0014] Optionally, the logic chip includes an arithmetic logic circuit, which can perform calculation operations such as multiplication and addition.

[0015] Optionally, the three-dimensional stacking packaging process includes: Hybrid bonding technology and / or TSV technology.

[0016] In order to achieve the above-mentioned invention object, the present application provides a memory control method, wherein the controller includes a logic chip and a memory chip, and the memory chip includes a plurality of memory groups, including the steps of:

[0017] Receive external operation instructions;

[0018] The logic chip sends a control instruction for controlling each memory group of the memory chip based on the external operation instruction; and

[0019] Each memory group performs data exchange with the logic chip in response to a corresponding control instruction.

[0020] Optionally, the memory control method further comprises the step of: different memory groups executing completely different, partially identical or completely identical operations in response to corresponding control instructions.

[0021] In order to achieve the above-mentioned purpose of the invention, the present application provides an electronic device using the memory described above.

[0022] The memory provided by the present application, when external operation instructions are input into the memory, the memory will convert these external operation instructions into control instructions for each memory group controller through the logic chip, and send them to the corresponding memory groups respectively. Therefore, taking the read operation as an example, the memory under the traditional architecture can only read data from the memory block in the specific memory group each time through a single interface according to the address information, while the memory provided by the present embodiment can support multiple interfaces to access different memory groups in the memory at the same time due to the use of a distributed architecture.

[0023] Through advanced packaging methods and distributed architecture design, the number of IO interfaces for external communication of storage chips has been increased, fundamentally changing the memory's access mode to its internal storage groups and storage blocks, from the original centralized working mode to a distributed working mode, thereby supporting storage groups and storage blocks to perform related operations at the same time, improving the resource utilization of the storage, providing a larger data bandwidth for efficient computing, and effectively alleviating the "storage wall" bottleneck faced by the storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the architecture of the memory in the prior art.

[0025] Figure 2 It is an improved memory architecture in the prior art.

[0026] Figure 3 It is an improved memory architecture in the prior art.

[0027] Figure 4 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0028] Figure 5 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0029] Figure 6 It is a schematic diagram of the steps of a memory control method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] like Figure 4 As shown, this embodiment provides a memory, including a memory chip 100 and a logic chip 200. The memory chip 100 and the logic chip 200 are packaged using a three-dimensional stacking packaging process. The memory chip 100 includes multiple memory groups 110 and multiple first interfaces 120 corresponding to the memory groups 110. Each memory 110 interacts with the logic chip 200 for data through an independent first interface 120.

[0032] Specifically, the memory also includes a memory group controller 210 which is arranged in a position corresponding to the memory group 110 on the logic chip 200 and corresponds one-to-one to the memory group 110. Each memory group 110 can exchange data with the logic chip 200 through the memory group controller 210 via a first interface 120 which is independently arranged. Based on this, the logic chip 200 can control multiple memory groups 110 in the memory chip 100 to perform operations simultaneously, thereby significantly improving the resource utilization of the memory chip 100 and providing a higher data bandwidth for the logic chip 200.

[0033] Furthermore, the logic chip 200 is provided with a second interface 220 corresponding to the first interface 120. Taking the logic chip 200 and the memory chip 100 as an example in which they are stacked in a vertical direction, the setting position of the first interface 120 corresponds to the memory group 110 in a horizontal direction, and the second interface 220 corresponds to the position of the first interface 120 in the horizontal direction. In other words, the first interface 120 and the second interface 220 are correspondingly arranged along the stacking direction of the logic chip 200 and the memory chip 100.

[0034] In this embodiment, the specific process of three-dimensional stacking packaging of the logic chip 200 and the memory chip 100 is Hybrid bonding technology or TSV technology. More specifically, the first interface 120 and the second interface 220 are connected along the stacking direction of the logic chip 200 and the memory chip 100 by Hybrid bonding process and / or TSV process. Hybrid Bonding is a direct bonding technology that directly bonds wafers or chips through chemical-mechanical methods and is commonly used for 3D integration. It achieves high-density connection by combining metal with metal and dielectric with dielectric. Its advantage lies in the ultra-high interconnection density: Hybrid Bonding supports nanometer-level metal interconnection spacing (hundreds of nanometers to several microns), which can achieve extremely high signal transmission density to further reduce the chip area, and is particularly suitable for high-density 3D integration. Due to the short interconnection channel and low signal loss, Hybrid Bonding reduces parasitic resistance and capacitance, thereby significantly reducing power consumption. Very suitable for low-power chips (such as mobile devices, AI accelerators, etc.). Performance improvement: Provides faster data transmission speed and lower latency. Meet the needs of high-performance computing (HPC), especially for the integration of high-bandwidth storage, processors and accelerators. Higher design flexibility: supports chip-level or wafer-level stacking, does not require additional silicon area, and allows complex heterogeneous integration (such as the combination of logic and storage, analog and digital circuits). Cost optimization: Hybrid Bonding is integrated through wafer-level processes, reducing process steps and material waste, and has certain cost advantages. TSV is a vertical interconnection technology through silicon vias. It realizes electrical connection between chips by processing through holes on silicon wafers and filling them with conductive materials. TSV is a three-dimensional interconnection technology that can realize chip stacking (such as HBM high-bandwidth storage stacking of DRAM), supports direct interconnection of multiple chip layers, and improves integration density. TSV provides a high-bandwidth inter-chip communication path, especially in applications that require high data throughput (such as graphics processors, AI accelerators). Reduces signal transmission delay and increases operating speed. Compared with traditional packaging (such as Flip-Chip or WireBonding), TSV significantly shortens the signal transmission path, thereby reducing power consumption. The TSV process allows chips of different process nodes and different types (such as logic, storage, and analog chips) to be stacked together, which is suitable for heterogeneous computing platforms. After years of development, the TSV process is relatively mature and has been successfully applied in many commercial products (such as HBM2 storage and 3D NAND).

[0035] The memory provided in this embodiment, wherein the memory chip 100 and the logic chip 200 adopt three-dimensional stacking packaging, and the three-dimensional stacking packaging is specifically realized by the above two processes, and the two can be combined or used separately according to specific needs. For example, TSV is used for global connection in three-dimensional integrated design, and Hybrid Bonding is used to achieve local high-density interconnection, thereby giving full play to their respective advantages.

[0036] It should be noted that the memory chip 100 can be configured so that some memory groups 110 are provided with independent interfaces, and the remaining memory groups 110 exchange data with the logic chip 200 by sharing one interface; it can also be configured so that all memory groups 110 are provided with independent interfaces, and exchange data with the logic chip 200 through independent interfaces. The above implementation modes are all within the scope of protection of the present invention.

[0037] Optionally, in this embodiment, the memory chip 100 and the logic chip 200 are electrically connected in a vertical direction by using a hybrid bonding technology.

[0038] Optionally, in this embodiment, the memory chip 100 and the logic chip 200 are electrically connected in a vertical direction by TSV technology.

[0039] The electrical connection between the memory chip 100 and the logic chip 200 can be realized by using the above two electrical connection methods, which can significantly reduce the chip area occupied by the electrical interface, thereby providing a basis for each memory group 110 to separately set up a first interface 120 for interacting with the logic chip 200.

[0040] like Figure 5 As shown, this embodiment also provides a memory, which is Figure 4 The difference of the memory shown is that the memory bank controller 130 is disposed in the memory chip 100 . In this case, the memory bank controller 130 is connected between the corresponding memory bank 110 and the corresponding first interface 120 .

[0041] If the memory group controller 130 is set in the memory chip 100, because it is located in the same chip as the memory group 110, the two are more closely coupled, with strong stability, and it is not easy to have problems such as signal distortion; if the memory group controller 130 is set in the logic chip 200, because the process of the logic chip 200 is more advanced than that of the memory chip 100, when the memory group controller 130 is set in the logic chip 200, its performance will be better.

[0042] In the actual design process, based on the spirit of the present invention, technical personnel in this field may need to make trade-offs between stability and controller performance based on indicators such as process and interface signal frequency, and select a memory group controller design that is more suitable for the current application scenario. The above implementation methods are all within the scope of protection of this application.

[0043] Regardless of the specific location of the memory group controller 130 , its location along the horizontal direction corresponds to the corresponding memory group 110 . Such a design can reduce the difficulty and cost of wiring.

[0044] by Figure 4 Taking the memory shown as an example, when external operation instructions are input into the memory, the memory will convert these external operation instructions into control instructions for each memory group controller 210 through the logic chip 200, and send them to the corresponding memory groups respectively. Therefore, taking the read operation as an example, the memory under the traditional architecture can only read data from the memory block in the specific memory group each time through a single interface according to the address information, while the memory provided in this embodiment can support multiple interfaces to access different memory groups in the memory at the same time due to the use of a distributed architecture.

[0045] Through advanced packaging methods and distributed architecture design, the number of interfaces for external communication of memory chips has been increased, fundamentally changing the memory's access mode to its internal memory groups and memory blocks, from the original centralized working mode to a distributed working mode, thereby supporting memory groups and memory blocks to perform related operations at the same time, improving memory resource utilization, providing greater data bandwidth for efficient computing, and effectively alleviating the "storage wall" bottleneck faced by memory.

[0046] Optionally, each memory group 110 includes at least one memory block, and different memory blocks are configured to have different address information, based on which, in response to the address information in the control instruction, the memory block corresponding to the address information executes the control instruction.

[0047] Optionally, different memory bank controllers 130 are configured to control corresponding memory banks to execute completely different, partially identical, or completely identical operation instructions at the same time.

[0048] Alternatively, if Figure 6 As shown, this embodiment provides a method for controlling a memory, and controls the memory provided by this embodiment, including the steps of:

[0049] Receive external operation instructions;

[0050] The logic chip sends a control instruction for controlling each memory group of the memory chip based on the external operation instruction; and

[0051] Each memory group performs data exchange with the logic chip in response to the corresponding control instruction.

[0052] Optionally, the control method comprises the steps of:

[0053] Different memory groups perform completely different, partially identical, or completely identical operations in response to corresponding control instructions.

[0054] With such a configuration, compared with the memory in the prior art, the memory control method provided by this embodiment is more flexible, and different memory groups can execute different control instructions based on demand, thereby improving memory utilization, data interaction efficiency and diversity of working modes.

[0055] Optionally, in this embodiment, the logic chip 200 further includes a functional circuit 230 , which includes an arithmetic logic circuit that performs calculation operations such as multiplication and addition.

[0056] Optionally, in this embodiment, the memory chip 100 further includes a functional circuit 140 responsible for address resolution, error correction, power management and other operations. The coordinated operation of these circuits ensures that the memory chip can operate in an efficient, stable and reliable manner.

[0057] Optionally, in this embodiment, the memory chip 100 is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

[0058] Optionally, the first interface 120 of the memory group 110 is configured to receive any signal and combinations thereof, including address input signals, data input / output signals, word or byte selection input signals, hardware reset / sector protection unlock signals, output enable signals, command lane signals, address lane signals, Ready / Busy indication signals, differential clock signals, clock enable signals, chip select signals, row address select signals, column address select signals, write enable signals, data read and write clock signals, BANK address signals, data mask signals, termination resistor signals, calibration signals, command address signals, and data bus signals.

[0059] Optionally, when the memory has multiple layers of stacked memory chips, the upper memory chip and the bottom memory chip are connected via IO of the advanced packaging interface and are controlled by the memory group controller on the logic chip. For example, when a certain memory group controller on the logic chip is working, it can simultaneously access the memory groups corresponding to the memory group controller on these memory chips.

[0060] Optionally, this embodiment further provides an electronic device, which uses the memory provided by this embodiment, and the electronic device may be a computer.

[0061] So far, the technical solution of the present invention has been described in conjunction with the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to the above-mentioned specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A memory, characterized in that: It includes a memory chip and a logic chip, wherein the memory chip and the logic chip are packaged using a three-dimensional stacking packaging process, the memory chip includes multiple memory groups and a first interface corresponding to at least part of the memory groups, and the at least part of the memory groups exchange data with the logic chip through the independent first interface.

2. The memory according to claim 1, characterized in that: The memory further includes a memory group controller, which corresponds one-to-one to at least part of the memory groups and can control the corresponding memory group in response to a control instruction of the logic chip.

3. The memory according to claim 2, characterized in that: The memory group controller is disposed in the memory chip, and the memory group controller is connected between the corresponding at least part of the memory group and the first interface.

4. The memory according to claim 2, characterized in that: The memory group controller is arranged in the logic chip, and the memory group controller is connected to the corresponding memory group through the corresponding first interface.

5. The memory according to claim 2, characterized in that: Along the direction of three-dimensional stacking of the logic chip and the memory chip, corresponding to the position of the first interface, the logic chip is provided with a second interface, and the first interface and the second interface are connected along the direction of three-dimensional stacking of the logic chip and the memory chip by a hybrid bonding process and / or a TSV process.

6. The memory according to any one of claims 2 to 5, characterized in that: Different memory bank controllers are configured to control corresponding memory banks to execute completely different, partially identical or completely identical operation instructions at the same time.

7. The memory according to any one of claims 1 to 5, characterized in that: The memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

8. The memory according to any one of claims 1 to 5, characterized in that: The logic chip includes an arithmetic logic circuit capable of performing calculation operations.

9. The memory according to any one of claims 1 to 5, characterized in that: The three-dimensional stacking packaging process is: Hybrid bonding technology or TSV technology.

10. A method for controlling a memory, wherein the controller comprises a logic chip and a memory chip, and the memory chip comprises a plurality of memory groups, wherein: Includes steps: Receive external operation instructions; The logic chip sends a control instruction for controlling each memory group of the memory chip based on the external operation instruction; as well as Each memory group performs data exchange with the logic chip in response to a corresponding control instruction.

11. The memory control method according to claim 10, characterized in that: Includes steps: Different memory groups execute completely different, partially identical, or completely identical operations in response to corresponding control instructions.

12. An electronic device, characterized in that: Application of the memory described in any one of claims 1 to 9.

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