A method and system for simultaneous online upgrade applicable to multiple groups of parallel ARM devices

Abstract

The present invention provides a method and system for simultaneous online upgrade applicable to multiple groups of parallel ARM devices, including the following steps: S1: The host computer sends an upgrade verification instruction to the first device to be upgraded through an external network, and any device to be upgraded transmits the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through an internal network, and the ARM chips of all devices to be upgraded receive the upgrade verification instruction respectively. S2: Based on the upgrade verification instruction, the ARM chip of any device to be upgraded respectively judges the upgrade requirements of its own system. The host computer sends an upgrade file to the first device to be upgraded through an external network, and any device to be upgraded transmits the upgrade file to another device to be upgraded connected to its adjacent rear through an internal network. The ARM chips of the devices to be upgraded with upgrade requirements receive the upgrade file respectively and perform system upgrade. Through the present invention, the simultaneous online upgrade function of multiple groups of parallel ARM devices can be realized, and the upgrade efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of information and communication technologies, and particularly relates to a method and system for simultaneous online upgrade applicable to multiple groups of parallel ARM devices. Background Art

[0002] In the field of embedded systems, processors based on the ARM architecture are widely adopted due to their excellent performance and low power consumption characteristics. With the progress and rapid evolution of technology, the need for device firmware and software updates is increasing. For traditional systems, the host computer usually needs to communicate with the processor based on the ARM architecture through a serial port chip to achieve data interaction. In this process, the ARM chip, as the core controller, is responsible for receiving and parsing the instruction packets separately output from the host computer, and performing corresponding update and upgrade operations accordingly. Although the above method shows high efficiency in handling the upgrade tasks of a single device, it faces challenges when multiple devices of the same type need to be simultaneously upgraded online. The traditional method of upgrading devices one by one not only takes a long time but also increases the risk of errors, resulting in an increase in maintenance costs and a decrease in upgrade efficiency. Summary of the Invention

[0003] The present invention aims to provide a method and system for simultaneous online upgrade applicable to multiple groups of parallel ARM devices, so as to solve the technical problem that in the prior art, the conventional ARM device upgrade method cannot achieve the function of simultaneous online upgrade of multiple groups of parallel ARM devices, resulting in low upgrade efficiency.

[0004] To solve the above problems, the technical solution of the present invention is as follows: A method for simultaneous online upgrade applicable to multiple groups of parallel ARM devices, comprising the following steps:

[0005] S1: The host computer sends an upgrade verification instruction to the first device to be upgraded through an external network, and any device to be upgraded transmits the upgrade verification instruction to another device to be upgraded connected in series behind it through an internal network, and the ARM chips of all devices to be upgraded respectively receive the upgrade verification instruction;

[0006] S2: Based on the upgrade verification instruction, the ARM chip of any device to be upgraded respectively judges the upgrade requirements of its own system. The host computer sends an upgrade file to the first device to be upgraded through an external network, and any device to be upgraded transmits the upgrade file to another device to be upgraded connected in series behind it through an internal network. The ARM chips of the devices to be upgraded with upgrade requirements respectively receive the upgrade file and perform system upgrade.

[0007] Preferably, in S1, the host computer sends an upgrade verification instruction to multiple groups of parallel devices to be upgraded, specifically including the following steps:

[0008] S11: The first device to be upgraded receives the upgrade verification instruction sent by the host computer through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected adjacent to its rear through its second Ethernet port;

[0009] S12: Except for the first device to be upgraded, any device to be upgraded receives the upgrade verification instruction sent by another device to be upgraded connected adjacent to its front through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected adjacent to its rear through its second Ethernet port.

[0010] Preferably, in S12, the device to be upgraded receives the upgrade verification instruction through its first Ethernet port and sends the upgrade verification instruction through its second Ethernet port, which specifically includes the following steps:

[0011] S121: After the device to be upgraded receives the upgrade verification instruction through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade verification instruction into a digital signal and transmits it to the FPGA chip of the device to be upgraded;

[0012] The FPGA chip of the device to be upgraded outputs the upgrade verification instruction to its second PHY chip, and the second PHY chip converts the digital signal of the upgrade verification instruction into an analog signal, and the device to be upgraded outputs the upgrade verification instruction through its second Ethernet port.

[0013] Preferably, in S2, the ARM chip of the device to be upgraded judges the upgrade requirement of its own system based on the upgrade verification instruction, which specifically includes the following steps:

[0014] S21: The ARM chip of any device to be upgraded receives the upgrade verification instruction, compares the system version of the current ARM chip with the system version recorded in the upgrade verification instruction. If the system version recorded in the upgrade verification instruction is higher than the system version of the current ARM chip, the ARM chip outputs the corresponding upgrade confirmation flag and the ARM chip serial number, and the device to be upgraded sends the upgrade confirmation flag and the ARM chip serial number back to the host computer; if the system version recorded in the upgrade verification instruction is equal to or lower than the system version of the current ARM chip, the ARM chip only outputs the ARM chip serial number, and the device to be upgraded sends the ARM chip serial number back to the host computer.

[0015] Preferably, in S21, the device to be upgraded sends back the upgrade confirmation flag and / or the ARM chip serial number to the host computer, which specifically includes the following steps:

[0016] S211: The device to be upgraded receives the backhaul data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The second PHY chip of the device to be upgraded converts the analog signal of the backhaul data into a digital signal and transmits it to the FPGA chip of the device to be upgraded;

[0017] S212: The ARM chip of the device to be upgraded sends its own backhaul data to its FPGA chip. The FPGA chip of the device to be upgraded packetizes its own backhaul data and the backhaul data, and sends the integrated backhaul data to its first PHY chip. The first PHY chip of the device to be upgraded converts the digital signal of the backhaul data into an analog signal, and the device to be upgraded sends the backhaul data to another device to be upgraded connected to its adjacent front through its first Ethernet port;

[0018] S213: Repeat steps S211 - S212 until the first device to be upgraded receives the backhaul data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The first device to be upgraded sends the backhaul data integrated with its own backhaul data to the host computer through the first Ethernet port.

[0019] Preferably, between the first PHY chip and the FPGA chip of the device to be upgraded, between the FPGA chip and the second PHY chip of the device to be upgraded, and between the FPGA chip and the ARM chip, communication connections are respectively achieved through MII interfaces.

[0020] Preferably, after the host computer receives the backhaul data of several devices to be upgraded in S213, the following steps are further included:

[0021] S22: The host computer saves the upgrade confirmation flags and ARM chip serial number data sent back by several devices to be upgraded;

[0022] S23: The first device to be upgraded receives the upgrade file sent by the host computer through its first Ethernet port and sends the upgrade file to another device to be upgraded connected to its adjacent rear through its second Ethernet port;

[0023] S24: Except for the first device to be upgraded, any device to be upgraded respectively receives the upgrade file sent by another device to be upgraded connected to its adjacent front through its first Ethernet port and sends the upgrade file to another device to be upgraded connected to its adjacent rear through its second Ethernet port.

[0024] Preferably, when the device to be upgraded receives the upgrade file through its first Ethernet port and sends the upgrade file through its second Ethernet port in S24, the specific steps are as follows:

[0025] S241: After the device to be upgraded receives the upgrade file through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade file into a digital signal. If there is an upgrade requirement for the ARM chip system of the current device to be upgraded, the upgrade file is transmitted to the ARM chip through the FPGA chip, and the ARM chip performs the online upgrade operation;

[0026] Moreover, the FPGA chip of the device to be upgraded outputs the upgrade file to its second PHY chip, and the second PHY chip converts the digital signal of the upgrade file into an analog signal, and the device to be upgraded outputs the upgrade file through its second Ethernet port.

[0027] Preferably, in S241, when the host computer sends the upgrade file and the device to be upgraded performs the ARM chip system upgrade, the following steps are further included:

[0028] S25: After the ARM chip systems of several devices to be upgraded with upgrade requirements are upgraded, the ARM chips of the devices to be upgraded output the corresponding upgrade success flags and ARM chip serial numbers, and send them to the host computer;

[0029] The host computer compares the received upgrade success flags and ARM chip serial numbers corresponding to several devices to be upgraded with the saved upgrade confirmation flags and ARM chip serial numbers corresponding to several devices to be upgraded. If there is a device to be upgraded that has not been upgraded successfully, the host computer locates the device to be upgraded that has not been upgraded successfully and outputs an alarm message.

[0030] Based on the same concept, the present invention also provides a simultaneous online upgrade system applicable to multiple groups of parallel ARM devices, which is used to execute the simultaneous online upgrade method applicable to multiple groups of parallel ARM devices described in any one of the above, including:

[0031] A host computer, which is used to provide upgrade files to several devices to be upgraded;

[0032] Several devices to be upgraded. The first Ethernet port of the first device to be upgraded is communicatively connected to the host computer through an external network. Except for the first device to be upgraded, the first Ethernet port of any device to be upgraded is communicatively connected to the second Ethernet port of another adjacent pre-connected device to be upgraded through an internal network, and the second Ethernet port of any device to be upgraded is communicatively connected to the first Ethernet port of another adjacent post-connected device to be upgraded through an internal network.

[0033] Due to the adoption of the above technical solutions, the present invention has the following advantages and positive effects compared with the prior art:

[0034] The present invention provides a method and system for simultaneous online upgrading of multiple groups of parallel ARM devices. Among them, the first device to be upgraded communicates with the host computer through an external network, and the remaining several devices to be upgraded are respectively connected to adjacent front-end and adjacent back-end devices to be upgraded for communication. The upgrade verification instruction and upgrade file output by the host computer are sequentially transmitted from the first device to be upgraded to the last device to be upgraded through multiple groups of devices to be upgraded by serial communication. In this system, multiple groups of parallel ARM devices do not need to be directly connected to the host computer for communication, that is, data sharing and simultaneous online upgrading functions between multiple devices to be upgraded can be realized, effectively shortening the overall update and upgrade time of the multiple groups of parallel ARM device system, and the online upgrading of several devices to be upgraded can be completed by sending commands and data from the host computer without disassembling and assembling the devices to be upgraded, which can not only improve the control efficiency, but also avoid possible damage to the devices to be upgraded during the disassembly and assembly process. Brief Description of the Drawings

[0035] Figure 1 Structural schematic diagram of a simultaneous online upgrading system for multiple groups of parallel ARM devices provided by the present invention;

[0036] Figure 2 Flowchart of a method for simultaneous online upgrading of multiple groups of parallel ARM devices provided by the present invention. Detailed Embodiments

[0037] The following further elaborates in detail on a method and system for simultaneous online upgrading of multiple groups of parallel ARM devices proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will be clearer according to the following description and the claims.

[0038] First Embodiment

[0039] Refer to Figures 1 to 2 , this embodiment provides a method for simultaneous online upgrading of multiple groups of parallel ARM devices, which is used to improve the upgrading efficiency of multiple groups of parallel ARM devices, and specifically includes the following steps:

[0040] S1: The host computer sends an upgrade verification instruction to the first device to be upgraded through an external network. The upgrade verification instruction is used to verify whether the device to be upgraded needs to perform a system upgrade. After receiving the upgrade verification instruction, any device to be upgraded transmits the upgrade verification instruction to another device to be upgraded connected to its adjacent back-end through the internal network in sequence until all devices to be upgraded receive the upgrade verification instruction. Finally, the ARM chips in all devices to be upgraded respectively receive the upgrade verification instruction.

[0041] S2: Based on the upgrade verification instruction, the ARM chip of any device to be upgraded can respectively judge the upgrade requirements of its own system. When there is at least one group of devices to be upgraded with upgrade requirements, the host computer sends the upgrade file to the first device to be upgraded through the external network. Any device to be upgraded transmits the upgrade file to another device to be upgraded connected to its adjacent rear through the internal network. The ARM chips of the devices to be upgraded with upgrade requirements respectively receive the upgrade file and perform system upgrade.

[0042] Specifically, in this embodiment, there are a host computer, a first device to be upgraded, a second device to be upgraded, a third device to be upgraded,..., an nth device to be upgraded. The first device to be upgraded is set as the first device to be upgraded. The first device to be upgraded is respectively communicatively connected to the host computer and the second device to be upgraded. In addition to being connected to the first device to be upgraded, the second device to be upgraded is also communicatively connected to the third device to be upgraded. In addition to being connected to the second device to be upgraded, the third device to be upgraded is also communicatively connected to the fourth device to be upgraded,..., until the nth device to be upgraded. In this embodiment, after the host computer sends the upgrade verification instruction to the first device to be upgraded, while obtaining the upgrade verification instruction, the first device to be upgraded further transmits the upgrade verification instruction to the second device to be upgraded. While obtaining the upgrade verification instruction, the second device to be upgraded further transmits the upgrade verification instruction to the third device to be upgraded,..., until the nth device to be upgraded obtains the upgrade verification instruction. After all the devices to be upgraded respectively judge their own system upgrade requirements based on the upgrade verification instruction, the host computer sends the upgrade file to the first device to be upgraded. While obtaining the upgrade file, the first device to be upgraded further transmits the upgrade file to the second device to be upgraded. While obtaining the upgrade file, the second device to be upgraded further transmits the upgrade file to the third device to be upgraded,..., until the nth device to be upgraded obtains the upgrade file. Among them, the devices to be upgraded with upgrade requirements realize the system upgrade of their ARM chips based on the upgrade file.

[0043] It should be noted that in this embodiment, the ARM devices among several devices to be upgraded are in a parallel structure, and the operations among them do not affect each other. The communication connection between adjacent devices to be upgraded is only used to realize the system upgrade function of the ARM chip.

[0044] It can be seen from this that the present application provides a simultaneous online upgrade method applicable to multiple groups of parallel ARM devices, which realizes serial communication of the upgrade data link for the ARM devices with multiple groups of parallel jobs. The host computer only forms a direct communication connection with the first device to be upgraded, and then the data sharing and simultaneous upgrade functions between multiple devices to be upgraded can be realized, effectively shortening the overall update and upgrade time of the multiple groups of parallel ARM device system. Moreover, the online upgrade of several devices to be upgraded can be completed by the host computer sending commands and data, without disassembling and assembling the devices to be upgraded, which can not only improve the control efficiency, but also avoid the possible damage of the devices to be upgraded during the disassembly and assembly process.

[0045] Next, the specific implementation steps and functions of the simultaneous online upgrade method applicable to multiple groups of parallel ARM devices provided in this embodiment will be further described in detail:

[0046] Preferably, in this embodiment, any device to be upgraded is provided with a first Ethernet port and a second Ethernet interface. In S1, the host computer sends an upgrade verification instruction to multiple groups of parallel devices to be upgraded, which specifically includes the following steps:

[0047] S11: The host computer outputs an upgrade verification instruction. The first device to be upgraded receives the upgrade verification instruction sent by the host computer through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through its second Ethernet port.

[0048] S12: Except for the first device to be upgraded, any device to be upgraded respectively receives the upgrade verification instruction sent by another device to be upgraded connected to its adjacent front through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through its second Ethernet port.

[0049] In this embodiment, the host computer and the first Ethernet port of the first device to be upgraded are connected for communication through a twisted pair network cable, and the second Ethernet port of the device to be upgraded and the first Ethernet port of another device to be upgraded connected to its adjacent rear are connected for communication through a twisted pair network cable.

[0050] Preferably, in this embodiment, the devices to be upgraded are respectively provided with a first PHY chip and a second PHY chip corresponding to the first Ethernet port and the second Ethernet port. The PHY chip is used to convert digital signals into analog signals suitable for transmission through specific physical media (such as twisted pairs, optical fibers, etc.), and perform the reverse process to ensure that data can be correctly transmitted and received.

[0051] In S12, the device to be upgraded receives the upgrade verification instruction through its first Ethernet port and sends the upgrade verification instruction through its second Ethernet port, which specifically includes the following steps:

[0052] S121: After the device to be upgraded receives the upgrade verification instruction through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade verification instruction into a digital signal and transmits it to the FPGA chip of the device to be upgraded, so that the FPGA chip of the device to be upgraded can obtain the readable upgrade verification instruction.

[0053] After the FPGA chip of the device to be upgraded obtains the upgrade verification instruction, the FPGA chip outputs the same upgrade verification instruction to the second PHY chip. The second PHY chip converts the digital signal of the upgrade verification instruction into an analog signal, and the device to be upgraded outputs the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through its second Ethernet port, thereby realizing the lossless transmission of the upgrade verification instruction between several devices to be upgraded.

[0054] Preferably, in S2, the ARM chip of the device to be upgraded judges the upgrade requirement of its own system based on the upgrade verification instruction, which specifically includes the following steps:

[0055] S21: After the FPGA chip of the device to be upgraded obtains the upgrade verification instruction, the FPGA chip preprocesses the upgrade verification instruction and further transmits it to the ARM chip. The ARM chip of any device to be upgraded receives the upgrade verification instruction, compares the system version of the current ARM chip with the system version recorded in the upgrade verification instruction. If the system version recorded in the upgrade verification instruction is higher than the system version of the current ARM chip, it proves that the system of the current ARM chip needs to be upgraded. The ARM chip outputs the corresponding upgrade confirmation flag and the ARM chip serial number, and the device to be upgraded transmits the upgrade confirmation flag and the ARM chip serial number back to the host computer.

[0056] If the system version recorded in the upgrade verification instruction is equal to or lower than the system version of the current ARM chip, it proves that the system of the current ARM chip does not need to be upgraded. The ARM chip only outputs the ARM chip serial number, and the device to be upgraded transmits the ARM chip serial number back to the host computer.

[0057] Further, in S21, the device to be upgraded transmits the upgrade confirmation flag and / or the ARM chip serial number back to the host computer, which specifically includes the following steps:

[0058] S211: The device to be upgraded receives the rear return data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The return data includes the upgrade confirmation flag and / or the ARM chip serial number. The second PHY chip of the device to be upgraded converts the analog signal of the rear return data into a digital signal and transmits it to the FPGA chip of the device to be upgraded.

[0059] S212: The ARM chip of the device to be upgraded sends its self-transmitted data to its FPGA chip. The FPGA chip of the device to be upgraded performs packet processing on its self-transmitted data and the post-transmitted data, and sends the integrated transmitted data to its first PHY chip. The first PHY chip of the device to be upgraded converts the digital signal of the transmitted data into an analog signal, and the device to be upgraded sends the transmitted data to another device to be upgraded connected to its adjacent front end through its first Ethernet port.

[0060] S213: Repeat steps S211 - S212 until the first device to be upgraded receives the post-transmitted data sent by another device to be upgraded connected to its adjacent back end through its second Ethernet port. The first device to be upgraded sends the transmitted data integrated from its self-transmitted data and the post-transmitted data to the host computer through the first Ethernet port.

[0061] That is, in this embodiment, the transmitted data composed of the upgrade confirmation flag and / or the ARM chip serial number of several devices to be upgraded will be continuously packet-integrated during the process of being uploaded step by step from the last device to be upgraded. Every time it passes through a new group of devices to be upgraded, the post-transmitted data will be packet-processed with the self-transmitted data of the current device to be upgraded until the transmitted data of all devices to be upgraded is sent to the host computer through the first device to be upgraded.

[0062] Preferably, in this embodiment, between the first PHY chip and the FPGA chip of the device to be upgraded, between the FPGA chip and the second PHY chip of the device to be upgraded, and between the FPGA chip and the ARM chip, communication connections are respectively achieved through MII interfaces. As a standard interface, the MII interface is used to connect the FPGA chip and the PHY chip, and the FPGA chip and the ARM chip, which can keep the compatibility between the connection interfaces, simplify the design complexity of the internal communication link of the device to be upgraded. At the same time, the MII interface can support different data transmission rates, and can flexibly adjust the upgrade rate of the device to be upgraded according to needs to adapt to the requirements of different application scenarios.

[0063] Preferably, in this embodiment, after the host computer receives the transmitted data of several devices to be upgraded in S213, the following steps are further included:

[0064] S22: The host computer saves the upgrade confirmation flags and ARM chip serial number data transmitted back by several devices to be upgraded.

[0065] S23: If there is at least one group of devices to be upgraded with upgrade requirements, the host computer outputs an upgrade file. The first device to be upgraded receives the upgrade file sent by the host computer through its first Ethernet port and sends the upgrade file to another device to be upgraded connected to its adjacent back end through its second Ethernet port.

[0066] S24: Except for the first device to be upgraded, each device to be upgraded receives the upgrade file sent by another device to be upgraded connected to its adjacent front-end through its first Ethernet port, and sends the upgrade file to another device to be upgraded connected to its adjacent back-end through its second Ethernet port.

[0067] Similarly, referring to the transmission logic of the upgrade verification instruction among several devices to be upgraded, steps S23 - S24 can achieve the lossless transmission of the upgrade file among several devices to be upgraded.

[0068] Furthermore, in S24, the device to be upgraded receives the upgrade file through its first Ethernet port and sends the upgrade file through its second Ethernet port, which specifically includes the following steps:

[0069] S241: After the device to be upgraded receives the upgrade file through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade file into a digital signal. If there is an upgrade requirement for the ARM chip system of the current device to be upgraded, the FPGA chip receives the upgrade file and transfers the upgrade file to the ARM chip, and the ARM chip performs an online upgrade action based on the upgrade file.

[0070] Moreover, the FPGA chip of the device to be upgraded outputs the upgrade file to its second PHY chip, and the second PHY chip converts the digital signal of the upgrade file into an analog signal, and the device to be upgraded outputs the upgrade file to another device to be upgraded connected to its adjacent back-end through its second Ethernet port.

[0071] Even further, in S241, the host computer sends the upgrade file and the device to be upgraded performs an upgrade on the ARM chip system, which further includes the following steps:

[0072] S25: After the ARM chip systems of several devices to be upgraded with upgrade requirements are upgraded, the ARM chips of the devices to be upgraded output the corresponding upgrade success flag and the ARM chip serial number, and send them to the host computer.

[0073] The host computer compares the received upgrade success flags and ARM chip serial numbers corresponding to several devices to be upgraded with the upgrade confirmation flags and ARM chip serial numbers corresponding to several devices to be upgraded saved by it. If there is a device to be upgraded that has not been upgraded successfully, that is, within the specified time, the host computer stores the upgrade confirmation flag corresponding to a certain ARM chip serial number, and if there is no upgrade success flag corresponding to this ARM chip serial number, it proves that the upgrade of the ARM chip system corresponding to this ARM chip serial number has failed. The host computer outputs an alarm message and locates this device to be upgraded to remind the operator to perform inspection and maintenance.

[0074] Among them, the ARM chip of the device to be upgraded outputs the corresponding upgrade success flag and the ARM chip serial number, and sends them to the host computer. Specifically, it includes the following steps:

[0075] S251: The device to be upgraded receives the post-back data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The post-back data includes the upgrade success flag and the ARM chip serial number. The second PHY chip of the device to be upgraded converts the analog signal of the post-back data into a digital signal and transmits it to the FPGA chip of the device to be upgraded.

[0076] S252: The ARM chip of the device to be upgraded sends its own post-back data to its FPGA chip. The FPGA chip of the device to be upgraded performs packet processing on its own post-back data and the post-back data, and sends the integrated post-back data to its first PHY chip. The first PHY chip of the device to be upgraded converts the digital signal of the post-back data into an analog signal, and the device to be upgraded sends the post-back data to another device to be upgraded connected to its adjacent front through its first Ethernet port.

[0077] S253: Repeat steps S251 - S252 until the first device to be upgraded receives the post-back data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The first device to be upgraded integrates its own post-back data and the post-back data, and sends the integrated post-back data to the host computer through the first Ethernet port.

[0078] Second Embodiment

[0079] Based on the same concept, the present invention further provides a simultaneous online upgrade system applicable to multiple groups of parallel ARM devices, which is used to execute the simultaneous online upgrade method applicable to multiple groups of parallel ARM devices described in any one of the first embodiments, including:

[0080] A host computer, which is used to provide upgrade files to several devices to be upgraded.

[0081] Several devices to be upgraded. The first Ethernet port of the first device to be upgraded is communicatively connected to the host computer through an external network. Except for the first device to be upgraded, the first Ethernet port of any device to be upgraded is communicatively connected to the second Ethernet port of another device to be upgraded connected to its adjacent front through an internal network. The second Ethernet port of any device to be upgraded is communicatively connected to the first Ethernet port of another device to be upgraded connected to its adjacent rear through an internal network.

[0082] Among them, any device to be upgraded is provided with a first PHY chip, a second PHY chip, an FPGA chip and an ARM chip. The first PHY chip and the second PHY chip are respectively electrically connected to the FPGA chip, and the FPGA chip is also electrically connected to the ARM chip.

[0083] In this embodiment, the first device to be upgraded, the second device to be upgraded, the third device to be upgraded, …, the nth device to be upgraded are used for illustration. The host computer can send an upgrade verification instruction or an upgrade file to the first device to be upgraded. While receiving the sent upgrade verification instruction or upgrade file, the first device to be upgraded can also transmit the upgrade verification instruction or the upgrade file to the second device to be upgraded. While receiving the sent upgrade verification instruction or upgrade file, the second device to be upgraded can also transmit the upgrade verification instruction or the upgrade file to the third device to be upgraded, and so on, until the nth device to be upgraded receives the sent upgrade verification instruction or upgrade file.

[0084] In the simultaneous online upgrade system applicable to multiple groups of parallel ARM devices provided in this embodiment, it is not necessary for multiple groups of parallel ARM devices to be directly communicatively connected to the host computer. That is, the data sharing and simultaneous upgrade functions of multiple devices to be upgraded can be realized, effectively shortening the overall update and upgrade time of the ARM chip systems inside multiple groups of parallel ARM devices. Moreover, the online upgrade of several devices to be upgraded can be completed by sending commands and data from the host computer without disassembling and assembling the devices to be upgraded, which can not only improve the control efficiency but also avoid the possible damage to the devices to be upgraded during the disassembly and assembly process.

[0085] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, provided that these changes fall within the scope of the claims of the present invention and their equivalent technologies, they still fall within the protection scope of the present invention.

Claims

1. A simultaneous online upgrade method applicable to multiple groups of parallel ARM devices, characterized in that, The ARM device applied to multiple groups of parallel jobs realizes serial communication of the upgrade data link, including the following steps: S1: The host computer sends an upgrade verification instruction to the first device to be upgraded through the external network. Any device to be upgraded transmits the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through the internal network. The ARM chips of all devices to be upgraded respectively receive the upgrade verification instruction; Among them, step S1 includes: S11: The first device to be upgraded receives the upgrade verification instruction sent by the host computer through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through its second Ethernet port; S12: Except for the first device to be upgraded, any device to be upgraded respectively receives the upgrade verification instruction sent by another device to be upgraded connected to its adjacent front through its first Ethernet port, and sends the upgrade verification instruction to another device to be upgraded connected to its adjacent rear through its second Ethernet port; S2: The ARM chip of any device to be upgraded respectively judges the upgrade requirement of its own system based on the upgrade verification instruction. The host computer sends an upgrade file to the first device to be upgraded through the external network. Any device to be upgraded transmits the upgrade file to another device to be upgraded connected to its adjacent rear through the internal network. The ARM chips of the devices to be upgraded with upgrade requirements respectively receive the upgrade file and perform system upgrade; Among them, step S2 includes: S211: The device to be upgraded receives the rear return data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port; S212: The device to be upgraded performs packet processing on its own return data and the rear return data, and the device to be upgraded sends the return data to another device to be upgraded connected to its adjacent front through its first Ethernet port; S213: Repeat steps S211 - S212 until the first device to be upgraded receives the rear return data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The first device to be upgraded sends the return data after integrating its own return data and the rear return data to the host computer through the first Ethernet port.

2. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices according to claim 1, characterized in that, In S12, the device to be upgraded receives the upgrade verification instruction through its first Ethernet port and sends the upgrade verification instruction through its second Ethernet port, which specifically includes the following steps: S121: After the device to be upgraded receives the upgrade verification instruction through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade verification instruction into a digital signal and transmits it to the FPGA chip of the device to be upgraded; The FPGA chip of the device to be upgraded outputs the upgrade verification instruction to its second PHY chip. The second PHY chip converts the digital signal of the upgrade verification instruction into an analog signal, and the device to be upgraded outputs the upgrade verification instruction through its second Ethernet port.

3. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices according to claim 1, characterized in that In S2, the ARM chip of the device to be upgraded judges the upgrade requirement of its own system based on the upgrade verification instruction, which specifically includes the following steps: S21: The ARM chip of any device to be upgraded receives the upgrade verification instruction, compares the system version of the current ARM chip with the system version recorded in the upgrade verification instruction. If the system version recorded in the upgrade verification instruction is higher than the system version of the current ARM chip, the ARM chip outputs the corresponding upgrade confirmation flag and the ARM chip serial number, and the device to be upgraded sends the upgrade confirmation flag and the ARM chip serial number back to the host computer; if the system version recorded in the upgrade verification instruction is equal to or lower than the system version of the current ARM chip, the ARM chip only outputs the ARM chip serial number, and the device to be upgraded sends the ARM chip serial number back to the host computer.

4. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices as described in claim 3, characterized in that, In S21, the device to be upgraded sends back the upgrade confirmation flag and / or the ARM chip serial number to the host computer, which specifically includes the following steps: S211: The device to be upgraded receives the post-back data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The second PHY chip of the device to be upgraded converts the analog signal of the post-back data into a digital signal and transmits it to the FPGA chip of the device to be upgraded. S212: The ARM chip of the device to be upgraded sends its own back data to its FPGA chip. The FPGA chip of the device to be upgraded performs packet processing on its own back data and the post-back data, and sends the integrated back data to its first PHY chip. The first PHY chip of the device to be upgraded converts the digital signal of the back data into an analog signal, and the device to be upgraded sends the back data to another device to be upgraded connected to its adjacent front through its first Ethernet port. S213: Repeat steps S211 - S212 until the first device to be upgraded receives the post-back data sent by another device to be upgraded connected to its adjacent rear through its second Ethernet port. The first device to be upgraded sends the back data integrated with its own back data and the post-back data to the host computer through the first Ethernet port.

5. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices as claimed in claim 2 or 4, wherein, Between the first PHY chip and the FPGA chip of the device to be upgraded, between the FPGA chip and the second PHY chip of the device to be upgraded, and between the FPGA chip and the ARM chip, communication connections are respectively achieved through the MII interface.

6. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices according to claim 4, wherein After the host computer receives the back data of several devices to be upgraded in S213, it further includes the following steps: S22: The host computer saves the upgrade confirmation flags and ARM chip serial number data sent back by several devices to be upgraded. S23: The first device to be upgraded receives the upgrade file sent by the host computer through its first Ethernet port and sends the upgrade file to another device to be upgraded connected to its adjacent rear through its second Ethernet port. S24: Except for the first device to be upgraded, any device to be upgraded respectively receives the upgrade file sent by another device to be upgraded connected to its adjacent front through its first Ethernet port and sends the upgrade file to another device to be upgraded connected to its adjacent rear through its second Ethernet port.

7. The simultaneous online upgrade method for multiple groups of parallel ARM devices as described in claim 6, characterized in that, In S24, the device to be upgraded receives the upgrade file through its first Ethernet port and sends the upgrade file through its second Ethernet port, which specifically includes the following steps: S241: After the device to be upgraded receives the upgrade file through its first Ethernet port, the first PHY chip of the device to be upgraded converts the analog signal of the upgrade file into a digital signal. If there is an upgrade requirement for the ARM chip system of the current device to be upgraded, the upgrade file is transmitted to the ARM chip through the FPGA chip, and the ARM chip performs an online upgrade operation; Moreover, the FPGA chip of the device to be upgraded outputs the upgrade file to its second PHY chip, and the second PHY chip converts the digital signal of the upgrade file into an analog signal, and the device to be upgraded outputs the upgrade file through its second Ethernet port.

8. The simultaneous online upgrade method applicable to multiple groups of parallel ARM devices as claimed in claim 7, wherein In S241, when the host computer sends the upgrade file and the device to be upgraded performs an ARM chip system upgrade, it further includes the following steps: S25: After the ARM chip systems of several devices to be upgraded with upgrade requirements are upgraded, the ARM chip of the device to be upgraded outputs the corresponding upgrade success flag and the ARM chip serial number, and sends them to the host computer; The host computer compares the received upgrade success flags and ARM chip serial numbers corresponding to several devices to be upgraded with the saved upgrade confirmation flags and ARM chip serial numbers corresponding to several devices to be upgraded. If there is a device to be upgraded that has not been successfully upgraded, the host computer locates the device to be upgraded that has not been successfully upgraded and outputs an alarm message.

9. A simultaneous online upgrade system applicable to multiple groups of parallel ARM devices, characterized in that, For implementing the simultaneous online upgrade method applicable to multiple groups of parallel ARM devices according to any one of claims 1-8, it includes: A host computer, which is used to provide upgrade files to several devices to be upgraded; Several devices to be upgraded. The first Ethernet port of the first device to be upgraded is communicatively connected to the host computer through an external network. Except for the first device to be upgraded, the first Ethernet port of any device to be upgraded is communicatively connected to the second Ethernet port of another adjacent pre-connected device to be upgraded through an internal network, and the second Ethernet port of any device to be upgraded is communicatively connected to the first Ethernet port of another adjacent post-connected device to be upgraded through an internal network.

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