Thermal simulation grid generation method for Chiplet chip and storage medium

Abstract

The invention relates to the field of integrated circuit design, and provides a thermal simulation grid generation method for a Chiplet chip and a storage medium. According to the method, the problems of low generation efficiency, high computing resource consumption and poor grid quality of the Chiplet chip thermal simulation grid in the prior art are solved. According to the main scheme, the method comprises the following steps: 1) acquiring coordinates of a Die module, and generating a Chiplet geometry; 2) inputting radiator, TIM and Package information, and generating a thermal simulation geometry; 3) geometric verification; 4) projecting to generate a two-dimensional geometry and an information file; 5) generating a two-dimensional grid through a Delauney algorithm; 6) stretching to form a three-dimensional grid; 7) inputting information again, generating a thermal simulation geometry, and generating an initial thermal simulation grid by the tetrahedral grid; and 8) verifying the grid quality, and if not, increasing the grid points and repeating the step 6. The grid generation efficiency is improved, the resource consumption is reduced, the quality is improved, multiple requirements are met, automation and intellectualization are achieved, and thermal simulation technology application is promoted.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and provides a thermal simulation grid generation method for a chiplet chip and a storage medium. Background Art

[0002] With the rapid development of integrated circuit technology, the integration and complexity of chips are constantly improving, and chiplet technology has become an important integrated solution. Chiplet chip is a chip that integrates multiple small core particle (Die) modules (called chiplets) into a package, and then electrically interconnects and packages them through the underlying substrate (Substrate). The packaging structure of the chiplet chip often includes a silicon interposer (Interposer), through silicon vias (TSV) and through vias (Via). The silicon interposer is used to achieve high-speed interconnection between Die modules, and through silicon vias (TSV) and through vias (Via) are used to vertically connect the chiplet chip to the substrate or other levels.

[0003] Chiplets adopt this multi-layer packaging structure design, which can improve performance while reducing production costs. However, the multi-layer packaging structure of chiplets and the differences in material properties in different areas lead to uneven heat distribution during operation, resulting in local overheating problems, which can seriously affect the stability and service life of chiplets. Therefore, how to effectively manage heat dissipation becomes a key challenge in the design and optimization of chiplets.

[0004] Thermal simulation technology helps designers optimize chip structures and heat dissipation solutions by simulating and analyzing heat conduction, convection, and radiation inside the chip. It can effectively solve the heat dissipation problem in the chip and has become an indispensable tool for chip optimization. In the process of thermal simulation, accurate grid generation is one of the key steps, which directly affects the accuracy of the simulation results of thermal simulation. At present, thermal simulation technology has been widely used in chiplet chip design.

[0005] Existing thermal simulation mesh generation methods usually use the Delauney mesh generation method. For traditional chips, the scale difference of their three-dimensional entities in the x, y, and z directions is small, and the Delauney mesh generation method generates meshes with high accuracy. However, since the chiplet chip has a special physical structure that is completely different from traditional chips, its scale in the z direction is much smaller than that in the x and v directions, and the difference even reaches the million level. In addition, the underlying substrate area of ​​the chiplet chip contains tens of thousands of through holes (vias), while the silicon interposer area has hundreds of thousands of through silicon vias (TSVs). The underlying substrate area and the silicon interposer area are also divided into multiple levels. For traditional chip thermal simulation, through holes (vias) and through silicon vias (TSVs) are small structures. These small structures are usually ignored when performing three-dimensional mesh division, but they are complex structures in chiplets and have a significant impact on the heat dissipation performance of chiplets. Therefore, for chiplets, if the Delauney mesh generation method ignores these complex structures during the mesh generation process, and does not process these complex structures, the generated mesh quality is poor, and it is difficult to fully reflect the fine thermal flow characteristics inside the chiplet chip. If this complex structure is processed, and at the same time, since the scale of the chiplet chip in the z direction is much smaller than the scale in the x and y directions, the Delauney mesh generation method needs to consume huge computing resources to generate high-precision meshes, resulting in high costs. The above problems limit the promotion and popularization of thermal simulation technology in the actual application of chiplets. Summary of the invention

[0006] The present invention aims to solve the problems existing in the existing chiplet chip thermal simulation grid generation method, namely, it is difficult to generate high-precision grids and the cost is high, which is not conducive to the promotion and popularization of thermal simulation technology in the actual application of chiplet chips.

[0007] The existing methods mainly use the Delauney grid generation method, but for the special physical structure of chiplets, this method has the following problems:

[0008] 1. The z-direction scale of the chiplet is much smaller than the x- and v-direction scales, which results in the Delauney mesh generation method consuming huge computing resources to generate high-precision meshes.

[0009] 2. The bottom substrate area of ​​the chiplet chip contains tens of thousands of through holes (vias), while the silicon interposer area has hundreds of thousands of through silicon vias (TSVs). These complex structures have a significant impact on the heat dissipation performance, but the Delauney mesh generation method often ignores these structures, resulting in poor quality of the generated mesh, which makes it difficult to fully reflect the fine thermal flow characteristics inside the chiplet chip.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] The present invention provides a method for generating a thermal simulation grid for a chiplet chip, comprising the following steps:

[0012] Step 1: Obtain the 3D coordinate information of each Die module from the physical design file of the chiplet chip and generate the corresponding chiplet geometry;

[0013] Step 2: Input the chiplet’s heat sink, TIM, and package geometry information into the thermal simulation software to generate the thermal simulation geometry.

[0014] Step 3: Perform geometric verification on the chiplet geometry and thermal simulation geometry;

[0015] Step 4: Project the chiplet geometry onto a two-dimensional plane to generate the chiplet two-dimensional geometry and information conversion file;

[0016] Step 5: Use the Delauney triangular mesh generation algorithm to process the chiplet two-dimensional geometry to obtain a two-dimensional mesh;

[0017] Step 6: Stretch the two-dimensional grid according to the recorded z-axis coordinate position to obtain a three-dimensional grid;

[0018] Step 7: Re-enter the chiplet chip's heat sink, TIM (thermal interface material) and package geometry information in the thermal simulation software to generate the thermal simulation geometry, and use the tetrahedral mesh generation method to obtain the initial thermal simulation mesh;

[0019] Regenerate the thermal simulation geometry in the thermal simulation software and use the tetrahedral mesh generation method to obtain the initial thermal simulation mesh;

[0020] Step 8: Verify the quality of the initial thermal simulation mesh. If it fails, add mesh points and re-execute step 6 until the verification passes.

[0021] In the above technical solution, step 1 includes:

[0022] Step 1.1: Get and parse the physical design file to obtain the original data set containing the three-dimensional coordinate information of each Die module;

[0023] Step 1.2: Filter and extract the three-dimensional coordinate information of each Die module to obtain a list of three-dimensional coordinate information of each Die module;

[0024] Step 1.3: Based on the 3D coordinate information list of each Die module, use 3D modeling technology to build a 3D model of each Die module according to the coordinate information, and integrate it into the underlying substrate, silicon interposer, through-hole and silicon via structures to form the basic chiplet geometry;

[0025] If thermal simulation is performed on the chiplet package, the chiplet geometry retains the information inside the underlying substrate. The silicon interposer and through silicon via (TSV) are considered as a die with no power consumption. The chiplet geometry includes the geometric information of each die module, the underlying substrate, and the through via.

[0026] If the silicon interposer of the chiplet is simulated, the chiplet geometry retains the internal information of the silicon interposer. The underlying substrate and via can be regarded as a homogeneous plate, and the internal via does not need to be meshed. At this time, the chiplet geometry includes the geometric information of each die module, silicon interposer, and through silicon via (TSV).

[0027] In the above technical solution, step 3 specifically includes:

[0028] Chiplet geometry verification sub-steps:

[0029] Step 3.1. Determine the position of each via in the chiplet geometry to confirm whether it is located below the corresponding Die module and on the underlying substrate, and record the position status of each via.

[0030] Step 3.2: Determine the position of each through silicon via (TSV) in the chiplet geometry to confirm whether it is located inside the silicon interposer, and record the position status of each through silicon via (TSV);

[0031] Step 3.3: Based on the recorded results of steps 3.1 and 3.2, determine whether the positions of all through holes (Via) and through silicon vias (TSV) in the chiplet geometry meet the preset requirements. If they do, the geometry verification of the chiplet geometry is considered to have passed, and the verification sub-step of the thermal simulation geometry is entered; if not, the geometry verification of the chiplet geometry is considered to have failed, the process ends, and mesh generation cannot continue.

[0032] The preset requirements in step 3.3 are as follows:

[0033] If all the vias in the chiplet geometry are located below the corresponding die module and on the underlying substrate, and all the through-silicon vias (TSVs) are located inside the silicon interposer;

[0034] Verification sub-steps for thermal simulation geometry:

[0035] Step 3.4, measuring the bottom surface height of the thermal simulation geometric body to obtain the bottom surface height value of the thermal simulation geometric body;

[0036] Step 3.5, compare the bottom surface height value of the thermal simulation geometry obtained in step 3.4 with the top surface height value of the chiplet geometry;

[0037] Step 3.6, determine whether the comparison results in step 3.5 are equal. If they are equal, it is considered that the geometric verification of the thermal simulation geometry has passed, and proceed to step 4; if they are not equal, it is considered that the geometric verification of the thermal simulation geometry has failed, the process ends, and mesh generation cannot continue.

[0038] In the above technical solution, step 4 specifically includes:

[0039] Step 4.1, traverse each component in the chiplet geometry and extract its three-dimensional coordinate information, including x-axis, y-axis, and z-axis coordinates;

[0040] Step 4.2, set the z-axis coordinate of each component extracted in step 4.1 to 0, retain the x-axis and y-axis coordinates, and obtain the two-dimensional coordinate information of each component;

[0041] Step 4.3: Based on the two-dimensional coordinate information of each component obtained in step 4.2, a two-dimensional representation of the chiplet geometry is constructed, that is, the two-dimensional coordinate information of all components is integrated to form a two-dimensional chiplet geometry;

[0042] Step 4.4: Generate a file for converting chiplet geometry from 3D to 2D, and record the correspondence between the original 3D coordinate information of each component and its corresponding 2D coordinate information for use in subsequent steps.

[0043] Step 4.5: Output the chiplet 2D geometry as input for subsequent mesh generation steps.

[0044] In the above technical solution, step 7 specifically includes: re-inputting the geometric information of the heat sink, TIM (thermal interface material) and package (packaging) of the chiplet chip in the thermal simulation software, regenerating the thermal simulation geometry on the three-dimensional mesh currently obtained in step 6, and using the tetrahedral mesh generation method to obtain the mesh of the area where the regenerated thermal simulation geometry is located, and using the mesh of the area where the regenerated thermal simulation geometry is located as the initial thermal simulation mesh of the chiplet chip;

[0045] In the above technical solution, step 8 includes the following steps:

[0046] Step 8.1: Calculate the geometric properties of the grid cells

[0047] For each grid cell in the initial thermal simulation grid of the chiplet chip, calculate its aspect ratio and inclination. The aspect ratio is defined as the ratio of the maximum side length to the minimum side length of the grid cell. The inclination is used to measure the degree of deviation of the shape of the grid cell from the ideal geometric shape.

[0048] Step 8.2: Evaluate the orthogonality of adjacent grid cells

[0049] Check the intersection angle between two adjacent grid cells to ensure that the orthogonality between them meets the preset quality requirements;

[0050] Step 8.3. Compare grid cell characteristics with preset standards

[0051] The calculated aspect ratio, inclination, and orthogonality of adjacent grid cells of each grid cell are compared with preset quality standards;

[0052] Step 8.4: Determine whether the mesh quality meets the requirements

[0053] If the aspect ratio, inclination and orthogonality of adjacent grid cells of all grid cells meet the preset quality requirements, it is considered that the quality verification of the initial thermal simulation grid of the current chiplet chip has passed; if the characteristics of at least one grid cell do not meet the preset requirements, it is considered that the quality verification of the initial thermal simulation grid of the current chiplet chip has failed;

[0054] Step 8.5: Optimize the 2D grid

[0055] If the verification result in step 8.4 is not passed, the current two-dimensional mesh is optimized, a mesh point is added at the centroid of each triangular mesh of the current two-dimensional mesh, and the mesh point at the centroid of each triangular mesh is connected to each vertex of the triangular mesh to form a new triangular mesh, and the two-dimensional mesh obtained at this time is used as the current two-dimensional mesh;

[0056] Step 8.6: Return to step 6 to regenerate the 3D mesh

[0057] If the mesh optimization in step 8.6 is performed, the optimized two-dimensional mesh is returned to step 6 to generate the three-dimensional mesh again;

[0058] Step 8.8, loop iteration until verification is passed

[0059] Repeat steps 8.1 to 8.7 until the quality verification of the initial thermal simulation mesh of the chiplet chip is passed.

[0060] The present invention also provides a storage medium, and when a processor executes a program in the storage medium, the processor implements the thermal simulation grid generation method for a chiplet chip.

[0061] Because the present invention adopts the above technical means, it has the following beneficial effects:

[0062] 1. Improve grid generation efficiency:

[0063] The present invention projects the chiplet geometry onto a two-dimensional plane, uses the Delauney triangle mesh generation algorithm to process the two-dimensional geometry, and then stretches the two-dimensional mesh according to the recorded z-axis coordinate position to obtain a three-dimensional mesh. This effectively avoids the problem of excessive consumption of computing resources caused by directly processing complex structures (such as through holes and silicon vias) in three-dimensional space. The efficiency of mesh generation is significantly improved, and tens of thousands of through holes and silicon vias can be processed in a short time, which is several times higher than the existing methods.

[0064] 2. Reduce computing resource consumption:

[0065] The projection method provided by the present invention converts a three-dimensional geometric body into a two-dimensional geometric body, simplifies the mesh generation process, and reduces the computational complexity. It overcomes the problem that the traditional Delauney mesh generation method consumes huge computing resources when processing chiplets due to the small scale in the z direction. It greatly reduces the computing resources required for mesh generation, reduces costs, and is conducive to the promotion and popularization of thermal simulation technology.

[0066] 3. Improve mesh quality:

[0067] The geometric verification provided by the present invention ensures the accuracy of the chiplet geometry and thermal simulation geometry; the mesh quality verification and optimization steps ensure that the generated mesh meets the preset quality standards. The problem that the existing method ignores the complex structure, resulting in poor mesh quality and difficulty in reflecting the fine thermal flow characteristics inside the chip is solved. The accuracy of the generated mesh is achieved, which can fully reflect the thermal flow characteristics inside the chiplet chip and improve the accuracy of the thermal simulation.

[0068] 4. Adapt to different simulation needs:

[0069] According to the simulation object (package or silicon interposer), the internal information retention degree of the chiplet geometry can be flexibly adjusted. The different requirements of different simulation scenarios for mesh generation details are met. The applicability of the method is enhanced, and efficient and accurate mesh generation can be performed for packages or silicon interposers.

[0070] 5. Automatic and intelligent grid generation:

[0071] Through programming, a series of steps such as obtaining information from physical design files, geometry generation, verification, mesh generation, quality verification and optimization are automated. This reduces manual intervention and improves the intelligence level of mesh generation. It achieves fast, accurate and automated thermal simulation mesh generation, improving design efficiency.

[0072] In summary, the present invention effectively solves the problems of efficiency, cost, quality and adaptability in the generation of thermal simulation grids for chiplets through a combination of innovative technical means, achieves the effects of high efficiency, low cost, high precision and wide applicability, and promotes the application of thermal simulation technology in chiplet chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 It is a flow chart of the method for generating a thermal simulation grid for a chiplet chip according to the present invention;

[0074] Figure 2 This is a mesh division bottom surface effect diagram of the thermal simulation mesh generation method for chiplet chips of the present invention. As shown in the figure, detailed chiplet geometry information such as via is contained inside;

[0075] Figure 3 This is a mesh division effect diagram of the thermal simulation mesh generation method for chiplet chips of the present invention. As shown in the figure, the chiplet thermal simulation geometry is divided into tetrahedral meshes, and the chiplet geometry is divided into triangular prism meshes in a stretching manner. DETAILED DESCRIPTION

[0076] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions made to the present invention should all be included in the scope of the claims of the present invention.

[0077] In addition, in order to better illustrate the present invention, numerous specific details are given in the following specific embodiments. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0078] The present invention provides a method for generating a thermal simulation grid for a chiplet chip, comprising the following steps:

[0079] Step 1: Obtain the 3D coordinate information of each Die module of the chiplet chip from the physical design file of the chiplet chip, and generate the 3D geometric body corresponding to the chiplet chip based on the 3D coordinate information of each Die module of the chiplet chip, which is called the chiplet geometric body; if thermal simulation is performed on the chiplet chip package, the chiplet geometric body needs to retain the information inside the underlying substrate in detail. The silicon interposer and through silicon via (TSV) can be regarded as a die without power consumption. The chiplet geometric body includes The chiplet geometry includes the geometry information of the die modules, the underlying substrate, and the through-holes (TSV). If the chiplet chip's silicon interposer is simulated, the chiplet geometry needs to retain the information inside the silicon interposer in detail. The underlying substrate and the through-holes (Via) can be regarded as a homogeneous plate, and the internal through-holes (Via) do not need to be meshed. At this time, the chiplet geometry includes the geometry information of the die modules, the silicon interposer, and the through-silicon vias (TSV).

[0080] Step 2: Input the chiplet chip's heat sink, TIM (thermal interface material) and package geometry information into the thermal simulation software, and generate the corresponding three-dimensional geometry, which is called the thermal simulation geometry.

[0081] Step 3, respectively verify the chiplet geometry and thermal simulation geometry, wherein the specific method of geometric verification of the chiplet geometry is: determine whether each through hole (Via) in the chiplet geometry is below its corresponding Die module and on the underlying substrate (Substrate), and whether each through silicon via (TSV) is inside the silicon interposer (Interposer); the specific method of verifying the thermal simulation geometry is: determine whether the bottom surface height of the thermal simulation geometry is equal to the top surface height of the chiplet geometry;

[0082] If all the conditions are satisfied at the same time, that each through hole (Via) in the chiplet geometry is below its corresponding Die module and on the underlying substrate (Substrate), that each through silicon via (TSV) is inside the silicon interposer, and that the bottom surface height of the thermal simulation geometry is equal to the top surface height of the chiplet geometry, then the verification is considered to have passed, and step 4 is entered. If all the conditions are not satisfied at the same time, that each through hole (Via) in the chiplet geometry is below its corresponding Die module and on the underlying substrate (Substrate), that each through silicon via (TSV) is inside the silicon interposer, and that the bottom surface height of the thermal simulation geometry is equal to the top surface height of the chiplet geometry, then the verification is considered to have failed, indicating that the physical design file of the chiplet chip is incorrect, and the process ends at this time, and mesh generation cannot continue;

[0083] Step 4, record the z-axis coordinate position of each component of the chiplet geometry in the three-dimensional coordinate, set the z-axis coordinate of each component of the chiplet geometry in the three-dimensional coordinate to 0, project the chiplet geometry onto the two-dimensional plane, obtain the two-dimensional geometry corresponding to the chiplet geometry, and generate the information conversion file of the chiplet geometry from three-dimensional to two-dimensional. The two-dimensional geometry obtained at this time is called the chiplet two-dimensional geometry. The components included in the chiplet two-dimensional geometry are the same as those included in the chiplet geometry, except that the z-axis coordinate of each component in the chiplet two-dimensional geometry in the three-dimensional coordinate is 0;

[0084] Step 5: Use the Delauney triangular mesh generation algorithm to process the chiplet two-dimensional geometry obtained in step 4 to obtain a two-dimensional mesh composed of several triangular meshes;

[0085] Step 6: According to the z-axis coordinate positions of the components of the chiplet geometry recorded in step 4 in the three-dimensional coordinates, for the two-dimensional mesh obtained in step 5, stretch all the two-dimensional meshes upward in the direction perpendicular to the two-dimensional mesh plane until they reach the z-axis coordinate position. At this time, the two-dimensional triangular mesh is stretched into a three-dimensional triangular prism mesh. The stretching method reduces the complexity of generating the spatial mesh and obtains the corresponding three-dimensional mesh.

[0086] Step 7. Re-enter the chiplet chip's heat sink, TIM (thermal interface material) and package geometry information in the thermal simulation software, regenerate the thermal simulation geometry on the three-dimensional mesh currently obtained in step 6, and use the tetrahedral mesh generation method to obtain the mesh of the area where the regenerated thermal simulation geometry is located, and use the mesh of the area where the regenerated thermal simulation geometry is located as the initial thermal simulation mesh of the chiplet chip;

[0087] Step 8: Verify the quality of the initial thermal simulation mesh of the chiplet chip currently obtained. If the verification is passed, the initial thermal simulation mesh of the chiplet chip currently obtained is the thermal simulation mesh of the chiplet chip finally generated. If the verification is not passed, a grid point is added at the centroid of each triangular mesh of the currently obtained two-dimensional mesh, and the grid point at the centroid of each triangular mesh is connected to each vertex of the triangular mesh respectively, so that three new triangular meshes are formed at each triangular mesh, and then the two-dimensional mesh obtained at this time is used as the current two-dimensional mesh, and the execution is returned to step 6 and started again until the quality verification of the initial thermal simulation mesh of the chiplet chip currently obtained is passed.

[0088] Furthermore, in step 8, the specific method of verifying the quality of the initial thermal simulation grid of the chiplet chip currently obtained is:

[0089] Step 88-1, calculate the aspect ratio and inclination of each grid cell in the initial thermal simulation grid of the chiplet chip currently obtained, and the orthogonality between two adjacent grid cells, where the aspect ratio of the grid cell = the maximum side length of the grid cell / the minimum side length of the grid cell, the inclination is used to measure the degree to which the shape of the grid cell deviates from the ideal geometric shape, and the orthogonality refers to the intersection angle between two adjacent grid cells;

[0090] Step 88-2: determine whether the aspect ratio and inclination of all grid cells and the orthogonality between all two adjacent grid cells meet the preset quality requirements. If yes (i.e., the aspect ratio and inclination of all grid cells and the orthogonality between all two adjacent grid cells meet the preset quality requirements), the quality verification of the initial thermal simulation grid of the chiplet chip currently obtained passes. If no (at least one of the aspect ratio and inclination of all grid cells and the orthogonality between all two adjacent grid cells does not meet the preset quality requirements), the quality verification of the initial thermal simulation grid of the chiplet chip currently obtained fails.

[0091] In summary, the present invention has the following characteristics:

[0092] After obtaining the correct chiplet geometry, the projection method is used to convert the chiplet geometry from a three-dimensional geometry into a two-dimensional geometry, and then a two-dimensional network is generated based on the two-dimensional geometry, and then the generation of the grid in the z-axis direction is completed by simple stretching to form a three-dimensional grid. In the process of generating the two-dimensional network using the Delauney triangle grid generation algorithm, the size of the chiplet geometry in the z-axis direction is ignored, and a large number of projected through holes (Via) and through silicon vias (TSV) can be quickly meshed. In this way, the size of the through holes (Via) and through silicon vias (TSV) and the chiplet geometry in the z-axis direction no longer has a great impact on the efficiency of grid generation, and does not require a large amount of computing resources. Therefore, the thermal simulation of chiplets of the present invention is simple and convenient. The mesh generation method combines the projection method with the stretching method, and adopts the Delauney triangle mesh generation algorithm in conjunction with the tetrahedral mesh generation method. While generating high-precision meshes, it does not require a large amount of computing resources, and has a low cost, which is conducive to the promotion and popularization of thermal simulation technology in the actual application of chiplets. After testing, the thermal simulation mesh generation method for chiplets of the present method can generate its mesh in 155 seconds when the chiplet chip has two thousand through silicon vias (TSVs), and can quickly process tens of thousands of through holes (Via) and through silicon vias (TSVs). In contrast, the existing method that simply uses the tetrahedral mesh generation method can only process hundreds of through holes (Vias) and through silicon vias (TSVs), which has been significantly improved and has a wider application.

Claims

1. A method for generating a thermal simulation grid for a chiplet, characterized in that: The following steps are involved: Step 1: Obtain the 3D coordinate information of each Die module from the physical design file of the chiplet chip and generate the corresponding chiplet geometry; Step 2: Input the chiplet’s heat sink, TIM, and Package geometry information into the thermal simulation software to generate a thermal simulation geometry, where TIM stands for thermal interface material and Package stands for package. Step 3: Perform geometric verification on the chiplet geometry and thermal simulation geometry; Step 4: Project the chiplet geometry onto a two-dimensional plane to generate the chiplet two-dimensional geometry and information conversion file; Step 5: Use the Delauney triangular mesh generation algorithm to process the chiplet two-dimensional geometry obtained in step 4 to obtain a two-dimensional mesh composed of several triangular meshes; Step 6: According to the z-axis coordinate positions of the components of the chiplet geometry in the three-dimensional coordinates recorded in step 4, for the two-dimensional mesh obtained in step 5, stretch all the two-dimensional meshes upward in the direction perpendicular to the two-dimensional mesh plane until they reach the z-axis coordinate position. At this time, the two-dimensional triangular mesh is stretched into a three-dimensional triangular prism mesh, and the corresponding three-dimensional mesh is obtained; Step 7: Re-enter the chiplet’s heat sink, TIM, and package geometry information in the thermal simulation software to generate the thermal simulation geometry, and use the tetrahedral mesh generation method to obtain the initial thermal simulation mesh; Regenerate the thermal simulation geometry in the thermal simulation software and use the tetrahedral mesh generation method to obtain the initial thermal simulation mesh; Step 8: Verify the quality of the initial thermal simulation mesh. If it fails, add mesh points and re-execute step 6 until the verification passes.

2. The method for generating a thermal simulation grid for a chiplet according to claim 1, characterized in that: Step 1 includes: Step 1.1: Get and parse the physical design file to obtain the original data set containing the three-dimensional coordinate information of each Die module; Step 1.2: Filter and extract the three-dimensional coordinate information of each Die module to obtain a list of three-dimensional coordinate information of each Die module; Step 1.3: Based on the 3D coordinate information list of each Die module, use 3D modeling technology to build a 3D model of each Die module according to the coordinate information, and integrate it into the underlying substrate, silicon interposer, through-hole and silicon via structures to form the basic chiplet geometry; If thermal simulation is performed on the chiplet package, the chiplet geometry retains the information inside the underlying substrate. The silicon interposer and the through silicon via are regarded as a core particle with no power consumption, that is, a die module with no power consumption. The chiplet geometry includes the geometric information of each die module, the underlying substrate, and the through-hole. If the silicon interposer of the chiplet chip is simulated, the chiplet geometry retains the information inside the silicon interposer. The underlying substrate and the through-holes can be regarded as a homogeneous plate, and the internal through-holes do not need to be meshed. At this time, the chiplet geometry includes the geometric information of each Die module, silicon interposer, and silicon through-hole.

3. The method for generating a thermal simulation grid for a chiplet according to claim 1, characterized in that: The verification sub-step of the chiplet geometry in step 3: Step 3.1, determine the position of each through hole in the chiplet geometry to confirm whether it is located below the corresponding Die module and on the underlying substrate, and record the position status of each through hole; Step 3.2: Determine the position of each through silicon via in the chiplet geometry to confirm whether it is located inside the silicon interposer, and record the position status of each through silicon via; Step 3.3: Based on the recorded results of steps 3.1 and 3.2, determine whether the positions of all through holes and through silicon vias in the chiplet geometry meet the preset requirements. If so, it is considered that the geometry verification of the chiplet geometry has passed, and the verification sub-step of the thermal simulation geometry is entered; if not, it is considered that the geometry verification of the chiplet geometry has failed, the process ends, and mesh generation cannot continue.

4. The method for generating a thermal simulation grid for a chiplet according to claim 3, characterized in that: The preset requirements in step 3.3 are as follows: If it is satisfied that each through hole in the chiplet geometry is below its corresponding Die module and on the underlying substrate, and each silicon through via is inside the silicon interposer.

5. The method for generating a thermal simulation grid for a chiplet according to claim 4, characterized in that: Verification sub-steps of thermal simulation geometry in step 3: Step 3.4, measuring the bottom surface height of the thermal simulation geometric body to obtain the bottom surface height value of the thermal simulation geometric body; Step 3.5, compare the bottom surface height value of the thermal simulation geometry obtained in step 3.4 with the top surface height value of the chiplet geometry; Step 3.6, determine whether the comparison results in step 3.5 are equal. If they are equal, it is considered that the geometric verification of the thermal simulation geometry has passed, and proceed to step 4; if they are not equal, it is considered that the geometric verification of the thermal simulation geometry has failed, the process ends, and mesh generation cannot continue.

6. The method for generating a thermal simulation grid for a chiplet according to claim 1, characterized in that: Step 4 specifically includes: Step 4.1, traverse each component in the chiplet geometry and extract its three-dimensional coordinate information, including x-axis, y-axis, and z-axis coordinates; Step 4.2, set the z-axis coordinate of each component extracted in step 4.1 to 0, retain the x-axis and y-axis coordinates, and obtain the two-dimensional coordinate information of each component; Step 4.3: Based on the two-dimensional coordinate information of each component obtained in step 4.2, a two-dimensional representation of the chiplet geometry is constructed, that is, the two-dimensional coordinate information of all components is integrated to form a two-dimensional chiplet geometry; Step 4.4: Generate a file for converting chiplet geometry from 3D to 2D, and record the correspondence between the original 3D coordinate information of each component and its corresponding 2D coordinate information for use in subsequent steps. Step 4.5: Output the chiplet 2D geometry as input for subsequent mesh generation steps.

7. The method for generating a thermal simulation grid for a chiplet according to claim 1, characterized in that: Step 7 specifically includes: re-inputting the geometric information of the heat sink, TIM and Package of the chiplet chip in the thermal simulation software, regenerating the thermal simulation geometry on the three-dimensional mesh currently obtained in step 6, and using the tetrahedral mesh generation method to obtain the mesh of the area where the regenerated thermal simulation geometry is located, and using the mesh of the area where the regenerated thermal simulation geometry is located as the initial thermal simulation mesh of the chiplet chip.

8. The method for generating a thermal simulation grid for a chiplet according to claim 1, characterized in that: Step 8.1: Calculate the geometric properties of the grid cells For each grid cell in the initial thermal simulation grid of the chiplet chip, calculate its aspect ratio and inclination. The aspect ratio is defined as the ratio of the maximum side length to the minimum side length of the grid cell. The inclination is used to measure the degree of deviation of the shape of the grid cell from the ideal geometric shape. Step 8.2: Evaluate the orthogonality of adjacent grid cells Check the intersection angle between two adjacent grid cells to ensure that the orthogonality between them meets the preset quality requirements; Step 8.

3. Compare grid cell characteristics with preset standards The calculated aspect ratio, inclination, and orthogonality of adjacent grid cells of each grid cell are compared with preset quality standards; Step 8.4: Determine whether the mesh quality meets the requirements If the aspect ratio, inclination and orthogonality of adjacent grid cells of all grid cells meet the preset quality requirements, it is considered that the quality verification of the initial thermal simulation grid of the current chiplet chip has passed; if the characteristics of at least one grid cell do not meet the preset requirements, it is considered that the quality verification of the initial thermal simulation grid of the current chiplet chip has failed; Step 8.5: Optimize the 2D mesh If the verification result in step 8.4 is not passed, the current two-dimensional mesh is optimized, a mesh point is added at the centroid of each triangular mesh of the current two-dimensional mesh, and the mesh point at the centroid of each triangular mesh is connected to each vertex of the triangular mesh to form a new triangular mesh, and the two-dimensional mesh obtained at this time is used as the current two-dimensional mesh; Step 8.6: Return to step 6 to regenerate the 3D mesh If the mesh optimization in step 8.6 is performed, the optimized two-dimensional mesh is returned to step 6 to generate the three-dimensional mesh again; Step 8.8, repeat step 8 until verification is passed Repeat steps 8.1 to 8.7 until the quality verification of the initial thermal simulation mesh of the chiplet chip is passed.

9. A storage medium, characterized in that: When the processor executes the program in the storage medium, the method for generating a thermal simulation grid for a chiplet chip according to any one of claims 1 to 8 is implemented.

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