United verification method and device of USART and DMA, equipment and medium

Abstract

The invention relates to a USART (Universal Synchronous Asynchronous Receiver Transmitter) and DMA (Direct Memory Access) joint verification method and device, equipment and a medium. The method is applied to a verification platform comprising a verification environment component and a to-be-tested design, the to-be-tested design comprises a memory, a plurality of DMAs and a plurality of USARTs, and the method comprises the following steps: reading to-be-sent first data from the memory through a first DMA in the plurality of DMAs, transmitting the first data to a first USART in the plurality of USARTs based on a first channel which is pre-configured in the first DMA and is used for data transmission; establishing a transmission connection between the first USART and a second USART in the plurality of USART by using the verification environment component, so as to transmit second data to the second USART; second data in the second USART is transmitted to a second DMA in the multiple DMAs based on the second channel, so that the second DMA writes the second data into the memory; and comparing the first data with the second data through the verification environment component to generate a verification result. The united verification of the USART and the DMA is realized, and the verification efficiency is improved while the verification correctness and stability are ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a USART and DMA joint verification method, device, equipment and medium. Background Art

[0002] With the continuous advancement of semiconductor technology and the increasing complexity of integrated circuits, system-level verification has become a key link to ensure the correctness and stability of digital systems. In digital systems, Universal Synchronous / Asynchronous Receiver / Transmitter (USART) and Direct Memory Access (DMA) are two important functional modules. Among them, USART is responsible for serial communication of data, supports both synchronous and asynchronous communication modes, and is widely used in various communication interfaces. DMA is responsible for fast data transmission between memory and external devices without the participation of the Central Processing Unit (CPU), greatly improving the data transmission efficiency of the system.

[0003] In system-level verification, traditional verification methods are often unable to cope with the verification requirements of complex systems. Therefore, there is an urgent need to provide a verification method that can perform joint verification of USART and DMA at the system level, verify the functions of each module in USART and DMA, and the interaction between USART and DMA. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present disclosure provide a USART and DMA joint verification method, device, equipment and medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a joint verification method of USART and DMA, which is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, multiple DMAs, and multiple USARTs, and the method includes:

[0006] Reading first data to be sent from a memory through a first DMA among the multiple DMAs, and transmitting the first data to a first USART among the multiple USARTs based on a first channel preconfigured in the first DMA for data sending;

[0007] Using the verification environment component to establish a transmission connection between the first USART and a second USART among the multiple USARTs, so as to transmit second data to the second USART; wherein the second data is obtained according to the first data;

[0008] Based on the second channel, the second data in the second USART is transmitted to the second DMA in the plurality of DMAs, so that the second DMA writes the second data into the memory; wherein the second channel is a channel pre-configured in the second DMA for data reception;

[0009] The first data and the second data are compared by the verification environment component to generate a verification result.

[0010] The verification environment component includes an interface component and a driver component, wherein the interface component pre-defines multiple interfaces, the multiple interfaces are connected one by one with corresponding multiple ports, the multiple ports refer to multiple USART ports, the multiple interfaces include a sending interface and a receiving interface, and the driver component is used to connect the sending interface and the receiving interface.

[0011] Optionally, establishing a transmission connection between the first USART and a second USART among the multiple USARTs using a verification environment component includes:

[0012] A transmission connection between a first transmitting interface and a first receiving interface is established by using a driving component; wherein the first transmitting interface corresponds to a first transmitting port of a first USART, and the first receiving interface corresponds to a first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0013] Optionally, establishing a transmission connection between the first sending interface and the first receiving interface by using a driving component includes:

[0014] Obtain verification requirements that reflect verification functions and / or verification timing;

[0015] Determine the target time for establishing a transmission connection between the first sending interface and the first receiving interface according to the verification requirement;

[0016] A transmission connection between the first transmitting interface and the first receiving interface is established at a target time using a driving component.

[0017] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes:

[0018] Performing register configuration on the plurality of DMAs so that a plurality of channels for data transmission included in at least one of the plurality of DMAs are connected to at least one of the plurality of USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width;

[0019] The memory is configured for reading and writing so that data can be written into the memory in a preset language and data can be read from the memory in a preset language.

[0020] Optionally, the verification environment component includes a monitoring component, a reference model, and a scoreboard component. The verification environment component is used to compare the first data with the second data to generate a verification result, including:

[0021] receiving, by the monitoring component, second data read from the memory in a preset language, and transmitting it to the scoreboard component as actual data;

[0022] Reading the content of the configuration file through the reference model, and transmitting the read content to the scoreboard component as expected data; wherein the content of the configuration file is generated by extracting the stimulus data in a preset language, and the content of the configuration file includes a register configuration and first data obtained by writing the stimulus data into a memory;

[0023] The actual data is compared with the expected data through the scoreboard component to generate verification results.

[0024] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes:

[0025] A verification combination between multiple DMAs and multiple USARTs is set according to the verification requirements to perform joint verification of USART and DMA under the verification combination; wherein the verification combination includes a first combination, a second combination, a third combination, and a fourth combination, wherein:

[0026] The first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs;

[0027] The second combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are the same USART;

[0028] The third combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are different USARTs;

[0029] The fourth combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART.

[0030] Optionally, when multiple DMAs need to read data from the memory and / or write data to the memory, the method further includes:

[0031] Obtain a first priority preset for each of the multiple DMAs;

[0032] Reading first data to be sent from a memory through a first DMA among the multiple DMAs includes:

[0033] Reading first data from a memory according to a first priority through a first DMA;

[0034] The second DMA writes the second data into the memory, including:

[0035] The second DMA writes the second data into the memory according to the first priority.

[0036] Optionally, the first DMA includes a plurality of preconfigured transmission channels for data transmission, and when the first DMA transmits data to at least two USARTs through the plurality of transmission channels, transmitting the first data to a first USART among the plurality of USARTs based on the first channel preconfigured for data transmission in the first DMA includes:

[0037] Obtaining a second priority preset for each sending channel among a plurality of sending channels;

[0038] According to a second priority, first data is transmitted to a first USART based on a first channel; wherein the plurality of transmission channels include the first channel, and the at least two USARTs include the first USART.

[0039] Optionally, the second DMA includes multiple receiving channels, and when at least two USARTs are to transmit data to the second DMA through the multiple receiving channels, transmitting the second data in the second USART to the second DMA in the multiple DMAs based on the second channel includes:

[0040] Obtaining a third priority preset for each receiving channel among a plurality of receiving channels;

[0041] According to a third priority, the corresponding second data in the second USART is transferred to the second DMA based on the second channel; wherein the plurality of receiving channels include the second channel, and the at least two USARTs include the second USART.

[0042] In a second aspect, an embodiment of the present disclosure provides a joint verification device of USART and DMA, which is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, multiple DMAs, and multiple USARTs, and the device includes:

[0043] a first transmission unit, configured to read first data to be sent from a memory through a first DMA among the multiple DMAs, and transmit the first data to a first USART among the multiple USARTs based on a first channel for data sending preconfigured in the first DMA;

[0044] A connection establishing unit, used for establishing a transmission connection between the first USART and a second USART among the plurality of USARTs by using the verification environment component, so as to transmit second data to the second USART; wherein the second data is obtained according to the first data;

[0045] A second transmission unit is used to transmit the second data in the second USART to a second DMA in the plurality of DMAs based on a second channel, so that the second DMA writes the second data into the memory; wherein the second channel is a pre-configured channel in the second DMA for data reception;

[0046] The verification unit is used to compare the first data and the second data through a verification environment component to generate a verification result.

[0047] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

[0048] Memory;

[0049] Processor; and

[0050] Computer programs;

[0051] The computer program is stored in the memory and is configured to be executed by the processor to implement the method of the first aspect as described above.

[0052] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method of the first aspect are implemented.

[0053] The joint verification method of USART and DMA provided by the present disclosure is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, multiple DMAs and multiple USARTs, and the method includes: reading the first data to be sent from the memory through the first DMA in the multiple DMAs, and transmitting the first data to the first USART in the multiple USARTs based on the first channel pre-configured for data transmission in the first DMA; using the verification environment component to establish a transmission connection between the first USART and the second USART in the multiple USARTs to transmit the second data to the second USART; wherein the second data is obtained according to the first data; based on the second channel, the second data in the second USART is transmitted to the second DMA in the multiple DMAs, so that the second DMA writes the second data into the memory; wherein the second channel is a pre-configured channel for data reception in the second DMA; and the first data and the second data are compared by the verification environment component to generate a verification result. The method provided by the present application performs joint verification of multiple USARTs and multiple DMAs at the system level, which ensures the correctness and stability of the system-level verification while also improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0056] Figure 1 A schematic diagram of the structure of a traditional verification system provided by an embodiment of the present disclosure;

[0057] Figure 2 A flowchart of a joint verification method of USART and DMA provided in an embodiment of the present disclosure;

[0058] Figure 3 A schematic diagram of the structure of a verification platform provided by an embodiment of the present disclosure;

[0059] Figure 4 A structural schematic diagram of a USART and DMA joint verification device provided in an embodiment of the present disclosure;

[0060] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0063] Specifically, it is verified at the system level that multiple USARTs and multiple DMAs can operate normally at the same time and improve the verification efficiency. However, system-level verification is complex. Specifically, with the rapid development of integrated circuit (IC) technology, the demand for complex digital systems in fields such as digital communications is increasing, and the integration scale and functional complexity of chips are showing exponential growth. Among them, integrated circuits are microelectronic devices that integrate multiple electronic components (such as transistors, resistors, capacitors, etc.) and their interconnections on a small semiconductor substrate. In the actual operation of the chip, there are scenarios where multiple USARTs and multiple DMAs jointly transmit data. In order to cover the functional points of this scenario, the system-level verification becomes extremely complex. Therefore, an efficient and wide-coverage verification method is required to ensure the correctness and stability of the system-level verification. In addition, for system-level verification, traditional verification methods still have limitations. Specifically, traditional verification methods, such as verification methods based on directional testing, have problems such as poor reusability and low verification efficiency. When multiple USARTs and multiple DMAs are jointly verified at the system level, multiple slaves or hosts corresponding to the USART are required to receive data from the USART or drive the data obtained from the DMA and transmit it to the USART. Such a traditional verification structure makes the overall system-level verification framework more complicated, and the timing of stimulus driving and detection during joint verification becomes more difficult to grasp. At the same time, due to the existence of multiple master / slave machines during verification and debugging, it is difficult to quickly locate the problem, thereby reducing verification efficiency. For example, see Figure 1 , Figure 1 A schematic diagram of a conventional verification system provided by an embodiment of the present disclosure is shown in FIG. Figure 1In the traditional structure shown, the host drives the data obtained from the DMA, for example, the excitation data is driven into a waveform according to the timing and sent to the USART, and the slave monitors the data received from the USART, for example, the received waveform is monitored and restored into data according to the timing. However, the driving timing and monitoring timing during the joint verification of the master / slave are difficult to grasp; the slave scoreboard takes the data monitored by the slave as the actual data, and the data extracted by the slave reference model according to the configuration file as the expected data, and the actual data is compared with the expected data, so as to judge the correctness and stability of the design to be tested; correspondingly, the host reference model takes the data driven by the host as the expected data, and the host scoreboard takes the data received from the design to be tested as the actual data, and the actual data is compared with the expected data, so as to judge the correctness and stability of the design to be tested. This kind of master / slave verification makes the verification structure more complicated; in addition, multiple USARTs may correspond to multiple master / slave machines. During verification and debugging, due to the existence of multiple master / slave machines, it is difficult to quickly locate the component with the problem, thereby reducing the verification efficiency.

[0064] In summary, the existing system-level verification methods have the following problems:

[0065] (1) Mismatch between technical complexity and verification requirements

[0066] As verification requirements increase, it is difficult to perform joint simulation on multiple modules (multiple USARTs and multiple DMAs) at the system level. Existing verification methods may not be able to fully cover all possible test scenarios, resulting in insufficient verification completeness.

[0067] (2) Difficulty in building and debugging the verification environment

[0068] System-level verification involves multiple modules and multiple components (such as Figure 1 It takes a lot of time and resources to build and debug the verification environment, which leads to inefficient construction of the verification environment and may contain difficult-to-find errors, affecting the accuracy of the verification.

[0069] In view of the above technical problems, the embodiments of the present disclosure provide a joint verification method of USART and DMA, construct a verification platform based on the Universal Verification Methodology (UVM), and utilize the componentized structure of UVM to combine multiple USARTs and multiple DMAs to perform overall functional verification, so as to fit the actual application scenario and cover more functional points, thereby improving the completeness of the joint operation verification of multiple USARTs and multiple DMAs at the system level. Figure 1In the existing method shown, the host driver needs to convert the data into a waveform according to the timing, and the slave monitoring needs to restore the waveform to data according to the timing. Therefore, if the master / slave is built, the timing problem between the two needs to be considered. The present application does not need to build a master / slave in the verification platform, and does not need to pay extra attention to the timing problems in the driving or monitoring process. The verification environment can be easily built and debugged, reducing the complexity and cost of building the verification environment. Among them, the general verification methodology, as an advanced verification method, aims to provide a unified framework and best practices to improve the efficiency, reusability and scalability of hardware verification. It is described in detail through one or more of the following embodiments.

[0070] The joint verification method of USART and DMA provided in the embodiment of the present disclosure can be applied to the scenario of USART and DMA performing system-level verification. The method can be performed by a joint verification device of USART and DMA, which can be implemented by software and / or hardware, and the device can be integrated in an electronic device. Among them, the electronic device can include but is not limited to mobile terminals such as smart phones, laptops, digital broadcast receivers, personal digital assistants (Personal Digital Assistant, PDA), tablet computers (Tablet Personal Computer, Tablet PC), PMP (portable multimedia player), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable devices, etc., and fixed terminals such as digital televisions, desktop computers, smart home devices, etc.

[0071] Figure 2 A flow chart of a joint verification method of USART and DMA provided in an embodiment of the present disclosure is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, multiple DMAs and multiple USARTs.

[0072] For example, see Figure 3 , Figure 3 A structural diagram of a verification platform provided by an embodiment of the present disclosure is as follows: Figure 3 As shown, the verification platform includes an environment component and a design to be tested (hereinafter referred to as the design to be tested). The environment component includes an agent component, a reference model and a scoreboard component. The environment component also refers to the verification platform component. The agent component includes a monitoring component, a driver component and an interface component. The design to be tested includes a memory, multiple DMAs and multiple USARTs, wherein the memory can be a static random access memory, such as Figure 3As shown, multiple DMAs include DMA0 to DMA3, where 0-3 refers to numbers, and multiple USARTs include USART0 to USART7, where 0-7 also refers to numbers. Each DMA includes multiple channels, and DMA can establish a transmission connection with any USART and memory through multiple channels. For example, DMA0 establishes a transmission connection with USART0 through channel 0 and channel 1, and establishes a transmission connection with USART1 through channel 2 and channel 3.

[0073] Specifically, the joint verification method of USART and DMA includes the following steps:

[0074] S201 . Read first data to be sent from a memory through a first DMA among multiple DMAs, and transmit the first data to a first USART among multiple USARTs based on a first channel preconfigured in the first DMA for data sending.

[0075] It is understandable that, according to the verification requirements, a first DMA to be verified is determined among multiple DMAs, and a first USART to be verified is determined among multiple USARTs. Subsequently, the first data to be sent is read from the memory through the first DMA, wherein the first data is the stimulus data written into the corresponding address in the memory through a preset language. Before the joint verification is performed, the stimulus data involved in the verification requirements can be written into the corresponding address in the memory so that the DMA can directly read the data to be sent, and the data to be sent is the first data. After reading the first data, the first data is transmitted to the first USART based on the first channel pre-configured in the first DMA for data transmission with the first USART, wherein each DMA includes multiple channels, each channel can transmit data with at least one USART, and the DMA can only have one channel to transmit data with the memory or USART at the same time. Figure 3 As shown, the first DMA is DMA0, the first channel is channel 0, the first USART is USART0, and a sending path is that DMA0 transmits the first data read from the memory to USART0 through channel 0.

[0076] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes:

[0077] Registers of multiple DMAs are configured so that multiple channels for data transmission included in at least one of the multiple DMAs are connected to at least one of the multiple USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width; and read and write configurations are performed on the memory so that data can be written into the memory through a preset language and data can be read from the memory through a preset language.

[0078] It is understandable that before joint verification, multiple DMAs are configured with registers, and multiple channels in multiple DMAs are configured to be connected to multiple USARTs for transmission, for example, the first channel in the first DMA is configured to be connected to the first USART for transmission, and the second channel in the second DMA is configured to be connected to the second USART for transmission. Wherein, the register configuration includes at least one configuration of channel selection, transmission direction, transmission mode and data width, channel selection refers to selecting a specific channel to be connected to the USART for transmission, and the transmission direction refers to whether the data is sent by the DMA or received by the DMA. The memory can also be configured for reading and writing, and the configuration can read data from the memory through a preset language and write data to the memory through a preset language, wherein the preset language can be C language, for example, the stimulus data is written into the corresponding address of the static random access memory in the design to be tested through the C language, and the stimulus data will be sent out after being transported to the USART through the DMA based on the sending path, and for example, the data received by the USART will be transported to the corresponding address of the static random access memory in the design to be tested through the DMA based on the receiving path, and can then be read through the C language.

[0079] It can be understood that one possible sending path is: DMA obtains the data written into the memory by C language, and transmits it to USART through the channel, and then sends it out through USART; one possible receiving path is: USART stores the received waveform in its receiving data register, and stores the waveform restored data into the memory through the DMA channel, which can then be read through C language.

[0080] S202: Use the verification environment component to establish a transmission connection between the first USART and a second USART among the multiple USARTs, so as to transmit the second data to the second USART.

[0081] The second data is obtained based on the first data.

[0082] It can be understood that, based on the above S201, a transmission connection between the first USART and the second USART is established by using the verification environment component, so that the first USART transmits the second data to the second USART, wherein the first USART refers to a USART that receives the first data from the first DMA, and the second USART refers to a USART that receives the second data from the first USART, which can be specifically determined from multiple USARTs according to the verification requirements, wherein the second data can be understood as the waveform of the first data, and the first USART transmits the waveform of the first data to the second USART, and the second USART will subsequently restore the waveform to data according to the timing and transmit it to the second DMA, and the timing between the first USART and the second USART can be synchronized by the verification component. In addition, the first USART and the second USART can be the same USART or different USARTs. For example, the verification requirement is to verify the transmission function between the two USARTs, and the first USART and the second USART can also be the same USART. For example, the verification requirement is to verify the transmission function between a certain USART and DMA.

[0083] Among them, the verification environment component includes an interface component and a driver component, wherein a plurality of interfaces are pre-defined in the interface component, and the plurality of interfaces are connected one by one with corresponding plurality of ports, and the plurality of ports refer to a plurality of USART ports, and the plurality of interfaces include a sending interface and a receiving interface, and the driver component is used to connect the sending interface and the receiving interface.

[0084] It can be understood that the verification environment component includes an interface component and a driver component, wherein the interface component contains the interface signal definitions of all USARTs, and the interface signals are used to connect the port signals of at least one corresponding USART in the design to be tested one by one. Specifically, a plurality of interfaces are pre-defined in the interface component, each USART has a port, and a plurality of USARTs have a plurality of ports, and a plurality of ports are connected one by one with the corresponding plurality of interfaces, that is, the interface component defines a one-to-one connection between the interface signals and the port signals. Among them, the plurality of interfaces include a sending interface and a receiving interface, and the plurality of ports include a sending port and a receiving port. The sending port of the USART is connected to the sending interface defined for the USART in the interface component, and at the same time, the sending interface is connected to the receiving interface defined for another USART or the USART itself in the interface component, so as to establish a transmission connection between the USART and another USART or the USART itself. As Figure 3As shown, the sending port of USART0 (0 is the number of USART, and a digital suffix is ​​used to number it when there are multiple USARTs) and the USART0 sending interface defined in the interface component are connected through interface signals and port signals, and the USART0 sending interface is connected through the driver component and the USART1 receiving port defined in the interface component.

[0085] It is understood that the drive components do not need to be as Figure 1 The host driver module in the traditional structure shown in the figure also focuses on the specific data transmission timing (the data transmission timing is used to convert data into waveforms and restore waveforms to data). Its main function is to connect the sending interface and the receiving port defined in the interface component. Figure 1 As shown, the transmit interface signal of USART1 is connected to the receive interface signal of USART0.

[0086] Optionally, in the above S202, using the verification environment component to establish a transmission connection between the first USART and the second USART among the multiple USARTs can be specifically implemented by the following steps:

[0087] A transmission connection between a first transmitting interface and a first receiving interface is established by using a driving component; wherein the first transmitting interface corresponds to a first transmitting port of a first USART, and the first receiving interface corresponds to a first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0088] It is understandable that the first transmitting interface of the first USART is defined in the interface component, and the first transmitting interface is connected to the first transmitting port of the first USART. The first receiving interface of the second USART is also defined in the interface component, and the first receiving interface is connected to the first receiving port of the second USART. Based on this definition, the first transmitting interface and the first receiving interface are connected by using a driving component. Among them, the above-mentioned multiple interfaces include the first transmitting interface and the first receiving interface, and the above-mentioned multiple ports include the first transmitting port and the first receiving port. In addition, if the first USART and the second USART are the same USART, the first transmitting interface and the first receiving interface are both two interfaces of the same USART defined in the interface component. Similarly, the first transmitting port and the first receiving port are two ports of the same USART. Other possible interfaces and the USART to which the ports belong are not limited.

[0089] Optionally, the above-mentioned use of the driving component to establish a transmission connection between the first sending interface and the first receiving interface can be specifically implemented through the following steps:

[0090] Acquire a verification requirement that reflects the verification function and / or verification timing; determine a target time for establishing a transmission connection between the first sending interface and the first receiving interface according to the verification requirement; and use a driving component to establish a transmission connection between the first sending interface and the first receiving interface at the target time.

[0091] Understandably, the verification requirements are obtained, and the verification requirements reflect the verification function and / or verification timing. For example, the verification function refers to the verification of the transmission function between the two USARTs, and the verification timing refers to the timing when the driver component connects the sending interface and the receiving interface, such as the driver component connects the sending interface and the receiving interface after 1 minute, that is, an appropriate delay can be added. Subsequently, the connection timing of the first sending interface and the first receiving interface is selected according to the verification timing, and the specific connection time is determined, and the connection time is the target time. Subsequently, at the target time, the transmission connection between the first sending interface and the first receiving interface is established using the driver component, that is, the connection timing can be selected or an appropriate delay can be added according to the verification requirements.

[0092] Optionally, when multiple DMAs need to read data from the memory and / or write data to the memory, the method further includes:

[0093] A first priority preset for each of a plurality of DMAs is obtained.

[0094] It is understandable that there is a pre-set first priority among the multiple DMAs, and the first priority represents the order in which each DMA reads data from the memory and writes data. Figure 3 As shown, the priority of DMA0 is higher than that of DMA1. At a certain moment, if DMA0 and DMA1 both need to write data to the memory, the writing order of DMA0 must be before DMA1.

[0095] Optionally, reading the first data to be sent from the memory by using a first DMA among the multiple DMAs can be specifically implemented by the following steps:

[0096] First data is read from the memory according to a first priority through a first DMA.

[0097] Understandably, when the first priority of the first DMA is higher than the first priority of other DMAs, if the first DMA and other DMAs both need to read data from the memory, the first DMA will read the first data from the memory first. The scenario where multiple DMAs need to write data to the memory is not described here.

[0098] Optionally, the first DMA includes a plurality of preconfigured transmission channels for data transmission. When the first DMA transmits data to at least two USARTs through the plurality of transmission channels, transmitting the first data to a first USART among the plurality of USARTs based on the first channel for data transmission preconfigured in the first DMA can be specifically implemented by the following steps:

[0099] Obtain a second priority level preset for each of the plurality of transmission channels; transmit the first data to the first USART based on the first channel according to the second priority level; wherein the plurality of transmission channels include the first channel, and the at least two USARTs include the first USART.

[0100] It can be understood that in the first DMA, multiple transmission channels for data transmission are pre-configured through register configuration, such as Figure 3 The DMA0 shown is configured with channel 0 and channel 2 for transmission. When the first DMA sends data to at least two USARTs through multiple transmission channels, and the first DMA can only use one channel to transmit data to the USART at the same time, the preset priority of each transmission channel is determined, and the channel with a high priority is preferentially controlled to transmit data to the USART. If the priority of the first channel is higher than that of the remaining transmission channels, the first data is preferentially transmitted to the first USART based on the first channel, such as Figure 3 As shown, DMA0 needs to use channel 0 to send data to USART0, and at the same time needs to use channel 2 to send data to USART1. In this case, the priorities of channel 0 and channel 2 are compared, and the channel with higher priority sends data to its corresponding USART first.

[0101] S203 . Transmit the second data in the second USART to a second DMA among the multiple DMAs based on the second channel, so that the second DMA writes the second data into the memory.

[0102] The second channel is a channel pre-configured in the second DMA for data reception.

[0103] It is understandable that, based on the above S202, a second DMA corresponding to the second USART for receiving data is determined in multiple DMAs according to the verification requirements, wherein the second DMA and the first DMA can be the same DMA or different DMAs. After determining the second DMA, the second data in the second USART is transmitted to the second DMA based on the second channel for data reception pre-configured in the second DMA. In the case where the first USART and the second USART are different, the second channel is as follows: Figure 3 As shown in channel 3 of DMA0 shown in FIG. 1 , the second DMA then writes the second data into the memory, as shown in FIG. Figure 3As shown, DMA0 writes the second data (received data) into the static random access memory.

[0104] Optionally, the second DMA writes the second data into the memory, which can be specifically implemented by the following steps:

[0105] The second DMA writes the second data into the memory according to the first priority.

[0106] Understandably, when multiple DMAs all need to write their received data into the memory, the writing order of the multiple DMAs is determined according to the priority of each DMA. For the second DMA, the second data is written into the memory based on the writing order determined by the first priority of the second DMA.

[0107] Optionally, the second DMA includes multiple receiving channels. When at least two USARTs need to transmit data to the second DMA through the multiple receiving channels, transmitting the second data in the second USART to the second DMA in the multiple DMAs based on the second channel can be specifically implemented by the following steps:

[0108] Obtain a third priority level preset for each of the multiple receiving channels; and transmit the second data in the second USART to the second DMA based on the second channel according to the third priority level; wherein the multiple receiving channels include the second channel, and the at least two USARTs include the second USART.

[0109] It is understandable that the second DMA includes multiple receiving channels, each receiving channel is pre-set with a third priority, and in the case where at least two USARTs need to transmit data through multiple receiving channels, a transmission order is set according to the third priority of each receiving channel, and based on the transmission order, the second data is transmitted to the second DMA using a second channel among the multiple receiving channels. Figure 3 As shown, the second DMA is DMA0, channel 1 needs to transmit data from USART0, and channel 3 needs to transmit data from USART1. In this case, the priority of channel 1 and channel 3 is determined, and the channel with higher priority transmits data first. In addition, in the case where at least two USARTs need to transmit data through the same receiving channel, the transmission order is set according to the priority of each USART. Other possible ways of setting the transmission order according to priority are not limited and can be set according to user needs.

[0110] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes:

[0111] A verification combination between multiple DMAs and multiple USARTs is set according to the verification requirements to perform joint verification of USART and DMA under the verification combination; wherein the verification combination includes a first combination, a second combination, a third combination and a fourth combination, wherein: the first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs; the second combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are the same USART; the third combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are different USARTs; the fourth combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART.

[0112] It is understandable that, according to the verification requirements, a specific USART and a specific DMA for verification can be determined from multiple USARTs and multiple DMAs, and there are multiple verification combinations between specific DMAs and specific USARTs. Among them, the verification combination includes the first combination, the second combination, the third combination and the fourth combination. The first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs, that is, a combination of one DMA and multiple USARTs, such as Figure 3 In the transmission path shown, the first DMA and the second DMA are DMA0, the first USART is USART0, and the second USART is USART1, that is, data transmission between USART0 and USART1 is realized based on DMA0. The second combination refers to that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are also the same USART, that is, a combination of a DMA and a USART, such as realizing data transmission between DMA1 and USART2, and this combination form is used for self-loop testing. The third combination refers to that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are also different USARTs, that is, a combination of multiple DMAs and multiple USARTs, such as realizing data transmission between DMA2, DMA3, USART4, and USART6. The fourth combination refers to that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART, that is, a combination of multiple DMAs and a USART, such as realizing data transmission between DMA2, USART4, and USART6, and the forms of other combinations are not limited. In fact, it is also a process of determining the first DMA and the second DMA in multiple DMAs and determining the first USART and the second USART in multiple USARTs according to verification requirements.

[0113] S204: Compare the first data and the second data through a verification environment component to generate a verification result.

[0114] It can be understood that, based on the above S203, the first data read from the memory and the second data written into the memory are compared by the verification environment component to determine the correctness and stability of the design to be tested and generate a verification result.

[0115] Optionally, the verification environment component includes a monitoring component, a reference model, and a scoreboard component. The verification environment component is used to compare the first data and the second data to generate a verification result, which can be specifically implemented by the following steps:

[0116] The monitoring component receives the second data read from the memory by the preset language, and transmits it to the scoreboard component as actual data; the content of the configuration file is read by the reference model, and the read content is transmitted to the scoreboard component as expected data; wherein the content of the configuration file is generated by extracting the stimulus data of the preset language, and the content of the configuration file includes the register configuration and the first data obtained by writing the stimulus data into the memory; the actual data and the expected data are compared by the scoreboard component to generate a verification result.

[0117] It can be understood that the verification environment component includes a monitoring component, a reference model and a scoreboard component, wherein the monitoring component does not need to collect data waveforms according to the transmission timing like the slave monitoring component of the traditional structure, but can read the data from the memory through a preset language, that is, the collected data can read the data (second data) received by the memory through the C language and pass it to the monitoring component; in addition, the verification environment component also includes an agent component, which includes an interface component, a driver component and a monitoring component. The main function of the reference model is to read the content of the configuration file and transmit it to the scoreboard component as the expected data. The content of the configuration file is generated by extracting the stimulus data, including the register configuration and the first data. The scoreboard component obtains the expected data in the reference model and the actual data in the monitoring component, compares the two, determines the correctness and stability of the design to be tested, and generates a verification result.

[0118] A kind of Figure 3In the embodiment shown, after the configuration of the design to be tested is completed, the stimulus data is written into the sending address of the static random access memory through the C language, and meets USART0 through the channel 0 version in DMA0, and passes through the sending port of USART0 to the receiving port of USART1, wherein the sending port and the receiving port are connected through the driver component, and after USART1 receives the data, it is moved to the receiving address of the static random access memory through channel 3 in DMA0, and finally the receiving data is read from the static random access memory through the C language, and passed to the monitoring component of the verification platform, and the monitoring component passes it to the scoreboard as actual data, and at the same time, the configuration file extracted from the C language is given to the reference model as expected data, and the scoreboard component compares the actual data with the expected data, thereby completing the verification of a complete sending and receiving path. The overall verification of multiple sending and receiving paths of multiple USARTs and multiple DMAs is the same as the above process, which will not be repeated here.

[0119] The joint verification method of USART and DMA provided by the present application interconnects multiple USARTs to make them mutually master / slave, solves the problem that the verification structure becomes large and complicated due to the setting of multiple master / slave components in the traditional structure, simplifies the verification structure, and solves the problem that the verification of a single USART in the traditional structure requires a corresponding host driver component and a slave monitoring component, and also needs to pay attention to the timing information in these two components, so that each USART does not need to pay too much attention to the transmission timing problem when performing data transmission, and multiple USARTs can be synchronized, making the control of data flow and later debugging including the maintenance and update of the verification environment simple, thereby improving the verification efficiency. In addition, the joint verification can also cover a variety of scenarios, such as multiple masters and multiple slaves or one master and multiple slaves of USART, that is, not only there are multiple verification combinations between multiple USARTs and multiple DMAs, but also there are multiple connection relationships between multiple USARTs, and it is only necessary to modify the connection relationship in the driver component.

[0120] Based on the above embodiments, see Figure 4 , Figure 4 The structural diagram of a USART and DMA joint verification device provided by an embodiment of the present disclosure. The USART and DMA joint verification device provided by an embodiment of the present disclosure can execute the processing flow provided by the USART and DMA joint verification method embodiment, and is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, multiple DMAs, and multiple USARTs, such as Figure 4 As shown, the joint verification device 400 of USART and DMA includes a first transmission unit 401, a connection establishment unit 402, a second transmission unit 403 and a verification unit 404, wherein:

[0121] A first transmission unit 401 is used to read first data to be sent from a memory through a first DMA among the multiple DMAs, and transmit the first data to a first USART among the multiple USARTs based on a first channel for data sending preconfigured in the first DMA;

[0122] A connection establishing unit 402, used for establishing a transmission connection between the first USART and a second USART among the plurality of USARTs by using the verification environment component, so as to transmit second data to the second USART; wherein the second data is obtained according to the first data;

[0123] A second transmission unit 403 is used to transmit the second data in the second USART to a second DMA in the plurality of DMAs based on a second channel, so that the second DMA writes the second data into the memory; wherein the second channel is a pre-configured channel in the second DMA for data reception;

[0124] The verification unit 404 is used to compare the first data and the second data through a verification environment component to generate a verification result.

[0125] Among them, the verification environment component includes an interface component and a driver component, wherein a plurality of interfaces are pre-defined in the interface component, and the plurality of interfaces are connected one by one with corresponding plurality of ports, and the plurality of ports refer to a plurality of USART ports, and the plurality of interfaces include a sending interface and a receiving interface, and the driver component is used to connect the sending interface and the receiving interface.

[0126] Optionally, the connection establishing unit 402 is configured to:

[0127] A transmission connection between a first transmitting interface and a first receiving interface is established by using a driving component; wherein the first transmitting interface corresponds to a first transmitting port of a first USART, and the first receiving interface corresponds to a first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0128] Optionally, the connection establishing unit 402 is configured to:

[0129] Obtain verification requirements that reflect verification functions and / or verification timing;

[0130] Determine the target time for establishing a transmission connection between the first sending interface and the first receiving interface according to the verification requirement;

[0131] A transmission connection between the first transmitting interface and the first receiving interface is established at a target time using a driving component.

[0132] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the joint verification device 400 of USART and DMA is further used to:

[0133] Performing register configuration on the plurality of DMAs so that a plurality of channels for data transmission included in at least one of the plurality of DMAs are connected to at least one of the plurality of USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width;

[0134] The memory is configured for reading and writing so that data can be written into the memory in a preset language and data can be read from the memory in a preset language.

[0135] The verification environment components include monitoring components, reference models, and scoreboard components.

[0136] Optionally, the verification unit 404 is used to:

[0137] receiving, by the monitoring component, second data read from the memory in a preset language, and transmitting it to the scoreboard component as actual data;

[0138] Reading the content of the configuration file through the reference model, and transmitting the read content to the scoreboard component as expected data; wherein the content of the configuration file is generated by extracting the stimulus data in a preset language, and the content of the configuration file includes a register configuration and first data obtained by writing the stimulus data into a memory;

[0139] The actual data is compared with the expected data through the scoreboard component to generate verification results.

[0140] Optionally, before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the joint verification device 400 of USART and DMA is further used to:

[0141] A verification combination between multiple DMAs and multiple USARTs is set according to the verification requirements to perform joint verification of USART and DMA under the verification combination; wherein the verification combination includes a first combination, a second combination, a third combination, and a fourth combination, wherein:

[0142] The first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs;

[0143] The second combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are the same USART;

[0144] The third combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are different USARTs;

[0145] The fourth combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART.

[0146] Optionally, when multiple DMAs need to read data from a memory and / or write data to a memory, the USART and DMA joint verification device 400 is further used to:

[0147] Obtain a first priority preset for each of the multiple DMAs;

[0148] Optionally, the first transmission unit 401 is used for:

[0149] Reading first data from a memory according to a first priority through a first DMA;

[0150] The second DMA writes the second data into the memory, including:

[0151] The second DMA writes the second data into the memory according to the first priority.

[0152] The first DMA includes a plurality of pre-configured transmission channels for data transmission.

[0153] Optionally, when the first DMA transmits data to at least two USARTs through multiple transmission channels, the first transmission unit 401 is used to:

[0154] Obtaining a second priority preset for each sending channel among a plurality of sending channels;

[0155] According to a second priority, first data is transmitted to a first USART based on a first channel; wherein the plurality of transmission channels include the first channel, and the at least two USARTs include the first USART.

[0156] Wherein, the second DMA includes multiple receiving channels. When at least two USARTs need to transmit data to the second DMA through the multiple receiving channels, the second transmission unit 403 is used to:

[0157] Obtaining a third priority preset for each receiving channel among a plurality of receiving channels;

[0158] According to a third priority, the corresponding second data in the second USART is transferred to the second DMA based on the second channel; wherein the plurality of receiving channels include the second channel, and the at least two USARTs include the second USART.

[0159] Figure 4 The joint verification device of USART and DMA in the illustrated embodiment can be used to execute the technical solution of the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0160] Figure 5 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 5 , which shows a schematic diagram of the structure of an electronic device 500 suitable for implementing the embodiment of the present disclosure. The electronic device 500 in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), wearable electronic devices, etc., and fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 5 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0161] like Figure 5 As shown, the electronic device 500 may include a processing device 501 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503 to implement the joint verification method of USART and DMA of the embodiment described in the present disclosure. In RAM 503, various programs and data required for the operation of the electronic device 500 are also stored. The processing device 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0162] Typically, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 5 The electronic device 500 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0163] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart, thereby implementing the joint verification method of USART and DMA as described above. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 509, or installed from the storage device 508, or installed from the ROM 502. When the computer program is executed by the processing device 501, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0164] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0165] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0166] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0167] Optionally, when the above one or more programs are executed by the electronic device, the electronic device may also execute other steps described in the above embodiments.

[0168] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0169] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0170] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0171] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0172] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0173] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or gateway that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or gateway. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or gateway that includes the elements.

[0174] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A joint verification method of USART and DMA, characterized in that, The method is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, a plurality of DMAs and a plurality of USARTs, and the method includes: Reading first data to be sent from the memory through a first DMA among the multiple DMAs, and transmitting the first data to a first USART among the multiple USARTs based on a first channel for data sending preconfigured in the first DMA; Using the verification environment component to establish a transmission connection between the first USART and a second USART among the multiple USARTs, so as to transmit second data to the second USART; wherein the second data is obtained according to the first data; transmitting the second data in the second USART to a second DMA among the multiple DMAs based on a second channel, so that the second DMA writes the second data into the memory; wherein the second channel is a pre-configured channel for data reception in the second DMA; The first data and the second data are compared by the verification environment component to generate a verification result.

2. The method according to claim 1, characterized in that The verification environment component includes an interface component and a driver component, wherein the interface component is predefined with a plurality of interfaces, the plurality of interfaces are connected one by one with corresponding plurality of ports, the plurality of ports refer to the ports of the plurality of USARTs, the plurality of interfaces include a sending interface and a receiving interface, and the driver component is used to connect the sending interface with the receiving interface; The method of using the verification environment component to establish a transmission connection between the first USART and a second USART among the multiple USARTs includes: The driving component is used to establish a transmission connection between a first transmitting interface and a first receiving interface; wherein the first transmitting interface corresponds to a first transmitting port of the first USART, the first receiving interface corresponds to a first receiving port of a second USART among the multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

3. The method according to claim 2, characterized in that The step of using the driving component to establish a transmission connection between the first sending interface and the first receiving interface includes: Obtain verification requirements that reflect verification functions and / or verification timing; Determine a target time for establishing a transmission connection between the first sending interface and the first receiving interface according to the verification requirement; The driving component is used to establish a transmission connection between the first sending interface and the first receiving interface at the target time.

4. The method according to claim 1, characterized in that: Before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes: Performing register configuration on the multiple DMAs so that multiple channels for data transmission included in at least one DMA among the multiple DMAs are connected to at least one USART among the multiple USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width; The memory is configured for reading and writing so that data can be written into the memory in a preset language and data can be read from the memory in the preset language.

5. The method according to claim 4, characterized in that The verification environment component includes a monitoring component, a reference model, and a scoreboard component. The first data and the second data are compared by the verification environment component to generate a verification result, including: receiving, by the monitoring component, the second data read from the memory in the preset language, and transmitting it to the scoreboard component as actual data; Reading the content of the configuration file through the reference model, and transmitting the read content to the scoreboard component as expected data; wherein the content of the configuration file is generated by extracting the stimulus data of the preset language, and the content of the configuration file includes the register configuration and the first data obtained by writing the stimulus data into the memory; The actual data and the expected data are compared by the scoreboard component to generate a verification result.

6. The method according to claim 1, characterized in that Before reading the first data to be sent from the memory through the first DMA among the multiple DMAs, the method further includes: A verification combination between the multiple DMAs and the multiple USARTs is set according to the verification requirements to perform joint verification of USART and DMA under the verification combination; wherein the verification combination includes a first combination, a second combination, a third combination and a fourth combination, wherein: The first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs; The second combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are the same USART; The third combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are different USARTs; The fourth combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART.

7. The method according to claim 1, characterized in that In the case where the plurality of DMAs all need to read data from the memory and / or write data to the memory, the method further includes: Obtaining a first priority preset for each DMA among the multiple DMAs; The reading the first data to be sent from the memory by using the first DMA among the multiple DMAs includes: reading, by the first DMA, first data from the memory according to the first priority; The second DMA writes the second data into the memory, including: The second DMA writes the second data into the memory according to the first priority.

8. The method according to claim 1, characterized in that The first DMA includes a plurality of preconfigured transmission channels for data transmission. When the first DMA transmits data to at least two USARTs through the plurality of transmission channels, the first data is transmitted to a first USART among the plurality of USARTs based on the first channel preconfigured for data transmission in the first DMA, comprising: Obtaining a second priority preset for each sending channel among the multiple sending channels; According to the second priority, the first data is transmitted to a first USART based on a first channel; wherein the multiple transmission channels include the first channel, and the at least two USARTs include the first USART.

9. The method according to claim 1, characterized in that: The second DMA includes a plurality of receiving channels, and in a case where at least two USARTs are to transmit data to the second DMA through the plurality of receiving channels, transmitting the second data in the second USART to a second DMA in the plurality of DMAs based on the second channel includes: Obtaining a third priority preset for each receiving channel among the multiple receiving channels; According to the third priority, the second data in the second USART is transmitted to the second DMA based on the second channel; wherein the multiple receiving channels include the second channel, and the at least two USARTs include the second USART.

10. A joint verification device of USART and DMA, characterized in that: The device is applied to a verification platform including a verification environment component and a design to be tested, wherein the design to be tested includes a memory, a plurality of DMAs and a plurality of USARTs, and the device includes: a first transmission unit, configured to read first data to be sent from the memory through a first DMA among the multiple DMAs, and transmit the first data to a first USART among the multiple USARTs based on a first channel for data sending preconfigured in the first DMA; a connection establishing unit, configured to establish a transmission connection between the first USART and a second USART among the plurality of USARTs by using the verification environment component, so as to transmit second data to the second USART; wherein the second data is obtained according to the first data; A second transmission unit is used to transmit the second data in the second USART to a second DMA in the multiple DMAs based on a second channel, so that the second DMA writes the second data into the memory; wherein the second channel is a pre-configured channel for data reception in the second DMA; The verification unit is used to compare the first data and the second data through the verification environment component to generate a verification result.

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