Graphical processing method of chip power consumption information and electronic equipment

Abstract

The invention provides a chip power consumption information graphical processing method and electronic equipment, and the method comprises the steps: generating the circuit level information of a netlist according to a gate level netlist file, determining the power consumption data of each module, primitive and signal and the flip rate data of the signal in the netlist according to a power consumption configuration file of a chip, and generating a graphical result of the chip power consumption information according to the circuit level information, the modules in the netlist, the primitive, the power consumption data of the signals and the turnover rate data of the signals. The hierarchical structure information of the circuit is extracted from the gate-level netlist file and is clearly displayed in a graphical form, so that a user can quickly understand the structure of the circuit, and the efficiency of subsequent circuit analysis is improved. The power consumption data of the signal, the module and the primitive and the turnover rate data of the signal are displayed in the hierarchical structure diagram, so that a designer can visually and quickly position a high-power-consumption and high-turnover-rate region, and the power consumption optimization analysis efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for graphically processing chip power consumption information and an electronic device. Background Art

[0002] Chip power estimation is an important part of integrated circuit design. Its main purpose is to predict and optimize the power consumption of the chip during operation. Chip power consumption includes two parts: static power consumption and dynamic power consumption. In chip power consumption analysis, the flip rate is one of the key factors in calculating dynamic power consumption. By accurately calculating the flip rate, the power consumption performance of the chip can be more accurately evaluated.

[0003] Currently, there are many technical means to estimate chip power consumption and signal toggle rate. Many electronic design automation (EDA) tools can estimate the toggle rate of signals in the design and the energy consumption of the chip under different working conditions. However, these estimation results are often presented in the form of lengthy digital reports, so they lack intuitiveness, which not only increases the difficulty for users to understand the power consumption characteristics of the chip, but also increases the difficulty of subsequent power consumption and performance optimization. Summary of the invention

[0004] The purpose of this application is to provide a graphical processing method and electronic device for chip power consumption information in view of the deficiencies in the above-mentioned prior art, so as to solve the problem that the power consumption and flip rate calculation results in the prior art lack intuitiveness.

[0005] To achieve the above objectives, the technical solutions adopted in this application are as follows:

[0006] In a first aspect, the present application provides a method for graphically processing chip power consumption information, the method comprising:

[0007] Generate circuit level information of the netlist according to the gate-level netlist file, wherein the circuit level information is used to characterize the hierarchical relationship between modules and modules and between modules and primitives, and the signal connection relationship between modules and modules, modules and primitives, and primitives and primitives;

[0008] Determine the power consumption data and flip rate data of each module, primitive and signal in the netlist according to the power consumption profile of the chip;

[0009] A graphical result of the chip power consumption information is generated based on the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist. The graphical result includes a tree list and at least one hierarchical structure diagram. The hierarchical structure diagram includes: the modules, primitives and signals in the netlist, and the power consumption data of the modules, primitives and signals in the netlist and the flip rate data of each signal.

[0010] In a second aspect, the present application provides a graphical processing device for chip power consumption information, the device comprising:

[0011] A first generating module is used to generate circuit level information of a netlist according to a gate-level netlist file, wherein the circuit level information is used to characterize the hierarchical relationship between modules and modules and between modules and primitives, and the signal connection relationship between modules and modules, between modules and primitives, and between primitives;

[0012] An information determination module, used to determine the power consumption data and flip rate data of each module, primitive and signal in the netlist according to the power consumption configuration file of the chip;

[0013] The second generation module is used to generate a graphical result of the chip power consumption information based on the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist, wherein the graphical result includes a tree list and at least one hierarchical structure diagram, and the hierarchical structure diagram includes: the modules, primitives and signals in the netlist, and the power consumption data of the modules, primitives and signals in the netlist and the flip rate data of each signal.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of a method for graphically processing chip power consumption information as described in any one of the first aspects.

[0015] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a method for graphically processing chip power consumption information as described in any one of the first aspects are executed.

[0016] The beneficial effects of the present application are: by extracting the hierarchical structure information of the circuit from the gate-level netlist file and clearly displaying it in a graphical form, it can help users quickly understand the structure of the circuit and improve the efficiency of subsequent circuit analysis. By displaying signals, modules and primitives in a hierarchical structure diagram, and displaying the power consumption data of signals, modules and primitives and the flip rate data of signals, designers can intuitively and quickly locate high power consumption and high flip rate areas, thereby improving the efficiency of power optimization analysis.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A flowchart of a method for graphically processing chip power consumption information provided by an embodiment of the present application is shown;

[0020] Figure 2 An example diagram of a graphical result provided by an embodiment of the present application is shown;

[0021] Figure 3 A flowchart of constructing circuit level information provided by an embodiment of the present application is shown;

[0022] Figure 4 A flowchart for determining a hierarchical relationship and a signal connection relationship provided by an embodiment of the present application is shown;

[0023] Figure 5 A flowchart of generating a graphical result provided by an embodiment of the present application is shown;

[0024] Figure 6 A flowchart of generating an initial structure diagram provided by an embodiment of the present application is shown;

[0025] Figure 7 A flow chart of marking change points provided by an embodiment of the present application is shown;

[0026] Figure 8 A schematic diagram showing the structure of a device for graphically processing chip power consumption information provided by an embodiment of the present application is shown;

[0027] Fig. 9 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0029] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0030] Chip power consumption is divided into two parts: static power consumption and dynamic power consumption. Static power consumption is mainly caused by leakage current, which is mainly related to process technology, temperature and voltage. This part of power consumption still exists when the chip does not perform any operation. Dynamic power consumption is mainly caused by the flipping of signals in the circuit, which is the power consumption generated when the chip performs logical operations. Among them, the flip rate is one of the key factors in calculating dynamic power consumption. Many EDA tools can estimate the flip rate of signals in the design and the energy consumption of the chip under different working conditions.

[0031] However, these estimation results are generally presented in the form of digital reports, lacking an intuitive graphical expression. Users need to spend a lot of time interpreting data reports, which not only increases the difficulty for users to understand the power consumption characteristics of the chip, but also makes it difficult for users to make power consumption and performance measurement decisions directly based on data reports when optimizing the chip.

[0032] Based on this, the present application proposes a graphical processing method for chip power consumption information, which can display the flip rate of the signal and the power consumption of each module in a hierarchical structure of a netlist design, thereby providing a graphical representation of the power consumption data and the flip rate data, and the user can interact with the graphical results, reducing the difficulty for the user to understand the chip power consumption characteristics and improving the intuitiveness of the display of the chip power consumption data and the flip rate data.

[0033] Next, combine Figure 1 The graphical processing method of the chip power consumption information of the present application is described. The execution subject of the method can be an electronic device with processing capabilities, such as Figure 1 As shown, the method includes:

[0034] S101. Generate circuit hierarchy information of the netlist according to the gate-level netlist file. The circuit hierarchy information is used to characterize the hierarchical relationship between modules and modules, modules and primitives, and signal connection relationships between modules, modules and primitives, and primitives.

[0035] The gate-level netlist file is used to describe the connection relationship between circuit elements in the chip, including information of each design module, such as the input and output information of the module, the connection relationship between modules, the inclusion relationship between modules, and the logic units contained in the module.

[0036] The module name can be extracted from the gate-level netlist file, and the extracted modules are traversed to extract the sub-module information, primitive information, input and output information, and location information contained in each module.

[0037] By matching the name of the logic unit contained in the module with the primitive in the primitive library, the primitive contained in the module and the primitive information can be obtained. If the name of the logic unit contained in the module is not in the primitive library, the logic unit can be used as a submodule to obtain the submodule and submodule information of the module.

[0038] The primitive information includes: primitive type, primitive instantiation name and the number of instances of each primitive type. The submodule information includes the module name of the submodule, the name of the module instantiation and the number of module instantiations. The type of primitive can be a lookup table or a register, etc. The primitive information and module information can also indicate that the primitive or module is called by other modules or calls other modules. The submodule can include smaller submodules, primitives and signals.

[0039] Input and output information is used to characterize the boundaries of modules and primitives, as well as the direction and method of data flow between modules and primitives. Position information is used to record the location information of modules, primitives or signals in the gate-level netlist file, such as the line number in the gate-level netlist file.

[0040] Optionally, the hierarchical relationship can be a calling relationship, in which a module that is not called by other modules can be used as a main module, and a called module can be used as a submodule. A correct circuit design has one and only one main module. The main module can call a submodule or a primitive, and the submodule can also call other submodules or primitives. Exemplarily, module 1 calls module 1-1 and module 1-2, and module 1-2 calls module 1-2-1. If module 1 is not called by other modules, module 1 is the main module, and module 1-1, module 1-2, and module 1-2-1 are submodules.

[0041] By analyzing the calling relationship in the primitive information and module information, the hierarchical relationship between modules and between modules and primitives can be obtained. By analyzing the input and output information in the primitive information and module information, the signal connection relationship between modules, primitives and primitives, and modules and primitives can be obtained.

[0042] S102 , determining the power consumption data and flip rate data of each module, primitive, and signal in the netlist according to the power consumption configuration file of the chip.

[0043] Among them, the power consumption configuration file of the chip contains all parameter information required to calculate the power consumption, such as chip model, ambient temperature information, heat dissipation information, voltage information, simulation waveform file, etc.

[0044] The flip rate indicates the number of flips of a signal (including clock, data and other signals) in a unit time. A signal flip is the number of times a signal changes from a high level (logic 1) to a low level (logic 0) or from a low level to a high level. The simulation waveform file (such as a VCD file) contains complete information about the signal changes. By reading the simulation waveform file, traversing each timestamp and corresponding signal value in the waveform file, for each signal, check whether its value has flipped from 0 to 1 or from 1 to 0. If the signal flips, the number of flips is increased by 1, and the number of flips of each signal is recorded to obtain the flip rate of each signal in the netlist file.

[0045] The flip rate of each signal can be obtained through the simulation waveform file in the power consumption configuration file. According to the power consumption model and the flip rate of the signal, the power consumption data of each module, each primitive and each signal can be obtained.

[0046] Among them, the power consumption model contains the power consumption data and calculation methods of all primitives and signals. Therefore, based on the power consumption model, the power consumption data of each signal and each primitive can be determined. The power consumption data of a module can be equal to the sum of the power consumption of all sub-modules, primitives and signals contained in the module at this level.

[0047] S103. Generate a graphical result of the chip power consumption information according to the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist. The graphical result includes a tree list and at least one hierarchical structure diagram. The hierarchical structure diagram includes: modules, primitives and signals in the netlist, as well as the power consumption data of each module, primitive and signal in the netlist and the flip rate data of each signal.

[0048] Optionally, each module and each primitive can be represented by a graphic symbol, and the signal can be represented by a connecting line. The modules and primitives can be arranged according to the circuit hierarchy information and connected by connecting lines. The power consumption data of each module and primitive and the flip rate data of the signal can be marked around the symbol to obtain at least one hierarchical structure diagram representing the chip power consumption information.

[0049] Each module, primitive and signal in the tree list can be represented as a node, and each node is arranged according to the hierarchical relationship in the circuit hierarchy information. The tree list is associated with the hierarchical structure diagram. After the user selects a node in the tree list, the hierarchical structure diagram can display the module, primitive or signal represented by the node selected by the user.

[0050] Each hierarchical structure diagram is used to characterize the submodules and primitives connected to a module. Specifically, starting from the main module, the hierarchical structure diagram of the main module can be generated based on the submodule information of each submodule called by the main module, the primitive information of the primitive, the power consumption data of each submodule and the primitive, and the flip rate data. In the hierarchical structure diagram of the main module, it is not necessary to reflect the calling relationship and hierarchical structure within the submodule. After generating the hierarchical structure diagram of the main module, each submodule can be traversed in turn according to the circuit hierarchy structure to generate the hierarchical structure diagram of each submodule.

[0051] In the first implementation method, a tree list can be generated according to the circuit hierarchy structure, and then each module in the tree list can be traversed to generate a hierarchical structure diagram for each module with a deeper calling relationship, and the tree list and all the hierarchical structure diagrams can be used as the graphical results of the chip power consumption information.

[0052] In the second implementation method, a hierarchical structure diagram of each module can be generated for modules with a deeper calling relationship, and then a tree list is generated based on the hierarchical structure diagram, and the tree list and all the hierarchical structure diagrams are used as graphical results of the chip power consumption information.

[0053] like Figure 2 The figure shows an example of a graphical result provided by this application. Figure 2 , area 1 is a tree list, and area 2 is a hierarchical structure diagram. After the user clicks module 1 in the tree list of area 1, if there is a corresponding hierarchical structure diagram for module 1, the hierarchical structure diagram of module 1 can be displayed in area 2. If the user clicks a signal node or a primitive node in the tree list of area 1, the signal or primitive selected by the user can be highlighted in area 2.

[0054] In an embodiment of the present application, circuit hierarchy information of the netlist is generated based on a gate-level netlist file, the circuit hierarchy information is used to characterize the hierarchical relationship between modules and modules, and between modules and primitives, as well as the signal connection relationship between modules and modules, modules and primitives, and primitives and primitives, the power consumption data and flip rate data of each module, primitive and signal in the netlist are determined based on the power consumption configuration file of the chip, and a graphical result of the chip power consumption information is generated based on the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist, the graphical result includes a tree list and at least one hierarchical structure diagram, the hierarchical structure diagram includes: modules, primitives and signals in the netlist, and the power consumption data of each module, primitive and signal in the netlist and the flip rate data of each signal.

[0055] By extracting the hierarchical structure information of the circuit from the gate-level netlist file and displaying it clearly in a graphical form, it can help users quickly understand the structure of the circuit and improve the efficiency of subsequent circuit analysis. By displaying signals, modules, and primitives in the hierarchical structure diagram according to the hierarchical relationship and connection relationship, and displaying the power consumption data of signals, modules, and primitives and the flip rate data of signals, designers can intuitively and quickly locate high power consumption and high flip rate areas, thereby improving the efficiency of power optimization analysis.

[0056] The following is a further explanation of the circuit level information of generating a netlist based on the gate-level netlist file. Figure 3 As shown, the above step S101 includes:

[0057] S301 . Extract and process a gate-level netlist file to obtain at least one module of the netlist.

[0058] Optionally, a module name in a gate-level netlist file may be extracted to obtain a module corresponding to the module name.

[0059] S302: extract information from each module to obtain module information of each module, where the module information includes: submodule information, primitive information, input and output information, and location information included in the module.

[0060] Based on the primitive library, each module can be matched to determine the primitives therein, and information can be extracted from the gate-level netlist file to obtain the primitive information, input-output information, and location information of the primitives. For non-primitive modules, they can be first determined as sub-modules, and the sub-module information, input-output information, and location information of the sub-modules can be extracted from the gate-level netlist file.

[0061] S303: Construct circuit level information of the netlist according to the module information.

[0062] Optionally, the module information can characterize the calling relationship between modules. Based on the calling relationship between modules, the hierarchical relationship between modules and between modules and primitives can be determined. Based on the input and output information in the module information, the signal connection relationship between modules, between modules and primitives, and between primitives can be determined.

[0063] The following is a further explanation of the circuit level information of the above-mentioned netlist constructed based on the module information, such as Figure 4 As shown, the above step S303 includes:

[0064] S401. Determine the calling relationship of each module according to the submodule information and primitive information contained in the module. The calling relationship is used to indicate the information of module calling and the information of module being called.

[0065] The module calling information may indicate other modules called by the module or module calling primitives. The module being called information may indicate the upper level module that calls the current module.

[0066] As a possible implementation method, the module information may include the calling information of the module. For example, if the calling information of module 1 includes module 1-1 and primitive 1-2, it can be determined that module 1-1 is a sub-module of module 1, and primitive 1-2 is a primitive called by module 1. If the called information of module 1 includes module 0, it can be determined that module 1 is a sub-module of module 0.

[0067] S402. If the calling relationship of the module indicates that the current module has not been called by other modules, the current module is taken as the main module, and at least one sub-module and / or primitive called by the main module is determined according to the calling relationship of the main module, and a hierarchical relationship between the main module and the sub-module and / or a hierarchical relationship between the main module and the primitive is constructed.

[0068] If the current module is not called by other modules, it means that the current module is the main module, and the module information and / or primitive information called by the current module can be determined, and the module called by the current module is used as a submodule of the current module, and the hierarchical relationship between the main module and the submodule and the hierarchical relationship between the main module and the primitive are constructed. The current module can only call modules or primitives, or call modules and primitives at the same time.

[0069] S403 . Determine the submodules and primitives called by each submodule according to the calling relationship of each submodule, and construct the hierarchical relationship between each submodule and the submodules called by each submodule and the hierarchical relationship between each submodule and the primitives.

[0070] After determining the main module, each sub-module in the main module can be traversed one by one. For the current sub-module traversed, the calling relationship of the sub-module can be determined according to the module information of the sub-module. If the sub-module calls other modules and primitives, the sub-modules and primitives called by the current sub-module can be determined, thereby obtaining the hierarchical relationship between the current sub-module and the calling sub-module and the hierarchical relationship between the current sub-module and the called primitive.

[0071] S404: construct signal connection relationships among the main modules, sub-modules and primitives according to the input and output information of the main module, sub-modules and primitives.

[0072] According to the input and output information of each module and primitive, the signal connection relationship between the main module and each sub-module, between the main module and each primitive, between the sub-module and each sub-module, and between the sub-module and each primitive can be constructed.

[0073] Exemplarily, signal A is input from the input port of module 1, output from the output port of module 1, and then input to the input port of module 2. It can be determined that there is a clear signal path between the output port of module 1 and the input port of module 2.

[0074] After generating the circuit level information of the netlist and determining the flip rate data and power consumption data, a graphical result of the chip power consumption information can be generated based on the circuit level information and the power consumption data and flip rate data of each module, primitive and signal in the netlist, such as Figure 5 As shown, the above step S103 includes:

[0075] S501. Generate at least one initial structure diagram of the netlist according to circuit level information of the netlist. The initial structure diagram includes at least one module and primitive. The modules and primitives are connected by signal connection lines.

[0076] For modules that call other modules or primitives, the initial structure diagram of the module can be generated according to the circuit hierarchy of the netlist. In the initial structure diagram, modules and primitives are represented by different graphic symbols, and modules and primitives with signal connection relationships are connected through signal connection lines according to the signal connection relationship indicated in the circuit hierarchy. The signal flow direction can be represented by the arrow direction of the signal connection line, and the arrow direction is the signal flow direction.

[0077] It is worth noting that the specific information of the called sub-modules may not be displayed in each initial structure diagram. For example, the modules called by module 1 include module 1-1 and module 1-2, and module 1-1 calls module 1-1-1 and primitive 1-1-2. When generating the initial structure diagram of module 1, only module 1-1 and module 1-2 may be reflected, and module 1-1-1 and primitive 1-1-2 called inside module 1-1 shall be reflected in the hierarchical structure diagram of module 1-1.

[0078] S502 , adding the power consumption data, flip rate data and module information of each module, primitive and signal in the netlist to the corresponding position of each initial structure diagram to obtain a hierarchical structure diagram of the netlist.

[0079] For each initial structure diagram, the power consumption data and flip rate data of the modules, primitives and signals in the initial structure diagram can be added to the symbols corresponding to the modules, primitives and signals, and the module information of the modules and the primitive information of the primitives can also be added to the corresponding symbols to obtain a hierarchical structure diagram corresponding to each initial structure diagram.

[0080] After adding power consumption data, flip rate data, module information and primitive information to all initial structure diagrams, all the obtained hierarchical structure diagrams can be used as hierarchical structure diagrams of the netlist. It should be understood that each hierarchical structure diagram of the netlist is used to represent the hierarchical structure of a main module or a submodule.

[0081] S503 , generating a tree list according to the circuit hierarchy information of the netlist, and using the tree list and the hierarchy diagram as the graphical result of the chip power consumption information, wherein each module, primitive and signal in the tree list is arranged according to the hierarchy relationship indicated by the hierarchy diagram.

[0082] Based on the circuit hierarchy information, the hierarchical relationship between modules, modules and primitives, and primitives can be determined, as well as the signal connection relationship between modules, modules and primitives, and primitives. Each module, primitive and signal is represented as a node and arranged according to the hierarchical relationship and connection relationship to obtain a tree list.

[0083] It should be noted that when constructing a tree list, the nodes in the tree list can be associated with the hierarchical structure diagram. For example, module 1 corresponds to the hierarchical structure Figure 1 , you can create a tree list with module 1 and a hierarchical structure Figure 1 , and establish the submodules, primitives and hierarchical structures called by module 1 Figure 1 The association relationship between the corresponding symbols in the tree list allows the user to switch the display of primitives, signals and sub-modules in the hierarchical structure diagram by selecting the nodes in the tree list.

[0084] The following is a further description of generating at least one initial structure diagram of the netlist according to the circuit level information of the netlist. Figure 6 As shown, the above step S501 includes:

[0085] S601 . Determine submodules and primitives connected to a main module according to circuit level information.

[0086] Optionally, the submodules and primitives called by the main module may be used as submodules and primitives connected to the main module.

[0087] S602. Taking the input port of the main module as the starting point, the main module is represented as the first symbol, each sub-module is represented as the second symbol, and each primitive is represented as the third symbol. According to the signal connection relationship between the main module and each sub-module and primitive, the connection lines between each sub-module, primitive and main module are generated to obtain the initial structure diagram of the main module.

[0088] Before generating the initial structure diagram, the relative distance and overall layout between modules and primitives, primitives and primitives, or modules and modules can be set according to the complexity of the design.

[0089] The input port of the main module is used as the starting point of the hierarchical structure diagram, the signal is represented as a connecting line, the main module, sub-module and primitive are represented as symbols, and each module and primitive is connected by connecting lines according to the hierarchical relationship and signal connection relationship indicated in the circuit hierarchy information to obtain the initial structure diagram of the main module.

[0090] The first symbol, the second symbol, and the third symbol may be the same graphic symbol or different graphic symbols. As an example, a rectangle may be used to represent a submodule, a triangle may be used to represent a primitive, and a rounded rectangle may be used to represent a main module.

[0091] S603, traversing the submodules of the main module, for the current submodule traversed, if the current submodule contains a called submodule, taking the submodule as a new main module, and determining the submodules and primitives connected to the new main module according to the circuit level information.

[0092] If the circuit level information indicates that the current submodule calls other submodules, the current submodule can be used as the main module currently drawn, and the submodules and primitives connected to the current submodule are determined according to the circuit level information.

[0093] S604. Taking the input port of the new main module as the starting point, the new main module is represented as the first symbol, each sub-module is represented as the second symbol, and each primitive is represented as the third symbol. According to the signal connection relationship between the new main module and each sub-module and primitive, the connection lines between each sub-module, primitive and main module are generated to obtain the initial structure diagram of the current sub-module.

[0094] The input port of the new main module is used as the starting point of the hierarchical structure diagram, the signal is represented as a connecting line, the new main module, sub-module and primitive are represented as symbols, and each module and primitive is connected by connecting lines according to the hierarchical relationship and signal connection relationship indicated in the circuit hierarchy information to obtain the initial structure diagram of the new main module.

[0095] The above steps S603 - S604 are repeatedly executed until the current submodule does not contain the called submodule, and all the obtained initial structure diagrams are used as the initial structure diagrams of the netlist.

[0096] After drawing all the sub-modules that call other modules, all the initial structure diagrams can be used as the initial structure diagrams of the netlist.

[0097] It should be noted that when generating the initial structure diagram, the user may also specify the sub-modules to be drawn based on actual needs, and use all the generated initial structure diagrams as the initial structure diagrams of the netlist.

[0098] After the initial structure diagram is obtained, power consumption data and flip rate data may be added to the initial structure diagram to obtain a hierarchical structure diagram of the netlist.

[0099] As another possible implementation method, after generating each initial structure diagram, the power consumption data, flip rate data and module information can be added to the corresponding position of the initial structure diagram to obtain a hierarchical structure diagram. After generating the hierarchical structure diagram of the main module, a primary structure diagram is generated for each traversed sub-module, and the power consumption data, flip rate data and module information are added to the initial structure diagram to obtain the hierarchical structure diagram of the sub-module, and so on, until the drawing of all levels is completed.

[0100] The following is a further description of adding the power consumption data, flip rate data and module information of each module, primitive and signal in the netlist to the corresponding position of each initial structure diagram to obtain the hierarchical structure diagram of the netlist. The above S502 step includes:

[0101] In the initial structure diagram, add the corresponding input port information to the left side of the symbols corresponding to each module, primitive and signal, add the corresponding output port information to the right side of the symbols corresponding to each module, primitive and signal, add the corresponding power consumption data below the symbols corresponding to each module and primitive, add the corresponding type and name to the symbols corresponding to each module and primitive, add the corresponding flip rate data and power consumption data below each signal connection line, and obtain the hierarchical structure diagram corresponding to the initial structure diagram.

[0102] Reference Figure 2The hierarchical structure diagram shown in area 2. The primitive name and instantiation name of the module / primitive are marked in the graphic symbol representing the module / primitive, the input port information is displayed on the left side of the graphic symbol, the output port information is displayed on the right side of the graphic symbol, the power consumption data is displayed below the primitive / module graphic, and the signal flip rate data and power consumption data are displayed below the signal connection line.

[0103] like Figure 2 As shown in the figure, in1~in4 represents the input port information of the primitive or module; out1~outn represents the output port information of the primitive or module; prim1: inst1, prim1 represents the primitive type, such as lookup table, register, etc., inst1 represents the instantiation name of the primitive; submodule1: moduleinst1, submodule1 represents the module name of the submodule, moduleinst1 represents the instantiation name of the module; TR represents the flip rate data toogle rate, where the flip rate is expressed as a percentage of the ratio of the number of signal flips to the number of clock flips, refer to Figure 2 , tr0%, tr1% represent the specific flip rate values; P represents the power consumption data power, p1, p2... represent the specific power consumption values, the unit is W; the total power consumption ALLPower of this level is displayed in the upper left corner of this level.

[0104] It should be noted that the present application only provides an example of adding information. It should be understood that power consumption data can also be displayed above the graphic symbol, and the flip rate and power consumption data can be displayed above the signal connection line. The present application does not limit the adding location.

[0105] The step of generating a tree list according to the hierarchical structure diagram of chip power consumption information includes:

[0106] Treat each module, primitive and signal as a node, arrange the nodes according to the hierarchical relationship indicated by the hierarchical structure diagram, and add a click event listener to each node.

[0107] After adding a click event listener to the node, when the user clicks a node, the currently selected node can be recorded and the circuit hierarchy diagram can be updated.

[0108] The following is a further description of the user interaction process. Specifically:

[0109] In response to a first operation on a node in the tree list, a hierarchical structure subgraph corresponding to the node in the hierarchical structure graph is displayed on the current graphical user interface.

[0110] Reference Figure 2The user can click on a module in the tree list in area 1. After the click event listener receives the event, it displays the hierarchical structure diagram corresponding to the module clicked by the user in area 2.

[0111] The first operation may be a single-click operation, a double-click operation, or the like.

[0112] In response to a second operation on a node representing a signal in the tree list, a signal connection line corresponding to the signal is highlighted on the current graphical user interface.

[0113] The second operation may be a single-click operation or a double-click operation. The user may click on a node representing a signal in the tree list, and after the event listener is clicked, the signal connection line corresponding to the signal is highlighted in the hierarchical structure diagram in area 2.

[0114] In response to a third operation on a module or a primitive in the hierarchical structure diagram, a source code corresponding to the module or the primitive in the source file is obtained.

[0115] The third operation may be a right-click or a double-click operation. The user may right-click a module or a primitive in the hierarchical structure diagram to jump to the source code location corresponding to the module or primitive in the source file.

[0116] As a possible implementation method, the user clicks on a module or primitive in the hierarchical structure diagram. After listening to the event, the click event listener can obtain the location information of the module or primitive, thereby jumping to the row position of the module or primitive in the gate-level netlist file, and determining the corresponding source code position in the source file based on the row position.

[0117] In the process of optimizing the design of the netlist, multiple power consumption calculations may be performed. In the embodiment of the present application, the modified points and power consumption changes can also be displayed based on the graphical results after the last power consumption calculation and the graphical results after the current power consumption calculation, such as Figure 7 As shown, the method of the present application also includes:

[0118] S701 , using the circuit level information of the previous netlist and the power consumption data of each module, primitive and signal in the netlist as an input file for current power consumption calculation.

[0119] S702. Generate the current graphical result of the chip power consumption information based on the current gate-level netlist file. If the gate-level netlist file of the chip is changed, determine the change point based on the input file, current power consumption data, current flip rate data and current graphical result, and mark the change point in the graphical result.

[0120] Optionally, the last circuit hierarchy information of the netlist can be compared with the current circuit hierarchy information to determine the change points, and the power consumption data of each module, primitive and signal as well as the flip rate data of the signal can be compared with the power consumption data of each module, primitive and signal as well as the flip rate data of the signal this time to determine the power consumption change points and the flip rate change points. The change points, power consumption change points and flip rate change points are taken as change points and highlighted in the hierarchical structure diagram, for example, highlighted or marked in red, so that the user can clearly see the change points and the corresponding power consumption changes.

[0121] Based on the same inventive concept, an embodiment of the present application also provides a graphical processing device for chip power consumption information corresponding to the graphical processing method for chip power consumption information. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the graphical processing method for chip power consumption information in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0122] Figure 8 The schematic diagram of the structure of a graphical processing device for chip power consumption information provided by an embodiment of the present application is shown. The device includes a first generating module 801, an information determining module 802 and a second generating module 803.

[0123] A first generating module 801 is used to generate circuit level information of a netlist according to a gate-level netlist file, wherein the circuit level information is used to represent the hierarchical relationship between modules and modules and between modules and primitives, and the signal connection relationship between modules and modules, modules and primitives, and primitives and primitives;

[0124] An information determination module 802 is used to determine the power consumption data and flip rate data of each module, primitive and signal in the netlist according to the power consumption configuration file of the chip;

[0125] The second generation module 803 is used to generate a graphical result of the chip power consumption information based on the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist. The graphical result includes a tree list and at least one hierarchical structure diagram. The hierarchical structure diagram includes: modules, primitives and signals in the netlist, as well as the power consumption data of the modules, primitives and signals in the netlist and the flip rate data of each signal.

[0126] Optionally, the first generating module 801 is specifically used for:

[0127] Extracting and processing the gate-level netlist file to obtain at least one module of the netlist;

[0128] Extract information from each module to obtain module information of each module, the module information includes: submodule information, primitive information, input and output information and location information contained in the module;

[0129] The circuit level information of the netlist is constructed based on the module information.

[0130] Optionally, the first generating module 801 is specifically used for:

[0131] Determine the calling relationship of each module according to the submodule information and primitive information contained in the module, where the calling relationship is used to indicate the information of module calling and the information of module being called;

[0132] If the calling relationship of the modules indicates that the current module is not called by other modules, the current module is taken as the main module, at least one submodule and / or primitive called by the main module is determined according to the calling relationship of the main module, and a hierarchical relationship between the main module and the submodule and / or a hierarchical relationship between the main module and the primitive is constructed;

[0133] According to the calling relationship of each submodule, determine the submodules and primitives called by each submodule, and build the hierarchical relationship between each submodule and the submodules called by each submodule and the hierarchical relationship between each submodule and the primitive;

[0134] According to the input and output information of the main module, each sub-module and primitive, the signal connection relationship of each main module, sub-module and primitive is constructed.

[0135] Optionally, the second generating module 803 is specifically used for:

[0136] Generate at least one initial structure diagram of the netlist according to the circuit level information of the netlist, wherein the initial structure diagram includes at least one module and a primitive, and each module and primitive is connected by a signal connection line;

[0137] Add the power consumption data, flip rate data and module information of each module, primitive and signal in the netlist to the corresponding position of each initial structure diagram to obtain a hierarchical structure diagram of the netlist;

[0138] A tree list is generated according to the circuit hierarchy information of the netlist, and the tree list and the hierarchy diagram are used as graphical results of the chip power consumption information. The modules, primitives and signals in the tree list are arranged according to the hierarchy relationship indicated by the hierarchy diagram.

[0139] Optionally, the second generating module 803 is specifically used for:

[0140] A. Determine the submodules and primitives connected to the main module according to the circuit level information;

[0141] B. Taking the input port of the main module as the starting point, the main module is represented as the first symbol, each submodule is represented as the second symbol, and each primitive is represented as the third symbol. According to the signal connection relationship between the main module and each submodule and primitive, the connection lines between each submodule, primitive and main module are generated to obtain the initial structure diagram of the main module;

[0142] C. Traverse the submodules of the main module. For the current submodule traversed, if the current submodule contains the called submodule, use the submodule as the new main module, and determine the submodules and primitives connected to the new main module according to the circuit level information;

[0143] D. Taking the input port of the new main module as the starting point, representing the new main module as the first symbol, representing each submodule as the second symbol, and representing each primitive as the third symbol, generating connection lines between each submodule, primitive, and main module according to the signal connection relationship between the new main module and each submodule and primitive, and obtaining the initial structure diagram of the current submodule;

[0144] Repeat steps CD until the current submodule does not contain the called submodule, and use all the obtained initial structure diagrams as the initial structure diagrams of the netlist.

[0145] Optionally, the second generating module 803 is specifically used for:

[0146] In the initial structure diagram, add the corresponding input port information to the left side of the symbols corresponding to each module, primitive and signal, add the corresponding output port information to the right side of the symbols corresponding to each module, primitive and signal, add the corresponding power consumption data below the symbols corresponding to each module and primitive, add the corresponding type and name to the symbols corresponding to each module and primitive, add the corresponding flip rate data and power consumption data below each signal connection line, and obtain the hierarchical structure diagram corresponding to the initial structure diagram.

[0147] Optionally, the second generating module 803 is specifically used for:

[0148] Each module, primitive and signal is regarded as a node, each node is arranged according to the hierarchical relationship indicated by the circuit hierarchy information, and a click event listener is added to each node.

[0149] Optionally, the device further includes a response module, specifically configured to:

[0150] In response to a first operation on a node in the tree list, displaying a hierarchical structure subgraph corresponding to the node in the hierarchical structure graph on the current graphical user interface;

[0151] In response to a second operation on a node representing a signal in the tree list, highlighting a signal connection line corresponding to the signal on the current graphical user interface;

[0152] In response to a third operation on a module or a primitive in the hierarchical structure diagram, a source code corresponding to the module or the primitive in the source file is obtained.

[0153] Optionally, the device further comprises a comparison module, specifically configured to:

[0154] The circuit level information of the previous netlist and the power consumption data of each module, primitive and signal in the netlist are used as the input file for the current power consumption calculation;

[0155] Generate a graphical result of the chip power consumption information based on the current gate-level netlist file. If the gate-level netlist file of the chip is changed, determine the change point based on the input file, current power consumption data, current flip rate data and current graphical result, and mark the change point in the graphical result.

[0156] The embodiment of the present application extracts the hierarchical structure information of the circuit from the gate-level netlist file and displays it clearly in a graphical form, which can help users quickly understand the structure of the circuit and improve the efficiency of subsequent circuit analysis. By displaying the power consumption data of signals, modules and primitives and the flip rate data of signals in the hierarchical structure diagram, designers can intuitively and quickly locate high power consumption and high flip rate areas, thereby improving the efficiency of power optimization analysis.

[0157] Fig. 9 A structural schematic diagram of an electronic device provided in an embodiment of the present application is shown, including: a processor 901, a storage medium 902 and a bus 903, wherein the storage medium 902 stores machine-readable instructions executable by the processor 901. When the electronic device runs a graphical processing method for chip power consumption information such as in the embodiment, the processor 901 communicates with the storage medium 902 via the bus 903, and the processor 901 executes the machine-readable instructions and the preamble of the method item of the processor 901 to execute the steps of the above-mentioned graphical processing method for chip power consumption information.

[0158] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. The computer program is executed when a processor is running, and the processor executes the steps of the above-mentioned method for graphically processing chip power consumption information.

[0159] In the embodiment of the present application, the computer program can also execute other machine-readable instructions when run by the processor to execute other methods described in the embodiment. For the specific execution method steps and principles, please refer to the description of the embodiment, which will not be repeated here.

[0160] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0161] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0163] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0164] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0165] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A graphical processing method for chip power consumption information, characterized in that: include: Generate circuit level information of the netlist according to the gate-level netlist file, wherein the circuit level information is used to characterize the hierarchical relationship between modules and modules and between modules and primitives, and the signal connection relationship between modules and modules, modules and primitives, and primitives and primitives; Determine the power consumption data and flip rate data of each module, primitive and signal in the netlist according to the power consumption profile of the chip; A graphical result of the chip power consumption information is generated based on the circuit hierarchy information and the power consumption data and flip rate data of each module, primitive and signal in the netlist. The graphical result includes a tree list and at least one hierarchical structure diagram. The hierarchical structure diagram includes: the modules, primitives and signals in the netlist, and the power consumption data of the modules, primitives and signals in the netlist and the flip rate data of each signal.

2. The method according to claim 1, characterized in that The circuit level information of the netlist is generated according to the gate-level netlist file, including: Extracting the gate-level netlist file to obtain at least one module of the netlist; Extracting information from each module to obtain module information of each module, wherein the module information includes: submodule information, primitive information, input and output information, and location information included in the module; The circuit level information of the netlist is constructed according to the module information.

3. The method according to claim 2, characterized in that The circuit level information of the netlist is constructed according to the module information, including: Determine the calling relationship of each module according to the submodule information and primitive information contained in the module, wherein the calling relationship is used to indicate the information of module calling and the information of module being called; If the calling relationship of the modules indicates that the current module is not called by other modules, the current module is taken as the main module, at least one submodule and / or primitive called by the main module is determined according to the calling relationship of the main module, and a hierarchical relationship between the main module and the submodules and / or a hierarchical relationship between the main module and the primitives is constructed; According to the calling relationship of each submodule, the submodules and primitives called by each submodule are determined, and the hierarchical relationship between each submodule and the submodules called by each submodule and the hierarchical relationship between each submodule and the primitive are constructed; According to the input and output information of the main module, each of the sub-modules and primitives, a signal connection relationship among each of the main modules, sub-modules and primitives is constructed.

4. The method according to claim 1, characterized in that: Generating a graphical result of the chip power consumption information according to the circuit level information and the power consumption data and flip rate data of each module, primitive and signal in the netlist includes: Generate at least one initial structure diagram of the netlist according to the circuit level information of the netlist, wherein the initial structure diagram includes at least one module and a primitive, and each of the modules and primitives is connected by a signal connection line; Adding power consumption data, flip rate data and module information of each module, primitive and signal in the netlist to corresponding positions of each of the initial structure diagrams to obtain a hierarchical structure diagram of the netlist; A tree list is generated according to the circuit hierarchy information of the netlist, and the tree list and the hierarchical structure diagram are used as graphical results of the chip power consumption information. The modules, primitives and signals in the tree list are arranged according to the hierarchical relationship indicated by the hierarchical structure diagram.

5. The method according to claim 4, characterized in that Generating at least one initial structure diagram of the netlist according to the circuit level information of the netlist includes: A. Determine each submodule and primitive connected to the main module according to the circuit level information; B. Taking the input port of the main module as the starting point, the main module is represented as a first symbol, each submodule is represented as a second symbol, and each primitive is represented as a third symbol. According to the signal connection relationship between the main module and each submodule and primitive, connection lines between each submodule, primitive and the main module are generated to obtain an initial structure diagram of the main module; C. traversing the submodules of the main module, for the traversed current submodule, if the current submodule includes the called submodule, taking the submodule as a new main module, and determining the submodules and primitives connected to the new main module according to the circuit level information; D. Taking the input port of the new main module as the starting point, representing the new main module as a first symbol, representing each of the submodules as a second symbol, and representing each of the primitives as a third symbol, generating connection lines between each of the submodules, primitives, and the main module according to the signal connection relationship between the new main module and each of the submodules and primitives, and obtaining an initial structure diagram of the current submodule; Repeat steps CD until the current submodule does not contain the called submodule, and use all the obtained initial structure diagrams as the initial structure diagrams of the netlist.

6. The method according to claim 4, characterized in that The step of adding the power consumption data, flip rate data and module information of each module, primitive and signal in the netlist to the corresponding position of each initial structure diagram to obtain the hierarchical structure diagram of the netlist includes: In the initial structure diagram, add corresponding input port information to the left side of the symbols corresponding to each module, primitive and signal, add corresponding output port information to the right side of the symbols corresponding to each module, primitive and signal, add corresponding power consumption data below the symbols corresponding to each module and primitive, add corresponding types and names in the symbols corresponding to each module and primitive, add corresponding flip rate data and power consumption data below each signal connection line, and obtain a hierarchical structure diagram corresponding to the initial structure diagram.

7. The method according to claim 4, characterized in that The step of generating a tree list according to the circuit level information of the netlist includes: Each of the modules, primitives and signals is respectively regarded as a node, each node is arranged according to the hierarchical relationship indicated by the circuit hierarchy information, and a click event listener is added to each of the nodes.

8. The method according to claim 7, characterized in that The method further comprises: In response to a first operation on a node in the tree list, displaying a hierarchical structure subgraph corresponding to the node in the hierarchical structure graph on the current graphical user interface; In response to a second operation on a node representing a signal in the tree list, highlighting a signal connection line corresponding to the signal on the current graphical user interface; In response to a third operation on a module or a primitive in the hierarchical structure diagram, a source code corresponding to the module or the primitive in a source file is obtained.

9. The method according to claim 1, characterized in that: The method further comprises: Using the circuit level information of the last netlist and the power consumption data of each module, primitive and signal in the netlist as an input file for current power consumption calculation; Generate a graphical result of the chip power consumption information based on the current gate-level netlist file. If the gate-level netlist file of the chip is changed, determine the change point based on the input file, current power consumption data, current flip rate data and current graphical result, and mark the change point in the graphical result.

10. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of a method for graphically processing chip power consumption information as described in any one of claims 1 to 9.

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