Digital-analog hybrid neural coding circuit

Abstract

The invention discloses a digital-analog hybrid neural coding circuit, and the circuit comprises an integrator which is used for receiving a current signal, and the integrator carries out the integration of the current signal, so as to simulate the integration effect of a membrane capacitor, thereby causing the rising of a membrane potential; the comparator 1 and the comparator 2 are used for judging the threshold value of the membrane potential, when the membrane potential is higher than the positive threshold value, the comparator 1 outputs a high level, when the membrane potential is lower than the positive threshold value, the comparator 1 outputs a low level, and the output of the comparator 1 is a P pulse sequence; when the membrane potential is lower than a negative threshold value, the comparator 2 outputs a high level, and when the membrane potential is higher than the negative threshold value, the comparator 2 outputs a low level, and the output of the comparator 2 is an N pulse sequence; and the non-response period module is used for receiving the P pulse sequence or the N pulse sequence after logic AND operation, and resetting the integrator to zero through a reset switch. The neural coding circuit realized by the invention has higher biological similarity and electronic compatibility.

Description

Technical Field

[0001] The present invention relates to the field of neural simulation technology, and in particular to a digital-analog hybrid neural coding circuit. Background Art

[0002] There are neurons that realize neural coding functions in sensory organs such as vision, hearing, smell, touch and taste. Although they are different, they can all convert environmental signals into analog signals and then into neural coding signals, that is, action potential pulse sequences, which are then transmitted to the brain to realize the perception and cognition of environmental information. A single nerve pulse has the characteristics of all or nothing, and the information of the analog signal is encoded into the pulse interval Δt. Therefore, the applicant has realized a neural coding circuit and applied for a patent. The authorization announcement number is CN112182974B. Figure 1 As shown in FIG. 1 , the circuit is designed based on the current-mode conduction (Current-Mode Conductance-based) working mode. By simulating the specific electrophysiological characteristics of the excitatory neuron cell membrane and reconstructing the conductive channel, the purpose of simulating neuron behavior is achieved. The current source generates a current I ext It simulates the external stimulation signal to the neurons. Figure 2 The HH model (Hodgkin-Huxley model) is similar to the equivalent circuit. This circuit model contains few components, is small in size, and is easy to implement on a large scale. Although analog circuit implementation has the advantages of fast computing speed, low power consumption, and high integration, it also has problems with biological similarity and electronic compatibility. Therefore, the applicant further explored the implementation of digital-analog hybrid circuits. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a digital-analog hybrid neural coding circuit.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0005] A digital-analog hybrid neural coding circuit includes: an integrator for receiving a current signal, wherein the integrator integrates the current signal to simulate the integration effect of a membrane capacitance, thereby causing an increase in membrane potential;

[0006] Comparator 1 and Comparator 2 are used to determine the threshold of membrane potential. When the membrane potential is higher than the positive threshold, Comparator 1 outputs a high level, and when the membrane potential is lower than the positive threshold, the output is a low level. The output of Comparator 1 is a P pulse sequence; when the membrane potential is lower than the negative threshold, Comparator 2 outputs a high level, and when the membrane potential is higher than the negative threshold, the output is a low level. The output of Comparator 2 is an N pulse sequence.

[0007] The refractory period module is used to receive a P pulse sequence or an N pulse sequence after a logical AND operation, and reset the integrator to zero through a reset switch; when the membrane potential is higher than the positive threshold, the comparator 1 output is a high level, causing the reset switch to close and the membrane potential to start to decrease. When it is lower than the positive threshold, the comparator 1 output changes to a low level. Due to the delay effect of the refractory period module, the reset switch will not be disconnected immediately, so that the membrane capacitance continues to discharge until it returns to zero. After the delay time is reached, the reset switch is disconnected and the integrator starts to charge; when the membrane potential is lower than the negative threshold, the comparator 2 output is a high level, causing the reset switch to close and the membrane potential starts to decrease. When it is higher than the positive threshold, the comparator 2 output changes to a low level. Due to the delay effect of the refractory period module, the reset switch will not be disconnected immediately, so that the membrane capacitance continues to discharge until it returns to zero. After the delay time is reached, the reset switch is disconnected and the integrator starts to charge.

[0008] Furthermore: it also includes a voltage-to-current converter, which is used to convert the input voltage signal into a current signal and transmit the current signal to the integrator.

[0009] Further: the voltage-to-current converter includes a HOWLAND current source circuit.

[0010] Further: the integrator includes the integrator including U1 precision switch integral transimpedance amplifier, U2 inverter and R1, R2, R3 resistors, the resistance values ​​of R1, R2, R3 are all 0 ohm resistors, and the sensitivity of the circuit is controlled by the selective connection of the three resistors. When only R1 is connected, the feedback capacitance of the circuit is 10pf, and the sensitivity of the circuit is the highest. When all three resistors are connected, the feedback capacitance of the circuit is 100pf, and the sensitivity of the circuit is the lowest. The analog input port is used to receive an analog current signal input from the outside, the switch control port is used to receive an external logic control signal, and the output port outputs the analog voltage value of the feedback capacitance;

[0011] The logic control signal controls the closing of switch S1, and the logic control signal controls the closing of switch S2 after being inverted by inverter U2; when the switch control signal is at a logic low level, switch S1 is closed, switch S2 is opened, and the analog input current signal flows into the feedback capacitor C. The accumulation of charge in the capacitor causes the voltage at both ends to increase, thereby increasing the output voltage signal; when the switch control signal is at a logic high level, switch S1 is opened, switch S2 is closed, the analog input current signal is disconnected, and the charge accumulated in the capacitor is neutralized through S2, so that the voltage at both ends will be 0V, and the output voltage signal will also be 0V.

[0012] Further: the refractory period module includes an asymmetric current absorption inverter, including a PMOS transistor and two NMOS transistors, receiving the V_spike logic signal output by the threshold comparison circuit, and outputting the membrane capacitance switch control logic signal Switch_control to the switch integrator circuit. When the V_spike input changes from a high level to a low level, U1 is turned on and U2 is turned off, Switch_control outputs a high level, and the rising and falling edge time is negligible; when the V_spike input changes from a low level to a high level, U1 is turned off and U2 is turned on, the Switch_control output becomes a low level, and the falling edge time is determined by the leakage current from the drain of U3 to GND, and its size is controlled by the gate voltage Vtdelay of U3. By adjusting the size of Vtdelay, the control of the refractory period pulse width is achieved.

[0013] Compared with the prior art, the present invention has the following technical advances:

[0014] Compared with the neural coding prototype circuit from two major aspects of biological similarity and electronic compatibility, the neural coding circuit implemented by the digital-analog hybrid circuit in the present invention has higher biological similarity and electronic compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0016] In the attached picture:

[0017] Figure 1 Neural coding circuits for analog circuits;

[0018] Figure 2 is the equivalent circuit of the HH neuron model;

[0019] Figure 3 A neural coding circuit model diagram of the digital-analog hybrid circuit of the present invention;

[0020] Figure 4 This is a schematic diagram of the current source circuit of the present invention;

[0021] Figure 5 The schematic diagram of the switching integrator circuit of the present invention is shown in FIG.

[0022] Figure 6 This is a schematic diagram of the asymmetric current absorption inverter circuit of the present invention;

[0023] Figure 7 This is a schematic diagram of a threshold comparison circuit of the present invention;

[0024] Figure 8This is a diagram of the encoding result of the present invention under the input sine wave (f=10Hz, Vpp=500mV);

[0025] Fig. 9 This is a diagram of the encoding result of the present invention when a sine wave (f=100 Hz, Vpp=500 mV) is input;

[0026] Fig.10 This is a diagram of the encoding result of the present invention when a sine wave (f=100 Hz, Vpp=5 V) is input;

[0027] Fig.11 This is a diagram of the encoding result of the present invention when a square wave (f=100 Hz, Vpp=0.5 V) is input;

[0028] Fig.12 This is a diagram of the encoding result of the present invention when a square wave (f=10Hz, Vpp=5V) is input;

[0029] Fig.13 This is a diagram of the encoding result of the present invention when a sawtooth wave (f=10Hz, Vpp=5V) is input;

[0030] Fig.14 This is a diagram of the encoding result of the present invention when a sawtooth wave (f=100 Hz, Vpp=1 V) is input;

[0031] Fig.15 This is a diagram of the encoding result of the present invention when a triangle wave (f=100 Hz, Vpp=0.5 V) is input;

[0032] Fig.16 This is a diagram of the encoding result of the present invention when a triangle wave (f=10Hz, Vpp=5V) is input;

[0033] Fig.17 This is a diagram of the encoding result of the present invention under the input noise signal (BW=1KHz, Vpp=5V);

[0034] Fig.18 Output pulse signal for the logic analyzer acquisition circuit of the present invention DETAILED DESCRIPTION

[0035] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0036] like Figure 2As shown, the digital-analog hybrid neural coding circuit includes: the analog signal input from the outside, if it is a current signal, is directly input into the integrator; if it is a voltage signal, it is necessary to convert the voltage signal into a current signal through a voltage-to-current converter and then input it into the integrator. Furthermore, a capacitor is used to integrate the current signal to simulate the integration effect of the membrane capacitance, thereby causing the membrane potential to rise. Two comparators are used to realize the positive threshold and negative threshold of the membrane potential. When the membrane potential exceeds the positive threshold, the output of comparator 1 is a high level, and when the membrane potential is lower than the positive threshold, the output of comparator 1 is a low level. Similarly, when the membrane potential is lower than the negative threshold, the output of comparator 2 is a high level, and when the membrane potential is higher than the negative threshold, the output of comparator 2 is a low level. After the outputs of the two comparators are operated by "logic AND", the pulse width is controlled by the refractory period module. The refractory period module realizes asymmetric delay by delaying the falling edge of the comparator output without affecting the rising edge. The output of the refractory period module realizes the reset of the charge integrator to zero through the reset switch. Therefore, when the membrane potential exceeds the positive threshold, the output of comparator 1 is high, causing the reset switch to close and the membrane potential to begin to drop. When it is lower than the positive threshold, the output of comparator 1 changes to a low level, but due to the delay of the refractory period module, the reset switch will not be disconnected immediately, so that the membrane capacitance continues to discharge until it returns to zero. After the delay time is reached, the reset switch is disconnected, the integrator begins to charge, and comparator 1 realizes a complete pulse signal process. Similarly, when the membrane potential is lower than the negative threshold, comparator 2 repeats the above process and also realizes a complete pulse signal process. The outputs of the two comparators are the P pulse sequence and N pulse sequence of the encoding circuit, which correspond to the neural encoding of the signal with a positive or negative input signal amplitude, respectively. It is worth noting that when the reset switch is closed, the integrator enters the signal discharge process and will not respond to the input of external signals at this time.

[0037] Figure 3 (B) is a circuit implementation of a digital-analog hybrid neural encoding module, which uses a HOWLAND current source module to achieve voltage-current signal conversion. The HOWLAND current source module achieves voltage-current signal conversion. Figure 4 As shown; the switch integrator realizes signal integration and reset as shown Figure 5As shown, it consists of U1 precision switch integral transimpedance amplifier (IVC102U), U2 inverter (SN74LVC1G04DCKR) and R1, R2, R3 resistors. The resistance values ​​of R1, R2, R3 are all 0 ohm resistors. The sensitivity of the circuit is controlled by the selection and connection of the three resistors. When only R1 is connected, the feedback capacitance of the circuit is 10pf, and the sensitivity of the circuit is the highest. When all three resistors are connected, the feedback capacitance of the circuit is 100pf, and the sensitivity of the circuit is the lowest. The other sensitivities are similar. The analog input port (Analog_input) is used to receive the analog current signal input from the outside, the switch control port (Switch_control) is used to receive the external logic control signal, and the output port (output) outputs the analog voltage value of the feedback capacitor.

[0038] The logic control signal controls the closing of switch S1, and the logic control signal controls the closing of switch S2 after being inverted by inverter U2. When the switch control signal is at a logic low level, switch S1 is closed, switch S2 is opened, and the analog input current signal flows into the feedback capacitor C. The accumulation of charge in the capacitor causes the voltage at both ends to increase, thereby increasing the output voltage signal. When the switch control signal is at a logic high level, switch S1 is opened, switch S2 is closed, the analog input current signal is disconnected, and the charge accumulated in the capacitor is neutralized through S2, so that the voltage at both ends will be 0V, and the output voltage signal will also be 0V.

[0039] Asymmetric current sink inverter to achieve refractory period time control Figure 6 As shown in (a), it consists of a PMOS transistor and two NMOS transistors, receives the V_spike logic signal output by the threshold comparison circuit, and outputs the membrane capacitance switch control logic signal Switch_control to the switch integrator circuit. When the V_spike input changes from a high level to a low level, U1 is turned on and U2 is turned off, Switch_control outputs a high level, and the rising and falling edge time can be ignored. When the V_spike input changes from a low level to a high level, U1 is turned off and U2 is turned on, and the Switch_control output becomes a low level. The falling edge time is determined by the leakage current from the drain of U3 to GND, and its size is controlled by the gate voltage Vtdelay of U3. By adjusting the size of Vtdelay, the control of the refractory period pulse width is achieved.

[0040] Figure 6(b) is the circuit schematic diagram of the commercial device design that completes the function of this circuit. Q1 and Q2 (LBSS8402DW1T1G) are two transistor integrated circuits, each chip consists of a PMOS and an NMOS transistor. The sliding resistor R and operational amplifier U1 are used to realize the adjustable DC voltage output signal, which is output to Vtdelay to control the refractory period pulse width of the circuit.

[0041] Comparators and logic gates are used to implement threshold comparison and generate pulse waveforms, such as Figure 7 As shown, it consists of comparators U1, U2 (LT1011CS8#PBF) and logic OR gate circuit U3 (SN74AHC1G32DBVR), VC_output is connected to the voltage signal output by the switch integrator circuit, V_TH_H and V_TH_L are connected to the positive threshold voltage and negative threshold voltage signals respectively. When the voltage of VC_output is higher than V_TH_H, U1 outputs a high level, and when the voltage of VC_output is lower than V_TH_H, U1 outputs a low level. When the voltage of VC_output is lower than V_TH_L, U2 outputs a high level, and when the voltage of VC_output is higher than V_TH_L, U2 outputs a low level. U3 performs a logic OR operation on the outputs of U1 and U2, and then outputs it to the V_spike port. Therefore, the function of this circuit is that when the voltage of VC_output is between V_TH_H and V_TH_L, V_spike outputs a low level, otherwise, V_spike outputs a high level. .

[0042] The encoding results of the neural coding circuit under different input signals are as follows: Figure 8-Figure 17 As shown in Figure 1, since the output of the digital-analog hybrid circuit is a logic pulse signal, the circuit output pulse signal can be acquired using a logic analyzer, such as Fig.18 As shown, the two neural coding prototype circuits were compared from two major aspects: biological similarity and electronic compatibility. The results are shown in Table 1. The tables with √ are better results.

[0043] Table 1 Comparison of two neural coding circuits

[0044]

[0045] It can be seen from Table 1 that the neural coding circuit implemented by the mixed digital-analog circuit has higher biological similarity and electronic compatibility.

[0046] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of protection of the claims of the present invention.

Claims

1. A digital-analog hybrid neural coding circuit, characterized in that: include: an integrator, used for receiving a current signal, wherein the integrator integrates the current signal to simulate an integration effect of a membrane capacitance, thereby causing an increase in membrane potential; Comparator 1 and Comparator 2 are used to determine the threshold of membrane potential. When the membrane potential is higher than the positive threshold, Comparator 1 outputs a high level, and when the membrane potential is lower than the positive threshold, the output is a low level. The output of Comparator 1 is a P pulse sequence; when the membrane potential is lower than the negative threshold, Comparator 2 outputs a high level, and when the membrane potential is higher than the negative threshold, the output is a low level. The output of Comparator 2 is an N pulse sequence. The refractory period module is used to receive a P pulse sequence or an N pulse sequence after a logical AND operation, and reset the integrator to zero through a reset switch; when the membrane potential is higher than the positive threshold, the comparator 1 output is a high level, causing the reset switch to close and the membrane potential to start to decrease. When it is lower than the positive threshold, the comparator 1 output changes to a low level. Due to the delay effect of the refractory period module, the reset switch will not be disconnected immediately, so that the membrane capacitance continues to discharge until it returns to zero. After the delay time is reached, the reset switch is disconnected and the integrator starts to charge; when the membrane potential is lower than the negative threshold, the comparator 2 output is a high level, causing the reset switch to close and the membrane potential starts to decrease. When it is higher than the positive threshold, the comparator 2 output changes to a low level. Due to the delay effect of the refractory period module, the reset switch will not be disconnected immediately, so that the membrane capacitance continues to discharge until it returns to zero. After the delay time is reached, the reset switch is disconnected and the integrator starts to charge.

2. The digital-analog hybrid neural coding circuit according to claim 1, characterized in that: It also includes a voltage-to-current converter, which is used to convert an input voltage signal into a current signal and transmit the current signal to the integrator.

3. The digital-analog hybrid neural coding circuit according to claim 2, characterized in that: The voltage-to-current converter includes a HOWLAND current source circuit.

4. The digital-analog hybrid neural coding circuit according to claim 1, characterized in that: The integrator includes a U1 precision switch integral transimpedance amplifier, a U2 inverter, and R1, R2, and R3 resistors. The resistance values ​​of R1, R2, and R3 are all 0 ohm resistors. The sensitivity of the circuit is controlled by the selective connection of the three resistors. When only R1 is connected, the feedback capacitance of the circuit is 10pf, and the sensitivity of the circuit is the highest. When all three resistors are connected, the feedback capacitance of the circuit is 100pf, and the sensitivity of the circuit is the lowest. The analog input port is used to receive an analog current signal input from the outside, the switch control port is used to receive an external logic control signal, and the output port outputs the analog voltage value of the feedback capacitance. The logic control signal controls the closing of switch S1, and the logic control signal controls the closing of switch S2 after being inverted by inverter U2; when the switch control signal is at a logic low level, switch S1 is closed, switch S2 is opened, and the analog input current signal flows into the feedback capacitor C. The accumulation of charge in the capacitor causes the voltage at both ends to increase, thereby increasing the output voltage signal; when the switch control signal is at a logic high level, switch S1 is opened, switch S2 is closed, the analog input current signal is disconnected, and the charge accumulated in the capacitor is neutralized through S2, so that the voltage at both ends will be 0V, and the output voltage signal will also be 0V.

5. The digital-analog hybrid neural coding circuit according to claim 4, characterized in that: The refractory period module includes an asymmetric current absorption inverter, including a PMOS transistor and two NMOS transistors, receiving the V_spike logic signal output by the threshold comparison circuit, and outputting the membrane capacitor switch control logic signal Switch_control to the switch integrator circuit. When the V_spike input changes from a high level to a low level, U1 is turned on and U2 is turned off, Switch_control outputs a high level, and the rising and falling edge time is negligible; when the V_spike input changes from a low level to a high level, U1 is turned off and U2 is turned on, Switch_control output changes to a low level, and the falling edge time is determined by the leakage current from the drain of U3 to GND, and its size is controlled by the gate voltage Vtdelay of U3. By adjusting the size of Vtdelay, the control of the refractory period pulse width is achieved.

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