Local refreshing method of display panel, display panel and electronic equipment

Abstract

The invention discloses a display panel local refreshing method, a display panel and electronic equipment, which are used for realizing local refreshing of the display panel and reducing refreshing power consumption. For example, in the electronic equipment, a display driving chip is connected with a system-on-chip and a display panel, the system-on-chip comprises a first image to be refreshed, only partial area on the first image needs to be updated, the display panel comprises n rows of pixels, and n is a positive integer. The display driving chip determines that the ith line on the first image needs to be refreshed according to the indication of the system-on-chip, the ith line is located in the partial region, and i is a positive integer; and the display driving chip writes the ith row of image data sent by the system-on-chip into the ith row of pixels of the display panel, wherein the ith row of image data is the ith row of image data in the partial region.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a display panel partial refresh method, a display panel and an electronic device. Background Art

[0002] With the rapid development of display technology, electronic devices are increasingly pursuing high refresh rates and high resolutions. Although high refresh rates and high resolutions can improve the smoothness of display and enhance user experience, they also increase power consumption, especially for large-screen devices, which have a greater impact on power consumption. Summary of the invention

[0003] The embodiments of the present application provide a display panel partial refresh method, a display panel, and an electronic device for reducing power consumption generated by refreshing a display screen.

[0004] In a first aspect, a method for partial refresh of a display panel is provided, which is applied to a display driver chip, wherein the display driver chip is connected to a system on chip and a display panel respectively, wherein the system on chip includes a first image to be refreshed, and only a partial area on the first image needs to be updated, and the display panel includes n rows of pixels, where n is a positive integer. The method comprises: the display driver chip determines, according to an instruction of the system on chip, that the i-th row on the first image needs to be refreshed, wherein the i-th row is located in the partial area, and i is a positive integer; and the display driver chip writes the i-th row of image data sent by the system on chip into the i-th row of pixels of the display panel, wherein the i-th row of image data is the image data of the i-th row in the partial area.

[0005] In an embodiment of the present application, the electronic device can partially refresh the display panel. Compared with a solution of refreshing the display panel in full screen, the embodiment of the present application can save power consumption and improve efficiency.

[0006] In one possible design, the display driver chip determines that the i-th row on the first image needs to be refreshed according to the indication of the on-chip system, including: the display driver chip receives first indication information sent by the on-chip system, the first indication information is used to indicate a refresh start row and a refresh end row, the refresh start row corresponds to a start row of the partial area, and the refresh end row corresponds to an end row of the partial area.

[0007] In an embodiment of the present application, the display driver chip can determine which rows need to be refreshed according to the instructions of the on-chip system, and only partially refresh the rows that need to be refreshed on the display panel. For the rows that do not need to be refreshed, they are not refreshed, thereby saving power consumption and improving efficiency.

[0008] In one possible design, the first indication information is carried in a frame synchronization signal or CMD.

[0009] It should be noted that the first indication information can be carried in any signal sent by the system on chip to the display driver chip, as long as it indicates the refresh start row and the refresh end row to the display driver chip, and the embodiment of the present application is not limited thereto.

[0010] In a possible design, the first indication information is carried in CMD, and the display driver chip receives the first indication information sent by the system on chip, including: the display driver chip receives the first indication information sent by the system on chip at time T1; the time T1 is within the blanking period and before the time T2, the time T2 is the receiving time of the frame synchronization signal, and the frame synchronization signal is used to achieve frame synchronization between the display driver chip and the display panel.

[0011] In an embodiment of the present application, before the next frame image is refreshed, the on-chip system sends a frame synchronization signal to the display driver chip. Before the frame synchronization signal, CMD can be sent to the display driver chip to indicate the refresh start row and the refresh end row, so that the display driver chip can prepare. For example, the display driver chip can enable the counter in advance.

[0012] In a possible design, before the display driver chip writes the i-th row of image data sent by the on-chip system into the i-th row of pixels of the display panel, the method also includes: the display driver chip receives the frame synchronization signal at the T2 moment; the display driver chip starts counting the counter, and the counter counts by 1 each time a row synchronization signal is received; the display driver chip receives a row synchronization signal at the T3 moment, and the count of the counter reaches K+i; the display driver chip determines that the row synchronization signal received at the T3 moment is the row synchronization signal of the i-th row; the display driver chip establishes clock synchronization with the i-th row of pixels on the display panel according to the row synchronization signal of the i-th row; wherein K is the number of row synchronization signals received by the display driver chip during the period from the T2 moment to the T4 moment, the T4 moment is the start time of transmission of the first row of image data in the first image, and the T4 moment is earlier than or equal to the T3 moment.

[0013] In the embodiment of the present application, the display driver chip can determine whether the currently received row synchronization signal is the row synchronization signal of the row that needs to be refreshed by counting, and if so, the image data of this row is received accordingly, and if not, the image data of this row is not received. In this way, the display panel can be partially refreshed, saving power consumption and improving efficiency.

[0014] In one possible design, the method further includes: before the T3 moment, the display driver chip does not receive image data from the system on chip.

[0015] In the embodiment of the present application, for a row that does not need to be refreshed, the display driver chip may not receive the image data of the row, thereby reducing power consumption.

[0016] In one possible design, the display driver chip determines that the i-th row on the first image needs to be refreshed according to the indication of the on-chip system, including: the display driver chip receives a row synchronization signal of the i-th row sent by the on-chip system, the row synchronization signal of the i-th row includes second indication information, and the second indication information is used to indicate the refresh of the row.

[0017] In the embodiment of the present application, the row synchronization signal may indicate whether the row needs to be refreshed. For rows that do not need to be refreshed, they may not be refreshed to reduce power consumption.

[0018] In one possible design, before the display driver chip determines, based on an indication of the system on chip, that the i-th row on the first image needs to be refreshed, the method further includes: the display driver chip receives third indication information sent by the system on chip, wherein the third indication information is used to indicate a partial refresh of the next frame of the image.

[0019] In the embodiment of the present application, the on-chip system may also indicate to the display driver chip that the next frame of image needs to be partially refreshed, so that the display driver chip can prepare for the partial refresh in advance.

[0020] In one possible design, the third indication information is carried in a frame synchronization signal or CMD.

[0021] It should be noted that the third indication information can be carried in any signal sent by the system on chip to the display driver chip, as long as it indicates to the display driver chip that the next frame of image needs to be partially refreshed, and the embodiment of the present application is not limited thereto.

[0022] In a second aspect, a method for partial refresh of a display panel is also provided, which is applied to a system on chip, wherein the system on chip is connected to a display driver chip, and the system on chip includes a first image to be refreshed, and only a partial area on the first image needs to be updated. The method includes: the system on chip indicates to the display driver chip that the i-th row on the first image needs to be refreshed, and the i-th row is located in the partial area, and i is a positive integer; the system on chip sends the i-th row of image data to the display driver chip, and the i-th row of image data is used to be written into the i-th row of pixels in the display panel, and the i-th row of image data is the image data of the i-th row in the partial area.

[0023] In one possible design, the on-chip system indicates to the display driver chip that the i-th row on the first image needs to be refreshed, including: the on-chip system sends first indication information to the display driver chip, the first indication information is used to indicate a refresh start row and a refresh end row, the refresh start row corresponds to a start row of the partial area, and the refresh end row corresponds to an end row of the partial area.

[0024] In one possible design, the first indication information is carried in a frame synchronization signal or CMD.

[0025] In a possible design, the first indication information is carried in CMD, and the on-chip system sends the first indication information to the display driver chip, including: the on-chip system sends the first indication information to the display driver chip at time T1; the T1 time is within the blanking period and before the T2 time, the T2 time is the sending time of the frame synchronization signal, and the frame synchronization signal is used to achieve frame synchronization between the display driver chip and the display panel.

[0026] In one possible design, the on-chip system sends the i-th row of image data to the display driver chip, including: the on-chip system sends the i-th row of image data to the display driver chip at time T3, the time T3 is after the time T2, and before the time T3, the on-chip system does not send image data to the display driver chip.

[0027] In one possible design, the on-chip system indicates to the display driver chip that the i-th row on the first image needs to be refreshed, including: the on-chip system sends a row synchronization signal of the i-th row to the display driver chip, the row synchronization signal of the i-th row includes second indication information, and the second indication information is used to indicate the refresh of the current row.

[0028] In one possible design, before the on-chip system indicates to the display driver chip that the i-th row on the first image needs to be refreshed, the method further includes: the on-chip system sends third indication information to the display driver chip, and the third indication information is used to indicate a partial refresh of the next frame image.

[0029] In one possible design, the third indication information is carried in a frame synchronization signal or CMD.

[0030] In a third aspect, a display panel is also provided, including:

[0031] A pixel array, wherein the pixel array includes n rows of pixels, where n is a positive integer;

[0032] A column scanning circuit connected to the pixel array and used for writing image data into the pixel array;

[0033] A row scanning circuit, comprising n control circuits, each of the n control circuits being connected to a row of pixels in the n rows of pixels and used to control the on or off of the row of pixels, the n control circuits comprising a first control circuit, the first control circuit being any one of the n control circuits, the first control circuit comprising: an input module, a control module and an output module, the control module being connected to the input end and the first output module respectively; wherein,

[0034] The input module is used to input signals;

[0035] The control module is used to control the output signal according to the reference signal. When the reference signal is a high level signal, the output module is a high level signal, and when the reference signal is a low level signal, the output signal is a low level signal;

[0036] The first output module is used to output a signal;

[0037] Among them, when the first output module outputs a high-level signal, the first control circuit controls the pixels of the first row to turn on, the first row is the row corresponding to the first control circuit, and the column scanning circuit writes image data into the pixels of the first row. When the first output module outputs a low-level signal, the first control circuit controls the pixels of the first row to turn off.

[0038] In one possible design, the control module includes: a first transistor;

[0039] The gate of the first transistor is connected to the input module;

[0040] The drain of the first transistor is connected to a reference signal output module, and the reference signal output module is used to input a reference signal to the drain;

[0041] A source of the first transistor is connected to the first output module.

[0042] In one possible design, the control module further includes: a second transistor;

[0043] The drain of the second transistor is connected to a clock signal output module, and the clock signal output module is used to output a clock signal;

[0044] The source of the first transistor is connected to the first output module, comprising:

[0045] The drain of the first transistor is connected to the gate of the second transistor, and the source of the second transistor is connected to the first output module;

[0046] Among them, when the first transistor is turned on, if the reference signal input to the drain by the reference signal output module is a high-level signal, the second transistor is turned on, if the clock signal output by the clock signal output module is a high-level signal, then the first output module outputs a high-level signal, and if the clock signal is a low-level signal, then the first output module outputs a low-level signal.

[0047] In one possible design, the control module further includes: a third transistor;

[0048] The gate of the third transistor is connected to the input module;

[0049] The drain of the third transistor is connected to the clock signal output module;

[0050] The source of the third transistor is connected to a second output module, the second output module is connected to an input module of a second control circuit, the second control circuit is used to control the opening or closing of pixels in a second row, and the second row is the next row of the first row.

[0051] In a possible design, a capacitor is included between the gate and source of the third transistor.

[0052] In one possible design, the control module further includes: a fourth transistor;

[0053] The gate of the fourth transistor is connected to the power supply VDD;

[0054] The drain of the fourth transistor is connected to the gate of the second transistor;

[0055] The source of the fourth transistor is connected to the low level output terminal.

[0056] In a fourth aspect, a display driver chip is also provided, for executing the method described in the first aspect.

[0057] In a fifth aspect, a system on chip is also provided for executing the method described in the second aspect.

[0058] In a sixth aspect, a display system architecture is also provided, including: a system on chip and a display driver chip; wherein,

[0059] The system on chip is used to execute the method as described in the second aspect above;

[0060] The display driver chip is used to execute the method described in the first aspect above.

[0061] In a seventh aspect, a display system architecture is also provided, including: a system on chip, a display driver chip, and a display panel; wherein:

[0062] The system on chip is used to execute the method as described in the second aspect above;

[0063] The display driver chip is used to execute the method described in the first aspect above;

[0064] The display panel is the display panel provided in the third aspect above.

[0065] In an eighth aspect, an electronic device is also provided, comprising: a structure as described in any one of the fourth aspect, fifth aspect, sixth aspect, or seventh aspect above.

[0066] In the ninth aspect, a computer-readable storage medium is also provided, wherein the computer-readable storage medium is used to store a computer program. When the computer program is run on a computer, the computer executes the method described in any one of the first aspect or the second aspect above.

[0067] In the tenth aspect, a computer program product is also provided, comprising a computer program, which, when executed on a computer, enables the computer to execute the method described in any one of the first aspect or the second aspect.

[0068] For the technical effects that can be achieved in the above-mentioned second to tenth aspects, please refer to the description of the technical effects that can be achieved by the corresponding design scheme in the above-mentioned first aspect, and this application will not repeat them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1A A schematic diagram of a display screen of an electronic device provided in one embodiment of the present application;

[0070] Figure 1B A schematic diagram of partial refresh of a display screen of an electronic device provided by an embodiment of the present application;

[0071] Figure 2 A schematic diagram of a display system architecture of an electronic device provided in an embodiment of the present application;

[0072] Figure 3 A schematic diagram of a display screen refresh process in Command Mode provided in an embodiment of the present application;

[0073] Figure 4 A schematic diagram of a display screen refresh process in Video Mode provided in an embodiment of the present application;

[0074] Figure 5 A schematic diagram of a partial refresh process of a display screen in Video Mode according to an embodiment of the present application;

[0075] Figure 6A schematic diagram of a first local refresh solution provided in an embodiment of the present application;

[0076] Figure 7 A schematic diagram of a second local refresh solution provided in an embodiment of the present application;

[0077] Figure 8 A schematic diagram of a third local refresh solution provided in an embodiment of the present application;

[0078] Fig. 9 A schematic diagram of the structure of a display panel provided in one embodiment of the present application;

[0079] Fig.10 A schematic diagram of the structure of a GOA provided in one embodiment of the present application;

[0080] Fig.11 A schematic diagram of GOA controlling partial refresh of a display panel provided in an embodiment of the present application;

[0081] Fig.12 Another structural schematic diagram of the GOA provided in one embodiment of the present application;

[0082] Fig.13 Another schematic diagram of GOA controlling partial refresh of a display panel provided in an embodiment of the present application;

[0083] Fig.14 A schematic diagram of a first structure of an electronic device provided by an embodiment of the present application;

[0084] Fig.15 A schematic diagram of a second structure of an electronic device provided by an embodiment of the present application;

[0085] Fig.16 A third structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0086] Fig.17 A fourth structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0087] Below, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0088] The at least one involved in the embodiment of the present application includes one or more; wherein, more than one means greater than or equal to two. In addition, it should be understood that in the description of this specification, the words "first", "second", etc. are only used for the purpose of distinguishing the description, and cannot be understood as expressing or implying relative importance, nor can they be understood as expressing or implying order. For example, the first row synchronization signal and the second row synchronization signal do not represent the importance of the two or the order of the two, but are only for distinguishing the description. In the embodiment of the present application, "and / or" is only a description of the association relationship, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship.

[0089] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the specification. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0090] As used in this specification, the term “when” or “after” may be interpreted to mean “if” or “after” or “in response to determining that” or “in response to detecting that”, depending on the context. Similarly, the phrase “upon determining that” or “if (stated condition or event) is detected” may be interpreted to mean “if determining that” or “in response to determining that” or “upon detecting (stated condition or event)” or “in response to detecting (stated condition or event)”, depending on the context.

[0091] The display panel partial refresh method provided in the embodiment of the present application is applicable to electronic devices. Exemplarily, the electronic device can be a portable electronic device such as a mobile phone, a tablet computer, a laptop computer, or a wearable device such as a watch or a bracelet, or a virtual reality (VR) device, an augmented reality (AR) device, a mixed reality (MR) device, or a vehicle-mounted device, etc. In short, the embodiment of the present application does not limit the specific type of electronic device. For the convenience of description, this article mainly takes the electronic device as a tablet computer as an example for explanation.

[0092] In electronic devices, various graphical user interfaces (GUIs) are superimposed on other display content sources to form a complete display screen presented to the user. Currently, electronic devices on the market mainly use a global refresh method (also known as a full-screen refresh). In this method, the image content in the display screen needs to be globally drawn, rendered, synthesized, and data transmitted, and the display driver chip needs to globally refresh the display panel and finally display the image content. In simple terms, a full-screen refresh is to refresh the entire display panel.

[0093] In actual applications, there is a possible scenario: only a small area of ​​the display screen of the electronic device needs to be refreshed, and other areas do not need to be refreshed.

[0094] For example, see Figure 1A , an electronic device (for example, a tablet computer) displays an interface, which includes area 1 and area 2. Area 1 displays a video being played (for example, a video of playing football). Area 2 displays text. The information in area 1 changes dynamically, and the information in area 2 is static. In this case, if the full-screen refresh method is used, the entire display panel will be refreshed, that is, both area 1 and area 2 will be refreshed. But in fact, whether area 2 is refreshed or not will not have much impact on the user experience, because the content of area 2 has not changed, so area 2 does not actually need to be refreshed. Obviously, in this case, using the full-screen refresh method will waste power consumption.

[0095] The embodiment of the present application provides a display panel partial refresh solution, which can reduce the display refresh power consumption, improve efficiency, and will not affect the display effect of high dynamic response. Figure 1A Taking the scenario shown in the figure as an example, if the local refresh solution provided by the embodiment of the present application is used, only the area where the content has changed (i.e., area 1) needs to be drawn, rendered, transmitted, and the local refresh of the display panel is performed and finally displayed, and the area where the content has not changed (i.e., area 2) does not need to be drawn, rendered, transmitted, and refreshed. Figure 1B .

[0096] The following describes, in conjunction with the accompanying drawings, a partial refresh solution for a display panel provided in an embodiment of the present application.

[0097] See also Figure 2 , is a schematic diagram of a display system architecture of an electronic device provided in an embodiment of the present application. The electronic device may be, for example, a tablet computer.

[0098] like Figure 2 The display system architecture of an electronic device includes a system on a chip (Soc), a display driver chip and a display panel (panel).

[0099] The system on chip may include a display content source and control module (the display-related part of the system on chip is called the display content source and control module), which includes a video source and an image drawing source, a video codec, a DDR memory, a hardware synthesis module, and a display subsystem (including various display engines, display bottom-layer drivers, and physical layer interfaces, etc.). The display content source and control module in the system on chip is the provider and controller of the display screen. For example, the display content source in the system on chip can draw and render the display screen by itself, or it can also receive a rendered display screen or video source sent by other devices (for example, a CPU, a GPU, or an AP).

[0100] The display driver chip is used to receive the image content of the system on chip and drive the display panel to completely display the image content on the display panel. Exemplarily, the display driver chip can be a display driver integrated circuit (display driver IC, DDIC).

[0101] Optionally, the image content can be refreshed line by line on the display panel. For example, the system on chip transmits the image content in a serial transmission manner. The first line of image content is first transmitted to the display driver chip, and after the display driver chip completes the refresh display of the line of image content on the display panel, the next line is processed in sequence. After the last line of image content is transmitted and displayed, the refresh of one frame of image is completed.

[0102] It should be noted that the interaction between the system on chip and the display driver chip can be based on the Display Serial Interface (DSI). DSI is generated based on the Mobile Industry Processor Interface (MIPI). MIPI supports two transmission modes: Command Mode and Video Mode. In these two modes, the interaction process between the system on chip and the display driver chip is different.

[0103] 1. Command Mode

[0104] For example, when the DSI between the system on chip and the display driver chip is based on MIPI, and MIPI is based on CommandMode, the interaction process between the system on chip and the display driver chip can be referred to Figure 3 .

[0105] First of all, it should be noted that since the DSI between the system on chip and the display driver chip is based on CommandMode, when the system on chip transmits image content to the display driver chip, the image content is transmitted serially according to the set transmission speed and the order of the rows. One cycle is one frame, and there is no strict requirement for row synchronization alignment.

[0106] like Figure 3 In (a), the system on chip includes a DDR memory, such as a frame buffer. Correspondingly, the display driver chip includes a DDR memory, such as a frame buffer. For the sake of distinction, the frame buffer in the system on chip is referred to as frame buffer 1, and the frame buffer in the display driver chip is referred to as frame buffer 2. The frame buffer 1 in the system on chip includes image content to be transmitted.

[0107] In a cycle, if Figure 3 In (a), after receiving the tearing effect (TE) signal sent by the display driver chip, the system on chip sends the image content 1 in the frame buffer 1 to the display driver chip. The image content 1 is a complete image frame, and Figure 3 In (a), the image content 1 needs to be completely refreshed as an example (i.e., the image content 1 is completely indicated by slashes). The process of the system on chip transmitting the image content to the display driver chip can also be called the display transmission process. After the display driver chip receives the image content 1, the image content 1 can be temporarily stored in the frame buffer 2 in the display driver chip, and the display panel can be refreshed by full-screen refresh so that the display panel displays the image content 1.

[0108] In the next cycle, if Figure 3 In (b), after receiving the next TE signal sent by the display driver chip, the on-chip system needs to send the image content 2 in the frame buffer 1 to the display driver chip. Image content 2 is a complete frame of image, for example, it can be the next frame of image content 1. Since only part of the image content 2 needs to be refreshed compared to image content 1 (indicated by diagonal lines), the on-chip system only sends the image content in the area that needs to be refreshed (i.e., the diagonal part) to the display driver chip. After the display driver chip receives this part of the image content (diagonal area), it can synthesize this part of the image content with the image content of the previous frame into a complete image, and then cache the complete image in frame buffer 2, and refresh the display panel using a full-screen refresh method so that the display panel displays the complete image.

[0109] Obviously, Figure 3 In the example, although the next frame image (ie, image content 2) only needs to be partially refreshed, the display driver chip still uses a full-screen refresh method, resulting in a waste of refresh power consumption.

[0110] 2. Video Mode

[0111] For example, when the DSI between the system on chip and the display driver chip is based on MIPI, and MIPI is based on Video Mode, the interaction process between the system on chip and the display driver chip can be referred to Figure 4 .

[0112] First of all, it should be noted that since the DSI between the system on chip and the display driver chip is based on Video Mode, the system on chip transmits image content to the display driver chip line by line, that is, each time a line of image data is transmitted, strict line synchronization alignment is required.

[0113] like Figure 4 In (a), the on-chip system includes a frame buffer. The frame buffer includes image content waiting to be transmitted.

[0114] In a cycle, if Figure 4 In (a), the system on chip sends a frame synchronization signal to the display driver chip to instruct the display driver chip to prepare for refreshing the next frame of image content (i.e., image content 1). Afterwards, the system on chip needs to send the frame buffer including image content 1 to the display driver chip. In order to ensure row synchronization, each time the system on chip sends a row synchronization signal to the display driver chip, it sends a row of image data in image content 1. Each time the display driver chip receives a horizontal synchronization signal (Hsync), it receives a row of image data and then caches the image data of the row in the row buffer. The display driver chip achieves row synchronization with the system on chip based on the row synchronization signal, and refreshes the image data of this row from the row buffer to the corresponding row on the display panel.

[0115] Here, it should be noted that, unlike the Command Mode, in the Command Mode, a frame buffer needs to be set in the display driver chip, while in the Video Mode, a line buffer needs to be set in the display driver chip.

[0116] In the next cycle, if Figure 4In (b), the system on chip sends the next frame synchronization signal to the display driver chip to instruct the display driver chip to prepare for refreshing the next frame of image content (i.e., image content 2). After that, the system on chip needs to send the frame buffer including image content 2 to the display driver chip. In order to ensure row synchronization, each time the system on chip sends a row synchronization signal to the display driver chip, it sends a row of image data in image content 2. Each time the display driver chip receives an Hsync, it receives a row of image data and then caches the image data of the row in the row buffer. The display driver chip achieves row synchronization with the system on chip based on the row synchronization signal, and refreshes the image data of this row from the row buffer to the corresponding row on the display panel.

[0117] It should be noted that Figure 4 There is a possible situation: only part of the image content 2 (the diagonal area) needs to be updated relative to the image content 1. In this case, according to the above interaction process, even if only part of the image content 2 needs to be updated, the display transmission process still transmits the complete image of the image content 2. In fact, only the image data of each line in the diagonal area needs to be transmitted, which wastes transmission power consumption. Moreover, the display driver chip uses a full-screen refresh method to refresh the image content 2, which wastes refresh power consumption.

[0118] From the above description, it can be seen that the two transmission modes supported by MIPI cannot achieve partial refresh of the display panel. The embodiment of the present application provides a partial refresh solution, which can be applied to any of the above two transmission modes. For ease of understanding, the following mainly takes Video Mode as an example for explanation.

[0119] Please compare Figure 4 (b) and Figure 5 Since only part of the image content 2 (for example, the oblique line area) needs to be updated relative to the image content 1, Figure 5 In the display process, after adopting the local refresh solution provided in the embodiment of the present application, the on-chip system only needs to send the image data of each row in the oblique line area in the image content 2 to the display driver chip, for example, sending the image data from the i-th row to the last n rows (the last row), and there is no need to send the image data of all rows. In other words, in Video Mode, if the technical solution provided in the embodiment of the present application is adopted, for the rows that need to be refreshed, the on-chip system will send the image data of the row, that is, the whole link is in a high-speed state or a high-power consumption mode. For the rows that do not need to be refreshed, the on-chip system will not transmit the image data of the row, that is, the whole link returns from the high-speed state to the low-speed state (or low-power consumption mode). Figure 4 (b) in the figure is to send all rows of image data, so the technical solution of the embodiment of the present application reduces the transmission power consumption. Figure 5 In the example, when the display driver chip refreshes the display panel, it only needs to refresh the i-th row to the last row on the display panel, and other rows do not need to be refreshed. Figure 4 (b) in the figure is to refresh all the rows on the display panel, so the technical solution of the present application reduces the refresh power consumption of the display panel.

[0120] The following continues Figure 5 Take the following as an example to illustrate the local refresh solution provided by the embodiment of the present application.

[0121] The first option

[0122] Continue with Figure 5 For example, the system on chip sends a frame synchronization signal (Vsync) to the display driver chip, and Vsync may include an indication information, which is used to indicate that the next frame of image content (i.e., image content 2) is partially refreshed. The display driver chip can determine that the next frame of image content only needs to be partially refreshed based on Vsync. Optionally, the indication information can be located in any field in Vsync, which is not limited in the embodiment of the present application.

[0123] It is understandable that, although the display driver chip can determine that only a partial refresh is required for the next frame of image content according to Vsync, it cannot determine which rows in the next frame of image content need to be refreshed. One possible implementation is that, for rows that need to be refreshed, the Hsync corresponding to the row includes indication information for indicating that the row is refreshed. For rows that do not need to be refreshed, the Hsync corresponding to the row may not include indication information. Figure 5 For example, since the i-th row to the n-th row (the last row) on the image content 2 need to be refreshed, each Hsync from Hsync i to Hsync n includes indication information for indicating that the row is refreshed, and each Hsync from Hsync 1 to Hsync i-1 does not include indication information. Alternatively, for the row that needs to be refreshed, the Hsync corresponding to the row does not include indication information; for the row that does not need to be refreshed, the Hsync corresponding to the row includes indication information for indicating that the row is not refreshed. Figure 5 For example, each Hsync from Hsync i to Hsync n does not include indication information, and each Hsync from Hsync 1 to Hsync i-1 includes indication information for indicating that the row is not to be refreshed. Alternatively, for a row that needs to be refreshed, the Hsync corresponding to the row includes indication information 1, and indication information 1 is used to indicate that the row is refreshed. For a row that does not need to be refreshed, the Hsync corresponding to the row includes indication information 2, and indication information 2 is used to indicate that the row is not to be refreshed. Optionally, the indication information can be located in any field in the Hsync, which is not limited in the embodiment of the present application.

[0124] For example, see Figure 6 , is a signal diagram between the system on chip and the display driver chip in the first solution. It should be noted that Figure 6 (as well as Figure 7 , Figure 8 ) where VSS stands for Vsync and HSS stands for Hsync.

[0125] like Figure 6 , the display driver chip receives Vsync at time T1, and Vsync includes indication information for indicating that the next frame of image content (i.e., image content 2) is partially refreshed. It should be noted that Figure 6 Vsync that includes indication information is represented by VSS*.

[0126] Optional, Figure 6 In the figure, time T1 is in the blanking period of the display panel. The blanking period can be understood as a period after the system on chip sends the last line of image data of the previous frame of image content (i.e., image content 1) and before sending the first line of image data of the next frame of image content (i.e., image content 2). During this period, the system on chip will send Hsync of each line to the display driver chip, but will not send image data. The display driver chip establishes line synchronization with each line on the display panel based on the Hsync of each line, but will not write image data to any line of the display panel. It can be simply understood that before the display driver chip receives the next frame of image content, it first performs a line synchronization with the system on chip.

[0127] Optionally, the blanking period of the display panel may include a forward vertical blanking period and a backward vertical blanking period, and time T1 may be located within the forward vertical blanking period.

[0128] Optionally, the T1 moment may be any moment within the blanking period. Alternatively, the T1 moment may be fixed, for example, Figure 6 , time T1 is within the blanking period, and the duration from time T2 is a fixed duration, during which the number of Hsyncs transmitted is fixed, for example, Figure 6 In the example, after time T1, the display driver chip receives 6 Hsyncs before reaching time T2. Time T2 is the start time of the display valid data area.

[0129] like Figure 6 , the display driver chip receives Hsync1 (i.e., the Hsync of the first row) at time T2. Since Hsync1 includes indication information, the indication information indicates that the row is not refreshed. It should be noted that Figure 6HSS* is used to represent Hsync that contains indication information. Since the indication information in Hsync1 indicates that the row is not to be refreshed, the display driver chip may not receive the image data of the row, that is, it may not receive the first long package (LGP) (as mentioned above, the system on chip does not actually send the image data of the row). Therefore, the display driver chip will not write new image data into the first row of pixels of the display panel, that is, the pixels of the first row still retain the image data of the first row of the previous frame of image content (i.e., image content 1). The same principle applies to the second row to the i-1th row.

[0130] like Figure 6 , the display driver chip receives Hsync i at time T3. Since Hsync i does not include indication information, HSS is used in the figure. The display driver chip determines that the i-th row needs to be refreshed, so it receives the image data corresponding to the row, that is, the i-th LGP. After receiving the i-th LGP, the display driver chip writes the image data in the i-th LGP into the pixels of the i-th row of the display panel. The same principle applies to the i-th row to the last row.

[0131] Therefore, the first to i-1th rows on the display panel retain the image data of the previous frame, and the i-th to n-th rows are refreshed as the image data of the next frame, that is, partial refresh of the display screen.

[0132] Optionally, there are other variations of the first solution. For example, Figure 6 In the example, Vsync may not include indication information, that is, there is no need to indicate a partial refresh of the next frame of image content (i.e., image content 2). The display driver chip can determine whether the current row needs to be refreshed based on the indication information in Hsync. For another example, Vsync does not include indication information (indication information indicating a partial refresh of the next frame), but carries the indication information in other signals, such as in a certain Hsync during the blanking period; or, during the blanking period, in addition to Vsync and Hsync, the on-chip system also sends a DSI instruction to the display driver chip. The DSI instruction may be a command prompt (command, CMD). The DSI instruction may be located at any position within the blanking period, and the instruction includes indication information for indicating a partial refresh of the next frame.

[0133] Second option

[0134] The system on chip sends a DSI instruction to the display driver chip, and the DSI instruction may include a refresh start row and a refresh end row. For example, the refresh start row is the i-th row, and the refresh end row is the n-th row (the last row). Optionally, the DSI instruction may be CMD. Therefore, the display driver chip may determine which rows need to be refreshed through the DSI instruction.

[0135] For example, see Figure 7 , is a signal diagram between the system on chip and the display driver chip in the second solution.

[0136] like Figure 7 , the display driver chip receives CMD at time T0. CMD includes a refresh start line and a refresh end line. For example, the refresh start line is the i-th line, and the refresh end line is the n-th line (the last line). Optional, Figure 7 In the embodiment, the T0 moment is within the blanking period of the display panel. For the blanking period of the display panel, please refer to the above description. Optionally, the T0 moment can be any moment within the blanking period. Alternatively, the T0 moment can be the moment before the Vsync signal arrives within the blanking period, that is, Figure 7 , time T0 is before time T1 (the time when the Vsync signal arrives).

[0137] like Figure 7 , the display driver chip receives Vsync at time T1. When the display driver chip receives Vsync, it starts counting from zero, and each time it receives an Hsync, the count increases by 1. When the count reaches K, the current blanking area ends and enters the display valid data area, that is, the next Hsync is the Hsync of the first line. Figure 7 Take K=6 as an example, that is, after the display driver chip receives Vsync, it receives 6 Hsyncs, and the count reaches K. Optionally, the value of K is fixed and pre-set.

[0138] like Figure 7 , the display area receives Hsync1 at time T2. At this time, the counter continues to count, and the count reaches K+1. Since the count has not reached the K+ith row, the display determines that the first row will not be refreshed, and the display driver chip will not receive the image data of the first row, thereby reducing transmission power consumption. Moreover, the display driver chip will not write new image data into the pixels of the first row of the display panel. In other words, the pixels of the first row still retain the image data of the first row of the previous frame of image content (i.e., image content 1), thereby reducing refresh power consumption. The same principle applies to the second row to the i-1th row.

[0139] like Figure 7 , the display driver chip receives Hsync i at T3. At this time, the counter count reaches K+i, and the display driver chip determines that the i-th row needs to be refreshed, so the display driver chip receives the image data corresponding to the row, that is, the i-th LGP. After the display driver chip receives the i-th LGP, it writes the image data in the i-th LGP into the pixels of the i-th row of the display panel. The same principle applies to the i+1th row to the last n rows.

[0140] Therefore, the first to i-1th rows on the display panel retain the image data of the previous frame, and the i-th to n-th rows are refreshed as the image data of the next frame, that is, partial refresh of the display screen.

[0141] Optionally, there are other variations of the second solution.

[0142] For example, Figure 7 In the example, CMD is sent before Vsync. Optionally, CMD can also be sent after Vsync. If CMD is sent after Vsync, when the display driver chip receives CMD, the counter starts counting from zero. The principle is the same and will not be repeated.

[0143] For another example, Figure 7 In the embodiment, the refresh start row and the refresh end row are not carried in CMD, but in other signals, such as Vsync; or in a certain Hsync in the blanking period; or in any Hsync from Hsync1 to Hsync i-1 in the display valid data area.

[0144] The third option

[0145] The third solution can be understood as a combination of the first and second solutions. Figure 8 , is a signal diagram between the system on chip and the display driver chip under the third solution.

[0146] like Figure 8 , the display driver chip receives CMD at time T0. CMD includes the refresh start row and the refresh end row. For example, the refresh start row is the i-th row, and the refresh end row is the n-th row (i.e. the second solution). The display driver chip receives Vsync at time T1. Vsync includes indication information (so VSS* is used in the figure) to indicate that the next frame of image content (i.e. image content 2) is partially refreshed. When the display driver chip receives Vsync, the counter starts counting from zero, and the count increases by 1 for each Hsync received.

[0147] like Figure 8 , the display driver chip receives Hsync 1 at time T2, and Hsync 1 includes indication information for indicating that the current row is not refreshed. Moreover, the counter counts to 1. On the one hand, the display driver chip can determine that the first row is not refreshed according to Hsync 1. On the other hand, since the count of the counter has not reached K+i, the display driver chip determines that the first row is not refreshed. This method has a relatively high accuracy. When the display driver chip determines that the first row is not refreshed, it can not receive the image data corresponding to the first row, thereby reducing transmission power consumption. The same principle applies to the second row to the i-1th row.

[0148] like Figure 8 , the display driver chip receives Hsync i at time T3, which does not include indication information, that is, the current row is refreshed, so HSS is used to represent it. Moreover, the counter count reaches K+i, and it is determined that the row is the refresh start row and needs to be refreshed. The display driver chip receives the image data corresponding to the row, that is, the i-th LGP. After the display driver chip receives the i-th LGP, it writes the image data in the i-th LGP into the pixels of the i-th row of the display panel. The same principle applies to the i+1th row to the last row.

[0149] Therefore, the first to i-1th rows on the display panel retain the image data of the previous frame, and the i-th to n-th rows are refreshed as the image data of the next frame, that is, partial refresh of the display screen.

[0150] The embodiment of the present application also provides a display panel, which can achieve partial refresh under the control of a display driver chip.

[0151] like Fig. 9 The display panel includes a pixel transistor array (or pixel array), a row scanning circuit (GOA) and a column scanning circuit. The pixel transistor array includes n rows of pixel transistors, where n is a positive integer, and each row may include multiple pixel transistors. The row scanning circuit includes n circuits, each of which is used to control the pixel transistors of a row. For example, circuit 1 is used to control the on or off of the pixel transistors of the first row, circuit 2 is used to control the on or off of the pixel transistors of the second row, and so on. Taking circuit 1 as an example, a possible implementation method is as follows: Fig. 9 , the voltage signal output by circuit 1 is the gate voltage of all pixel transistors in the first row. The voltage signal can control the opening or closing of all pixel transistors in the first row. For example, when the voltage signal output by circuit 1 is in a low voltage (or low level) state, all pixel transistors in the first row are turned off, so that each pixel transistor in the first row is in a non-writable state. For another example, when the voltage signal output by circuit 1 is in a high voltage (or high level) state, all pixel transistors in the first row are turned on, so that each pixel transistor in the first row is in a writable state. When each pixel transistor in the first row is in a writable state, the column scanning circuit can write the image data of the first row in the column buffer in the display driver chip into the pixel transistor in the first row. The first row is taken as an example here, and the same principle applies to other rows.

[0152] Therefore, in the embodiment of the present application, if you want to control a row (for example, the first row) on the display panel to be refreshed, you only need to control the output voltage signal of the circuit (for example, circuit 1) corresponding to the row (for example, the first row) in the row scanning circuit to be in a high voltage state. If you want to control a row (for example, the first row) on the display panel not to be refreshed, you only need to control the output voltage signal of the circuit (for example, circuit 1) corresponding to the row (for example, the first row) in the row scanning circuit to be in a low voltage state. In the embodiment of the present application, the display driver chip can control the output voltage signal of each circuit in the circuit 1 to the circuit n in the row scanning circuit. When the display driver chip determines that a row (for example, the first row) needs to be refreshed, the output voltage signal of the circuit (for example, circuit 1) corresponding to the row (for example, the first row) in the column scanning circuit is controlled to be a high voltage signal. When the display driver chip determines that a row (for example, the first row) does not need to be refreshed, the output voltage signal of the circuit (for example, circuit 1) corresponding to the row (for example, the first row) in the column scanning circuit is controlled to be a low voltage signal.

[0153] For ease of understanding, Fig. 9 In the example, the first row does not need to be refreshed, while the second and third rows need to be refreshed.

[0154] like Fig. 9 When the display driver chip determines that the first row does not need to be refreshed (for example, it can be determined according to any of the three previous solutions), the output voltage signal of the circuit 1 in the GOA can be controlled to be a low voltage signal, so that the pixel transistors of the first row are turned off and are in a non-writable state. Moreover, the display driver chip will not receive the image data of the first row, nor will it write the image data of the first row into the line buffer. Therefore, the first row retains the image data of the previous frame.

[0155] like Fig. 9 When the display driver chip determines that the second row needs to be refreshed (for example, it can be determined according to any of the three previous solutions), the output voltage signal of the circuit 2 in the GOA can be controlled to be a high voltage signal, so that the pixel transistors of the second row are turned on and are in a writable state. Moreover, after receiving the image data of the second row, the display driver chip writes the image data into the line buffer. The column scanning circuit writes the image data of the second row in the line buffer into the pixel transistors of the second row of the display panel.

[0156] like Fig. 9When the display driver chip determines that the third row needs to be refreshed (for example, it can be determined according to any of the three previous solutions), the output voltage signal of the circuit 3 in the GOA can be controlled to be a high voltage signal, so that the pixel transistors of the third row are turned on and are in a writable state. Moreover, after receiving the image data of the third row, the display driver chip writes the image data into the line buffer. The column scanning circuit writes the image data of the third row in the line buffer into the pixel transistors of the third row of the display panel.

[0157] In the embodiment of the present application, the structure of the circuits in each row of the GOA is the same, for example, Fig. 9 In the embodiment, the structures of circuit 1, circuit 2, circuit 3, circuit 4, etc. are the same. The embodiment of the present application provides two structures. The first structure is Fig.10 The structure of (a) in GOA is Fig.10 The second structure is Fig.12 The structure of (a) in GOA is Fig.12 The principle of the first structure is first described below, and then the principle of the second structure is described below.

[0158] 1. The circuit of each row in GOA is Fig.10 In the structure (a), the principles of not refreshing the first row, refreshing the second row, and refreshing the third row are as follows:

[0159] (1) The first row is not refreshed.

[0160] like Fig.10 (a) is a schematic diagram of the structure of circuit 1. Circuit 1 includes multiple transistors. For the convenience of distinction, each transistor is marked, for example, T1 to T12. Circuit 1 is Fig.10 Gout connection in (a) Fig.10 In (b), Gout[1], since the first row does not need to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 1 to be a low-level signal, so Gout[1] is a low-level signal, so the pixel transistors of the first row are turned off, as shown in FIG. Fig.10 (b) in .

[0161] It should be noted that if Fig.10In (a), compared with conventional circuits, the circuit 1 provided in the embodiment of the present application adds a T7 transistor and introduces a second pull-up point PU2. The output (Gout[1]) of the circuit 1 can be controlled by a reference voltage (Voltage Reference, VREF) without affecting the row-by-row transmission of the original input signal. Moreover, the circuit 1 provided in the embodiment of the present application adds a T8 transistor to ensure that the PU2 point is at a low potential when the timing is not transmitted to the row, ensuring that the T9 transistor is in the off state.

[0162] In the embodiment of the present application, since the circuit 1 corresponds to the first row of pixel transistors, the input of the circuit 1 is a default signal, for example, it can be an STV signal or just a default high level signal (VGH).

[0163] As mentioned above, since the first row is not refreshed, the display driver chip requires the output of control circuit 1 (Gout[1]) to be a low level signal (VGL). Fig.11 (a) is a signal diagram of input[1], CK[1], PU[1], Out[1], VREF[1], and Gout[1] of circuit 1. In the embodiment of the present application, the output (Gout[1]) of circuit 1 can be controlled to be VGL through VERF[1] and CK[1]. It should be noted that, as mentioned above, each row of the circuit is Fig.10 In the structure of (a), this paper uses [1] to indicate that the circuit 1 in the first row adopts Fig.10 In the structure of (a), the ports in circuit 1 are indicated by [2], which indicates that circuit 2 in the second row adopts Fig.10 In the structure of (a), the ports in circuit 2 are similarly represented by [3], which indicates that circuit 3 in the third row adopts Fig.10 When the structure is (a) in, each port in circuit 3, and so on.

[0164] like Fig.11 In (a), at time T1, input[1] is VGH. Therefore, T1 in circuit 1 is turned on, so PU is at a high level, so Fig.11 In (a), PU[1] is in the high level state at time T1. When PU[1] is in the high level state, T5 and T7 are both turned on. After T5 is turned on, the level of Out[1] is determined by CK[1]. Fig.11 In (a), since CK[1] is low at T1, Out[1] is low at T1. After T7 is turned on, the level of VREF determines whether T9 is turned on. Since VREF is low at T1, T9 is not turned on, so Gout[1] is low. Fig.11In (a), Gout[1] is in a low level state at time T1. It should be noted that at time T1, the left end of capacitor C1 is VGH and the right end is CK[1]. Since CK[1] is VGL at time T1, the capacitance difference between the left and right ends of capacitor C1 is VGH-VGL at time T1.

[0165] like Fig.11 In (a), at time T2, input [1] is VGL, so T1 is not conducting, the potential of point PU is in a suspended state, and the left electrode of capacitor C1 retains the original voltage VGH at time T1, so, Fig.11 In (a), at T2, PU[1] is at a high level, so T5 and T7 remain turned on. T5 is turned on, so the level of Out[1] is determined by CK[1]. Since CK[1] is at a high level at T2, Out[1] is at a high level at T2. After T7 is turned on, the level of VREF determines whether T9 is turned on. Since VREF is at a low level at T2, T9 is not turned on, so the output of Gout[1] is at a low level. It should be noted that at T2, CK[1] at the right end of capacitor C1 switches to VGH, and since the capacitance difference between the left and right ends of capacitor C1 at T1 is VGH-VGL, due to the capacitor bootstrap principle, the voltage difference between the two ends of capacitor C1 will not change suddenly, so at T2, the voltage difference between the left and right ends of capacitor C1 needs to be maintained at VGH-VGL. Because CK[1] at the right end of capacitor C1 is switched to VGH at time T2, in order to ensure that the capacitance difference between the left and right ends of capacitor C1 remains at VGH-VGL, the voltage at the left end of capacitor C1 is adjusted to 2VGH-VGL. Fig.11 In (a), the level signal of PU[1] at time T2 is (2VGH-VGL) / VGH≈3 times the level signal at time T1 (because VGL=-VGH, for example, VGH=9v, VGL=-9v). At time T2, since the voltage at the right end of capacitor C1 switches to VGH, Out[1] is at a high level.

[0166] Therefore, at time T2, since Gout[1] of circuit 1 is a low level signal, Fig.10 In (b), the pixel transistors in the first row are in the off state, so the pixel transistors in the first row are not refreshed.

[0167] In addition, it should be noted that at time T2, Out[1] is at a high level, serving as the input (input[2]) signal of circuit 2.

[0168] (2) The second row is refreshed.

[0169] like Fig.10(a) is a schematic diagram of the structure of circuit 2. It should be noted that in the embodiment of the present application, each circuit in circuit 1 to circuit n may have the same structure. Fig.10 In (a), circuit 2 includes a plurality of transistors. For the convenience of distinction, each transistor is marked, for example, T1 to T12. Circuit 2 is Fig.10 Gout connection in (a) Fig.10 In (b), Gout[2], since the second row needs to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 2 to be a high-level signal, so Gout[2] is a high-level signal, so the pixel transistors of the second row are turned on, as shown in FIG. Fig.10 (b) in .

[0170] In the embodiment of the present application, the input (input[2]) of circuit 2 may be Out[1] of the previous row.

[0171] As mentioned above, since the second row is refreshed, the display driver chip requires the output (Gout[2]) of control circuit 2 to be a high level signal (VGH). Fig.11 (b) is a signal diagram of input[2], CK[2], PU[2], Out[2], VREF[2], and Gout[2] of circuit 2. In the embodiment of the present application, the output (Gout[2]) of circuit 2 can be controlled to be VGH through VERF[2] and CK[2].

[0172] like Fig.11 In (b), at time T2, input[2] is VGH (because Out[1] of the previous row is VGH at time T2). Therefore, T1 in circuit 2 is turned on, so PU is at a high level, corresponding to Fig.11 In (b), PU[2] is VGH at T2. When PU is at a high level, T5 and T7 are both turned on. After T5 is turned on, the level of Out[2] is determined by CK[2]. Since CK[2] is at a low level at T2, Out[2] is at a low level at T2. After T7 is turned on, the level of VREF determines whether T9 is turned on. Since VREF is at a low level at T2, T9 is not turned on, so the output of Gout[2] is at a low level. It should be noted that at T2, the left end of capacitor C1 is VGH and the right end is CK[2]. Since CK[2] is VGL at T2, the capacitance difference between the two ends of capacitor C1 is VGH-VGL at T2.

[0173] like Fig.11In (b), at time T3, input [2] is VGL, so T1 is not conducting, the potential of point PU is in a suspended state, and the left electrode of capacitor C1 retains the original voltage VGH at time T2, so, Fig.11 In (b), at time T3, since PU[2] is at a high level, T5 and T7 remain on. Since T5 is on, the level of Out[2] is determined by CK[2]. Since CK[2] is at a high level at T3, Out[2] is at a high level at T3. Since T7 is on, the level of VREF determines whether T9 is on. Since VREF is at a high level at T3, T9 is on. Therefore, the level of Gout[2] is determined by CK[2]. Since CK[2] is at a high level at T3, Gout[2] is at a high level.

[0174] It should be noted that at time T3, CK[2] at the right end of capacitor C1 is switched to VGH. Since the capacitance difference between the left and right ends of capacitor C1 is VGH-VGL at time T2, the voltage difference between the two ends of capacitor C1 does not change suddenly due to the capacitor bootstrap principle. Therefore, at time T3, the voltage difference between the left and right ends of capacitor C1 needs to be maintained at VGH-VGL. Because CK[2] at the right end of capacitor C1 is switched to VGH at time T3, in order to ensure that the capacitance difference between the left and right ends of capacitor C1 remains at VGH-VGL, the voltage at the left end of capacitor C1 is adjusted to 2VGH-VGL. Therefore, Fig.11 In (b), the level signal of PU[2] at time T3 is (2VGH-VGL) / VGH≈3 times the level signal at time T2. Since the voltage at the right end of capacitor C1 is switched to VGH at time T3, Out[2] is at a high level.

[0175] Therefore, at time T3, since Gout[2] of circuit 2 is a high level signal, Fig.10 In (b), the pixel transistors in the second row are in the on state, so the pixel transistors in the second row are refreshed.

[0176] In addition, it should be noted that at time T3, Out[2] is at a high level, serving as the input (input[3]) signal of circuit 3.

[0177] (3) The third row is refreshed.

[0178] like Fig.10 (a) is a schematic diagram of the structure of circuit 3. It should be noted that in the embodiment of the present application, each circuit in circuit 1 to circuit n may have the same structure. Fig.10 In (a), the circuit 3 includes a plurality of transistors. For the convenience of distinction, each transistor is marked, for example, T1 to T12. Fig.10 Gout connection in (a) Fig.10 In (b), Gout[3], since the third row needs to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 3 to be a high-level signal, so Gout[3] is a high-level signal, so the pixel transistors of the third row are turned on, as shown in FIG. Fig.10 (b) in .

[0179] In the embodiment of the present application, the input (input[3]) of circuit 3 may be Out[2] of the previous row.

[0180] As mentioned above, since the third row is refreshed, the display driver chip requires the output (Gout[3]) of the control circuit 3 to be a high level signal (VGH). Fig.11 (c) in FIG. 1 is a signal diagram of input[3], CK[3], PU[3], Out[3], VREF[3], and Gout[3] of circuit 3. In the embodiment of the present application, the output (Gout[3]) of circuit 3 can be controlled to be VGH through VERF[3] and CK[3]. It should be noted that the principle of refreshing the third row is the same as that of refreshing the second row, and for the sake of brevity of the specification, it will not be repeated.

[0181] 2. The circuit of each row in GOA is Fig.12 In the structure (a), the principles of not refreshing the first row, refreshing the second row, and refreshing the third row are as follows:

[0182] (1) The first row is not refreshed.

[0183] like Fig.12 (a) is a schematic diagram of the structure of circuit 1. Circuit 1 includes multiple transistors. For the convenience of distinction, each transistor is marked, for example, T1 to T10. Circuit 1 is Fig.12 Gout connection in (a) Fig.12 In (b), Gout[1], since the first row does not need to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 1 to be a low-level signal, so Gout[1] is a low-level signal, so the pixel transistors of the first row are turned off, as shown in FIG. Fig.12 (b) in .

[0184] In the embodiment of the present application, the circuit 1 is Fig.12 The input of (a) is a default one, for example, it can be an STV signal or just a default VGH.

[0185] As mentioned above, since the first row is not refreshed, the display driver chip requires the output of control circuit 1 (Gout[1]) to be a low level signal (VGL). Fig.13(a) is a signal diagram of input[1], CK[1], Out[1], VREF[1], and Gout[1] of circuit 1. In the embodiment of the present application, the output (Gout[1]) of circuit 1 can be controlled to be VGL through VERF[1] and CK[1]. It should be noted that, as mentioned above, each row of the circuit is Fig.12 In the structure of (a), this paper uses [1] to indicate that the circuit 1 in the first row adopts Fig.12 In the structure of (a), the ports in circuit 1 are indicated by [2], which indicates that circuit 2 in the second row adopts Fig.12 In the structure of (a), the ports in circuit 2 are similarly represented by [3], which indicates that circuit 3 in the third row adopts Fig.12 When the structure is (a) in, each port in circuit 3, and so on.

[0186] like Fig.13 In (a), at time T1, input[1] is VGH, so PU is VGH, so transistors 5 and 7 are turned on. After transistor 7 is turned on, whether PU2 is VGH or VGL is determined by VREF[1] at time T1. Fig.13 In (a), VREF[1] at time T1 is VGL, so PU2 is VGL. In this case, transistor 9 is not conducting, so Gout[1] is VGL. Since transistor 5 is conducting, whether Out[1] at time T1 is VGL or VGH is determined by CK[1] at time T1. Since CK[1] at time T1 is VGL, Out[1] at time T1 is VGL.

[0187] like Fig.13 In (a), at time T2, input[1] is VGL, so T1 is not conducting, the potential of point PU is in a floating state, PU is VGH, so transistors 5 and 7 are conducting. After transistor 7 is turned on, whether PU2 is VGH or VGL is determined by VREF[1] at time T2. Fig.13 In (a), VREF[1] at time T2 is VGL, so PU2 is VGL. In this case, transistor 9 is not turned on, so Gout[1] at time T2 is VGL. Since transistor 5 is turned on, whether Out[1] at time T2 is VGL or VGH is determined by CK[1] at time T2. Since CK[1] at time T2 is VGH, Out[1] at time T2 is VGH.

[0188] Therefore, at time T2, since Gout[1] of circuit 1 is a low level signal, Fig.12 In (b), the pixel transistors in the first row are in the off state, so the pixel transistors in the first row are not refreshed.

[0189] In addition, it should be noted that at time T2, Out[1] is VGH, which serves as the input (input[2]) signal of circuit 2.

[0190] (2) The second row is refreshed.

[0191] like Fig.12 (a) is the schematic diagram of the structure of circuit 2. Circuit 2 is Fig.12 Gout connection in (a) Fig.12 In (b), Gout[2], since the second row needs to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 2 to be a high-level signal, so Gout[2] is a high-level signal, so the pixel transistors of the second row are turned on, as shown in FIG. Fig.12 (b) in .

[0192] In the embodiment of the present application, the input (input[2]) of circuit 2 may be Out[1] of the previous row.

[0193] As mentioned above, since the second row is refreshed, the display driver chip requires the output (Gout[2]) of control circuit 2 to be a high level signal (VGH). Fig.13 (b) is a signal diagram of input[2], CK[2], Out[2], VREF[2], and Gout[2] of circuit 2. In the embodiment of the present application, the output (Gout[2]) of circuit 2 can be controlled to be VGH through VERF[2] and CK[2].

[0194] like Fig.13 In (b), at time T2, the input[2] of circuit 2 is the Out[1] of circuit 1 at time T2. Since Out[1] at time T2 is VGH, the input[2] of circuit 2 is VGH at time T2. Therefore, transistors 5 and 7 are turned on. After transistor 7 is turned on, whether PU2 is VGH or VGL is determined by VREF[2] at time T2. Fig.13 In (b), VREF[2] at time T2 is VGH, so PU2 is VGH, transistor 9 is turned on, and the level of Gout[2] is CK[2] at time T2. Fig.13 In (b), CK[2] at time T2 is VGL, so Gout[2] at time T2 is VGL. It should be noted that, since a capacitor is provided between PU2 and Gout[2], at time T2, the left end of the capacitor is PU2 node VGH, and the right end is VGL, that is, the voltage difference between the left and right ends is VGH-VGL.

[0195] At time T3, input[2] of circuit 2 is VGL, so T1 is not conducting, the potential of point PU is in a floating state, PU is VGH, and transistors 5 and 7 are conducting. After transistor 7 is conducting, whether PU2 is VGH or VGL is determined by VREF[2] at time T3. Fig.13 In (b), VREF[2] at time T3 is VGH, so PU2 is VGH. In this case, transistor 9 is turned on, so the level of Gout[2] is CK[2] at time T3. Fig.13 In (b), CK[2] at T3 is VGH, so Gout[2] at T3 is VGH. It should be noted that since a capacitor is set between PU2 and Gout[2], and at T2, the voltage difference across the capacitor has reached VGH-VGL. Due to the bootstrap characteristics of the capacitor, the voltage difference across the capacitor cannot change suddenly. Therefore, at T3, when the right end of the capacitor is switched to VGH, PU2 at the left end of the capacitor is adjusted to 2VGH-VGL, so as to ensure that the voltage difference across the capacitor does not change suddenly.

[0196] In addition, after transistor 5 is turned on, whether Out[2] is VGL or VGH is determined by CK[1]. Since CK[2] is VGH at time T3, Out[2] is VGH at time T3.

[0197] Therefore, at time T3, since Gout[2] of circuit 2 is a high level signal, Fig.12 In (b), the pixel transistors in the second row are in the off state, so the pixel transistors in the second row are not refreshed.

[0198] In addition, it should be noted that at time T3, Out[2] is VGH, which serves as the input (input[3]) signal of circuit 3.

[0199] (3) The third row is refreshed.

[0200] like Fig.12 (a) is a schematic diagram of the structure of circuit 3. Circuit 3 is Fig.12 Gout connection in (a) Fig.12 In (b), Gout[3], since the third row needs to be refreshed, the display driver chip needs the voltage signal of the output (Gout) of the control circuit 3 to be a high-level signal, so Gout[3] is a high-level signal, so the pixel transistors of the third row are turned on, as shown in FIG. Fig.12 (b) in .

[0201] In the embodiment of the present application, the input (input[3]) of circuit 3 may be Out[2] of the previous row.

[0202] As mentioned above, since the third row is refreshed, the display driver chip requires the output (Gout[3]) of the control circuit 3 to be a high level signal (VGH). Fig.13 (c) is a signal diagram of input[3], CK[3], Out[3], VREF[3], and Gout[3] of circuit 3. In the embodiment of the present application, the output (Gout[3]) of circuit 3 can be controlled to be VGH through VERF[3] and CK[3]. The specific implementation principle is the same as the principle of the second row, and for the sake of brevity of the specification, it will not be repeated.

[0203] Optional, Fig.12 In (a), the capacitor at T5 may or may not be present, which is not limited in the embodiment of the present application.

[0204] In the above embodiment, the GOA is set to the short side of the display panel as an example. Fig. 9 As shown, GOA is located on the short side of the tablet, i.e. Fig.14 (a) in Figure 1. In this setting, when the display panel is refreshed, each line is parallel to the long side and perpendicular to the short side. Suppose a user opens an application and displays the interface of the application in landscape mode, such as Fig.14 In (a), the upper area of ​​the display panel may be refreshed, while the lower area may not be refreshed, or the lower area may be refreshed, while the upper area may not be refreshed (not shown in the figure), etc. If the user displays the interface of the application in portrait mode, such as Fig.14 In (b), the left area of ​​the display panel can be refreshed, while the right area is not refreshed (not shown in the figure), or the right area is refreshed, while the left area is not refreshed, and so on.

[0205] Optionally, the GOA may also be located on the long side of the tablet, i.e. Fig.15 (a) in Figure 1. In this setting, when the display panel is refreshed, each line is parallel to the short side and perpendicular to the long side. Suppose a user opens an application and displays the interface of the application in landscape mode, such as Fig.15 In (a), the left area of ​​the display panel may be refreshed, but the right area may not be refreshed (not shown in the figure), or the right area may be refreshed, but the left area may not be refreshed, etc. If the user displays the interface of the application in portrait mode, such as Fig.15 In (b), the upper area of ​​the display panel may be refreshed, while the lower area may not be refreshed (not shown in the figure), or the lower area may be refreshed, while the upper area may not be refreshed, and so on.

[0206] It should be noted that the display panel provided in the embodiment of the present application can be applicable to Command Mode or Video Mode.

[0207] Fig.16FIG. 1 is a schematic diagram showing the hardware structure of an electronic device. Fig.16 As shown, the electronic device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0208] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), a GUI signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Among them, different processing units may be independent devices or integrated into one or more processors. Among them, the controller may be the nerve center and command center of the electronic device. The controller may generate an operation control signal according to the instruction opcode and the timing signal to complete the control of fetching and executing instructions. A memory may also be set in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a high-speed cache memory. The memory may store instructions or data that the processor 110 has just used or circulated. If the processor 110 needs to use the instruction or data again, it can be directly called from the memory. Repeated access is avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved.

[0209] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0210] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple groups of I2C buses. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 193, etc. through different I2C bus interfaces. For example, the processor 110 may be coupled to the touch sensor 180K through the I2C interface, so that the processor 110 communicates with the touch sensor 180K through the I2C bus interface to realize the touch function of the electronic device.

[0211] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to achieve communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 via the I2S interface to achieve the function of answering a call through a Bluetooth headset.

[0212] The PCM interface can also be used for audio communication, sampling, quantizing and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface to realize the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0213] The UART interface is a universal serial data bus for asynchronous communication. The bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is generally used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 through the UART interface to implement the Bluetooth function. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 through the UART interface to implement the function of playing music through a Bluetooth headset.

[0214] The MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to realize the shooting function of the electronic device. The processor 110 and the display screen 194 communicate via the DSI interface to realize the display function of the electronic device.

[0215] The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0216] The USB interface 130 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge an electronic device, and can also be used to transfer data between an electronic device and a peripheral device. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

[0217] It is understandable that the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0218] The wireless communication function of the electronic device can be implemented by antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modulation and demodulation processor and baseband processor. Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antenna. For example, antenna 1 can be reused as a diversity antenna of a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0219] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to electronic devices. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0220] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to electronic devices. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0221] In some embodiments, antenna 1 of the electronic device is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, so that the electronic device can communicate with the network and other devices through wireless communication technology.

[0222] The display screen 194 is used to display the display interface of the application, etc. The display screen 194 includes a display panel. In some embodiments, the electronic device may include one or more display screens 194.

[0223] The electronic device can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor, etc. Among them, ISP is used to process the data fed back by camera 193.

[0224] The internal memory 121 can be used to store computer executable program codes, which include instructions. The processor 110 executes various functional applications and data processing of the electronic device by running the instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, and the software code of at least one application program, etc. The data storage area can store data (such as GUI, video, etc.) generated during the use of the electronic device, etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash memory, etc.

[0225] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as pictures and videos are stored in the external memory card.

[0226] The electronic device can implement audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0227] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be arranged in the processor 110, or some functional modules of the audio module 170 can be arranged in the processor 110.

[0228] The speaker 170A, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device can listen to music or listen to external scenarios such as hands-free calls through one or more speakers 170A.

[0229] The receiver 170B, also called a "earpiece", may be one or more and is used to convert an audio electrical signal into a sound signal. When the electronic device receives a call or voice message, the voice can be received by placing the receiver 170B close to the human ear.

[0230] Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals.

[0231] The earphone jack 170D is used to connect a wired earphone.

[0232] The pressure sensor 180A is used to sense the pressure signal and can convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A can be disposed on the display screen 194 .

[0233] The gyro sensor 180B can be used to determine the motion posture of the electronic device. In some embodiments, the angular velocity of the electronic device around three axes (i.e., x, y, and z axes) can be determined by the gyro sensor 180B. The gyro sensor 180B can be used for anti-shake shooting.

[0234] The air pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device calculates the altitude through the air pressure value measured by the air pressure sensor 180C to assist positioning and navigation.

[0235] The magnetic sensor 180D includes a Hall sensor. For example, the electronic device can use the magnetic sensor 180D to detect the opening and closing of the flip leather case.

[0236] The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device in various directions (generally three axes), and can detect the magnitude and direction of gravity when the electronic device is stationary.

[0237] Distance sensor 180F, used to measure distance. Electronic devices can measure distance through infrared or laser.

[0238] The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device emits infrared light outward through the light emitting diode. The electronic device uses the photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device. When insufficient reflected light is detected, the electronic device can determine that there is no object near the electronic device.

[0239] The ambient light sensor 180L is used to sense the brightness of the ambient light. The electronic device can adaptively adjust the brightness of the display screen 194 according to the sensed brightness of the ambient light.

[0240] The fingerprint sensor 180H is used to collect fingerprints.

[0241] The temperature sensor 180J is used to detect the temperature.

[0242] The touch sensor 180K is also called a "touch panel". The touch sensor 180K can be set on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen". The touch sensor 180K is used to detect a touch operation on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.

[0243] The bone conduction sensor 180M can obtain a vibration signal. In some embodiments, the bone conduction sensor 180M can obtain a vibration signal of a vibrating bone block of a human vocal part.

[0244] The button 190 includes a power button, a volume button, etc. The button 190 can be a mechanical button. It can also be a touch button. The electronic device can receive the button input and generate a key signal input related to the user settings and function control of the electronic device. The motor 191 can generate a vibration prompt. The motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. The indicator 192 can be an indicator light, which can be used to indicate the charging status, power changes, messages, missed calls, notifications, etc. The SIM card interface 195 is used to connect the SIM card. The SIM card can be inserted into the SIM card interface 195, or pulled out from the SIM card interface 195 to achieve contact and separation with the electronic device.

[0245] Understandably, Fig.16 The components shown do not constitute a specific limitation on the electronic device. The electronic device in the embodiment of the present application may include Fig.16 In addition, Fig.16 The combination / connection relationship between the components can also be adjusted and modified.

[0246] Based on the same concept, Fig.17 The electronic device 1700 provided by the present application is shown. The electronic device 1700 may be the tablet computer mentioned above. Fig.17As shown, the electronic device 1700 may include: one or more processors 1701; one or more memories 1702; a communication interface 1703, and one or more computer programs 1704, and the above-mentioned components may be connected via one or more communication buses 1705. The one or more computer programs 1704 are stored in the above-mentioned memory 1702 and are configured to be executed by the one or more processors 1701, and the one or more computer programs 1704 include instructions, and the above-mentioned instructions may be used to execute the relevant steps of the tablet computer in the above corresponding embodiments. The communication interface 1703 is used to realize communication with other devices, for example, the communication interface may be a transceiver.

[0247] In the embodiments provided by the present application, the method provided by the embodiments of the present application is introduced from the perspective of an electronic device (such as a tablet computer) as an execution subject. In order to implement the functions in the method provided by the embodiments of the present application, the electronic device may include a hardware structure and / or a software module, and the functions are implemented in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether a function of the above functions is executed in the form of a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.

[0248] As used in the above embodiments, the term "when..." or "after..." may be interpreted to mean "if..." or "after..." or "in response to determining..." or "in response to detecting...", depending on the context. Similarly, the phrase "when determining..." or "if (the stated condition or event) is detected" may be interpreted to mean "if determining..." or "in response to determining..." or "when (the stated condition or event) is detected" or "in response to detecting (the stated condition or event)", depending on the context. In addition, in the above embodiments, relational terms such as first and second are used to distinguish one entity from another, without limiting any actual relationship and order between the entities.

[0249] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0250] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc. In the absence of conflict, the solutions of the above embodiments can be used in combination.

[0251] Note: A portion of this patent application document contains material which is subject to copyright protection. The copyright owner reserves all rights reserved except for the production of copies of the material in the patent file or patent record in the Patent Office.

Claims

1. A method for partially refreshing a display panel, characterized in that: The method is applied to a display driver chip, wherein the display driver chip is connected to a system on chip and a display panel respectively, wherein the system on chip includes a first image to be refreshed, and only a part of the area on the first image needs to be updated, and the display panel includes n rows of pixels, where n is a positive integer. The method includes: The display driver chip determines, according to the instruction of the system on chip, that the i-th row on the first image needs to be refreshed, the i-th row is located in the partial area, and i is a positive integer; The display driver chip writes the i-th row of image data sent by the on-chip system into the i-th row of pixels of the display panel, wherein the i-th row of image data is the i-th row of image data in the partial area.

2. The method according to claim 1, characterized in that The display driver chip determines, according to the instruction of the system on chip, that the i-th row on the first image needs to be refreshed, including: The display driver chip receives first indication information sent by the system on chip, wherein the first indication information is used to indicate a refresh start line and a refresh end line, wherein the refresh start line corresponds to a start line of the partial area, and the refresh end line corresponds to an end line of the partial area.

3. The method according to claim 2, characterized in that The first indication information is carried in a frame synchronization signal or a command prompt CMD.

4. The method according to claim 3, characterized in that The first indication information is carried in the CMD, and the display driver chip receives the first indication information sent by the system on chip, including: The display driver chip receives first indication information sent by the system on chip at time T1; The time T1 is within the blanking period and before the time T2. The time T2 is the receiving time of the frame synchronization signal. The frame synchronization signal is used to achieve frame synchronization between the display driver chip and the display panel.

5. The method according to claim 4, characterized in that Before the display driver chip writes the i-th row of image data sent by the system on chip into the i-th row of pixels of the display panel, the method further includes: The display driver chip receives the frame synchronization signal at the time T2; The display driver chip starts counting the counter, and each time a horizontal synchronization signal is received, the counter counts by 1; The display driver chip receives a horizontal synchronization signal at time T3, and the count of the counter reaches K+i; The display driver chip determines that the row synchronization signal received at time T3 is the row synchronization signal of the i-th row; The display driver chip establishes clock synchronization with the i-th row of pixels on the display panel according to the row synchronization signal of the i-th row; Wherein, K is the number of line synchronization signals received by the display driver chip during the period from time T2 to time T4, time T4 is the start time of transmission of the first line of image data in the first image, and time T4 is earlier than or equal to time T3.

6. The method according to claim 5, characterized in that The method further comprises: Before the time T3, the display driver chip does not receive image data from the system on chip.

7. The method according to claim 1, characterized in that The display driver chip determines, according to the instruction of the system on chip, that the i-th row on the first image needs to be refreshed, including: The display driver chip receives a row synchronization signal of an i-th row sent by the system on chip, wherein the row synchronization signal of the i-th row includes second indication information, and the second indication information is used to indicate a refresh of the row.

8. The method according to any one of claims 1 to 7, characterized in that: Before the display driver chip determines, according to the instruction of the system on chip, that the i-th row on the first image needs to be refreshed, the method further includes: The display driver chip receives third indication information sent by the system on chip, where the third indication information is used to indicate a partial refresh of a next frame of image.

9. The method according to claim 8, characterized in that The third indication information is carried in the frame synchronization signal or CMD.

10. A method for partially refreshing a display panel, characterized in that: Applied to a system on chip, the system on chip is connected to a display driver chip, the system on chip includes a first image to be refreshed, and only a part of the area on the first image needs to be updated, the method includes: The system on chip indicates to the display driver chip that the i-th row on the first image needs to be refreshed, the i-th row is located in the partial area, and i is a positive integer; The system on chip sends the i-th row of image data to the display driver chip, where the i-th row of image data is used to be written into the i-th row of pixels of the display panel, and the i-th row of image data is the i-th row of image data in the partial area.

11. The method according to claim 10, characterized in that The system on chip indicates to the display driver chip that the i-th row on the first image needs to be refreshed, including: The system on chip sends first indication information to the display driver chip, wherein the first indication information is used to indicate a refresh start line and a refresh end line, wherein the refresh start line corresponds to a start line of the partial area, and the refresh end line corresponds to an end line of the partial area.

12. The method according to claim 11, characterized in that The first indication information is carried in a frame synchronization signal or a command prompt CMD.

13. The method according to claim 12, characterized in that The first indication information is carried in the CMD, and the on-chip system sends the first indication information to the display driver chip, including: The system on chip sends first indication information to the display driver chip at time T1; The time T1 is within the blanking period and before the time T2. The time T2 is the sending time of the frame synchronization signal. The frame synchronization signal is used to achieve frame synchronization between the display driver chip and the display panel.

14. The method according to claim 10, characterized in that The system on chip sends the i-th row of image data to the display driver chip, including: The system on chip sends the i-th row of image data to the display driver chip at time T3, and the time T3 is after the time T2, and before the time T3, the system on chip does not send image data to the display driver chip.

15. The method according to claim 10, characterized in that The system on chip indicates to the display driver chip that the i-th row on the first image needs to be refreshed, including: The system on chip sends a row synchronization signal of the i-th row to the display driver chip, wherein the row synchronization signal of the i-th row includes second indication information, and the second indication information is used to indicate a refresh of the row.

16. The method according to any one of claims 10 to 15, characterized in that: Before the system on chip indicates to the display driver chip that the i-th row on the first image needs to be refreshed, the method further includes: The system on chip sends third indication information to the display driver chip, where the third indication information is used to indicate a partial refresh of a next frame of image.

17. The method according to claim 16, characterized in that The third indication information is carried in the frame synchronization signal or CMD.

18. A display panel, characterized in that: include: A pixel array, wherein the pixel array includes n rows of pixels, where n is a positive integer; A column scanning circuit connected to the pixel array and used for writing image data into the pixel array; A row scanning circuit, comprising n control circuits, each of the n control circuits being connected to a row of pixels in the n rows of pixels and used to control the on or off of the row of pixels, the n control circuits comprising a first control circuit, the first control circuit being any one of the n control circuits, the first control circuit comprising: an input module, a control module and an output module, the control module being connected to the input end and the first output module respectively; wherein, The input module is used to input signals; The control module is used to control the output signal according to the reference signal. When the reference signal is a high level signal, the output module is a high level signal, and when the reference signal is a low level signal, the output signal is a low level signal; The first output module is used to output a signal; Among them, when the first output module outputs a high-level signal, the first control circuit controls the pixels of the first row to turn on, the first row is the row corresponding to the first control circuit, and the column scanning circuit writes image data into the pixels of the first row. When the first output module outputs a low-level signal, the first control circuit controls the pixels of the first row to turn off.

19. The display panel according to claim 18, characterized in that: The control module comprises: a first transistor; The gate of the first transistor is connected to the input module; The drain of the first transistor is connected to a reference signal output module, and the reference signal output module is used to input a reference signal to the drain; A source of the first transistor is connected to the first output module.

20. The display panel according to claim 19, characterized in that: The control module further includes: a second transistor; The drain of the second transistor is connected to a clock signal output module, and the clock signal output module is used to output a clock signal; The source of the first transistor is connected to the first output module, comprising: The drain of the first transistor is connected to the gate of the second transistor, and the source of the second transistor is connected to the first output module; Among them, when the first transistor is turned on, if the reference signal input to the drain by the reference signal output module is a high-level signal, the second transistor is turned on, if the clock signal output by the clock signal output module is a high-level signal, then the first output module outputs a high-level signal, and if the clock signal is a low-level signal, then the first output module outputs a low-level signal.

21. The display panel according to claim 20, characterized in that: The control module further includes: a third transistor; The gate of the third transistor is connected to the input module; The drain of the third transistor is connected to the clock signal output module; The source of the third transistor is connected to a second output module, the second output module is connected to an input module of a second control circuit, the second control circuit is used to control the opening or closing of pixels in a second row, and the second row is the next row of the first row.

22. The display panel according to claim 21, characterized in that: A capacitor is included between the gate and the source of the third transistor.

23. The display panel according to claim 20, characterized in that: The control module further includes: a fourth transistor; The gate of the fourth transistor is connected to the power supply VDD; The drain of the fourth transistor is connected to the gate of the second transistor; The source of the fourth transistor is connected to the low level output terminal.

24. A display system architecture, characterized in that: include: System on chip and display driver chip; among them, The display driver chip is used to execute the method according to any one of claims 1 to 9; The system on chip is used to execute the method as claimed in any one of claims 10-17.

25. A display system architecture, characterized in that: include: System on chip, display driver chip, display panel; among them, The display driver chip is used to execute the method according to any one of claims 1 to 9; The system on chip is used to execute the method according to any one of claims 10 to 17; The display panel is the display panel as described in any one of claims 18 to 23.

26. An electronic device, characterized in that: include: The display system architecture as claimed in claim 24 or 25.

27. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and when the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 17.

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