Backward compatible capacitorless dram memory circuit macro construction method and apparatus

Abstract

The application relates to a method and device for constructing a back-compatible capacitorless DRAM storage circuit macro, wherein the method comprises the following steps: constructing a multi-layer capacitorless DRAM storage circuit macro according to a full back-compatible channel material meeting preset preparation requirements; constructing a peripheral circuit based on a back-compatible vertical complementary field effect transistor; constructing a complete multi-layer back-compatible capacitorless DRAM storage circuit macro according to each layer of capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and stacking the complete multi-layer back-compatible capacitorless DRAM storage circuit macro on a target silicon-based circuit based on an interlayer via, so as to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro. Therefore, the problems that the capacitorless DRAM storage circuit macro based on a silicon-based chip manufacturing process has a relatively short overall storage retention time, frequent refreshing and relatively high power consumption due to the relatively high leakage of a silicon transistor, is not conducive to actual application, and a storage peripheral circuit occupies a relatively large area in the entire circuit macro are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitorless DRAM memory devices, and particularly relates to a method and device for constructing a macro of a capacitorless DRAM memory circuit compatible with a back-end process. BACKGROUND

[0002] Traditional dynamic random access memory (DRAM) technology uses one transistor and one capacitor (1T1C) to store one bit of information. The transistor switch is used to control the reading and writing of information, and the capacitor is used to store information. Currently, as devices continue to shrink, there are increasing challenges to process and reliability.

[0003] 2T0C DRAM is composed of two transistors, without the need for additional capacitors to store information, and the charge is stored on the gate capacitor of the read transistor. However, the traditional silicon-based 2T0C DRAM has a relatively high off-current of the write transistor, and the gate capacitor of the read transistor is relatively small compared to the traditional capacitor, so the charge retention time of the silicon-based 2T0C has always been low, which has become the biggest factor limiting its application.

[0004] And the 2T0C DRAM memory cell prepared by the oxide semiconductor represented by IGZO makes it possible to achieve effective storage under small size conditions. Compared with traditional silicon-based devices, thin film transistors prepared based on such oxide semiconductors have extremely low leakage. Therefore, the retention time of small-size 2T0C devices will increase by orders of magnitude compared to silicon devices, meeting the requirements of data caching.

[0005] CMOS (Complementary Metal Oxide Semiconductor) technology builds a low static power consumption and efficient circuit system by planar integration of NMOS and PMOS transistors on the same silicon chip. Design based on planar CMOS technology is currently widely used in various scenarios, and is the core of various processors, application-specific integrated circuits, and memory peripheral circuits.

[0006] However, with the continuous evolution of integrated circuit technology, transistor size is constantly shrinking, and the distance between source and drain is getting shorter, causing various non-ideal effects such as short channel effects. The control ability of the transistor gate on the current is continuously weakened, the leakage current is increased, and the power consumption is increased. And the plane NMOS and PMOS still need to continuously reduce its size to ensure the improvement of integrated circuit density and the overall chip computing power. For this reason, people have developed many high-density transistor integration schemes, such as FinFET and GAAFET. However, in the manufacturing process of traditional silicon-based semiconductor transistors, the type and distribution of doping atoms are used to achieve the required electronic properties. But due to the diffusion phenomenon of doping atoms at a certain temperature, the plane CMOS needs to isolate PMOS and NMOS in space, causing waste of chip area.

[0007] To solve the above problems, the emergence of vertical complementary field effect transistor (CFET) provides a new solution. CFET stacks P-type and N-type field effect transistors in the vertical direction, so that they share one gate electrode as a signal input, while the drain connection is used as a signal output, and the two sources are grounded and powered, respectively. This design allows the size of NFET and PFET to be adjusted according to performance requirements, while the channels of NFET and PFET can use different semiconductor materials to match the mobility and improve the drive current. In addition, the vertically stacked structure helps to reduce device size and improve chip integration.

[0008] In addition to the most important 2T0C DRAM storage unit, the capacitorless DRAM storage circuit macro also needs to design circuit modules for storing address selection, row and column signal driving, sensitive amplification, data write back, data buffering, data precharge, etc. to realize the complete function of the storage circuit macro. These circuit modules all occupy part of the area in the storage circuit macro.

[0009] Among them, the storage address selection module is mainly realized by row and column decoders, which use smaller address information to select the corresponding storage unit in a larger array for operation. The row and column signal driving circuit is mainly dominated by inverter structure, and the main purpose is to enhance the corresponding signal to ensure that each storage unit correctly receives the signal. Since the stored data will leak over time, a data write back module needs to be set to connect the readout interface of the sensitive amplifier and write back to the storage unit to ensure the correctness and completeness of the stored data. This operation is also called refreshing. In addition, buffering, pre-charging and other supplementary modules are also needed to ensure the effective writing and reading of the stored data.

[0010] It is worth noting that for the capacitorless DRAM storage circuit macro, it has separate write and read circuits. Unlike the traditional 1T1C DRAM, it opens the write data to the capacitor through a transistor, and then reads the data from the capacitor to the bit line by opening the same transistor, so that the charge change on the bit line is reflected as a voltage change. The capacitorless DRAM (2T0C) stores data in the gate dielectric of the read transistor by opening the write transistor; when reading, the charge stored in the gate capacitor is read out in the form of current by adjusting the voltage on both sides of the source and drain of the read transistor. Therefore, for the capacitorless DRAM storage circuit macro, the current type sensitive amplifier needs to be selected, which is different from the voltage type sensitive amplifier of the traditional 1T1C DRAM.

[0011] The capacitorless DRAM storage macro is composed of only two transistors, and does not require additional capacitor process, so it can be compatible with logic process in process manufacturing in theory, but its disadvantages are also more obvious:

[0012] 1. Due to the high leakage of silicon transistors, the storage holding time of the circuit macro is short;

[0013] 2. Because the holding time is short, multiple refresh write-back data is required, so the overall storage circuit macro power consumption is high.

[0014] Traditional silicon-based integrated circuit semiconductor process needs to go through many process steps. For traditional silicon-based processes, after completing the preparation of a layer of transistors, it is difficult to prepare a second layer of devices on top of it, otherwise it will have a huge impact on the overall performance of the chip. Therefore, existing traditional silicon-based semiconductor integrated circuits are basically based on a plane, and the data path is long, and more speed and power loss is lost on the data path. Therefore, if a new layer of transistors needs to be integrated on the existing traditional silicon integrated circuit, the temperature of these transistor processes is crucial. At this stage, channel materials such as oxide semiconductors (IGZO, ITO, IWO, TeOx) and carbon nanotubes have the characteristics of low preparation temperature and can be used for further transistor preparation above the silicon transistor without damaging the silicon transistor in the previous process.

[0015] The monolithic three-dimensional integration technology refers to the technology of integrating multiple layers of transistors in the same chip by vertical stacking. The main advantages of this technology are as follows: 1. Temperature compatibility with subsequent process steps. Semiconductor processes are divided into front-end and back-end. The front-end refers to the preparation of silicon transistors, which requires high temperature. The back-end refers to the process steps after the preparation of transistors, such as metal interconnection. The process temperature of some new storage and computing devices and new materials is compatible with the back-end, so they can be vertically stacked on a single chip. The second advantage is that it greatly reduces the chip area. Because of the vertical stacking of devices and arrays, the data path between layers is short, which can greatly improve the data transmission bandwidth and increase the chip speed and integration. However, it should be noted that the Through-Silicon Vias (TSV) process in the "three-dimensional integration technology" at the packaging level is different. The monolithic three-dimensional integration process does not require multiple silicon wafers to be punched and interconnected, but uses Inter-layer Vias (ILV) of hundreds of nanometers, which means that the interconnection is between the insulating layers such as oxide layers within a process flow, rather than between silicon layers. This technology realizes high-bandwidth interconnection of multiple functional layers of devices on a single silicon wafer, which can improve the efficiency of data exchange.

[0016] In summary, the current capacitorless DRAM storage circuit macro based on silicon-based chip manufacturing process has high leakage of silicon transistors, which results in short overall storage retention time, frequent refreshing, high power consumption, and is not conducive to practical application. Moreover, the storage peripheral circuit occupies a large area in the entire circuit macro, which needs to be solved urgently. SUMMARY

[0017] The present application provides a back-end compatible capacitorless DRAM storage circuit macro construction method and device to solve the problem of the current capacitorless DRAM storage circuit macro based on silicon-based chip manufacturing process, which has high leakage of silicon transistors, resulting in short overall storage retention time, frequent refreshing, high power consumption, and is not conducive to practical application. Moreover, the storage peripheral circuit occupies a large area in the entire circuit macro.

[0018] The first aspect of the present application provides a macro construction method of a back-compatible capacitorless DRAM storage circuit, comprising the following steps: determining a full back-compatible channel material meeting a preset preparation requirement, and constructing a multi-layer capacitorless DRAM storage circuit macro by using the full back-compatible channel material; constructing a peripheral circuit corresponding to each layer of capacitorless DRAM storage circuit macro in the multi-layer capacitorless DRAM storage circuit macro based on a preset back-compatible vertical complementary field effect transistor; constructing a multi-layer complete back-compatible capacitorless DRAM storage circuit macro according to each layer of capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and performing a multi-layer stacking operation on a target silicon-based circuit based on an interlayer via, so as to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro.

[0019] Optionally, in an embodiment of the present application, the determination of the full back-compatible channel material meeting the preset preparation requirement and the construction of the multi-layer capacitorless DRAM storage circuit macro by using the full back-compatible channel material comprises: determining N-type channel material and P-type channel material in the full back-compatible channel material based on preset leakage properties, mobility and preparation temperature requirements of the oxide semiconductor; and preparing the N-type channel material and the P-type channel material according to a preset deposition method, and constructing the multi-layer capacitorless DRAM storage circuit macro by using the N-type channel material and the P-type channel material.

[0020] Optionally, in an embodiment of the present application, the construction of the peripheral circuit corresponding to each layer of capacitorless DRAM storage circuit macro in the multi-layer capacitorless DRAM storage circuit macro based on the preset back-compatible vertical complementary field effect transistor comprises: determining a storage circuit area of each layer of capacitorless DRAM storage circuit macro, and determining a circuit area of the peripheral circuit corresponding to each layer of capacitorless DRAM storage circuit macro according to the storage circuit area; constructing a circuit topology structure of the peripheral circuit based on a vertical complementary property of the back-compatible vertical complementary field effect transistor; and constructing the peripheral circuit corresponding to each layer of capacitorless DRAM storage circuit macro according to the circuit area of the peripheral circuit and the circuit topology structure, wherein the peripheral circuit comprises at least one of a storage address selection circuit, a row-column signal driving circuit, a sensitive amplification circuit, a data write-back circuit, a data buffer circuit and a data pre-charge circuit.

[0021] Optionally, in an embodiment of the present application, the interlayer via is used to enable the multi-layer complete back-compatible capacitorless DRAM storage circuit macro to be stacked on a target silicon-based circuit to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro.

[0022] The second aspect embodiment of the present application provides a back-compatible capacitorless DRAM storage circuit macro construction device, which comprises: a first construction module configured to determine a full back-compatible channel material meeting a preset preparation requirement, and to construct a multi-layer capacitorless DRAM storage circuit macro by using the full back-compatible channel material; a second construction module configured to construct a peripheral circuit corresponding to each layer of the capacitorless DRAM storage circuit macro based on a preset back-compatible vertical complementary field effect transistor; and a stacking module configured to construct a multi-layer complete back-compatible capacitorless DRAM storage circuit macro according to the each layer of the capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and to enable the multi-layer complete back-compatible capacitorless DRAM storage circuit macro to be stacked on a target silicon-based circuit to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro based on an interlayer via.

[0023] Optionally, in an embodiment of the present application, the first construction module comprises: a first determination unit configured to determine an N-type channel material and a P-type channel material in the full back-compatible channel material based on a preset leakage property, mobility and preparation temperature requirement of an oxide semiconductor; and a first establishment unit configured to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and to construct the multi-layer capacitorless DRAM storage circuit macro by using the N-type channel material and the P-type channel material.

[0024] Optionally, in an embodiment of the present application, the second construction module comprises: a second determination unit configured to determine a storage circuit area of the each-layer capacitorless DRAM storage circuit macro, and determine a circuit area of a peripheral circuit corresponding to the each-layer capacitorless DRAM storage circuit macro according to the storage circuit area; a second establishment unit configured to construct a circuit topology structure of the peripheral circuit based on the vertical complementary characteristic of the back-compatible vertical complementary field effect transistor; and a third establishment unit configured to construct the peripheral circuit corresponding to the each-layer capacitorless DRAM storage circuit macro according to the circuit area of the peripheral circuit and the circuit topology structure, wherein the peripheral circuit comprises at least one of a storage address selection circuit, a row-column signal driving circuit, a sensitive amplification circuit, a data write-back circuit, a data buffer circuit, and a data pre-charge circuit.

[0025] Optionally, in an embodiment of the present application, the stacking module comprises: a three-dimensional integration unit configured to stack the multi-layer complete back-compatible capacitorless DRAM storage circuit macro on the target silicon-based circuit based on the interlayer via corresponding to the multi-layer complete back-compatible capacitorless DRAM storage circuit macro, to obtain the monolithic three-dimensionally integrated full back-compatible capacitorless DRAM storage circuit macro.

[0026] The third aspect embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the back-compatible capacitorless DRAM storage circuit macro construction method as described in the above embodiments.

[0027] The fourth aspect embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the above back-compatible capacitorless DRAM storage circuit macro construction method.

[0028] The fifth aspect embodiment of the present application provides a computer program product, comprising a computer program, which is executed to implement the above back-compatible capacitorless DRAM storage circuit macro construction method.

[0029] Therefore, the embodiments of the present application have the following beneficial effects:

[0030] The embodiments of this application can be implemented by determining a fully back-end compatible channel material that meets preset fabrication requirements, and using the fully back-end compatible channel material to construct a multilayer capacitor-free DRAM memory macro. Based on preset back-end compatible vertical complementary field-effect transistors (CFETs), peripheral circuits corresponding to each layer of the multilayer capacitor-free DRAM memory macro are constructed. A multilayer complete back-end compatible capacitor-free DRAM memory macro is constructed based on each layer of the capacitor-free DRAM memory macro and its corresponding peripheral circuits. Using interlayer vias, the multilayer complete back-end compatible capacitor-free DRAM memory macro is stacked on a target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory macro. The capacitor-free DRAM memory macro of this application features long retention time, low refresh rate, low power consumption, and the ability to be stacked in multiple layers to fabricate high-density memory. Furthermore, the peripheral circuits of this application employ CFET technology, which further reduces the area of ​​the peripheral circuits, making the memory macro more compact and beneficial for future high-density memory integration. This solves the problems of current capacitor-free DRAM memory circuit macros based on silicon-based chip manufacturing processes, which suffer from short overall memory retention time, frequent refresh, and high power consumption due to the high leakage current of silicon transistors, making them unsuitable for practical applications, and also have a large area occupied by peripheral memory circuits in the entire circuit macro.

[0031] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0032] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0033] Figure 1 This is a flowchart of a back-end compatible capacitor-free DRAM memory circuit macro construction method according to an embodiment of this application;

[0034] Figure 2 A macro schematic diagram of a capacitor-free DRAM memory circuit is provided for one embodiment of this application;

[0035] Figure 3 A schematic diagram of a multi-layer stackable back-end capacitor-free DRAM memory circuit macro provided for one embodiment of this application;

[0036] Figure 4 A comparative schematic diagram of planar CMOS and vertical CFET for a back-end device is provided for one embodiment of this application;

[0037] Figure 5A schematic diagram of an overall capacitorless DRAM storage circuit macro area optimization for an embodiment of the present application;

[0038] Figure 6 A schematic diagram of a NAND, AND, NOR circuit topology constructed based on vertical complementary field effect transistors for an embodiment of the present application;

[0039] Figure 7 An example diagram of a back compatible capacitorless DRAM storage circuit macro construction apparatus according to an embodiment of the present application;

[0040] Figure 8 A schematic diagram of an electronic device according to an embodiment of the present application.

[0041] Wherein, 10-back compatible capacitorless DRAM storage circuit macro construction apparatus; 100-first construction module, 200-second construction module, 300-stacking module; 801-memory, 802-processor, 803-communication interface. DETAILED DESCRIPTION

[0042] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals are used throughout the drawing figures to refer to the same or like elements or elements having the same or similar functionality. The embodiments described below are exemplary and are intended to be illustrative of the present application and are not to be understood as limited.

[0043] A method and device for constructing a back-compatible capacitorless DRAM storage circuit macro are described below with reference to the accompanying drawings. To address the problems mentioned in the background, the present application provides a method for constructing a back-compatible capacitorless DRAM storage circuit macro. In the method, a full back-compatible channel material that meets predetermined preparation requirements is determined, and a multi-layer capacitorless DRAM storage circuit macro is constructed using the full back-compatible channel material. Based on a predetermined back-compatible vertical complementary field effect transistor, a peripheral circuit corresponding to each layer of the capacitorless DRAM storage circuit macro in the multi-layer capacitorless DRAM storage circuit macro is constructed. A complete multi-layer back-compatible capacitorless DRAM storage circuit macro is constructed according to each layer of the capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and based on an interlayer via, the complete multi-layer back-compatible capacitorless DRAM storage circuit macro is subjected to a multi-layer stacking operation on a target silicon-based circuit to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro. The capacitorless DRAM storage circuit macro of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and high-density storage that can be prepared in multiple layers. In addition, the peripheral circuit of the present application uses a vertical complementary field effect transistor (CFET) process, which can further compress the area of the peripheral circuit, making the storage circuit macro more compact and conducive to high-density integration of future storage. Thus, the problems of current capacitorless DRAM storage circuit macros based on silicon chip manufacturing processes, such as short overall storage retention time, frequent refreshing, high power consumption, and large area occupied by the storage peripheral circuit in the entire circuit macro, due to the high leakage of silicon transistors, are solved.

[0044] Specifically, Figure 1 A flowchart of a method for constructing a back-compatible capacitorless DRAM storage circuit macro according to an embodiment of the present application is shown in FIG. 1.

[0045] As Figure 1 shown, the method for constructing a back-compatible capacitorless DRAM storage circuit macro includes the following steps:

[0046] In step S101, a full back-compatible channel material that meets predetermined preparation requirements is determined, and a multi-layer capacitorless DRAM storage circuit macro is constructed using the full back-compatible channel material.

[0047] The embodiment of the present application first determines a full back-compatible channel material that meets predetermined preparation requirements (such as low leakage, large-scale uniform preparation, high mobility, etc.), and then constructs a multi-layer capacitorless DRAM storage circuit macro using the full back-compatible channel material.

[0048] Optionally, in one embodiment of the present application, a full back-end compatible channel material satisfying the preset preparation requirements is determined, and a multi-layer capacitorless DRAM storage circuit macro is constructed using the full back-end compatible channel material, including: determining N-type channel material and P-type channel material in the full back-end compatible channel material based on preset leakage of oxide semiconductor, mobility and preparation temperature requirements; preparing the N-type channel material and the P-type channel material according to a preset deposition method, and constructing the multi-layer capacitorless DRAM storage circuit macro through the N-type channel material and the P-type channel material.

[0049] It should be noted that the main feature of the capacitorless DRAM storage circuit macro in the embodiment of the present application is that the overall capacitorless DRAM storage circuit macro is prepared using back-end compatible materials. Among them, as the write transistor of the capacitorless DRAM, it needs to meet the low leakage requirement, so as to effectively delay the retention time; the write tube and the read tube preferably have high mobility to ensure the writing and reading speed.

[0050] In actual execution process, the embodiment of the present application can use N tube as write tube and P transistor as read tube for storage unit. The requirement of N-type channel material is low leakage, large-scale uniform preparation and high mobility; the requirement of P-type channel material is large-scale uniform preparation and good mobility; and both N-type and P-type channel materials need to have a relatively low preparation temperature, which is generally required to be at least lower than 500 degrees, and is close to the process temperature of the back-end interconnection process, which is a "back-end process compatible" material.

[0051] For N transistor, the embodiment of the present application can use oxide semiconductor materials such as IGZO, which has the characteristics of low leakage and low preparation temperature compared with silicon-based transistor; for P transistor, P-type oxide such as TeOx is used. Both of the above two kinds of oxide semiconductor based channel materials can be prepared at low temperature and in large scale, and can be prepared by atomic layer deposition ALD, physical vapor deposition PVD and other deposition methods.

[0052] It should be noted that those skilled in the art should understand that for capacitorless DRAM, the write tube requires low leakage, and the current N-type back-end channel material shows relatively low leakage characteristics. The N-type channel material can use any low-leakage, back-end-preparable, and well-uniform material, such as IWO, ITO and other oxide semiconductor materials in addition to IGZO; and the P-type channel material can use any back-end-preparable, large-scale-preparable, and well-uniform material, such as P-type oxide semiconductor materials such as SnO in addition to TeOx, P-type two-dimensional material, P-type carbon nanotube, etc. However, if the P-type back-end channel material shows low leakage characteristics in the later stage, the write tube can be replaced with P-type channel material, and the additional requirement for P-type channel material is low leakage.

[0053] Therefore, the memory circuit macros prepared based on the above materials can effectively achieve multi-layer stacking on silicon-based circuits without significantly affecting the performance of the underlying silicon-based circuits.

[0054] In step S102, based on the preset back-end compatible vertical complementary field-effect transistors, the peripheral circuits corresponding to each layer of the multilayer capacitor-free DRAM memory circuit macro are constructed.

[0055] Furthermore, embodiments of this application also require the use of back-end compatible vertical complementary field-effect transistors to construct the peripheral circuits corresponding to each layer of capacitor-free DRAM memory circuit macro.

[0056] Optionally, in one embodiment of this application, based on a preset back-end compatible vertical complementary field-effect transistor, the peripheral circuits corresponding to each layer of the multilayer capacitor-free DRAM memory circuit macro are constructed, including: determining the memory circuit area of ​​each layer of the capacitor-free DRAM memory circuit macro, and determining the circuit area of ​​the peripheral circuits corresponding to each layer of the capacitor-free DRAM memory circuit macro based on the memory circuit area; constructing the circuit topology of the peripheral circuits based on the vertical complementary characteristics of the back-end compatible vertical complementary field-effect transistors; and constructing the peripheral circuits corresponding to each layer of the capacitor-free DRAM memory circuit macro based on the circuit area and circuit topology of the peripheral circuits. The peripheral circuits include at least one of a memory address selection circuit, a row and column signal driving circuit, a sensitive amplification circuit, a data write-back circuit, a data buffer circuit, and a data precharge circuit.

[0057] It should be noted that the peripheral circuit design of the specific back-end compatible capacitorless DRAM memory circuit macro in the embodiments of this application is quite similar to that of the capacitorless DRAM memory circuit macro based on silicon-based CMOS.

[0058] Specifically, the peripheral circuits in this application embodiment mainly include circuit modules such as memory address selection, row and column signal driving, sensitive amplification, data write-back, data buffering, and data pre-charging, such as... Figure 2 As shown in the diagram. The storage address selection module primarily relies on row and column decoders, using smaller address information to select the corresponding storage unit from a larger array for operation. The row and column signal driving circuit mainly uses an inverter structure, primarily to amplify the corresponding signals to ensure each storage unit correctly receives the signal. A current-type sensitive amplifier is required. Since stored data may leak over time, a data write-back module is needed to connect to the sensitive amplifier's read interface and write back to the storage unit to ensure the correctness and integrity of the stored data; this operation can also be called refreshing. Furthermore, in actual implementation, this embodiment also requires supplementary modules such as buffering and pre-charging to ensure effective writing and reading of stored data.

[0059] It should be noted that, Figure 3 This is a schematic diagram of a back-end capacitor-free DRAM memory circuit macro that can be stacked in multiple layers. Both the memory array and the peripheral circuits must be fabricated using back-end compatible processes.

[0060] As one possible approach, embodiments of this application can employ back-end compatible vertical complementary field-effect transistors (CFETs) to implement the peripheral circuit design portion of a capacitorless DRAM memory macro, such as... Figure 4 As shown, compared to traditional CMOS process design, it can fabricate both N-type and P-type transistors within a single transistor cell area. In a capacitor-free DRAM memory circuit macro, the peripheral circuit occupies a certain area, the proportion of which depends on the size of the memory array. Although the area of ​​the peripheral circuit increases with the area of ​​the memory array, its growth rate is slower than that of the array area. When the memory array reaches 8 Mbit, the peripheral circuit accounts for approximately 30% of the overall memory circuit macro area. Therefore, vertical complementary field-effect transistors (PLTs) can reduce the area of ​​the peripheral circuit by nearly half, such as... Figure 5 As shown, this is beneficial for optimizing the area of ​​the overall storage circuit macro.

[0061] It is understood that, unlike traditional planar CMOS circuit design, in the embodiments of this application, when using vertical complementary field-effect transistors for circuit design, their vertical complementary characteristics can also be applied to design corresponding NOT gate, NAND gate, and NOR gate circuit topologies, which saves area and also saves some wiring. Figure 6 This demonstrates NOT, NAND, and NOR circuit topologies constructed based on vertical complementary field-effect transistors, such as... Figure 6 As shown, it demonstrates its unique construction method. Therefore, based on the designed logic gates, various functional peripheral circuit modules can be further built.

[0062] In summary, the peripheral circuit portion of the circuit macro in this embodiment is fabricated using vertical complementary field-effect transistor (CFET) technology. Compared to silicon-based capacitorless DRAM memory circuit macros that utilize low-leakage oxide semiconductors as write transistors, this embodiment features long hold time, low refresh rate, low power consumption, and the ability to fabricate high-density memory through multi-layer stacking. Furthermore, the use of CFET technology for the peripheral circuit further reduces the area of ​​the peripheral circuit, making the memory circuit macro more compact and beneficial for future high-density integration of memory.

[0063] In step S103, a multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro is constructed based on each layer of capacitor-free DRAM memory circuit macro and the corresponding peripheral circuit. Based on inter-layer vias, the multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

[0064] Subsequently, in the embodiments of this application, multiple complete back-end compatible capacitor-free DRAM memory circuit macros can be constructed by each layer of capacitor-free DRAM memory circuit macro and corresponding peripheral circuits. Through interlayer vias, multiple complete back-end compatible capacitor-free DRAM memory circuit macros can be stacked on the target silicon-based circuit, thereby obtaining a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

[0065] Optionally, in one embodiment of this application, based on interlayer vias, a multilayer complete back-end compatible capacitor-free DRAM memory circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro. This includes: stacking multiple layers of complete back-end compatible capacitor-free DRAM memory circuit macro on the target silicon-based circuit based on the interlayer vias corresponding to the multilayer complete back-end compatible capacitor-free DRAM memory circuit macro to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

[0066] Understandably, there are some problems with the current capacitorless DRAM memory circuit macro based on silicon-based chip manufacturing process. The main problems are that silicon transistors have high leakage current, resulting in short overall memory retention time, requiring frequent refresh, and high power consumption, making them unsuitable for practical applications. In addition, the memory circuit macro based on silicon cannot achieve multi-layer stacking in the later stages.

[0067] Therefore, the embodiments of this application utilize interlayer vias corresponding to multilayer complete back-end compatible capacitor-free DRAM memory circuit macros to stack multilayer complete back-end compatible capacitor-free DRAM memory circuit macros on the target silicon-based circuit, thereby obtaining a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

[0068] It should be noted that the embodiments of this application mainly use 2T0C capacitor-free DRAM as the basic example. In addition, capacitor-free DRAM also exists in the form of 2T0C, 3T0C, 4T0C, etc. Although their cell structure and operation programming scheme are somewhat different from those of the embodiments of this application, the CFET fabrication of capacitor-free DRAM memory peripheral circuit and the fully back-end integrated capacitor-free DRAM memory circuit of the embodiments of this application can be well applied to different capacitor-free DRAM memory cell structures.

[0069] According to the back-end compatible capacitor-free DRAM memory circuit macro construction method proposed in this application, a fully back-end compatible channel material that meets preset fabrication requirements is determined, and a multilayer capacitor-free DRAM memory circuit macro is constructed using the fully back-end compatible channel material. Based on preset back-end compatible vertical complementary field-effect transistors, peripheral circuits corresponding to each layer of the capacitor-free DRAM memory circuit macro are constructed. A multilayer complete back-end compatible capacitor-free DRAM memory circuit macro is constructed based on each layer of the capacitor-free DRAM memory circuit macro and its corresponding peripheral circuits. Based on interlayer vias, the multilayer complete back-end compatible capacitor-free DRAM memory circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro. The capacitor-free DRAM memory circuit macro of this application has the characteristics of long retention time, low refresh rate, low power consumption, and the ability to be stacked in multiple layers to fabricate high-density memory. Furthermore, the peripheral circuit of this application adopts the vertical complementary field-effect transistor (CFET) process, which can further compress the area of ​​the peripheral circuit, making the memory circuit macro more compact and beneficial for future high-density memory integration.

[0070] Secondly, with reference to the accompanying drawings, a back-end compatible capacitor-free DRAM memory circuit macro-construction apparatus according to an embodiment of this application is described.

[0071] Figure 7 This is a block diagram of a back-end compatible capacitor-free DRAM memory circuit macro-construction apparatus according to an embodiment of this application.

[0072] like Figure 7 As shown, the back-end compatible capacitor-free DRAM memory circuit macro construction device 10 includes: a first construction module 100, a second construction module 200, and a stacking module 300.

[0073] The first construction module 100 is used to determine a fully back-end compatible channel material that meets the preset preparation requirements, and to use the fully back-end compatible channel material to construct a multilayer capacitor-free DRAM memory circuit macro.

[0074] The second construction module 200 is used to construct the peripheral circuits corresponding to each layer of the capacitorless DRAM memory circuit macro in the multilayer capacitorless DRAM memory circuit macro based on the preset back-end compatible vertical complementary field-effect transistors.

[0075] The stacking module 300 is used to construct multi-layer complete back-end compatible capacitor-free DRAM memory circuit macros based on each layer of capacitor-free DRAM memory circuit macro and its corresponding peripheral circuits. Based on inter-layer vias, it enables multi-layer stacking of these complete back-end compatible capacitor-free DRAM memory circuit macros on the target silicon-based circuitry, resulting in a monolithic, three-dimensionally integrated, fully back-end compatible capacitor-free DRAM memory circuit macro.

[0076] Optionally, in one embodiment of this application, the first construction module 100 includes: a first determining unit and a first establishing unit.

[0077] The first determining unit is used to determine the N-type channel material and the P-type channel material in the fully back-end compatible channel material based on the preset leakage current, mobility and preparation temperature requirements of the oxide semiconductor.

[0078] The first building unit is used to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and to construct the multilayer capacitor-free DRAM memory circuit macro using the N-type channel material and the P-type channel material.

[0079] Optionally, in one embodiment of this application, the second construction module 200 includes: a second determining unit, a second establishing unit, and a third establishing unit.

[0080] The second determining unit is used to determine the storage circuit area of ​​each layer of capacitor-free DRAM storage circuit macro, and to determine the circuit area of ​​the peripheral circuit corresponding to each layer of capacitor-free DRAM storage circuit macro based on the storage circuit area.

[0081] The second establishment unit is used to construct the circuit topology of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field-effect transistor.

[0082] The third establishment unit is used to construct the peripheral circuit corresponding to each layer of the capacitorless DRAM memory circuit macro based on the circuit area and the circuit topology of the peripheral circuit. The peripheral circuit includes at least one of the following: memory address selection circuit, row and column signal driving circuit, sensitive amplification circuit, data write-back circuit, data buffer circuit, and data precharge circuit.

[0083] Optionally, in one embodiment of this application, the stacking module 300 includes: a three-dimensional integration unit, used to stack the multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro on the target silicon-based circuit based on the interlayer vias corresponding to the multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro, to obtain the monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

[0084] It should be noted that the foregoing explanation of the embodiment of the back-end compatible capacitor-free DRAM memory circuit macro construction method also applies to the back-end compatible capacitor-free DRAM memory circuit macro construction apparatus of this embodiment, and will not be repeated here.

[0085] The back-end compatible capacitor-free DRAM memory circuit macro-construction apparatus proposed in this application includes a first construction module for determining a fully back-end compatible channel material that meets preset fabrication requirements and constructing a multilayer capacitor-free DRAM memory circuit macro using the fully back-end compatible channel material; a second construction module for constructing peripheral circuits corresponding to each layer of the multilayer capacitor-free DRAM memory circuit macro based on preset back-end compatible vertical complementary field-effect transistors; and a stacking module for constructing a multilayer complete back-end compatible capacitor-free DRAM memory circuit macro based on each layer of the capacitor-free DRAM memory circuit macro and its corresponding peripheral circuit, and for performing multilayer stacking operations on a target silicon-based circuit based on interlayer vias to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro. The capacitor-free DRAM memory circuit macro of this application features long retention time, low refresh rate, low power consumption, and the ability to fabricate high-density memory through multilayer stacking. Furthermore, the peripheral circuit of this application uses vertical complementary field-effect transistor (CFET) technology, which can further compress the area of ​​the peripheral circuit, making the memory circuit macro more compact and beneficial for future high-density memory integration.

[0086] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0087] The memory 801, the processor 802, and the computer program stored on the memory 801 and capable of running on the processor 802.

[0088] When the processor 802 executes the program, it implements the macro construction method for back-end compatible capacitor-free DRAM storage circuits provided in the above embodiments.

[0089] Furthermore, electronic devices also include:

[0090] Communication interface 803 is used for communication between memory 801 and processor 802.

[0091] The memory 801 is used to store computer programs that can run on the processor 802.

[0092] The memory 801 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0093] If the memory 801, processor 802, and communication interface 803 are implemented independently, then the communication interface 803, memory 801, and processor 802 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0094] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.

[0095] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0096] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described method for constructing a back-end compatible capacitor-free DRAM memory circuit macro.

[0097] This application also provides a computer program product, including a computer program, which, when executed, is used to implement the above-described back-end compatible capacitor-free DRAM memory circuit macro construction method.

[0098] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0100] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0101] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0102] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0103] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0104] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0105] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for constructing a back-end compatible capacitor-free DRAM memory circuit macro, characterized in that, Includes the following steps: A fully back-end compatible channel material that meets the preset preparation requirements is identified, and a multilayer capacitor-free DRAM memory circuit macro is constructed using the fully back-end compatible channel material. Based on the preset back-end compatible vertical complementary field-effect transistor, construct the peripheral circuit corresponding to each layer of the capacitor-free DRAM memory circuit macro in the multilayer capacitor-free DRAM memory circuit macro. Based on each layer of capacitor-free DRAM memory circuit macro and the corresponding peripheral circuit, a multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro is constructed. Based on inter-layer vias, the multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

2. The method according to claim 1, characterized in that, The process of determining a fully back-end compatible channel material that meets preset fabrication requirements, and using the fully back-end compatible channel material to construct a multilayer capacitor-free DRAM memory circuit macro, includes: Based on the preset leakage current, mobility and fabrication temperature requirements of oxide semiconductors, the N-type channel material and P-type channel material in the fully back-channel compatible channel material are determined. The N-type channel material and the P-type channel material are prepared according to a preset deposition method, and the multilayer capacitor-free DRAM memory circuit macro is constructed using the N-type channel material and the P-type channel material.

3. The method according to claim 2, characterized in that, The peripheral circuits corresponding to each layer of the multilayer capacitor-free DRAM memory circuit macro are constructed based on the preset back-end compatible vertical complementary field-effect transistors, including: Determine the storage circuit area of ​​each layer of capacitor-free DRAM storage circuit macro, and determine the circuit area of ​​the peripheral circuit corresponding to each layer of capacitor-free DRAM storage circuit macro based on the storage circuit area. Based on the vertical complementary characteristics of the back-end compatible vertical complementary field-effect transistor, the circuit topology of the peripheral circuit is constructed. The peripheral circuits corresponding to each layer of the capacitorless DRAM memory circuit macro are constructed based on the circuit area and the circuit topology of the peripheral circuits. The peripheral circuits include at least one of the following: memory address selection circuit, row and column signal driving circuit, sensitive amplification circuit, data write-back circuit, data buffer circuit, and data precharge circuit.

4. The method according to claim 3, characterized in that, The method based on interlayer vias enables the multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro to be stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro, including: Based on the interlayer vias corresponding to the multilayer complete back-end compatible capacitor-free DRAM memory circuit macro, the multilayer complete back-end compatible capacitor-free DRAM memory circuit macro is stacked on the target silicon-based circuit to obtain the monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

5. A back-end compatible capacitor-free DRAM memory circuit macro-construction apparatus, characterized in that, include: The first construction module is used to determine the fully back-end compatible channel material that meets the preset preparation requirements, and to use the fully back-end compatible channel material to construct a multilayer capacitor-free DRAM memory circuit macro. The second construction module is used to construct the peripheral circuits corresponding to each layer of the capacitor-free DRAM memory circuit macro in the multilayer capacitor-free DRAM memory circuit macro based on the preset back-end compatible vertical complementary field-effect transistors. The stacking module is used to construct a multi-layer complete back-end compatible capacitor-free DRAM memory circuit macro based on each layer of capacitor-free DRAM memory circuit macro and the corresponding peripheral circuit, and based on inter-layer vias, to perform multi-layer stacking operations on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM memory circuit macro.

6. The apparatus according to claim 5, characterized in that, The first building module includes: The first determining unit is used to determine the N-type channel material and the P-type channel material in the fully back-end compatible channel material based on the preset leakage current, mobility and fabrication temperature requirements of the oxide semiconductor. The first building unit is used to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and to construct the multilayer capacitor-free DRAM memory circuit macro using the N-type channel material and the P-type channel material.

7. The apparatus according to claim 6, characterized in that, The second building module includes: The second determining unit is used to determine the storage circuit area of ​​each layer of capacitor-free DRAM storage circuit macro, and to determine the circuit area of ​​the peripheral circuit corresponding to each layer of capacitor-free DRAM storage circuit macro based on the storage circuit area. The second establishment unit is used to construct the circuit topology of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field-effect transistor. The third establishment unit is used to construct the peripheral circuit corresponding to each layer of the capacitorless DRAM memory circuit macro based on the circuit area and the circuit topology of the peripheral circuit. The peripheral circuit includes at least one of the following: memory address selection circuit, row and column signal driving circuit, sensitive amplification circuit, data write-back circuit, data buffer circuit, and data precharge circuit.

8. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the back-end compatible capacitor-free DRAM memory circuit macro construction method as described in any one of claims 1-4.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the back-end compatible capacitor-free DRAM memory circuit macro construction method as described in any one of claims 1-4.

10. A computer program product, comprising a computer program, characterized in that, The computer program is executed to implement the back-end compatible capacitor-free DRAM memory circuit macro construction method as described in any one of claims 1-4.

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