In-memory computing memory device and in-memory computing method

Abstract

The invention provides an in-memory computing (IMC) memory device and an in-memory computing method. A plurality of operation storage units and a plurality of balance operation storage units of the IMC memory device form a plurality of storage unit strings. During programming, the number of first impedance states of the balanced operational memory cells of the memory cell string is determined according to the number of first impedance states of the operational memory cells in the memory cell string. During operation, when a read voltage is applied to the operation storage units, the operation storage units generate a plurality of storage unit currents, and the storage unit currents form a plurality of storage unit string currents. Charging a load capacitor by the memory cell string current generated by the memory cell strings; measuring a capacitor voltage of the load capacitor; and determining an operation result of the input values and the weight values according to a relationship among the capacitor voltage of the load capacitor, at least one delay time and a predetermined voltage.

Description

Technical Field

[0001] The present invention relates to an in-memory computing (IMC) memory device and an in-memory computing method. Background Art

[0002] For neural network calculations and applications, vector-matrix multiplication, also known as perceptron operation, has been widely used. When implementing neural network calculations in memory, weight values ​​can be stored in a memory array and input values ​​can be applied to the memory array to perform perceptron calculations, thereby reducing power consumption and improving computational efficiency.

[0003] Due to the memory array architecture, the input values ​​of sensor calculation or vector-matrix multiplication are usually input from the word line side or the bit line side, and the calculation results are read out using sense amplifiers. Therefore, the number of input values ​​will be limited by the size of the memory array and the total accumulated current of the sense amplifier.

[0004] Because the number of input values ​​is limited, the current approach is to divide these input values ​​into multiple input value sets and use multiple sense amplifiers to sense the individual currents of these input value sets respectively. The reading results obtained by multiple different sense amplifiers must be summed, but this summation may cause reading errors and take more computing time and / or power consumption.

[0005] In addition, currently, there are two main architectures to evaluate the results of in-memory computing (IMC), one is the sum-of-current architecture, and the other is the sum-of-voltage architecture.

[0006] For existing current summing architectures, if the number of input values ​​is too large, the summing current may be too high, so it is necessary to reduce the current of each cell or to have a specially designed sense amplifier. However, this will increase the design complexity.

[0007] For the existing voltage summing architecture, the resistance of each arithmetic storage unit must be low in order to increase the induction current and reduce the body effect.

[0008] Furthermore, within a memory device, the weight values ​​of each memory string may not be evenly distributed, which may reduce the linearity of the neural network calculation.

[0009] Therefore, there is a need for an in-memory computing (IMC) memory device and an in-memory computing method to improve the shortcomings of the current approach. Summary of the invention

[0010] According to one aspect of the present disclosure, an in-memory computing (IMC) memory device is proposed, comprising: a memory control circuit, and a memory array coupled to the memory control circuit. The memory array comprises: a plurality of operation storage cells and a plurality of balanced operation storage cells, forming a plurality of storage cell strings, wherein the operation storage cells store a plurality of weight values; a load capacitor coupled to the operation storage cells; and a measurement circuit coupled to the load capacitor. During programming, the memory control circuit determines a first impedance state number of the balanced operation storage cells in the storage cell string according to a first impedance state number of the operation storage cells in the storage cell string. In which, when performing calculations, multiple input voltages are respectively input to these calculation storage units, these input voltages are related to multiple input values, and the memory control circuit sets these input voltages according to these input values; multiple balanced input voltages are respectively input to these balanced calculation storage units, these balanced input voltages are related to multiple balanced input values, these balanced input values ​​are consistent input values, and the memory control circuit sets these balanced input voltages according to these balanced input values; multiple effective impedance values ​​of these calculation storage units are related to these input voltages and these weight values; when a read voltage is applied to these calculation storage units, these calculation storage units generate multiple storage cell currents, and these storage cell currents form multiple storage cell string currents; these storage cell string currents generated by these storage cell strings charge the load capacitor; the measurement circuit measures a capacitor voltage of the load capacitor; and, according to a relationship between the capacitor voltage of the load capacitor, at least one delay time and a predetermined voltage, a calculation result of these input values ​​and these weight values ​​is determined.

[0011] According to another aspect of the present disclosure, an in-memory computing method is provided, which is applied to an in-memory computing memory device, wherein the in-memory computing memory device includes a plurality of operation storage units constituting a plurality of storage unit strings and a plurality of balancing operation storage units. The in-memory calculation method includes: during programming, determining a first impedance state number of the balanced operational storage cells of the storage cell string according to a first impedance state number of the operational storage cells in the storage cell string; storing a plurality of weight values ​​in a plurality of operational storage cells, the operational storage cells forming a plurality of storage cell strings; inputting a plurality of input voltages to the operational storage cells respectively, the input voltages being related to a plurality of input values, the effective impedance values ​​of the operational storage cells being related to the input voltages and the weight values; inputting a plurality of balanced input voltages to the balanced operational storage cells respectively, the balanced input voltages being related to a plurality of balanced input values, the balanced input values ​​being consistent input values, and the balanced input voltages being set according to the balanced input values; when a read voltage is applied to the operational storage cells, the operational storage cells generate a plurality of storage cell currents, the storage cell currents forming a plurality of storage cell string currents; charging the load capacitor by the storage cell string currents generated by the storage cell strings; measuring a capacitor voltage of the load capacitor; and determining a calculation result of the input values ​​and the weight values ​​according to a relationship between the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage.

[0012] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A functional block diagram of an in-memory computing (IMC) memory device according to an embodiment of the present disclosure is shown.

[0014] Figure 2 FIG. 4 is a diagram illustrating an architecture of a memory array of an in-memory computing memory device according to an embodiment of the present disclosure.

[0015] Figure 3A and Figure 3B A schematic diagram showing a measurement delay time according to an embodiment of the present disclosure.

[0016] Figure 4A FIG. 4 is a circuit diagram of an operation storage unit according to an embodiment of the present disclosure.

[0017] Figure 4B FIG. 4 is a circuit diagram of an operation storage unit according to an embodiment of the present disclosure.

[0018] Figure 4C FIG. 4 is a circuit diagram of an operation storage unit according to an embodiment of the present disclosure.

[0019] FIG. 5A to FIG. 5C A simulation diagram according to an embodiment of the present disclosure is shown.

[0020]

Explanation of symbols

[0021] 10: Memory device 20: Memory control circuit

[0022] 30: word line drive circuit 40: bit line drive circuit

[0023] 100: Memory array

[0024] I1~In: memory cell string current BL1~BLn: bit line

[0025] V11~Vmn、BV1~BVp:input voltage

[0026] IN11~INmn、BIN1~BINp:Input value

[0027] 100: memory array IN11~INmn: input value

[0028] S1~Sn: storage cell string C: load capacitance

[0029] 120: Measurement circuit Vread: Read voltage

[0030] BC11~BCpn: Balanced operation storage unit

[0031] RS1~RSn:Impedance elements

[0032] C(a)mn, C(c)mn, C(d)mn: operation storage unit

[0033] R(a)mn,R(c)mn:resistance

[0034] TRmn: Transistor

[0035] g: gate d: drain

[0036] s: source

[0037] 510A-510C: Curve DETAILED DESCRIPTION

[0038] The technical terms of this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition of this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0039] Figure 1 The functional block diagram of an in-memory computing (IMC) memory device according to one embodiment of the present disclosure is shown. The in-memory computing (IMC) memory device 10 according to one embodiment of the present disclosure includes: a memory control circuit 20, a word line driving circuit 30, a bit line driving circuit 40 and a memory array 100. The memory control circuit 20 is used to control the word line driving circuit 30 and the bit line driving circuit 40 to output a word line driving voltage and a bit line driving circuit to the memory array 100. The operation and architecture of the memory control circuit 20, the word line driving circuit 30 and the bit line driving circuit 40 are not particularly limited herein.

[0040] Figure 2 FIG. 1 is a diagram showing an architecture of a memory array 100 of an in-memory computing memory device according to an embodiment of the present disclosure. Figure 2 As shown, a memory array 100 of an in-memory computing (IMC) memory device according to an embodiment of the present disclosure includes: a plurality of operation storage cells C11-Cmn (m and n are positive integers), a plurality of balanced operation storage cells BC11-BCpn (p is a positive integer), a plurality of impedance elements RS1-RSn, a load capacitor C, and a measurement circuit 120. The operation storage cells C11-Cmn and the balanced operation storage cells BC11-BCpn are coupled to the load capacitor C and the measurement circuit 120. In a possible example, the measurement circuit 120 can be implemented by a sense amplifier. The measurement circuit 120 can compare the capacitor voltage VC of the load capacitor C with the reference voltage VREF.

[0041] The operation storage cells C11-Cmn are arranged in n vertical rows and m horizontal columns to perform in-memory computing (IMC). The balance operation storage cells BC11-BCpn are arranged in n vertical rows and p horizontal columns to improve the performance of the in-memory computing (IMC) memory device according to an embodiment of the present disclosure when performing in-memory computing.

[0042] The operation storage cells and the balanced operation storage cells in each vertical row can form storage cell strings S1-Sn. The storage cell string S1 includes operation storage cells C11, C21, ..., Cm1, balanced operation storage cells BC11, ... BCp1, and impedance element RS1. The rest can be deduced in the same way.

[0043] These operation storage units C11-Cmn receive input voltages V11-Vmn, respectively. Specifically, the operation storage units C11, C21, ..., Cm1 receive input voltages V11, V21, ..., Vm1, respectively; the operation storage units C12, C22, ..., Cm2 receive input voltages V12, V22, ..., Vm2, respectively. These input voltages V11-Vmn are related to a plurality of input values ​​IN11-INmn. The memory control circuit 20 sets these input voltages V11-Vmn according to these input values ​​IN11-INmn.

[0044] The operation storage units C11 ˜Cmn store a plurality of weight values ​​W11 ˜Wmn.

[0045] These balanced operation storage cells BC11~BCpn receive balanced input voltages BV1~BVp respectively. In detail, the balanced operation storage cells BC11, BC12...BC1n all receive the balanced input voltage BV1, and the rest can be deduced in the same way. These input voltages BV1~BVp are related to multiple balanced input values ​​BIN1~BINp. The memory control circuit 20 sets the balanced input voltages BV1~BVp according to these balanced input values ​​BIN1~BINp. Furthermore, in one embodiment of the present disclosure, these balanced operation storage cells BC11~BCpn electrically receive the balanced input voltages BV1~BVp respectively. Although the balanced operation storage cells BC11~BC1n electrically receive the same balanced input voltage BV1, these balanced operation storage cells BC11~BC1n do not need to be physically connected in series with each other. These balanced operation storage cells BC11~BC1n can also be distributed at different positions of the memory array 100, as long as these balanced operation storage cells BC11~BC1n can electrically receive the same balanced input voltage BV1. This is all within the spirit and scope of this disclosure.

[0046] The memory cell strings S1 -Sn are connected in parallel, and the memory cell string currents I1 -In generated by the memory cell strings S1 -Sn connected in parallel charge the load capacitor C.

[0047] In addition, the impedance elements RS1 to RSn are selective elements.

[0048] In an embodiment of the present disclosure, the operation storage cells C11 ˜Cmn and the balance operation storage cells BC11 ˜BCpn can be programmed to be in a high impedance state or a low impedance state.

[0049] In one embodiment of the present disclosure, in the programming stage, the operation storage cells C11-Cmn of the storage cell strings S1-Sn are programmed according to the IMC calculation to be performed by the in-memory computing memory device 10 according to one embodiment of the present disclosure (that is, the operation storage cells C11-Cmn of the storage cell strings S1-Sn are programmed to a high impedance state or a low impedance state).

[0050] As for the programming stage, whether these balanced operation storage cells BC11-BCpn are programmed into a high impedance state or a low impedance state is determined according to the number of high impedance states of these operation storage cells C11-Cmn in the same memory cell string S1-Sn. That is, in the programming stage, the memory control circuit 20 determines the number of high impedance states of these balanced operation storage cells BC11-BCpn according to the number of high impedance states of these operation storage cells C11-Cmn in the same memory cell string S1-Sn.

[0051] Specifically, p=3 is used as an example for explanation, but it should be known that the present disclosure is not limited thereto. For the memory cell string S1, when the number of high impedance states of the operational memory cells C11, C21, ..., Cm1 is 0 (i.e., the operational memory cells C11, C21, ..., Cm1 are all programmed to a low impedance state), the balanced operational memory cells BC11, BC21, and BC31 are all programmed to a high impedance state, i.e., the number of high impedance states of the balanced operational memory cells BC11, BC21, and BC31 is 3.

[0052] Similarly, for the memory cell string S1, when the number of high impedance states of the operational memory cells C11, C21, . . . , Cm1 is 1, the number of high impedance states of the balancing operational memory cells BC11, BC21 and BC31 is 2.

[0053] Similarly, for the memory cell string S1, when the number of high impedance states of the operational memory cells C11, C21, . . . , Cm1 is 2, the number of high impedance states of the balancing operational memory cells BC11, BC21 and BC31 is 1.

[0054] Similarly, for the memory cell string S1, when the number of high impedance states of the operational memory cells C11, C21, . . . , Cm1 is 3 or more, the number of high impedance states of the balancing operational memory cells BC11, BC21 and BC31 is 0.

[0055] In addition, when performing IMC calculation, the balanced input values ​​BIN1 -BINp are bit 1 (enable bit), so that the resistance values ​​of the balanced operation memory cells BC11 -BCpn can contribute to the memory cell strings.

[0056] Therefore, in an embodiment of the present disclosure, when more balanced operation memory cells are provided in each memory cell string, the number of high impedance states of these balanced operation memory cells in each memory cell string can be determined according to the above method during the programming stage.

[0057] That is, in one embodiment of the present disclosure, in each of the memory cell strings, when the number of high impedance states of the operational memory cells is small, the number of high impedance states of the balancing operational memory cells will be large; and in each of the memory cell strings, when the number of high impedance states of the operational memory cells is large, the number of high impedance states of the balancing operational memory cells will be small. Thus, the fast charging behavior of the memory cell strings can be improved.

[0058] In one embodiment of the present disclosure, when performing an IMC operation (such as multiply-and-accumulation (MAC)), a read voltage Vread is applied to one end of the operation memory cells C11-Cmn of the memory device 10, so that the operation memory cells C11-Cmn generate a plurality of cell currents. The cell currents generated by the operation memory cells of the same memory cell string are summed to become the memory cell string currents I1-In.

[0059] In one embodiment of the present disclosure, when performing an IMC operation, a read voltage Vread is applied to one end (for example but not limited to, the drain end) of the operational storage units C11-Cmn of the memory device 10, and the capacitance voltage VC of the load capacitor C is measured to measure the charging time (also referred to as the delay time) for the load capacitor C to be charged to a predetermined voltage. For the convenience of definition, the time point at which the read voltage Vread is applied is referred to as the first time point, and the time point at which the capacitance voltage VC of the load capacitor C is measured to be charged to the predetermined voltage is referred to as the second time point. In one embodiment of the present disclosure, the delay time is defined as: from the first time point to the second time point. The capacitance voltage VC of the load capacitor C can be measured by the measurement circuit 120 to measure the delay time of the load capacitor C.

[0060] In one embodiment of the present disclosure, the memory cell string resistance Ri (i=1-n) of the memory cell string Si (i=1-n) can be expressed as follows:

[0061] R i =∑ k＝1～m R ki (INki ).

[0062] Among them, i represents the storage unit string number, k represents the number of the operation storage unit in the storage unit string, and a storage unit string has m operation storage units.

[0063] Therefore, the memory cell string current Ii of the memory cell string Si can be expressed as follows:

[0064] I i =V read / ∑ k＝1～m R ki (IN ki )°

[0065] The weight values ​​W11-Wmn of the operation storage unit are functions of the input values ​​IN11-INmn, so the weight value Wki can be expressed as the impedance value Wki of the operation storage unit = R ki (IN ki ).

[0066] In one embodiment of the present disclosure, the charging time of the load capacitor C to be charged to the predetermined voltage can be used to represent the sum of products of the weight values ​​W11-Wmn of the operation storage units C11-Cmn and the input values ​​IN11-INmn. This is because, in one embodiment of the present disclosure, the sum of products of the weight values ​​of the operation storage units C11-Cmn and the input values ​​IN11-INmn is a total current Itotal. Itotal can be expressed as follows:

[0067] I Total =∑ i＝1～n I i =∑ i＝1～n V read / ∑ k＝1～m R ki (IN ki ).

[0068] This total current Itotal charges the load capacitor C, so the time point when the capacitor voltage VC of the load capacitor C is charged to the predetermined voltage is related to the capacitance value of the load capacitor C and the total current Itotal, and in one embodiment of the present disclosure, the capacitance value of the load capacitor C is known. Therefore, it can be known that in one embodiment of the present disclosure, the time point when the capacitor voltage VC of the load capacitor C is charged to the predetermined voltage can be regarded as negatively correlated with the total current Itotal, that is, when the total current Itotal is larger, the time point when the capacitor voltage VC of the load capacitor C is charged to the predetermined voltage is shorter, and when the total current Itotal is smaller, the time point when the capacitor voltage VC of the load capacitor C is charged to the predetermined voltage is longer.

[0069] Therefore, in an embodiment of the present disclosure, a predetermined relationship between the delay time for the load capacitor C to be charged to the predetermined voltage and the sum of the products of the weight values ​​of the operation storage units C11-Cmn and the input values ​​IN11-INmn under a predetermined condition can be found in advance. In the subsequent IMC operation, the sum of the products of the weight values ​​of the operation storage units C11-Cmn and the input values ​​IN11-INmn can be converted by measuring the delay time.

[0070] In addition, in an embodiment of the present disclosure, when the weight value and / or input value of the operation storage unit changes, the effective impedance value of the operation storage unit also changes accordingly, which will result in different delay times (charging times).

[0071] Figure 3A and Figure 3B A schematic diagram showing a measurement delay time according to an embodiment of the present disclosure. Figure 3A and Figure 3B In FIG. 1 , eRS1 , eRS2 , and eRS3 represent different total effective resistance values ​​of the memory cell strings S1 ˜Sn, wherein eRS1 < eRS2 < eRS3 .

[0072] exist Figure 3A In the embodiment, the delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to a predetermined voltage, and the predetermined voltage is determined according to the read voltage. For example, but not limited to, the predetermined voltage may be 0.7 times of the read voltage.

[0073] exist Figure 3A In the example, when the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS1, at time T1, the load capacitor C is charged to a predetermined voltage, so the delay time T1 represents that the sum of the products of the weight values ​​W11 to Wmn and the input values ​​IN11 to INmn is 001. Similarly, when the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS2, at time T2, the load capacitor C is charged to a predetermined voltage, so the delay time T2 represents that the sum of the products of the weight values ​​W11 to Wmn and the input values ​​IN11 to INmn is 010. Similarly, when the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS3, at time T3, the load capacitor C is charged to a predetermined voltage, so the delay time T3 represents that the sum of the products of the weight values ​​W11 to Wmn and the input values ​​IN11 to INmn is 011. The rest can be deduced in the same way.

[0074] In addition, in another embodiment of the present disclosure, a plurality of predetermined delay times may be selected. At these predetermined delay times, the capacitor voltage VC is compared with the reference voltage VREF, and the comparison result represents the operation result (sum of products) of these input values ​​and these weight values, such as Figure 3B As shown. That is, select several predetermined delay times (t0-t3), and at these predetermined delay times, check whether the capacitor voltage VC reaches the predetermined voltage VREF to determine the calculation results (sum of products) of these input values ​​and these weight values. If at the delay time t0, the capacitor voltage VC reaches the predetermined voltage, then the calculation results (sum of products) of these input values ​​and these weight values ​​are determined to be 000; if at the delay time t1, the capacitor voltage VC reaches the predetermined voltage, then the calculation results (sum of products) of these input values ​​and these weight values ​​are determined to be 001; the rest can be deduced in the same way.

[0075] exist Figure 3B In the example, when the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS1, at the delay time t1, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values ​​and the weight values ​​are determined to be 001. Similarly, when the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS2, at the delay time t1, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values ​​and the weight values ​​are determined to be 001. When the different total effective impedance values ​​of the memory cell strings S1 to Sn are eRS3, at the delay time t3, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values ​​and the weight values ​​are determined to be 011.

[0076] Various examples of an operation storage unit according to an embodiment of the present disclosure will now be described.

[0077] Figure 4A FIG. 1 is a circuit diagram of an operation storage unit C(a)mn according to an embodiment of the present disclosure. The operation storage unit C(a)mn can be used to implement the operation storage units C11-Cmn and the balanced operation storage units BC11-BCpn of the memory array 100 of FIG. 2. The operation storage unit C(a)mn includes a transistor TRmn and a resistor R(a)mn. The transistor TRmn is connected in parallel to the resistor R(a)mn, and the resistor R(a)mn has a fixed resistance value. The operation storage unit C(a)mn is connected to the nth bit line BLn. The drain d and the source s of the transistor TRmn are connected to the bit line BLn, and the gate g of the transistor TRmn receives the input voltage Vmn. The resistor R(a)mn is also connected to the bit line BLn.

[0078] The transistor TRmn is, for example, a floating gate transistor. The transistor TRmn has a threshold voltage Vt, and a programming voltage can be applied to adjust the voltage value of the threshold voltage Vt. When the transistor TRmn is in an erase state, the voltage value of the threshold voltage Vt is a first threshold voltage value VtL. When the transistor TRmn is in a programming state, the voltage value of the threshold voltage Vt can be programmed to a second threshold voltage value VtH. The second threshold voltage value VtH is greater than the first threshold voltage value VtL. The first threshold voltage value VtL is, for example, 0.4V, and the second threshold voltage value VtH is, for example, 4.8V. In addition, the threshold voltage Vt corresponds to a weight value Wmn stored in the operation storage unit C(a)mn. When the threshold voltage Vt is the first threshold voltage value VtL, the weight value Wmn stored in the operation storage unit C(a)mn is "0". When the threshold voltage Vt is the second threshold voltage value VtH, the weight value Wmn stored in the corresponding operation storage unit C(a)mn is “1”.

[0079] The gate g of the transistor TRmn receives an input voltage Vmn. The input voltage Vmn corresponds to the input value INmn received by the operation storage unit C(a)mn. When the voltage value of the input voltage Vmn is the first input voltage value VL, the corresponding input value INmn is "1". When the voltage value of the input voltage Vmn is the second input voltage value VH, the corresponding input value INmn is "0". The second input voltage value VH is greater than the first input voltage value VL. The second input voltage value VH is, for example, 3V. The first input voltage value VL is, for example, -1V. In addition, the second input voltage value VH is greater than the second threshold voltage value VtH and the first threshold voltage value VtL. Furthermore, the first input voltage value VL is less than the second threshold voltage value VtH and greater than the first threshold voltage value VtL.

[0080] The computational storage unit C(a)mn can receive a read voltage Vread via a bit line BLn to generate a cell current Imn. In operation, the computational storage unit C(a)mn can generate or not generate a cell current Imn in response to different voltage values ​​of the input voltage Vmn and the threshold voltage Vt.

[0081] When the input voltage Vmn received by the operation storage unit C(a)mn is the second input voltage value VH, and the threshold voltage Vt of the transistor TRmn is the first threshold voltage value VtL or the second threshold voltage value VtH, since the input voltage Vmn is greater than the threshold voltage Vt, the transistor TRmn is turned-on (i.e., conductive), so the operation storage unit C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the operation storage unit C(a)mn is the equivalent resistance value Rtr of the transistor TRmn itself connected in parallel with the resistor R(a)mn. In an example, the resistance value of the resistor R(a)mn is much greater than the equivalent resistance value Rtr of the transistor TRmn, so the equivalent impedance of the operation storage unit C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.

[0082] On the other hand, when the input voltage Vmn received by the operation storage unit C(a)mn is the first input voltage value VL, and the threshold voltage Vt of the transistor TRmn is the first threshold voltage value VtL, since the input voltage Vmn is greater than the threshold voltage Vt, the transistor TRmn is turned on, so the operation storage unit C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the operation storage unit C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.

[0083] Furthermore, when the input voltage Vmn received by the operation storage unit C(a)mn is the first input voltage value VL, and the threshold voltage Vt of the transistor TRmn is the second threshold voltage value VtH, since the input voltage Vmn is less than the threshold voltage Vt, the transistor TRmn is turned off (i.e., disconnected), and therefore, the operation storage unit C(a)mn does not generate the cell current Imn. In this case, the equivalent impedance of the operation storage unit C(a)mn is substantially equal to the resistor R(a)inn.

[0084] According to the operation mode of the arithmetic storage unit C(a)inn described above, Table 1 shows a truth table of whether the arithmetic storage unit C(a)mm generates a cell current Imn corresponding to the input value INmn and the weight value Wmn.

[0085] Table 1

[0086]

[0087] Referring to Table 1, when the input value INmn is "0" and the weight value Wmn is "0" or "1", the operation storage unit C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "0", the operation storage unit C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "1", the operation storage unit C(a)mn generates a smaller cell current Imn. Accordingly, the operation storage unit C(a)mn can perform a product operation of the input value INmn and the weight value Wmn, and the cell current Imn generated by the operation storage unit C(a)mn is related to the product of the input value INmn and the weight value Wmn.

[0088] Figure 4B FIG. 1 is a circuit diagram of a computational storage unit C(c)mn according to another embodiment of the present disclosure. The computational storage unit C(c)mn can be used to implement Figure 2 The operation storage units C11-Cmn of the memory array 100 and the balance operation storage units BC11-BCpn. Figure 4A The operation storage unit C(a)mn, Figure 4B The resistor R(c)mn of the operational storage unit C(c)mn is a variable resistor having a variable resistance value, and the resistance value of the resistor R(c)mn can be dynamically adjusted when the memory device is operating. In another example, the resistor R(c)mn has a fixed resistance value, however, the process parameters can be adjusted to adjust the resistance value of the resistor R(c)mn during the manufacturing process. Figure 4B In FIG. 1 , the transistor TRmn is a general transistor.

[0089] The resistor R(c)mn can be adjusted to four resistance values ​​R0, R1, R2, and R3, for example, wherein the resistance value R0 approaches zero and is much smaller than the resistance values ​​R1, R2, and R3. Furthermore, the equivalent resistance value Rtr of the transistor TRmn of the computational storage unit C(c)mn is also much smaller than the resistance values ​​R1, R2, and R3.

[0090] When the weight value Wmn stored in the computation storage unit C(c)mn is "0", the resistor R(c)mn is adjusted to the resistance value R0. Similarly, when the weight value Wmn stored in the computation storage unit C(c)mn is "1", "2", or "3", the resistor R(c)mn is adjusted to the resistance values ​​R1, R2, or R3.

[0091] When the input value INmn is "0", the input voltage Vmn is a second input voltage value VH of a high voltage value, the transistor TRmn is in an on state, the equivalent impedance of the operation storage unit C(c)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn itself, and the operation storage unit C(c)mn generates a cell current Imn. In this case, regardless of whether the weight value Wmn is set to "0", "1", "2" or "3" (i.e., regardless of whether the resistor R(c)mn is adjusted to a resistance value of R0, R1, R2 or R3), the operation storage unit C(c)mn generates a cell current Imn.

[0092] On the other hand, when the input value INmn is "1", the input voltage Vmn is a first input voltage value VL of a low voltage value, the transistor TRmn is in a closed state, and the calculation storage unit C(c)mn does not generate a cell current Imn. When the weight value Wmn is set to "0", "1", "2", or "3", the resistor R(c)mn is adjusted to a resistance value R0, R1, R2, or R3, and the cell current Imn generated by the calculation storage unit C(c)mn is related to the resistance values ​​R0, R1, R2, or R3. Accordingly, the calculation storage unit C(c)mn can perform a product operation, and the cell current Imn generated by the calculation storage unit C(c)mn is related to the product of the input value INmn and the weight value Wmn.

[0093] Figure 4C FIG. 1 is a circuit diagram of a computational storage unit C(d)mn according to another embodiment of the present disclosure. The computational storage unit C(d)mn can be used to implement Figure 2 The operation storage units C11-Cmn of the memory array 100 and the balance operation storage units BC11-BCpn. Figure 4A The operation storage unit C(a)mn, Figure 4C The arithmetic storage unit C(d)mn does not include a resistor. Figure 4C The weight value of the operation storage unit C(d)mn is determined according to the threshold voltage of the transistor TRmn.

[0094] In other possible embodiments of the present disclosure, the operational storage units C11~Cmn and these balanced operational storage units BC11~BCpn may also have other possible implementation architectures, such as but not limited to, (1) the operational storage units C11~Cmn and these balanced operational storage units BC11~BCpn may include a multiplexer and multiple resistors; (2) the operational storage units C11~Cmn and these balanced operational storage units BC11~BCpn may include multiple switch elements and multiple resistors.

[0095] According to the above-mentioned different embodiments of the present disclosure, the operation storage unit and these balanced operation storage units are composed of one or more transistors and / or resistors. The threshold voltage of the transistor can be adjusted to change the weight value stored in the operation storage unit, and the resistance can be adjusted to a high resistance value, a low resistance value or a resistance value of different proportions according to the weight value. In addition, the operation storage unit is controlled to operate in a "conduction state" or a "circuit-off state" according to the input voltage corresponding to the input value, and the read voltage is selectively applied to the transistor or resistor accordingly, so that the operation storage unit generates a corresponding cell current to represent the output value. The output value represents the result of the multiplication operation of the input value and the weight value, and the sum of the products can be obtained by summing. In addition, the operation storage unit may also include a multiplexer. Through the operation of the multiplexer, the read voltage is selectively applied to the resistor on the selected path, so that the operation storage unit performs a logical operation of the input value and the weight value, or a logical operation between the input values ​​of two bits.

[0096] FIG. 5A to FIG. 5C A simulation diagram according to an embodiment of the present disclosure is shown. FIG. 5A to FIG. 5C In the simulation, the memory array 100 has 32 memory cell strings, and each memory cell string has 32 operation memory cells. The high resistance of these operation memory cells and these balance operation memory cells is 555K ohms, and the low resistance of these operation memory cells and these balance operation memory cells is 13.5K ohms. The capacitance value CL of the load capacitor C is 1.5 pF.

[0097] In one embodiment of the present disclosure, the capacitance CL of the load capacitor C can be adjusted to adjust the delay time. In the following, the charging time required for the capacitor voltage VC of the load capacitor C to be charged to a predetermined voltage of 0.35V when the read voltage is 0.5V is used as an example for explanation, but it should be known that the present disclosure is not limited to this. That is, in this example, when the capacitor voltage VC of the load capacitor C reaches 0.7 times the read voltage, it is considered that the memory device 10 has generated a MAC (product sum) result.

[0098] FIG. 5A to FIG. 5C , curve 510A represents the case where the resistance of the impedance element is equal to the high resistance and there are three balanced operation memory cells in each memory cell string. Curve 510B represents the case where the resistance of the impedance element is equal to the high resistance and there are no balanced operation memory cells in each memory cell string. Curve 510C represents the case where each memory cell string has no balanced operation memory cells and no impedance element.

[0099] exist Figure 5A, the numbers of high-impedance states of these operational storage cells of these 32 storage cell strings are [6, 6, 1, 4, 6, 7, 3, 5, 5, 7, 3, 6, 6, 2, 7, 8, 7, 4, 7, 6, 3, 3, 2, 8, 4, 7, 4, 3, 7, 3, 9, 5] respectively.

[0100] exist Figure 5B , the numbers of high-impedance states of these operational storage cells of these 32 storage cell strings are [24, 23, 22, 20, 22, 21, 17, 23, 21, 22, 20, 19, 20, 20, 23, 20, 22, 20, 20, 23, 21, 22, 18, 21, 24, 24, 18, 18, 22, 20, 24, 23] respectively.

[0101] exist Figure 5C , the numbers of high-impedance states of these operational storage cells of these 32 storage cell strings are [7, 4, 7, 6, 3, 3, 2, 8, 4, 7, 4, 3, 7, 3, 9, 5, 24, 23, 22, 20, 22, 21, 17, 23, 21, 22, 20, 19, 20, 20, 23, 20] respectively.

[0102] Depend on FIG. 5A to FIG. 5C It can be seen that in one embodiment of the present disclosure, the delay time is proportional to the product sum. In one embodiment of the present disclosure, the function of the balancing operation storage unit is similar to an impedance element, which is used to limit the current to avoid the fast charging effect.

[0103] In addition, in one embodiment of the present disclosure, since a balanced operation storage unit is introduced, when evaluating the IMC operation result (product sum result), it is necessary to compensate for the influence of the balanced operation storage unit on the operation result. Figure 5C Taking the curve 510A (with balanced operation storage unit) as an example, the delay time corresponding to the product sum result of 400 is 0.4μs, and the delay time corresponding to the product sum result of 0 is 0.1μs. Figure 5C Taking the curve 510C (without any balancing operation storage unit) as an example, the delay time corresponding to the product sum result of 400 is 0.25 μs, and the delay time corresponding to the product sum result of 0 is 0.01 μs. Figure 5C From the curve 510C (without any balancing operation storage unit), the original delay time of 0.12 μs corresponds to the product sum of 200, but Figure 5CFrom the curve 510A (with a balanced operation storage unit), the delay time of 0.25 μs corresponds to an output value of the product-sum result of 200. Therefore, in one embodiment of the present disclosure, when compensating for the influence of the balanced operation storage unit on the operation result, the delay time is shifted backward by about 0.13 μs to correspond to the product-sum result.

[0104] In one embodiment of the present disclosure, a portion of the operation storage cells or a plurality of portions of the operation storage cells of the memory array may be defined as balanced operation storage cells. Moreover, each storage cell string includes the same number "NBW" of balanced operation storage cells and the same number "m" of operation storage cells.

[0105] When an additional high impedance state unit is added to the memory cell string (the high impedance state unit can be caused by impedance elements RS1-RSn or balanced operation memory cells), the current change amount will be [(1 / m)-(1 / (m+1))] when there is no high impedance state unit in the memory cell string. For example, from the following table,

[0106] m [(1 / m)-(1 / (m+1))] m [(1 / m)-(1 / (m+1))] 2 16.7％ 5 3.3％ 3 8.3％ 6 2.4％ 4 5.0％ 7 1.8％

[0107] For example, in each memory cell string, a high impedance state unit is added to make the current change 5%, then 4 high impedance state units need to be added to each memory cell string. Therefore, in one embodiment of the present disclosure, 3 balanced operation memory cells and 1 impedance element can be allocated to each memory cell string.

[0108] Alternatively, if a smaller current change is required, for example, a current change of 2%, then 7 high impedance state cells need to be added to each storage cell string. Therefore, in one embodiment of the present disclosure, 6 balanced operation storage cells and 1 impedance element can be allocated to each storage cell string.

[0109] Furthermore, in an embodiment of the present disclosure, the number of balanced operation storage units may be further adjusted in consideration of linearity, accuracy, chip area usage, and other parameters.

[0110] In one embodiment of the present disclosure, for a given neural network model, the weight values ​​and distribution are known and can be used to assign values ​​of balancing operation storage cells. There are many ways to configure the values ​​of balancing operation storage cells. For example, if the minimum number of high-impedance state storage cells of a storage cell string is "Nmin", the input values ​​of all balancing operation storage cells can be set to "1", and the number of high-impedance cells of this storage cell string can be increased to "Nmin+NBW" to further limit the current. Then, in this way, the values ​​of balancing operation storage cells are assigned to other storage cell strings so that the minimum number of high-impedance cells of each storage cell string is "Nmin+NBW".

[0111] In addition, in one embodiment of the present disclosure, "Nbw,Max" is defined as the number of balancing operation storage cells with a value of "1" in the sensor calculation. The balancing operation storage cells may affect the charging time of the sensor operation. The more balancing operation storage cells are assigned to "1", the longer the charging time is, and the greater the sensing overhead is.

[0112] Therefore, in one embodiment of the present disclosure, the number of "Nbw,Max" is limited to reduce the sensing overhead. For example, to limit the sensing overhead to 10%, the estimated maximum perceptron output value can be calculated, and "Nbw,Max" can be defined as 1 / 10 of the estimated maximum perceptron output value. For example, if the estimated maximum perceptron output value is about 164, then "Nbw,Max" can be defined as 16. Alternatively, in one embodiment of the present disclosure, "Nbw,Max" may be defined as approximately half of the total number of balanced operation storage units. This depends on the weight distribution.

[0113] In each memory cell string, the number of balancing operation memory cells may be 1 or greater than 1, and each memory cell string has the same number of balancing operation memory cells.

[0114] The input value of the balancing operation memory cell is set to "1" to enable the contribution of the balancing operation memory cell to each memory cell string.

[0115] The balancing operation storage unit may be placed at the beginning, end or other position of the storage unit string.

[0116] The impedance state of the balanced operation memory cell depends on the weight value distribution of the memory array.

[0117] In conventional technology, when performing IMC operation, fast charging behavior may occur. Fast charging behavior means that when all operation storage cells of the same storage cell string are in a low impedance state or only a few operation storage cells of the same storage cell string are in a high impedance state, the equivalent impedance of the same storage cell string is too low, so that the current of the same storage cell string is too high, and the charging current of the load capacitor C is too high, so that the potential of the load capacitor C rises rapidly, which leads to the possibility of misjudgment.

[0118] Therefore, in one embodiment of the present disclosure, these balancing operation storage cells BC11~BCpn and / or impedance elements RS1~RSn are additionally added to these storage cell strings S1~Sn to increase the equivalent impedance of these storage cell strings S1~Sn, so as to effectively reduce or avoid the rapid charging behavior. Even when all the operation storage cells of the same storage cell string are in a low impedance state, due to the additional addition of these balancing operation storage cells BC11~BCpn and / or impedance elements RS1~RSn (impedance elements RS1~RSn), the equivalent impedance of the same storage cell string will not be too low, so that the current of the same storage cell string will not be too high, the charging current of the load capacitor C will not be too high, and the potential of the load capacitor C will not increase rapidly, thereby reducing the possibility of misjudgment.

[0119] In one embodiment of the present disclosure, the operation storage units and the balanced operation storage units have at least two impedance states, a high impedance state and a low impedance state. When the operation storage units are in the high impedance state (also referred to as the first impedance state), the operation storage units have a high impedance value RH (also referred to as the first impedance value); and when the operation storage units are in the low impedance state (also referred to as the second impedance state), the operation storage units have a low impedance value RL (also referred to as the second impedance value).

[0120] In one embodiment of the present disclosure, the equivalent impedance RS of these impedance elements RS1-RSn is, for example but not limited to, RS=2RL, or RS=5RL, which can effectively reduce the fast charging behavior. In one embodiment of the present disclosure, the equivalent impedance RS of these impedance elements RS1-RSn is, for example but not limited to, RS=10RL, or RS≥0.5*RH, which can effectively avoid or even completely avoid the fast charging behavior.

[0121] It can be seen that the embodiments of the present disclosure can indeed reduce or avoid fast charging behavior, thereby reducing the possibility of misjudgment.

[0122] In one embodiment of the present disclosure, these impedance elements RS1-RSn are, for example, but not limited to, a resistor formed by a process. Alternatively, in one embodiment of the present disclosure, these impedance elements RS1-RSn are, for example, but not limited to, a transistor. Alternatively, in one embodiment of the present disclosure, these impedance elements RS1-RSn are, for example, but not limited to, a combination of a transistor and a resistor, and when performing a programming operation or calculating a storage unit weight adjustment, the transistor is turned on, and when performing a sensing operation, the transistor is turned off.

[0123] In one embodiment of the present disclosure, by adjusting the capacitance value of the load capacitor, the power consumption of the IMC operation of the IMC memory device can be adjusted to a reasonable range. In addition, for a given number of input values ​​and number of operation storage cells, properly arranging the number of storage cell strings and the number of operation storage cells in each storage cell string can also help adjust the power consumption.

[0124] In an embodiment of the present disclosure, the number of operational storage cells in a storage cell string is at least greater than or equal to 2, and the number of storage cell strings in the memory array can be arbitrary. Moreover, the impedance value of the operational storage cell can be changed by an input value.

[0125] In one embodiment of the present disclosure, when the memory device 10 is a NAND memory device, the read voltage Vread is lower than 1V.

[0126] In an embodiment of the present disclosure, the memory device 10 may be applied to, for example but not limited to, calculation of a neural network, or a product-sum operation, or comparing input data with stored data.

[0127] In other possible embodiments of the present disclosure, the operational storage units and the balanced operational storage units have three or more impedance states (ie, three or more impedance values), which are all within the scope of the present disclosure.

[0128] In an embodiment of the present disclosure, since a voltage summing architecture is not used to perform IMC, more input values ​​can be calculated simultaneously, and only a single sense amplifier can be used to satisfy IMC. The embodiment of the present disclosure has the advantage of reducing read errors and power consumption.

[0129] The IMC memory device of one embodiment of the present disclosure is a hybrid mode of a current summing architecture and a voltage summing architecture, which allows more input values ​​to be calculated simultaneously and can avoid the problems caused by a larger summing current in the current summing architecture and the problems caused by a low sensing current in the voltage summing architecture.

[0130] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. An in-memory computing (IMC) memory device, characterized in that: include: a memory control circuit, and A memory array is coupled to the memory control circuit, and the memory array includes: A plurality of operation storage units and a plurality of balance operation storage units form a plurality of storage unit strings, and the operation storage units store a plurality of weight values; A load capacitor coupled to the operational storage units; and a measuring circuit coupled to the load capacitor, Wherein, during programming, the memory control circuit determines the number of the first impedance states of the balanced operational storage cells of the memory cell string according to the number of the first impedance states of the operational storage cells in the memory cell string; Among them, when performing calculations, A plurality of input voltages are respectively input to the operation storage units. The input voltages are related to a plurality of input values. The memory control circuit sets the input voltages according to the input values. A plurality of balanced input voltages are respectively input to the balanced operation storage units, the balanced input voltages are related to a plurality of balanced input values, the balanced input values ​​are consistent input values, and the memory control circuit sets the balanced input voltages according to the balanced input values; The effective impedance values ​​of the operation storage units are related to the input voltages and the weight values. When a read voltage is applied to the operational memory cells, the operational memory cells generate a plurality of memory cell currents, which form a plurality of memory cell string currents. The memory cell string currents generated by the memory cell strings charge the load capacitor. The measuring circuit measures a capacitance voltage of the load capacitance, and A calculation result of the input values ​​and the weight values ​​is determined according to a relationship among the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage.

2. The in-memory computing (IMC) memory device according to claim 1, characterized in that in, The operation storage units and the balanced operation storage units have a first impedance value and a second impedance value, wherein the first impedance value is higher than the second impedance value. The first impedance state number of the operational storage cells represents a number of the operational storage cells programmed to the first impedance value, and the first impedance state number of the balanced operational storage cells represents a number of the balanced operational storage cells programmed to the first impedance value, Each storage unit string includes at least two operation storage units connected in series, These storage units are connected in series and in parallel. The delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to the predetermined voltage, and the predetermined voltage is determined according to the read voltage.

3. The in-memory computing (IMC) memory device according to claim 1, wherein: in, At a plurality of predetermined delay times, it is checked whether the capacitor voltage reaches the predetermined voltage to obtain a comparison result, wherein the comparison result represents the operation result of the input values ​​and the weight values.

4. The in-memory computing (IMC) memory device according to claim 1, wherein: Also includes: A plurality of impedance elements are formed in the memory cell strings, and the impedance elements are connected in series to the operational memory cells and the balanced operational memory cells.

5. The in-memory computing (IMC) memory device according to claim 4, characterized in that: in, The operational storage units and the balanced operational storage units have a first impedance value and a second impedance value, the first impedance value is higher than the second impedance value; and An equivalent impedance of these impedance elements is equal to or higher than twice the second impedance value, or the equivalent impedance of these impedance elements is equal to or higher than half of the first impedance value.

6. The in-memory computing (IMC) memory device of claim 1, wherein: in, In the memory cell strings, the number of the balancing operation memory cells is 1 or greater than 1, and the memory cell strings have the same number of the balancing operation memory cells; and In these memory cell strings, these balancing operation memory cells are located at a beginning, an end or other positions of these memory cell strings.

7. The in-memory computing (IMC) memory device of claim 1, wherein: in, The operational memory cells and the balanced operational memory cells have three or more impedance states.

8. An in-memory computing method, characterized in that: Applied to an in-memory computing memory device, the in-memory computing memory device includes a plurality of computing storage units and a plurality of balancing computing storage units constituting a plurality of storage unit strings, the in-memory computing method includes: During programming, the number of first impedance states of the balanced operational memory cells of the memory cell string is determined according to the number of first impedance states of the operational memory cells in the memory cell string; Storing a plurality of weight values ​​in a plurality of operation storage units, wherein the operation storage units constitute a plurality of storage unit strings; Inputting a plurality of input voltages to the operation storage units respectively, wherein the input voltages are related to a plurality of input values, and a plurality of effective impedance values ​​of the operation storage units are related to the input voltages and the weight values; Inputting a plurality of balanced input voltages to the balanced operation storage units respectively, wherein the balanced input voltages are related to a plurality of balanced input values, wherein the balanced input values ​​are consistent input values, and the balanced input voltages are set according to the balanced input values; When a read voltage is applied to the operational memory cells, the operational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory cell string currents; The memory cell string currents generated by the memory cell strings charge the load capacitors; measuring a capacitance voltage of the load capacitance; and A calculation result of the input values ​​and the weight values ​​is determined according to a relationship among the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage.

9. The in-memory computing method according to claim 8, characterized in that: in, The operation storage units and the balanced operation storage units have a first impedance value and a second impedance value, wherein the first impedance value is higher than the second impedance value. The first impedance state number of the operational storage cells represents a number of the operational storage cells programmed to the first impedance value, and the first impedance state number of the balanced operational storage cells represents a number of the balanced operational storage cells programmed to the first impedance value, The delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to the predetermined voltage, and the predetermined voltage is determined according to the read voltage.

10. The in-memory computing method according to claim 8, characterized in that: in, At a plurality of predetermined delay times, it is checked whether the capacitor voltage reaches the predetermined voltage to obtain a comparison result, wherein the comparison result represents the operation result of the input values ​​and the weight values.

11. The in-memory computing method according to claim 8, characterized in that: in, The in-memory computing memory device further includes: a plurality of impedance elements formed within the storage unit strings, the impedance elements being connected in series to the operation storage units and the balance operation storage units; The operational storage units and the balanced operational storage units have a first impedance value and a second impedance value, the first impedance value is higher than the second impedance value; and An equivalent impedance of these impedance elements is equal to or higher than twice the second impedance value, or the equivalent impedance of these impedance elements is equal to or higher than half of the first impedance value.

12. The in-memory computing method according to claim 8, characterized in that: in, In the memory cell strings, the number of the balancing operation memory cells is 1 or greater than 1, and the memory cell strings have the same number of the balancing operation memory cells; and In these memory cell strings, these balancing operation memory cells are located at a beginning, an end or other positions of these memory cell strings.

13. The in-memory computing method according to claim 8, characterized in that: in, The operational memory cells and the balanced operational memory cells have three or more impedance states.

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