Battery addressing circuit and battery pack

Abstract

The invention is suitable for the technical field of battery energy storage, and particularly relates to a battery addressing circuit and a battery pack. The battery addressing circuit comprises a control chip, a receiving circuit and an output circuit, the receiving circuit and the output circuit are connected with the control chip, the receiving circuit is connected with an output circuit of a previous battery pack or a battery host, and when the battery pack is not the last battery pack, the output circuit is used for being connected with a receiving circuit of a next battery pack. The control chip is connected with the output circuit, if the output circuit is connected with the receiving circuit, a first voltage is obtained, if the output circuit is not connected with the receiving circuit, a second voltage is obtained, when the addressing signal and the first voltage are obtained, the control chip controls the output circuit to output the addressing signal, and when the addressing signal and the second voltage are obtained, the control chip feeds back an addressing ending signal to the battery host. And the last battery pack is identified according to the first voltage and the second voltage, so that addressing can be completed in sequence according to a series connection sequence without sending addressing to each battery pack one by one, the communication frequency is effectively reduced, and the addressing efficiency is improved.

Description

Technical Field

[0001] The present application is applicable to the field of battery energy storage technology, and in particular relates to a battery addressing circuit and a battery pack. Background Art

[0002] With the development of new energy technology, batteries, as the application basis of energy storage technology, need to be precisely controlled. Most existing battery packs are built with many battery packs. Therefore, the addressing of battery packs needs to be accurate and efficient. The existing battery pack contains a battery control box (specifically, an HVB high-voltage box) and at least one battery pack. For battery packs with multiple battery packs, since each PACK (battery pack) slave is stacked arbitrarily, the host (i.e., the HVB high-voltage box) cannot identify the physical location of each PACK slave. Therefore, after the battery system is powered on for the first time, the host will set the address of each PACK slave.

[0003] At present, the battery pack is addressed by serial addressing. The host sends an addressing signal, and the first PACK slave receives the addressing signal from the host. Then, the first PACK slave is addressed as 1. After the addressing is completed, the first PACK slave feeds back to the host that the addressing is completed. Then, the first PACK slave sends an addressing signal to the second PACK slave with the addressing being 2. The addressing of the second PACK slave is completed, and the second PACK slave feeds back to the host that the addressing is completed. The above steps are repeated until all battery packs are addressed.

[0004] Since the above steps cannot identify the last PACK slave, the host needs to send addressing to PACK1. After addressing is successful, the addressing success instruction is returned to the host. The host then sends addressing to PACK2. After addressing is successful, the addressing success instruction is returned to the host. This requires returning the addressing success information to the host after each addressing is completed. If there are 3 PACK slaves, the addressing is sent and returned 6 times, and the addressing efficiency is slow.

[0005] Therefore, how to improve the addressing circuit in the battery pack so that the PACK slave can automatically identify the last PACK slave, thereby improving the addressing efficiency, becomes an urgent problem to be solved. Summary of the invention

[0006] In view of this, an embodiment of the present application provides a battery addressing circuit and a battery pack to solve the problem of how to improve the addressing circuit in the battery pack so that the PACK slave can automatically identify the last PACK slave, thereby improving the addressing efficiency.

[0007] In a first aspect, an embodiment of the present application provides a battery addressing circuit, the battery addressing circuit is applied to a battery pack consisting of a battery host and at least one battery pack belonging to the battery host, the battery host and the battery pack each include a control chip, a receiving circuit and an output circuit, the receiving circuit and the output circuit are respectively connected to the control chip; The receiving circuit is used to connect to the power-on signal or the output circuit of the previous battery pack or the battery host. When the battery pack to which the output circuit belongs is not the last battery pack, the output circuit is used to connect to the receiving circuit of the next battery pack; If the output circuit is connected to the receiving circuit, a first voltage is detected on the output circuit; if the output circuit is not connected to the receiving circuit, a second voltage is detected on the output circuit, and the first voltage is not equal to the second voltage; When the power-on signal or the addressing signal of the battery host or the previous battery pack and the first voltage are obtained, the control chip controls the output circuit to output the addressing signal of the next battery pack, and when the addressing signal of the battery host or the previous battery pack and the second voltage are obtained, the control chip feeds back an addressing end signal to the battery host; When the receiving circuit obtains an addressing signal, it instructs the control chip to perform addressing and controls the output circuit to output the addressing signal of the next battery pack.

[0008] In a second aspect, an embodiment of the present application provides a battery pack, comprising a battery host and at least one battery pack belonging to the battery host, wherein the battery host and the battery pack both include a control chip, a receiving circuit and an output circuit in the battery addressing circuit described in the first aspect above.

[0009] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the battery addressing circuit of the present application is applied to a battery pack consisting of a battery host and at least one battery pack belonging to the battery host, the battery host and the battery pack both include a control chip, a receiving circuit and an output circuit, the receiving circuit and the output circuit are respectively connected to the control chip; the receiving circuit is used to connect to a power-on signal or an output circuit of the previous battery pack or the battery host, and when the battery pack to which the output circuit belongs is not the last battery pack, the output circuit is used to connect to the receiving circuit of the next battery pack; if the output circuit is connected to the receiving circuit, then the receiving circuit is connected to the output circuit. A first voltage is detected on the circuit. If the output circuit is not connected to the receiving circuit, a second voltage is detected on the output circuit, and the first voltage is not equal to the second voltage. When the power-on signal or the addressing signal of the battery host or the previous battery pack and the first voltage are obtained, the control chip controls the output circuit to output the addressing signal of the next battery pack. When the addressing signal of the battery host or the previous battery pack and the second voltage are obtained, the control chip feeds back an addressing end signal to the battery host. When the receiving circuit obtains an addressing signal, the control chip is instructed to address and control the output circuit to output the addressing signal of the next battery pack. The above circuit structure can identify the last battery pack according to the first voltage and the second voltage, so that in the addressing process, it is not necessary to send the address to each battery pack one by one, and the addressing can be completed in sequence in the order of series connection, which effectively reduces the number of communications and improves the addressing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 It is a structural schematic diagram of a battery addressing circuit provided in Example 1 of the present application; Figure 2 This is a connection diagram of a battery addressing circuit provided in Example 2 of the present application; Figure 3 This is a connection diagram of a battery addressing circuit provided in Example 3 of the present application; Figure 4 This is a schematic diagram of a battery addressing process provided in Example 4 of the present application; Figure 5 This is a connection diagram of CAN communication provided in Example 5 of the present application. DETAILED DESCRIPTION

[0012] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0013] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0014] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0015] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0016] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0017] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0018] It should be understood that the size of the serial numbers of the steps in the following embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0019] In order to illustrate the technical solution of the present application, a specific embodiment is provided below for illustration.

[0020] See also Figure 1 , which is a structural schematic diagram of a battery addressing circuit provided in Example 1 of the present application, wherein a host (i.e., HVB) and two battery packs (i.e., PACK1 and PACK2) are provided. As an example, the host and the two battery packs subordinate to the host form a battery pack. It can be seen that the battery host and the battery pack both include a control chip, a receiving circuit and an output circuit. In any device, the receiving circuit and the output circuit are respectively connected to the control chip, the signal received by the receiving circuit is sent to the control chip, and the control chip generates a control signal and sends it to the output circuit.

[0021] like Figure 1 As shown, the receiving circuit of HVB is connected to the power-on signal, the output circuit of HVB is connected to the receiving circuit of PACK1 (i.e., the next battery pack), and the receiving circuit of PACK1 is connected to the output circuit of HVB, the output circuit of PACK1 is connected to the receiving circuit of PACK2 (i.e., the next battery pack), the receiving circuit of PACK2 is connected to the output circuit of PACK1 (i.e., the previous battery pack), and the output circuit of PACK2 has no receiving circuit connected to it, that is, PACK2 is the last battery pack.

[0022] That is, when the battery pack to which the output circuit belongs is not the last battery pack, the output circuit is used to connect to the receiving circuit of the next battery pack.

[0023] The output circuit in the current battery pack is connected to the receiving circuit of the next battery pack, which will change the voltage on the output circuit. Therefore, if the output circuit is connected to the receiving circuit, a first voltage is detected on the output circuit. If the output circuit is not connected to the receiving circuit, a second voltage is detected on the output circuit. The first voltage is not equal to the second voltage. Specifically, the voltage detection can be for the voltage at the output port of the output circuit. In one embodiment, the first voltage is greater than the second voltage, that is, the receiving circuit forms a voltage divider for the voltage at the output port of the output circuit. Of course, according to the design of the receiving circuit, the first voltage can also be made smaller than the second voltage.

[0024] For the HVB, when the power-on signal and the first voltage are obtained, it indicates that its output circuit is connected to the receiving circuit of the next battery pack. At this time, the power-on signal is used to instruct the control chip of the HVB to address the battery pack connected to it, thereby causing the output circuit of the HVB to output an addressing signal.

[0025] For a battery pack, when the receiving circuit of PACK1 receives the addressing signal of the battery host and the control chip obtains the first voltage through the output circuit, it indicates that the output circuit of PACK1 is connected to the receiving circuit of the next battery pack. At this time, the control chip of PACK1 performs addressing according to the received addressing signal and controls the output circuit to output the addressing signal to instruct the next battery pack to perform addressing. When the receiving circuit of PACK2 receives the addressing signal of the previous battery pack and the control chip obtains the second voltage through the output circuit, it indicates that PACK2 is the last battery pack and there is no battery pack connected thereafter. At this time, the control chip of PACK2 feeds back the addressing end signal to the battery host, and the addressing of the battery packs in the battery pack can be completed.

[0026] Specifically, the addressing process is that after power-on, HVB detects whether the next PACK is connected. If so, HVB sends an addressing instruction to PACK1. After receiving it, PACK1 sets the address to 1. Then PACK1 detects whether the next PACK is connected. If so, PACK1 sends an addressing instruction to PACK2. After receiving it, PACK2 sets the address to 2. The addressing is continued downward until the last PACK. After the last PACK receives the addressing instruction, it is set to the address of the last PACK. At the same time, the last PACK can detect that its position is at the end. After the last PACK is addressed, it will no longer address downwards. Then, the addressing completion information is sent to the host HVB through CAN communication to complete the addressing.

[0027] The battery addressing circuit of the present application is applied to a battery pack consisting of a battery host and at least one battery pack belonging to the battery host, wherein the battery host and the battery pack each include a control chip, a receiving circuit and an output circuit, wherein the receiving circuit and the output circuit are respectively connected to the control chip; the receiving circuit is used to connect to a power-on signal or an output circuit of a previous battery pack or the battery host, and when the battery pack to which the output circuit belongs is not the last battery pack, the output circuit is used to connect to the receiving circuit of the next battery pack; if the output circuit is connected to the receiving circuit, a first voltage is detected on the output circuit, and if If the output circuit is not connected to the receiving circuit, a second voltage is detected on the output circuit, and the first voltage is not equal to the second voltage; when the power-on signal or the addressing signal of the battery host or the previous battery pack and the first voltage are obtained, the control chip controls the output circuit to output the addressing signal of the next battery pack, and when the addressing signal of the battery host or the previous battery pack and the second voltage are obtained, the control chip feeds back an addressing end signal to the battery host; when the receiving circuit obtains an addressing signal, it instructs the control chip to address and control the output circuit to output the addressing signal of the next battery pack. The above circuit structure can identify the last battery pack according to the first voltage and the second voltage, so that in the addressing process, there is no need to send addressing to each battery pack one by one, and the addressing can be completed in sequence in the order of series connection, which effectively reduces the number of communications and improves the addressing efficiency.

[0028] See also Figure 2 , is a connection diagram of a battery addressing circuit provided in Embodiment 2 of the present application, wherein: Figure 2 The connection diagram of the receiving circuit is specifically shown in FIG. The receiving circuit includes a first input terminal (i.e., ID_IN) and a first output terminal (i.e., MCU_ID_IN), the first input terminal is used to connect to a power-on signal, an output circuit of a battery host, or an output circuit of a previous battery pack, the first output terminal is connected to a corresponding control chip, and a first level flip branch is provided between the first input terminal and the first output terminal, the first level flip branch is used to output a high level at the first output terminal when a low level is input to the first input terminal, and output a low level at the first output terminal when a high level is input to the first input terminal.

[0029] For example, when the first input terminal does not receive an addressing signal or a power-on signal, the level given to the control chip by the first output terminal is a high level. When the first input terminal receives an addressing signal or a power-on signal, after passing through the first level flipping branch, the level given to the control chip by the first output terminal becomes a low level. Therefore, it is possible to determine whether the addressing signal is received based on the change in the level. In addition, after the first input terminal is connected to the first level flipping branch, it is necessary to supply power to the first level flipping branch, thereby reducing the voltage at the output terminal of the output circuit connected to the first input terminal.

[0030] like Figure 2 As shown, the first level flipping branch includes a first switch tube (i.e., Q53), the control end of the first switch tube is connected to the first input end, the input end of the first switch tube is used to connect to the first voltage source (i.e., a +3.3V voltage source), the output end of the first switch tube is grounded (i.e., GND-S), and the first output end is connected to the line between the input end of the first switch tube and the first voltage source. When the first input end is at a high level, the first switch tube is turned on, so that the first output end is pulled down to a low level, and the level signal can be flipped using the switch tube, thereby improving the control accuracy.

[0031] In one embodiment, a first resistor (R222) is provided between the control end of the first switch tube and the first input end, a second resistor (R52) and a first capacitor (C94) connected in parallel with the second resistor are connected between the control end of the first switch tube and the output end of the first switch tube, a third resistor (R58) is provided between the input end of the first switch tube and the first voltage source, the first output end is connected to the line between the third resistor and the input end of the first switch tube through a fourth resistor (R125), and the output end of the first switch tube is connected to the line between the first output end and the fourth resistor through a second capacitor (C92). The above arrangement can effectively improve the stability of the circuit, thereby avoiding false triggering of the signal.

[0032] See also Figure 3 , is a connection diagram of a battery addressing circuit provided in Embodiment 2 of the present application, wherein: Figure 3 The connection diagram of the output circuit is specifically shown in FIG. The output circuit includes an output part and a detection part. The output part includes a second input terminal (i.e., MCU_ID_OUT) and a second output terminal (i.e., ID_OUT). The second input terminal is connected to the corresponding control chip, and the second output terminal is connected to the receiving circuit of the next battery pack.

[0033] A second level flipping branch is arranged between the second input terminal and the second output terminal, and the second level flipping branch is used to output a high level at the second output terminal when a low level is input at the second input terminal, and to output a low level at the second output terminal when a high level is input at the second input terminal; the detection part includes a voltage detection branch, the detection end of the voltage detection branch is connected to the second output terminal, and the voltage signal output end (i.e., ID_OUT_V) of the voltage detection branch is connected to the control chip of the corresponding battery pack.

[0034] For example, when an addressing signal is given at the second input terminal, the level of the second output terminal is a high level. When an addressing signal is given at the second input terminal, the level of the second output terminal becomes a low level after passing through the second level flipping branch. In addition, the level of the second output terminal is normally a high level, that is, the voltage detection branch can detect a high-level voltage at the second output terminal. If the second output terminal is connected to a receiving circuit, the voltage will be pulled down, so that the voltage detection branch detects a relatively low voltage.

[0035] like Figure 3 As shown, the second level flip branch includes a second switch tube (i.e., Q52), the control end of the second switch tube is connected to the second input end, the input end of the second switch tube is used to connect to the second voltage source (i.e., a +3.3V voltage source), the output end of the second switch tube is grounded, and the second output end is connected to the line between the input end of the second switch tube and the second voltage source. In one embodiment, the first voltage source and the second voltage source may be different in size.

[0036] In one embodiment, a fifth resistor (R29) is provided between the control end of the second switch tube and the second input end, a sixth resistor (R43) and a third capacitor (C88) connected in parallel with the sixth resistor are connected between the control end of the second switch tube and the output end of the second switch tube, a seventh resistor (R52) is provided between the input end of the second switch tube and the second voltage source, the second output end is connected to the line between the seventh resistor and the input end of the second switch tube through an eighth resistor (R221) and a first diode (D19), the output end of the second switch tube is connected to the line between the second output end and the first diode through a fourth capacitor (C99), the output end of the second switch tube is also connected to the line between the second output end and the first diode through a voltage regulator diode (D67), the voltage regulator diode is provided close to the first diode, and the fourth capacitor is provided close to the second output end. The above arrangement can effectively improve the stability of the circuit, thereby avoiding false triggering of the signal.

[0037] In one embodiment, the voltage detection branch includes a detection end and a voltage signal output end, a ninth resistor (i.e., R214) is provided between the detection end and the voltage signal output end, a grounding voltage stabilization branch and a bidirectional protection branch are provided between the voltage signal output end and the ninth resistor, the grounding voltage stabilization branch includes a fifth capacitor (i.e., C95), one end of the fifth capacitor is connected to the line between the voltage signal output end and the ninth resistor, the other end of the fifth capacitor is grounded, the bidirectional protection branch includes a second diode and a third diode, the two diodes form D69, D69 has three ports 1, 2, and 3, the output end of the second diode is connected to the input end of the third diode (i.e., end 3 of D69) and connected to the line between the voltage signal output end and the ninth resistor, the input end of the second diode (i.e., end 1 of D69) is grounded, and the output end of the third diode (i.e., end 2 of D69) is used to connect a third voltage source (i.e., a voltage source of +3.3V). In one embodiment, the voltage of the third voltage source may be different from that of the first voltage source and the second voltage source.

[0038] like Figure 3 As shown, the detection end of the voltage detection branch is connected to the line between the voltage stabilizing diode and the fourth capacitor, thereby realizing the collection of the voltage there, and being used to obtain the first voltage and the second voltage, which can reduce the influence of voltage changes to a certain extent.

[0039] See also Figure 4 , which is a schematic diagram of a battery addressing process provided in the fourth embodiment of the present application, wherein the previous PACK or host outputs an addressing signal, and then outputs the addressing signal through the output pin ID_OUT, and the end PACK or the next PACK access identification function: the circuit can simultaneously detect whether the next PACK is connected and whether the current PACK is the last PACK. The detection pin is ID_OUT_V. After receiving the addressing signal, the MCU_ID_IN pin level is flipped, and then PACK addressing is performed.

[0040] The control chip returns the addressing end signal to the host through CAN communication. When the last PACK is addressed, the addressing ends. After the last PACK sends the addressing end signal to the host, the entire addressing process is completed.

[0041] When addressing begins, the host sends an addressing signal to address the last PACK in sequence. When the last PACK detects that it is the last one, addressing is completed. The time to complete addressing is more efficient and faster than the existing solution.

[0042] like Figure 5 As shown, it is a connection diagram of CAN communication provided in Embodiment 5 of the present application, in which signal forwarding is realized through the CAN channel, thereby realizing communication between the battery pack and the battery host.

[0043] In one embodiment, the present application also provides a battery pack, including a battery host and at least one battery pack belonging to the battery host, and the battery host and the battery pack both include the control chip, receiving circuit and output circuit in the above-mentioned battery addressing circuit.

[0044] Any control chip in the present application may include: at least one processor, a memory, and a computer program stored in the memory and executable on at least one processor, and the processor implements the steps of any of the above-mentioned battery addressing circuit embodiments when executing the computer program. The control chip may include, but is not limited to, a processor and a memory. The so-called processor may be a CPU, and the processor may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application-specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0045] The memory includes a readable storage medium, an internal memory, etc., wherein the internal memory may be the memory of the control chip, and the internal memory provides an environment for the operation of the operating system and computer-readable instructions in the readable storage medium. The readable storage medium may be the hard disk of the control chip, and in other embodiments, it may also be an external storage device of the control chip, for example, a plug-in hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash card (FlashCard), etc. equipped on the control chip. Furthermore, the memory may also include both an internal storage unit of the control chip and an external storage device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of a computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.

[0046] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned device can refer to the corresponding process in the above-mentioned method embodiment, which will not be repeated here. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying computer program code, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0047] The present application implements all or part of the processes in the above-mentioned embodiment method, and may also be completed through a computer program product. When the computer program product runs on a control chip, the control chip can implement the steps in the above-mentioned method embodiment when it is executed.

[0048] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0049] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0050] In the embodiments provided in the present application, it should be understood that the disclosed device / control chip and method can be implemented in other ways. For example, the device / control chip embodiments described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0051] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0052] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A battery addressing circuit, characterized in that: The battery addressing circuit is applied to a battery pack consisting of a battery host and at least one battery pack belonging to the battery host, wherein the battery host and the battery pack each include a control chip, a receiving circuit and an output circuit, and the receiving circuit and the output circuit are respectively connected to the control chip; The receiving circuit is used to connect to the power-on signal or the output circuit of the previous battery pack or the battery host. When the battery pack to which the output circuit belongs is not the last battery pack, the output circuit is used to connect to the receiving circuit of the next battery pack; If the output circuit is connected to the receiving circuit, a first voltage is detected on the output circuit; if the output circuit is not connected to the receiving circuit, a second voltage is detected on the output circuit, and the first voltage is not equal to the second voltage; When the power-on signal or the addressing signal of the battery host or the previous battery pack and the first voltage are obtained, the control chip controls the output circuit to output the addressing signal of the next battery pack, and when the addressing signal of the battery host or the previous battery pack and the second voltage are obtained, the control chip feeds back an addressing end signal to the battery host; When the receiving circuit obtains an addressing signal, it instructs the control chip to perform addressing and controls the output circuit to output the addressing signal of the next battery pack.

2. The battery addressing circuit according to claim 1, characterized in that: The receiving circuit includes a first input terminal and a first output terminal, and a first level flipping branch is arranged between the first input terminal and the first output terminal. The first level flipping branch is used to output a high level at the first output terminal when a low level is input to the first input terminal, and to output a low level at the first output terminal when a high level is input to the first input terminal.

3. The battery addressing circuit according to claim 2, characterized in that: The first level flip branch includes a first switch tube, a control end of the first switch tube is connected to the first input end, the input end of the first switch tube is used to connect to a first voltage source, the output end of the first switch tube is grounded, and the first output end is connected to the line between the input end of the first switch tube and the first voltage source.

4. The battery addressing circuit according to claim 3, characterized in that: A first resistor is provided between the control end of the first switch tube and the first input end, and a second resistor and a first capacitor connected in parallel with the second resistor are connected between the control end of the first switch tube and the output end of the first switch tube; A third resistor is provided between the input end of the first switch tube and the first voltage source, and the first output end is connected to a line between the third resistor and the input end of the first switch tube through a fourth resistor; The output end of the first switch tube is connected to a line between the first output end and the fourth resistor through a second capacitor.

5. The battery addressing circuit according to claim 1, characterized in that: The output circuit includes an output part and a detection part, the output part includes a second input end and a second output end, a second level flipping branch is provided between the second input end and the second output end, the second level flipping branch is used to output a high level at the second output end when a low level is input to the second input end, and to output a low level at the second output end when a high level is input to the second input end; The detection part includes a voltage detection branch, a detection end of the voltage detection branch is connected to the second output end, and a voltage signal output end of the voltage detection branch is connected to a control chip of a corresponding battery pack.

6. The battery addressing circuit according to claim 5, characterized in that: The second level flip branch includes a second switch tube, the control end of the second switch tube is connected to the second input end, the input end of the second switch tube is used to connect to a second voltage source, the output end of the second switch tube is grounded, and the second output end is connected to the line between the input end of the second switch tube and the second voltage source.

7. The battery addressing circuit according to claim 6, characterized in that: A fifth resistor is provided between the control end of the second switch tube and the second input end, and a sixth resistor and a third capacitor connected in parallel with the sixth resistor are connected between the control end of the second switch tube and the output end of the second switch tube; A seventh resistor is provided between the input end of the second switch tube and the second voltage source, and the second output end is connected to the line between the seventh resistor and the input end of the second switch tube through an eighth resistor and a first diode; The output end of the second switching tube is connected to the line between the second output end and the first diode through a fourth capacitor, and the output end of the second switching tube is also connected to the line between the second output end and the first diode through a voltage regulator diode. The voltage regulator diode is arranged close to the first diode, and the fourth capacitor is arranged close to the second output end.

8. The battery addressing circuit according to claim 5, characterized in that: The voltage detection branch includes a detection end and a voltage signal output end, a ninth resistor is arranged between the detection end and the voltage signal output end, and a grounding voltage stabilization branch and a bidirectional protection branch are arranged between the voltage signal output end and the ninth resistor; The grounding voltage stabilization branch includes a fifth capacitor, one end of the fifth capacitor is connected to the line between the voltage signal output end and the ninth resistor, and the other end of the fifth capacitor is grounded; The bidirectional protection branch includes a second diode and a third diode, the output end of the second diode is connected to the input end of the third diode and is connected to the line between the voltage signal output end and the ninth resistor, the input end of the second diode is grounded, and the output end of the third diode is used to connect to a third voltage source.

9. The battery addressing circuit according to claim 8, characterized in that: The detection end is connected to a line between the voltage stabilizing diode and the fourth capacitor.

10. A battery pack, characterized in that: It comprises a battery host and at least one battery pack belonging to the battery host, wherein the battery host and the battery pack both comprise a control chip, a receiving circuit and an output circuit in the battery addressing circuit as described in any one of claims 1 to 9.

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