InAs / InP quantum dot single photon source device and preparation method thereof

Abstract

The invention discloses an InAs / InP quantum dot single photon source device and a preparation method thereof, and the method comprises the steps: preparing an InP substrate which sequentially comprises an InAs / InP quantum dot layer, an InGaAs sacrificial layer and an InP substrate layer from top to bottom; depositing a SiO2 spacer layer on the surface of the InAs / InP quantum dot layer of the InP substrate; evaporating an Au mirror layer on the surface of the SiO2 spacer layer; evaporating an Au mirror layer on the surface of the GaAs substrate; combining the Au mirror layer of the InP substrate with the Au mirror layer of the GaAs substrate by using a flip-chip bonding technology; removing the InP substrate layer and the InGaAs sacrificial layer through wet etching; depositing a first mask layer on the surface of the InAs / InP quantum dot layer; preparing a second mask layer on the surface of the first mask layer, and exposing and developing; performing dry etching on the first mask layer; and performing dry etching on the InAs / InP quantum dot layer to obtain the InAs / InP quantum dot single photon source device. Light field limitation and reflection efficiency can be enhanced, a high-Q-value resonant cavity is realized, and the brightness and purity of a single photon source are improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor materials and devices, and in particular to an InAs / InP quantum dot single-photon source device and a preparation method thereof. Background Art

[0002] With the rapid development of quantum communication and quantum information technology, single-photon sources in the communication band (1.3 µm and 1.55 µm) have become key components for achieving long-distance, high-security quantum communication. Semiconductor quantum dots, also known as quantum dots (QDs), have become ideal candidate materials for single-photon sources due to their excellent single-photon emission properties (high purity, high brightness, and wavelength tunability). Among many material systems, II-VI, III-V quantum dots and perovskite quantum dots represented by cadmium tin (CdSe) and indium phosphide (InP) are the most mature, with luminescence efficiencies of more than 90%. InP-based InAs quantum dots, in particular, stand out due to their natural matching with the communication band. The band gap of InP materials (~1.35 eV) enables it to efficiently cover the 1.3 µm and 1.55 µm bands. At the same time, the quantum confinement effect and efficient luminescence characteristics of InAs quantum dots further enhance the performance of single-photon sources.

[0003] However, the traditional InP substrate has certain optical absorption losses in the near-infrared band, which limits the efficiency of the device. In addition, the InP material itself is relatively brittle, and the preparation of optical microcavities is complex. The shortcomings of optical loss, thermal management challenges, wavelength tuning difficulties, mechanical stability issues and high costs still need further research and optimization. Summary of the invention

[0004] In order to solve the above-mentioned deficiencies in the art, the present application aims to provide an InAs / InP quantum dot single photon source device and a preparation method thereof.

[0005] According to one aspect of the present application, a method for preparing an InAs / InP quantum dot single-photon source device is provided, comprising: An InP substrate is prepared, wherein the InP substrate includes, from top to bottom, an InAs / InP quantum dot layer, an InGaAs sacrificial layer, and an InP substrate layer; Deposition of SiO on the surface of the InAs / InP quantum dot layer on the InP substrate 2 Spacer layer; In SiO 2 The Au mirror layer is evaporated on the surface of the spacer layer; An Au mirror layer is evaporated on the surface of the GaAs substrate; The Au mirror layer of the InP substrate is combined with the Au mirror layer of the GaAs substrate by using flip-chip bonding technology; The InP substrate layer and the InGaAs sacrificial layer are removed by wet etching; Depositing a first mask layer on the surface of the InAs / InP quantum dot layer; Preparing a second mask layer on the surface of the first mask layer, and performing exposure and development; performing dry etching on the first mask layer; The InAs / InP quantum dot layer is dry-etched to obtain an InAs / InP quantum dot single photon source device.

[0006] According to some embodiments of the present application, the first mask layer is SiO 2 Mask layer.

[0007] According to some embodiments of the present application, the InGaAs sacrificial layer is In 0.53 Ga 0.47 As sacrificial layer; According to some embodiments of the present application, the InAs / InP quantum dot layer is an InP layer containing InAs quantum dots.

[0008] According to some embodiments of the present application, removing the InP substrate layer and the InGaAs sacrificial layer by wet etching includes: removing the InP substrate layer by wet etching with HCl, and then removing the InP substrate layer by wet etching with HCl. 3 PO 4 :H 2 O 2 :H 2 The InGaAs sacrificial layer is removed by wet etching with an O mixed solution.

[0009] According to some embodiments of the present application, H 3 PO 4 :H 2 O 2 :H 2 The volume ratio of O is 2:3:30.

[0010] According to some embodiments of the present application, the exposure voltage is 30 kV-125 kV, and optionally, the exposure voltage is 125 kV.

[0011] According to some embodiments of the present application, the thickness of the InAs / InP quantum dot layer is 310 nm, the thickness of the InGaAs sacrificial layer is 200 nm, and the thickness of the InP substrate layer is 350 μm.

[0012] According to some embodiments of the present application, SiO 2 The thickness of the mask layer is 100 nm-200 nm. Optionally, SiO 2 The thickness of the mask layer is 150 nm.

[0013] According to another aspect of the present application, there is also provided an InAs / InP quantum dot single photon source device prepared by the above-mentioned method for preparing the InAs / InP quantum dot single photon source device.

[0014] According to some embodiments of the present application, the InAs / InP quantum dot single photon source device has a ring Bragg grating microcavity structure.

[0015] Compared with the prior art, this application has at least the following beneficial effects: The present application provides a method for preparing an InAs / InP quantum dot single-photon source device, which significantly reduces optical loss and improves thermal management performance by introducing substrate removal technology to remove the InP substrate.

[0016] The preparation method of the present application removes the InP substrate with a thickness of hundreds of microns by selecting the substrate transfer material of the InP substrate and controlling the stability of the combination of the InP substrate and the new substrate during the entire process. At the same time, the integrity and flatness of the film with a thickness of hundreds of nanometers left after the substrate is removed are ensured. The process accuracy of the ring Bragg grating with a size of hundreds of nanometers prepared on the surface of the InAs / InP film with a thickness of hundreds of nanometers is controlled.

[0017] The InAs / InP quantum dot single-photon source device of the present application is an enhanced InAs / InP quantum dot single-photon source device based on a ring-shaped Bragg grating structure, having an alloy mirror reflection layer (Au mirror layer) and a ring-shaped Bragg grating structure, which can further enhance the light field confinement and reflection efficiency, realize a high-Q value resonant cavity, and thus improve the brightness and purity of the single-photon source; it also provides a new solution for the miniaturization and integration of photonic integrated circuits (PICs), becoming an important research direction for single-photon sources in the communication band. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic structural diagram of an InP substrate according to an exemplary embodiment of the present application.

[0019] Figure 2 This is a schematic diagram of the preparation process flow of the InAs / InP quantum dot single photon source device according to an exemplary embodiment of the present application.

[0020] Figure 3 This is a stability comparison chart of the InP material of the exemplary embodiment of the present application after transfer on three different substrates.

[0021] Figure 4 This is a scanning electron microscope image of the surface morphology of the material after being processed by traditional wet etching technology according to an exemplary embodiment of the present application.

[0022] Figure 5 Optical microscope and scanning electron microscope images characterize example embodiments of the present application.

[0023] Figure 6 In the exemplary embodiment of the present application, the InAs / InP film is bonded to the new substrate using NOA61 and then deposited with SiO 2 Topography image of the surface behind the hard mask.

[0024] Figure 7 A comparison diagram of substrate transfer between the flip chip bonding technology and the curing adhesive bonding technology according to an exemplary embodiment of the present application.

[0025] Figure 8 The morphology images of the annular Bragg grating obtained by exposure at different acceleration voltages according to the exemplary embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solution of the present application will be clearly and completely described below in conjunction with the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] It is particularly important to point out that similar substitutions and modifications made to the present application are obvious to those skilled in the art, and they are all deemed to be included in the present application. Relevant personnel can obviously modify or appropriately change and combine the methods and applications described herein without departing from the content, spirit and scope of the present application to implement and apply the technology of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments.

[0028] If no specific conditions are specified in this application, the preparation shall be carried out under conventional conditions or the conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, for which the manufacturers are not specified, are all conventional products that can be obtained commercially.

[0029] The application is described in detail below.

[0030] The present application provides an InAs / InP quantum dot single photon source device and a preparation method thereof, in particular, an enhanced InAs / InP quantum dot single photon source device based on a ring Bragg grating structure, to overcome the following problems currently existing in the field and promote the practical application of InP materials in quantum communication and photonic integrated circuits.

[0031] Select the substrate transfer material of the InP substrate, control the stability of the combination of the InP substrate and the new substrate during the entire process, and remove the InP substrate with a thickness of hundreds of microns. Overcome the problem of high complexity in preparing optical microcavities due to the brittleness of the InP material itself, and ensure the integrity and flatness of the film with a thickness of hundreds of nanometers left after removing the substrate. At the same time, control the process accuracy of the hundreds-nanometer-sized annular Bragg grating prepared on the surface of the hundreds-nanometer InAs / InP film.

[0032] To solve the above technical problems, this application can be implemented as follows: Figure 2 The technical solution shown is implemented.

[0033] InP substrate preparation: The materials from top to bottom are: InP layer containing InAs quantum dots (hereinafter referred to as InAs / InP quantum dot layer), In 0.53 Ga 0.47 As sacrificial layer (hereafter referred to as InGaAs), (100)InP substrate.

[0034] InP substrate pretreatment: soak in acetone, ethanol and deionized water in sequence, and then blow dry with a nitrogen gun.

[0035] Preparation of spacer layer: Using plasma chemical vapor deposition system, deposit SiO 2 Spacer layer.

[0036] Preparation of Au mirror layer: Using electron beam evaporation coating system, deposit SiO 2 The Au mirror layer is evaporated on the InP substrate surface of the spacer layer and the GaAs surface of the new substrate.

[0037] Structural composite: The Au mirror of the InP substrate is firmly combined with the Au mirror of the GaAs substrate using flip-chip technology.

[0038] Wet etching: Remove the InP substrate layer by wet etching with HCl, and then immediately use H 3 PO 4 :H 2 O 2 :H 2 The InGaAs sacrificial layer is removed by wet etching with an O mixed solution, leaving an InAs / InP quantum dot layer.

[0039] Prepare the first mask layer: Use a plasma chemical vapor deposition system to deposit a layer of SiO on the surface of the InAs / InP quantum dot layer. 2 As the first mask layer of the ring Bragg grating.

[0040] Prepare the second mask layer: spin-coat a layer of electron beam resist on the surface of the first mask layer and bake it at high temperature to form the second mask layer; then use 30-125 kV voltage for electron beam exposure, and after development, the pattern of the layout is reproduced on the electron beam resist.

[0041] Dry etching: Use inductively coupled plasma etcher to etch SiO 2 The first mask layer is dry-etched. After etching, the residual electron beam glue is removed using a degumming liquid, an organic solvent, and a plasma degumming machine; the InAs / InP quantum dot layer is dry-etched using an inductively coupled plasma etcher to obtain the enhanced InAs / InP quantum dot single-photon source device based on the annular Bragg grating structure of the present application.

[0042] The technical solution of the present application is further described below in conjunction with specific embodiments.

[0043] Equipment: Electron beam evaporation coating system ADNANOTEK EBS150 model; Plasma chemical vapor deposition system SAMCO PD-220NL model; Flip chip bonding machine FINETECH FINEPLACER-96 model; Electron beam lithography equipment Elionix ELS-F125 model; Inductively coupled plasma etcher Plasma Pro 100 Cobra model.

[0044] Example 1 InP substrate preparation: The materials from top to bottom are: 310nm InAs / InP quantum dot layer, 200nm InGaAs sacrificial layer, 350μm (100)InP substrate (such as Figure 1 as shown).

[0045] InP substrate pretreatment: Cut the InP substrate into 1 cm × 1 cm pieces, soak them in acetone, ethanol and deionized water for 5 min respectively, and then blow dry them with a nitrogen gun.

[0046] Preparation of spacer layer: Using plasma chemical vapor deposition system, deposit 300nm SiO 2 The upper and lower electrode temperatures were set to 150°C and 350°C respectively, and the gas was SiH diluted with 100 sccm Ar. 4 (5%SiH 4 / 95%Ar) and 460sccmN 2 O, the process pressure is 80Pa, the RF power is 50W, and the growth time is 6min9s.

[0047] Preparation of Au mirror layer: Using electron beam evaporation coating system, deposit SiO 2 10nm Ti and 100nm Au were evaporated on the InP substrate surface of the spacer layer and the GaAs surface of the new substrate.

[0048] Structural composite: Use flip-chip technology to firmly bond one side of the Au mirror layer of the InP substrate to one side of the Au mirror layer of the GaAs substrate; Place the GaAs substrate with the Au side facing upward horizontally on the operating table, and place the InP substrate with the Au side facing downward horizontally on the GaAs substrate. Heat the operating table to 200°C and apply 5kN pressure.

[0049] Wet etching: Remove the InP substrate layer by wet etching with HCl, and then immediately use H 3 PO 4 :H 2 O 2 :H 2 The InGaAs sacrificial layer is removed by wet etching with a mixed solution of O=2:3:30, leaving an InAs / InP quantum dot layer.

[0050] Prepare the first mask layer: Use a plasma chemical vapor deposition system to deposit 150nm of SiO on the surface of the InAs / InP quantum dot layer. 2 As the first mask layer of the ring Bragg grating.

[0051] Prepare the second mask layer: Spin coat a layer of electron beam resist, ZEP520A, on the surface of the first mask layer, with the coating parameters of 300rpm, 6 seconds of rotation, acceleration to 3000rpm, 60 seconds of rotation, 380nm of coating thickness, 180℃ of temperature, and baking for 180 seconds to form the second mask layer; expose the sample after baking and cooling to room temperature. The exposure parameters are set as follows: writing field size 200×200μm, acceleration voltage 125kV, beam current 300pA, step length 2nm, aperture size 120μm, exposure dose 360μC / cm 2 .

[0052] The exposed samples were developed and fixed, with the developer being ZED-N50 for 60 seconds and the fixer being IPA for 20 seconds, and then the samples were dried with a nitrogen gun.

[0053] Dry etching: The sample to be etched is adhered to the single crystal silicon wafer with thermal conductive silicone oil, and placed in the pre-vacuum chamber. After the vacuum reaches the preset value, it is transferred to the etching chamber. Etching parameters: the sample stage temperature is set to 10°C, the pressure of He gas purge on the back of the sample is 10Torr, the process pressure is 1mTorr, the upper electrode power is 1000W, the lower electrode power is 35W, and the etching gas is a mixture of trifluoromethane and argon, and the gas component flow rate is CHF3 / Ar =20sccm / 10sccm, process time 2min.

[0054] Residual glue removal: After dry etching, the sample was immersed in ZEP520A degumming liquid N,N-dimethylacetamide for 5 minutes to dissolve the large area of ​​residual glue, and then a plasma degumming machine was used to remove the small area of ​​residual glue. 2 Flow rate: 50 sccm, RF power: 100 W, processing time: 5 min.

[0055] Dry etching: The pattern of the first mask layer is transferred to the InAs / InP quantum dot layer using an inductively coupled plasma etcher. The etching parameters are: the sample stage temperature is set at 25°C, the pressure of He gas purge on the back of the sample is 10 Torr, the process pressure is 4 mTorr, the upper electrode power is 1000W, the lower electrode power is 150W, and the etching gas is a mixture of methane, chlorine and argon, with a gas component flow rate of CH 4 / Cl 2 / Ar=12sccm / 6sccm / 3sccm, process time 1min.

[0056] Example 2 The preparation steps are basically the same as those in Example 1, except that a voltage of 30 kV is used and SiO 2 The thickness of the mask layer is 200 nm.

[0057] Comparative Example 1 The preparation steps are basically the same as those in Example 1, except that the new substrate material is a quartz glass substrate.

[0058] Comparative Example 2 The preparation steps are basically the same as those in Example 1, except that the new substrate material is a Si substrate.

[0059] Comparative Example 3 The preparation steps are basically the same as those in Example 1, except that UV-curable optical adhesive NOA61 is used to bond the InP substrate and the new substrate instead of flip-chip bonding. NOA61 is evenly spin-coated on the Au mirror surface of the InP substrate, and the GaAs substrate is replaced by quartz glass (quartz glass is selected here because NOA61 is most suitable for optical bonding of glass and metal surfaces, and the bonding effect is better), which is horizontally placed on the Au surface coated with adhesive, and the bonded sheet is placed in a drawer-type UV curing box for curing.

[0060] After the InP substrate and the quartz glass are bonded together, the InP substrate is removed by wet etching, and the preparation steps are the same as those in Example 1.

[0061] SiO was deposited on the surface of the 310 nm InAs / InP thin film sample left after the substrate was removed. 2The hard mask layer is prepared in the same steps as in Example 1. Since the tolerance temperature of NOA61 is 190°C, the SiO 2 The temperature was 300°C and SiO was deposited 2 After the film sample is exposed, a large number of cracks, wrinkles and bubbles appear on the surface, and the surface flatness of the sample does not meet the flatness requirements of the subsequent exposure process, such as Figure 6 shown.

[0062] Comparative Example 4 The preparation steps are basically the same as those in Example 1, except that conventional wet etching is used. The flip-chip soldered sample is placed in a beaker containing concentrated HCl. After 30 minutes of static etching, it is found that the sample thickness does not decrease significantly. The sample is taken out, soaked in isopropanol and deionized water for 5 minutes respectively, and then dried with a nitrogen gun. The sample surface is characterized by scanning electron microscopy, such as Figure 4 shown. Figure 4 (a) shows that at a magnification of 300X, the byproducts produced on the sample surface during the long-term corrosion process are not dissolved in time and deposited on the sample surface, blocking the progress of corrosion, resulting in different corrosion depths at different locations on the substrate and an uneven sample surface. Figure 4 (b) shows the poor surface cleanliness of the sample due to byproduct adhesion at 6kX magnification.

[0063] Comparative Example 5 The preparation steps are basically the same as those in Example 1, except that the first mask layer is not prepared.

[0064] According to Comparative Examples 1 and 2, Figure 3 As shown, the present application selects GaAs material as the new substrate of InP. The thermal expansion coefficient of GaAs as the new substrate is close to that of InP, which is suitable as the flip-chip substrate material of InP. In addition, the hardness of GaAs is higher than that of InP, which is suitable as the support material of the thin film with a thickness of hundreds of nanometers remaining after the InP substrate is removed. For comparison, Si substrate ( Figure 3 (a)) and quartz glass substrate ( Figure 3 (b) In the process of wet etching to remove the substrate of InP substrate, when the remaining thickness of the substrate is in the micron level, the flip-chip bonding effect between InP and the substrate material is not ideal. The InP film is separated from the Si substrate and the quartz glass substrate, but it is always firmly bonded to the GaAs substrate.

[0065] As shown in Comparative Example 3, the present application selects the flip-chip technology. The surface-to-surface bonding between metals has extremely good stability and is insensitive to acid-base corrosion, high-temperature baking, and organic solvent cleaning in subsequent processes. It effectively solves the problem of weak bonding and substrate falling off from the substrate when using curing glue for surface-to-surface bonding in subsequent process operations. For example, air bubbles appear during high-temperature baking, curing glue melts during organic solvent cleaning, and curing glue reacts and deforms during acid-base corrosion. These situations will cause the substrate and the substrate to separate, and the hundreds of nanometers thick film left after the substrate is removed from the substrate will be uneven and deformed, or even fall off the surface of the substrate. Figure 7 As shown in Figure 1, Figure (a) shows a sample prepared by flip-chip bonding technology. After acid-base corrosion, high-temperature baking, and organic solvent cleaning, it still has a flat and stable bond with the substrate material; Figure (b) shows a sample prepared by curing adhesive bonding. After high-temperature deposition of SiO 2 Sometimes wrinkles, cracks or even partial detachment occur, making it impossible to carry out the next experiment.

[0066] According to Comparative Example 4, Figure 4 As shown, HCl is selected as the etching solution for InP in this application. HCl reacts with InP to generate a soluble product InCl 3 and gaseous pH 3 , causing the material to gradually dissolve. Traditional wet etching is usually applicable to nanometer-level depths. For InP materials with a thickness of 350μm, byproducts will not be dissolved in time and deposited on the sample surface during the long-term etching process, blocking the progress of corrosion, resulting in different corrosion depths at different locations on the substrate, uneven sample surfaces, and poor experimental repeatability. In order to solve this problem, the etching liquid beaker is placed on a magnetic stirrer to keep the etching liquid in a flowing state during the entire etching process, preventing attachments from depositing on the sample surface and ensuring smooth corrosion. Select H 3 PO 4 :H 2 O 2 :H 2 The mixed solution of O etches the InGaAs sacrificial layer, and the etching solution hardly etches the InP material, thereby ensuring that the InGaAs sacrificial layer is completely etched without damaging the remaining InAs / InP film.

[0067] According to Comparative Example 5, in the preparation method of the present application, a layer of SiO is added on the basis of the electron beam glue. 2 The hard mask is due to the thick InAs / InP quantum dot layer. The etching ratio of electron beam gel to InP commonly used in the laboratory is about 3:1~2:1. The maximum etching depth of InP is about 200nm, which cannot meet the etching depth greater than 200nm.

[0068] According to Example 1 and Example 2, the high voltage of 125 kV selected during the electron beam exposure of the present application can reduce the forward scattering of electrons in the resist during the exposure process and reduce the proximity effect, so that the size of the pattern obtained after development is closer to the designed pattern line width. Figure 8 As shown in the figure, (a) and (b) are the annular Bragg gratings obtained by exposure at 30kV. Due to the forward scattering and proximity effect, the adjacent gratings are stuck or discontinuous. (c) is the annular Bragg grating obtained by exposure and etching at 30kV after adding a layer of conductive glue. Although the pattern is prepared, the pattern size is 60 nm wider than the designed size. (d) is the annular Bragg grating obtained by exposure and etching at 125kV. It can be seen that under the high voltage of 125kV, the pattern morphology is excellent and the edge verticality is good.

[0069] The InAs / InP annular Bragg grating quantum dot single photon source device prepared by the preparation method of the present application was characterized by optical microscope and scanning electron microscope images, such as Figure 5 As shown. It can be seen that the surface of the nanometer-thick film of the present application is smooth and flat, and the 100nm annular Bragg grating spacing structure has excellent morphology. The quantum dot single photon source of the present application combines the advantages of InP material, substrate removal technology and gold mirror reflection layer, and has important application value in photonics and optoelectronic devices. The device can reduce optical loss, increase the Q value of the cavity, improve thermal management performance, reduce heat accumulation in the microcavity, improve the temperature stability of the device, and can realize a low-threshold, high-efficiency laser. At the same time, the structure can be integrated with other photonic devices (such as modulators, detectors, etc.) to realize a multifunctional photonic integrated circuit.

[0070] The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for preparing an InAs / InP quantum dot single photon source device, characterized in that: include: An InP substrate is prepared, wherein the InP substrate comprises, from top to bottom, an InAs / InP quantum dot layer, an InGaAs sacrificial layer, and an InP substrate layer; Depositing a SiO2 spacer layer on the surface of the InAs / InP quantum dot layer of the InP substrate; Vapor depositing an Au mirror layer on the surface of the SiO2 spacer layer; An Au mirror layer is evaporated on the surface of the GaAs substrate; The Au mirror layer of the InP substrate is combined with the Au mirror layer of the GaAs substrate by using a flip-chip bonding technique; Removing the InP substrate layer and the InGaAs sacrificial layer by wet etching; Depositing a first mask layer on the surface of the InAs / InP quantum dot layer; Preparing a second mask layer on the surface of the first mask layer, and performing exposure and development; performing dry etching on the first mask layer; The InAs / InP quantum dot layer is dry-etched to obtain the InAs / InP quantum dot single-photon source device.

2. The method for preparing the InAs / InP quantum dot single photon source device according to claim 1, characterized in that: The first mask layer is a SiO2 mask layer.

3. The method for preparing the InAs / InP quantum dot single photon source device according to claim 1, characterized in that: The InGaAs sacrificial layer is In 0.53 Ga 0.47 As sacrificial layer; The InAs / InP quantum dot layer is an InP layer containing InAs quantum dots.

4. The method for preparing the InAs / InP quantum dot single photon source device according to any one of claims 1 to 3, characterized in that: Removing the InP substrate layer and the InGaAs sacrificial layer by wet etching includes: removing the InP substrate layer by wet etching with HCl, and then removing the InGaAs sacrificial layer by wet etching with a mixed solution of H3PO4:H2O2:H2O.

5. The method for preparing the InAs / InP quantum dot single photon source device according to claim 4, characterized in that: The volume ratio of H3PO4:H2O2:H2O is 2:3:

30.

6. The method for preparing the InAs / InP quantum dot single photon source device according to claim 5, characterized in that: The exposure voltage is 30 kV-125 kV.

7. The method for preparing the InAs / InP quantum dot single photon source device according to any one of claims 1 to 3, characterized in that: The thickness of the InAs / InP quantum dot layer is 310 nm, the thickness of the InGaAs sacrificial layer is 200 nm, and the thickness of the InP substrate layer is 350 μm.

8. The method for preparing the InAs / InP quantum dot single photon source device according to claim 2, characterized in that: The thickness of the SiO2 mask layer is 100 nm-200 nm.

9. An InAs / InP quantum dot single-photon source device prepared by the method for preparing an InAs / InP quantum dot single-photon source device according to any one of claims 1 to 8.

10. The InAs / InP quantum dot single photon source device according to claim 9, characterized in that: It has a ring Bragg grating microcavity structure.

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