A phase-locking method and computer storage medium suitable for single-phase grid voltage

Abstract

The present invention discloses a phase-locked method suitable for single-phase grid voltage. The phase-locked method includes a fundamental voltage extraction process, a fundamental voltage dq axis component construction process, a voltage-controlled oscillation link, and a modulo link, wherein the fundamental voltage extraction process includes: processing the single-phase grid voltage through a low-pass filter to obtain its DC component; processing the single-phase grid voltage through an nth band-pass filter to obtain its 2n+1 harmonic component; and performing a difference operation between the single-phase grid voltage and the DC component and the 2n+1 harmonic component to obtain the grid voltage fundamental signal. On the one hand, the phase-locked method of the present invention reduces the influence of odd harmonics, DC bias, etc. on the output signal of the phase-locked loop through the fundamental voltage extraction process and the fundamental voltage dq axis component construction process. On the other hand, the phase-locked method of the present invention eliminates the double frequency oscillation of the fundamental voltage dq axis component through a cross-decoupling algorithm, thereby improving the control accuracy and stability of the phase-locked loop.

Description

Technical Field

[0001] The present invention generally relates to the fields of renewable energy generation, energy storage systems, microgrids, and smart grids. More specifically, the present invention relates to a phase-locking method for single-phase grid voltage and a computer-readable storage medium. Background Art

[0002] Single-phase grid-connected inverters, rectifiers, and UPS are common electrical devices in single-phase smart grids. For stable operation, they must accurately obtain the angular frequency and phase information of the fundamental voltage at the grid's point of common connection (PCC), and even its amplitude. This requires phase-locking the grid voltage. For example, grid-connected inverters are widely used in low-power photovoltaic, wind power, and energy storage systems. They convert DC power into high-quality AC power and feed it into the grid, serving as the link between renewable energy and the grid. To ensure reliable grid-connected operation and protection, a phase-locked loop (PLL) is typically required to output accurate grid voltage phase, frequency, and amplitude information. However, practical power grids often contain numerous nonlinear loads, such as electrified rail vehicles, arc welders, and data center equipment. These devices generate harmonic currents that flow through line impedance, resulting in non-ideal grid voltages. These harmonics include odd-order background harmonics (3rd, 5th, and 7th harmonics), DC offsets, and frequency fluctuations, significantly impacting the PLL's output accuracy and stability. At the same time, due to the existence of these nonlinear loads, the adaptability of the phase-locked loop to changes in grid voltage amplitude will also be reduced.

[0003] To address the aforementioned issues with single-phase grid voltage phase-locked loops (PLLs), researchers have designed various quadrature signal generators (QSGs) within the phase-locked loop's phase detection circuitry to generate quadrature components with the same amplitude as the grid voltage. Phase detection is then performed using a rotating coordinate transformation (Park transform). Commonly used single-phase voltage phase detection methods include the second-order generalized integrator (SOGI), the T / 4 (T is the fundamental period) delay and differential loop (DPLL), and the inverse Park transform (IPT). While these prior art techniques have proposed some improvements, they still present several drawbacks. For example, under non-ideal grid voltage conditions, the SOGI-based phase-locked loop method cannot address the DC component of the grid voltage. Furthermore, the T / 4 delay structure and the IPT-PLL method have poor adaptability to grid frequency variations. Furthermore, in high-power applications, the measured signal inevitably introduces high-frequency noise, and the DPLL method's amplification of the noise signal significantly impacts phase-locked accuracy. Summary of the Invention

[0004] To address one or more of the problems described in the aforementioned background technology, the present invention provides a phase-locked method for single-phase grid voltage. This method proposes a fundamental voltage extraction process. This technique first processes the single-phase grid voltage through a low-pass filter to obtain its DC component. Simultaneously, the single-phase grid voltage is processed through multiple band-pass filters to obtain its odd-order harmonic components. Finally, the single-phase grid voltage is subtracted from the DC component and the odd-order harmonic components to obtain the grid voltage fundamental signal. To this end, the present invention provides solutions through the following multiple embodiments.

[0005] Specifically, the present invention discloses a phase-locked method for single-phase grid voltage. The phase-locked method includes a fundamental voltage extraction process, a fundamental voltage dq-axis component construction process, a voltage-controlled oscillation step, and a modulo step. The fundamental voltage extraction process includes: processing the single-phase grid voltage through a low-pass filter to obtain its DC component; processing the single-phase grid voltage through an nth band-pass filter to obtain its 2n+1 harmonic component; and performing a difference operation on the single-phase grid voltage, the DC component, and the 2n+1 harmonic component to obtain a grid voltage fundamental signal, where n is a positive integer.

[0006] In one embodiment, the fundamental voltage dq-axis component construction process includes: in response to the fundamental voltage extraction process, subjecting the grid voltage fundamental signal and the 0 signal to a first positive-sequence Park transformation process to generate a positive-sequence fundamental voltage d-axis component and a positive-sequence fundamental voltage q-axis component; in response to the fundamental voltage extraction process, subjecting the grid voltage fundamental signal and the 0 signal to a first negative-sequence Park transformation process to generate a negative-sequence fundamental voltage d-axis component and a negative-sequence fundamental voltage q-axis component; and performing a decoupling operation on the positive-sequence fundamental voltage d-axis component, the positive-sequence fundamental voltage q-axis component, the negative-sequence fundamental voltage d-axis component, and the negative-sequence fundamental voltage q-axis component to generate a fundamental voltage d-axis component and a fundamental voltage q-axis component.

[0007] In another embodiment, the decoupling operation includes: processing a grid voltage d-axis component DC signal through a first low-pass filter to generate a first filtered signal; processing a grid voltage q-axis component DC signal through a second low-pass filter to generate a second filtered signal; processing the first filtered signal and the second filtered signal through a second negative-sequence Park transform to generate a first intermediate result signal and a second intermediate result signal; performing a difference operation between the first intermediate result signal and the negative-sequence fundamental voltage d-axis component and processing the signal through a third low-pass filter to generate a third filtered signal; performing a difference operation between the second intermediate result signal and the negative-sequence fundamental voltage q-axis component and processing the signal through a fourth low-pass filter to generate a fourth filtered signal; performing a second positive-sequence Park transform on the third filtered signal and the fourth filtered signal to generate a third intermediate result signal and a fourth intermediate result signal; performing a difference operation between the third intermediate result signal and the positive-sequence fundamental voltage d-axis component to generate the grid voltage d-axis component DC signal; and performing a difference operation between the fourth intermediate result signal and the positive-sequence fundamental voltage q-axis component to generate the grid voltage q-axis component DC signal.

[0008] In another embodiment, the voltage-controlled oscillation link includes: performing a division operation on the fundamental voltage d-axis component and the fundamental voltage q-axis component to generate a first angular frequency signal; processing the first angular frequency signal through a voltage-controlled oscillator to generate a second angular frequency signal; performing a summing operation on the grid center angular frequency signal and the second angular frequency signal to output a third angular frequency signal; and processing the first angular frequency signal through an amplification link and performing a summing operation with the third angular frequency signal to output a fourth angular frequency signal.

[0009] In one embodiment, the modulo step includes: performing a modulo operation on the fourth angular frequency signal, wherein the algorithm of the modulo operation is: where θ s is the phase of the grid fundamental voltage, ω s3 is the angular frequency of the fourth angular frequency signal.

[0010] On the other hand, the present invention also discloses a computer-readable storage medium, which stores program instructions for implementing a phase-locked method applicable to a single-phase grid voltage. When the program instructions are executed by a processor, it implements the phase-locked method according to the above embodiment.

[0011] As can be seen from the schemes described in the multiple embodiments above, the phase-locking method of the present invention cleverly designs the fundamental voltage extraction process and the fundamental voltage dq-axis component construction process. Furthermore, the fundamental voltage dq-axis component construction process also includes a cross-decoupling process, which can suppress the second-harmonic frequency component of the fundamental voltage without generating delay. Through these technical means, the phase-locking method of the present invention can not only accurately output the frequency and phase information of the grid voltage, but also obtain the amplitude information of the grid fundamental voltage, thereby solving the problem of low phase-locking accuracy in the presence of non-ideal grid voltages with DC bias and excessive background harmonics. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above-mentioned features and advantages of the present invention can be better understood by reading the detailed description below with reference to the accompanying drawings, and its numerous purposes, features and advantages will be apparent to those skilled in the art. The drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort, among which:

[0013] Figure 1 is an overall flow chart showing a phase locking method applicable to a single-phase grid voltage according to an embodiment of the present invention;

[0014] Figure 2 is a principle diagram illustrating a phase locking method applicable to a single-phase grid voltage according to an embodiment of the present invention;

[0015] Figure 3 is a flow chart illustrating a fundamental voltage extraction process according to an embodiment of the present invention;

[0016] Figure 4 is a schematic diagram illustrating a fundamental voltage extraction process according to an embodiment of the present invention;

[0017] Figure 5 is a flowchart illustrating a process of constructing a fundamental voltage dq-axis component according to an embodiment of the present invention; and

[0018] Figure 6 FIG. 1 is a schematic diagram illustrating a process of constructing dq-axis components of a fundamental voltage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] Figure 1 is a general flow chart 100 showing a phase locking method applicable to a single-phase grid voltage according to an embodiment of the present invention; Figure 2 FIG2 is a schematic diagram showing a phase locking method for a single-phase grid voltage according to an embodiment of the present invention. It is understood that Figure 2 The schematic diagram 200 is Figure 1 A specific embodiment of the method flow chart 100. Figure 1 and Figure 2 The phase locking method of the present invention is described in detail.

[0021] like Figure 1 As shown, the overall process 100 of the phase-locking method for single-phase grid voltage of the present invention may include steps S101, S102, S103 and S104. First, the process 100 of the phase-locking method begins at step S101. At this step, the fundamental voltage extraction process is performed. Specifically, as Figure 2 As shown, the grid voltage u s After being processed by the fundamental voltage extraction unit 201, the grid voltage fundamental signal u is generated. s1 Then, the process 100 of the phase-locking method executes step S102. At this step, the fundamental voltage dq axis component construction process is executed. Specifically, as Figure 2 As shown, the input signals of the fundamental voltage dq axis component construction unit 202 are set to u s1 and 0, after processing, the output fundamental voltage d-axis component u sd1 and the fundamental voltage q-axis component u sq1 . Further, u sd1 The signal is processed by the 2x signal amplification unit to obtain the amplitude signal u of the grid fundamental voltage. sm1 .

[0022] Next, the process 100 of the phase-locked method proceeds to step S103. At this step, the voltage-controlled oscillation link is executed. It can be understood that, Figure 2 The block diagram 203 corresponds to Figure 1 In the voltage-controlled oscillation step S103, the fundamental voltage d-axis component and the fundamental voltage q-axis component are first divided to generate a first angular frequency signal. Specifically, Figure 2 As shown, in order to solve the problem of the phase-locked loop's adaptability to a large drop in the grid voltage amplitude, u sq1 with u sd1 Perform division operation to realize normalization of voltage signal and output the first angular frequency signal ω s . Further, multiply the signal by Thus, the grid frequency signal f is obtained sNext, the first angular frequency signal is processed by a voltage-controlled oscillator to generate a second angular frequency signal. Specifically, Figure 2 As shown, the first angular frequency signal ω s After being processed by the voltage-controlled vibrator, the second angular frequency signal ω is obtained s1 , where the transfer function of the voltage controlled oscillator is k I is the integral gain, and s is a complex variable. Subsequently, the grid center angular frequency signal and the second angular frequency signal are summed to output a third angular frequency signal. Specifically, Figure 2 As shown, in order to improve the speed of the phase-locked loop, the second angular frequency signal ω s1 The compensated angular frequency signal ω is generated by summing it with the central angular frequency signal ω0 of the power grid. s2 (i.e., the third angular frequency signal), where ω0 = 2π × f0, f0 is the rated frequency of industrial and civil AC power, 50 Hz. Finally, the voltage-controlled oscillation link performs the last step, processing the first angular frequency signal through the amplification link and performing a summation operation with the third angular frequency signal to output the fourth angular frequency signal. Specifically, as Figure 2 As shown, in order to further improve the speed and stability of the phase-locked loop, the first angular frequency signal ω s After the amplification link and the third angular frequency signal ω s2 and generate the fourth angular frequency signal ω s3 , where the gain of the amplifier is k P .

[0023] After the voltage-controlled oscillation process is completed, the process 100 of the phase-locked method of the present invention ends at step S104. In this step, the modulo process is executed to generate the phase signal θ of the grid fundamental voltage. s Specifically, Figure 2 As shown, the fourth angular frequency signal ω s3 Perform a modulo operation (corresponding to Figure 2 The mod module 204 in the embodiment of the present invention is as follows: where θ s is the phase of the grid fundamental voltage, ω s3 is the angular frequency of the fourth angular frequency signal.

[0024] Figure 3 is a flow chart 300 illustrating a fundamental voltage extraction process according to an embodiment of the present invention; Figure 4 FIG4 is a schematic diagram showing a fundamental voltage extraction process according to an embodiment of the present invention. It can be understood that Figure 4 The schematic diagram 400 is Figure 3 A specific embodiment of the method flow chart 300. Figure 3 and Figure 4 The fundamental voltage extraction process of the present invention is described in detail.

[0025] like Figure 3 As shown, the fundamental voltage extraction process of the present invention includes steps S301, S302 and S303. First, the process 300 of the fundamental voltage extraction process starts at step S301. In this step, the single-phase grid voltage is processed by a low-pass filter to obtain its DC component. Specifically, as Figure 4 As shown, the grid voltage u s After low-pass filter processing, u s The DC component u s0 At the same time as step S301, the fundamental voltage extraction process 300 executes step S302. In this step, the single-phase grid voltage is processed by the nth bandpass filter to obtain its 2n+1 harmonic component. Specifically, Figure 4 As shown, the grid voltage u s After being processed by bandpass filter 1, u s The third harmonic component u s3 Similarly, the grid voltage u s After being processed by bandpass filter 2, u s The fifth harmonic component u s5 ; Further, the grid voltage u s After being processed by bandpass filter n, u is obtained s The 2n+1th harmonic component u s(2n+1) , where n is a positive integer. Finally, the fundamental voltage extraction process 300 ends at step S303. In this step, the single-phase grid voltage is subjected to a difference operation with the DC component and the 2n+1 harmonic component to obtain the grid voltage fundamental signal. Specifically, Figure 4 As shown, the grid voltage u s With DC component u s0 , 3rd harmonic component u s3 , 5th harmonic component u s5 ......2n+1 harmonic component u s(2n+1) The grid voltage fundamental signal u is obtained by performing a subtraction. s1 .

[0026] In one embodiment, the transfer function of the low-pass filter can be set to: where ω c is the shear frequency of the low-pass filter, which is expressed as ω c =2π×f c , take f c ∈[0.5 5]; the transfer function of the nth bandpass filter can be set as: Where the damping coefficient ξ∈[0.50.707], the gain coefficient k r It can be set according to the stability margin of the phase-locked loop, and the general value is k r ∈(0 30].

[0027] Figure 5 is a flow chart 500 illustrating a process of constructing dq-axis components of a fundamental voltage according to an embodiment of the present invention; Figure 6 FIG6 is a schematic diagram showing a process of constructing the fundamental voltage dq axis components according to an embodiment of the present invention. It can be understood that Figure 6 The schematic diagram of 600 is Figure 5 A specific implementation of the method flow chart 500. Figure 5 and Figure 6 The construction process of the fundamental voltage dq axis components of the present invention is described in detail.

[0028] like Figure 5 As shown, the process 500 of constructing the fundamental voltage dq axis components may include steps S501-S510. First, the process 500 of the construction process begins at step S501. At this step, in response to the fundamental voltage extraction process, the grid voltage fundamental signal and the 0 signal are subjected to a first positive sequence Park transform to generate a positive sequence fundamental voltage d axis component and a positive sequence fundamental voltage q axis component. Specifically, the grid voltage fundamental signal u obtained at step S303 is converted into a positive sequence fundamental voltage d axis component and a positive sequence fundamental voltage q axis component. s1 The 0 signal undergoes a rotation with an angular frequency of ω s Positive sequence Park transform T1 + , thereby obtaining the positive sequence fundamental voltage d-axis component and the q-axis component of the positive sequence fundamental voltage At the same time as step S501, the process 500 of the construction process executes step S502. In this step, in response to the fundamental voltage extraction process, the grid voltage fundamental signal and the 0 signal are subjected to the first negative sequence Park transformation to generate the negative sequence fundamental voltage d-axis component and the negative sequence fundamental voltage q-axis component. Specifically, the grid voltage fundamental signal u obtained in step S303 is converted into s1 The 0 signal undergoes a rotation with an angular frequency of ω s Negative sequence Park transform T1 - , thereby obtaining the negative sequence fundamental voltage d-axis component and the negative sequence fundamental voltage q-axis component

[0029] It should be noted that because the input signals of the Park transform are not orthogonal, the output dq-axis components contain not only a DC component but also an AC component at twice the rotation frequency. Therefore, in order to eliminate the impact of the doubled rotation frequency signal on the phase-locked loop and obtain the DC signal of the dq-axis components, the present invention provides a cross-decoupling operation to eliminate the doubled frequency AC signal. Based on this, the fundamental voltage dq-axis component construction process of the present invention includes a decoupling operation. It is understood that the decoupling operation process may include steps S503-S510. In the decoupling operation, the positive-sequence fundamental voltage d-axis component, the positive-sequence fundamental voltage q-axis component, the negative-sequence fundamental voltage d-axis component, and the negative-sequence fundamental voltage q-axis component are decoupled to generate the fundamental voltage d-axis component and the fundamental voltage q-axis component. Following steps S501 and S502, the fundamental voltage dq-axis component construction process 500 performs the decoupling operation step S503. In this step, the grid voltage d-axis component DC signal is processed by a first low-pass filter to generate a first filtered signal. Specifically, Figure 6 As shown, the grid voltage d-axis component DC signal u sd1 After being processed by the first low-pass filter LPF1, a first filtered signal is generated. Similarly, the process 500 executes step S504. In this step, the DC signal of the grid voltage d-axis component is processed by a second low-pass filter to generate a second filtered signal. Specifically, Figure 6 As shown, the grid voltage d-axis component DC signal u sq1 After being processed by the second low-pass filter LPF2, a second filtered signal is generated.

[0030] Then, the process 500 of constructing the fundamental voltage dq axis component proceeds to step S505. In this step, the first filtered signal and the second filtered signal are subjected to a second negative sequence Park transform to generate a first intermediate result signal and a second intermediate result signal. Specifically, Figure 6 As shown, the first filtered signal and the second filtered signal After the rotation angular frequency is 2ω s The second negative sequence Park transform Processing, thereby generating a first intermediate result signal and the second intermediate result signal Next, the process 500 executes step S506. In this step, the first intermediate result signal and the negative sequence fundamental voltage d-axis component are subjected to a difference operation and processed by a third low-pass filter to generate a third filtered signal. Specifically, Figure 6 As shown, the first intermediate result signal The difference operation is performed with the negative sequence fundamental voltage d-axis component and processed by the third low-pass filter LPF3 to generate a third filtered signal Similarly, the process 500 executes step S507. In this step, the second intermediate result signal and the negative sequence fundamental voltage q-axis component are subjected to a difference operation and processed by a fourth low-pass filter to generate a fourth filtered signal. Specifically, Figure 6 As shown, the second intermediate result signal The difference operation is performed with the negative sequence fundamental voltage q axis component and processed by the fourth low pass filter LPF4 to generate a fourth filtered signal

[0031] Next, the process 500 of constructing the fundamental voltage dq axis components executes step S508. In this step, the third filtered signal and the fourth filtered signal are subjected to a second positive sequence Park transform to generate a third intermediate result signal and a fourth intermediate result signal. Specifically, Figure 6 As shown, the third filtered signal and the fourth filtered signal After the rotation angular frequency is 2ω s The second positive sequence Park transform Processing to generate a third intermediate result signal and the fourth intermediate result signal Finally, the process 500 of constructing the fundamental voltage dq axis components of the present invention ends at steps S509 and S510, wherein at step S509, a difference operation is performed between the third intermediate result signal and the positive sequence fundamental voltage d axis component to generate the fundamental voltage d axis component. Specifically, Figure 6 As shown, the third intermediate result signal and the d-axis component of the positive sequence fundamental voltage Perform the difference operation to generate the grid voltage d-axis component DC signal u sd1 Similarly, at step S510, a difference operation is performed between the fourth intermediate result signal and the positive sequence fundamental voltage q-axis component to generate the grid voltage q-axis component DC signal. Specifically, Figure 6 As shown, the fourth intermediate result signal and the q-axis component of the positive sequence fundamental voltage Perform the difference operation to generate the grid voltage q-axis component DC signal u sq1 From the above decoupling process, it can be seen that the decoupling operation of the present invention not only eliminates the double frequency component to obtain the DC component, but also avoids the occurrence of delay phenomenon during operation.

[0032] In one embodiment, the low-pass filters LPF1, LPF2, LPF3, and LPF4 can be set as first-order links, and their corresponding transfer functions are: where ω p =0.707ω0. In another embodiment, the first positive sequence Park transform T1 + The transformation matrix can be First negative sequence Park transform T1 - The transformation matrix can be

[0033]

[0034] Second positive sequence Park transform The transformation matrix can be Second negative sequence Park transform T2 - The transformation matrix can be

[0035] Based on the above description, it will be understood that the present invention describes only the brief steps of a phase-locked method applicable to single-phase grid voltage for purposes of illustration and simplicity. However, depending on different application scenarios, the phase-locked method may also include other additional steps. Furthermore, based on the above description, those skilled in the art will understand that the above-mentioned phase-locked method of the present invention may also be implemented with the assistance of hardware or software instructions. Thus, on the one hand, when the phase-locked method applicable to single-phase grid voltage is implemented via hardware, the present invention also discloses a novel phase-locked loop (PLL), which may include a fundamental voltage extraction module, a fundamental voltage dq-axis component construction module, a voltage-controlled oscillation module, and a modulus module. During the operation of this novel PLL, the present invention utilizes the aforementioned phase-locked method to separately control and operate each of the aforementioned modules, thereby enabling the novel PLL to output an accurate grid voltage phase signal. On the other hand, when the phase-locked method of the present invention is implemented via software, the present invention also discloses a computer-readable storage medium storing program instructions for controlling the PLL. When the program instructions are executed by a processor, the PLL implements the aforementioned phase-locked method applicable to single-phase grid voltage.

[0036] It should be understood that when the terms "first," "second," "third," and "fourth" are used in the claims, description, and drawings of the present invention, they are only used to distinguish different objects, rather than to describe a specific order. The terms "comprise" and "comprising" used in the description and claims of the present invention indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0037] It should also be understood that the terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used in the specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in the specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0038] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0039] Although the embodiments of the present invention are as described above, the contents are only examples used to facilitate understanding of the present invention and are not intended to limit the scope and application scenarios of the present invention. Any person skilled in the art of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention, but the scope of patent protection of the present invention shall still be based on the scope defined by the attached claims.

Claims

1. A phase locking method for single-phase grid voltage, characterized in that: It includes the fundamental voltage extraction process, the fundamental voltage dq component construction process, the voltage-controlled oscillation link and the modulus link, among which The fundamental voltage extraction process includes: Processing the single-phase grid voltage through a low-pass filter to obtain a DC component thereof; Processing the single-phase grid voltage through an nth bandpass filter to obtain its 2n+1th harmonic component; Performing a difference operation on the single-phase grid voltage, the DC component, and the 2n+1th harmonic component to obtain a grid voltage fundamental signal, where n is a positive integer; The fundamental voltage dq component construction process includes: In response to the fundamental voltage extraction process, the grid voltage fundamental signal and the 0 signal are subjected to a first positive-sequence Park transform to generate a positive-sequence fundamental voltage d component and a positive-sequence fundamental voltage q component; In response to the fundamental voltage extraction process, the grid voltage fundamental signal and the 0 signal are subjected to a first negative-sequence Park transformation to generate a negative-sequence fundamental voltage d component and a negative-sequence fundamental voltage q component; performing a decoupling operation on the positive-sequence fundamental voltage d component, the positive-sequence fundamental voltage q component, the negative-sequence fundamental voltage d component, and the negative-sequence fundamental voltage q component to generate a fundamental voltage d component and a fundamental voltage q component; The decoupling operation includes: Processing the grid voltage d-axis component DC signal through a first low-pass filter to generate a first filtered signal; Processing the q-axis component DC signal of the grid voltage through a second low-pass filter to generate a second filtered signal; Processing the first filtered signal and the second filtered signal by a second negative-sequence Park transform to generate a first intermediate result signal and a second intermediate result signal; performing a difference operation on the first intermediate result signal and the negative-sequence fundamental voltage d component and processing the resultant signal through a third low-pass filter to generate a third filtered signal; performing a difference operation on the second intermediate result signal and the negative-sequence fundamental voltage q component and processing the resultant signal through a fourth low-pass filter to generate a fourth filtered signal; Processing the third filtered signal and the fourth filtered signal with a second positive sequence Park transform to generate a third intermediate result signal and a fourth intermediate result signal; performing a difference operation on the third intermediate result signal and the positive-sequence fundamental voltage d component to generate the grid voltage d-axis component DC signal; performing a difference operation on the fourth intermediate result signal and the positive-sequence fundamental voltage q component to generate the grid voltage q-axis component DC signal; The voltage-controlled oscillation link includes: performing a division operation on the fundamental voltage d component and the fundamental voltage q component to generate a first angular frequency signal; Processing the first angular frequency signal through a voltage-controlled oscillator to generate a second angular frequency signal; performing a summation operation on the grid center angular frequency signal and the second angular frequency signal to output a third angular frequency signal; The first angular frequency signal is processed by an amplification link and summed with the third angular frequency signal to output a fourth angular frequency signal.

2. The phase locking method according to claim 1, characterized in that: The modulo step includes: performing a modulo operation on the fourth angular frequency signal, wherein the algorithm of the modulo operation is: where θ s is the phase of the grid fundamental voltage, ω s3 is the angular frequency of the fourth angular frequency signal.

3. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program instructions for implementing a phase-locking method applicable to a single-phase grid voltage. When the program instructions are executed by a processor, the phase-locking method according to any one of claims 1 to 2 is implemented.

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