Self-adaptive biasing circuit and power amplification circuit

Abstract

The invention provides a self-adaptive biasing circuit and a power amplification circuit. The self-adaptive biasing circuit comprises a coupling module, a direct current conversion module and a current copying module. The coupling module is connected with the amplifier and is configured to sample the voltage of the output end of the amplifier to generate a sampling voltage; the direct current conversion module is configured to receive the sampling voltage and convert the sampling voltage into direct current intermediate current; wherein the intermediate current is in positive correlation with the sampling voltage; and the current copying module is respectively connected with the bipolar transistor and the direct current conversion module, and is configured to receive the intermediate current, copy the intermediate current into bias current in proportion, and output the bias current to the input end of the bipolar transistor. Therefore, the bias current can be adjusted based on the change of the input signal, so that the amplifier can have better linearity and noise performance.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to an adaptive bias circuit and a power amplifier circuit. Background Art

[0002] RF driver amplifiers play an important role in phased array and transceiver systems. Their performance directly affects the overall performance of the system, so they have strict requirements on performance indicators such as output power and input noise figure. In the design of the amplifier, the design of the bias circuit is crucial. The bias circuit will directly affect the operating current of the amplifier tube, thereby further affecting the linearity, noise figure and other key parameters of the amplifier.

[0003] Heterojunction Bipolar Transistor (HBT) is favored in driver amplifier design due to its advantages in high frequency performance, noise and power consumption. However, HBT transistor is a base current controlled device, which is very sensitive to voltage changes. When the amplifier transistor of the amplifier is an HBT transistor, the following problems exist: 1. If the power of the input signal received by the amplifier is large, there will be a period of time when the HBT transistor cannot be turned on, thereby affecting the current swing of the HBT transistor under large signals; further, it has a greater impact on the linearity index of the amplifier.

[0004] 2. In the existing bias circuit, there is a low-resistance path to ground, which affects the noise coefficient performance when the input signal is a small signal.

[0005] Therefore, the bias circuit needs to meet the noise performance requirements at small signals and / or the linearity requirements at large signals. Summary of the invention

[0006] In view of this, the embodiments of the present disclosure provide an adaptive bias circuit and a power amplifier circuit to meet the noise performance requirements for small signals and / or the linearity requirements for large signals.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows: The embodiment of the present disclosure provides an adaptive bias circuit, wherein the amplifier includes a bipolar transistor; the bias circuit includes: a coupling module, a DC conversion module and a current copy module. The coupling module is connected to the output end of the amplifier and is configured to sample the voltage at the output end of the amplifier to generate a sampling voltage, wherein the sampling voltage is an AC voltage. The DC conversion module is connected to the output end of the coupling module and is configured to receive the sampling voltage and convert the sampling voltage into a DC intermediate current; wherein the intermediate current is positively correlated with the sampling voltage. The current copy module is respectively connected to the bipolar transistor and the DC conversion module and is configured to receive the intermediate current and proportionally copy the intermediate current into a bias current, and output the bias current to the input end of the bipolar transistor.

[0008] First, the coupling module is connected to the output end of the amplifier, and the coupling module will not affect the input signal of the amplifier. At the same time, the amplitude of the output voltage at the output end of the amplifier is positively correlated with the amplitude of the input signal, and the amplitude of the output voltage at the output end of the amplifier can reflect the amplitude of the input signal. The voltage amplitude at the output end of the amplifier is greater than the amplitude of the input signal, which helps to improve the sampling accuracy.

[0009] Second, the DC conversion module converts the sampling voltage into a DC intermediate current; the intermediate current is positively correlated with the sampling voltage. Therefore, as the amplitude (voltage value) of the input signal (RF signal) increases, the amplitude of the output signal increases, the amplitude of the sampling voltage increases, and the size of the intermediate current increases.

[0010] Third, the current copy module receives the intermediate current, and copies the intermediate current in proportion to the bias current, and outputs the bias current to the input end of the bipolar transistor. In other words, the bias current input to the bipolar transistor changes with the voltage amplitude at the output end of the amplifier. When the amplitude (voltage value) of the input signal increases, the sampling voltage amplitude increases accordingly, the intermediate current increases accordingly, the bias current increases, and the DC bias voltage (control terminal voltage) of the bipolar transistor increases, so that the sum of the input signal and the DC bias voltage is always greater than the turn-on voltage of the bipolar transistor, and then, the bipolar transistor is always turned on, and the working current of the bipolar transistor increases, thereby improving the linearity index of the amplifier.

[0011] Fourth, the current copy module can copy the current in proportion, and directly outputs the required bias current without the need for a DC conversion module. This can avoid the device area of ​​the DC conversion module being too large, reduce the integration area, and reduce power consumption.

[0012] In some embodiments, the coupling module includes a third voltage-dividing element and a fourth voltage-dividing element. When the third voltage-dividing element and the fourth voltage-dividing element are both resistors, the DC component of the sampled voltage is used as a bias voltage of the DC conversion module and provided to the transistor in the DC conversion module. In this way, the present disclosure does not need to additionally set a device for providing a bias voltage to the transistor in the DC conversion module, thereby further reducing the area of ​​the bias circuit, improving the integration, and reducing energy consumption.

[0013] In some embodiments, the resistance values ​​of the third voltage divider element and the fourth voltage divider element are both greater than 10 kilo-ohms. Thus, when the third voltage divider element and the fourth voltage divider element are used for voltage collection, current leakage is small, and power loss can be effectively reduced.

[0014] In some embodiments, the current copy module includes a fifth resistor, and the fifth resistor is connected to the input terminal of the bipolar transistor. The resistance of the fifth resistor is greater than 10 kilo-ohms. In this way, the fifth resistor can increase the internal resistance of the bias circuit, and then, the internal resistance of the bias circuit is high, which can effectively prevent the current of the bipolar transistor from leaking through the bias circuit, and when the amplifier (such as the driver amplifier) ​​works at a small signal, it has better noise performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 An amplifier and a bias circuit thereof according to a technique provided by an embodiment of the present disclosure; Figure 2 Schematic diagram of input signal provided by the embodiment of the present disclosure Figure 1 ; Figure 3 Schematic diagram of input signal provided by the embodiment of the present disclosure Figure 2 ; Figure 4 A schematic diagram of the structure of the bias circuit provided in the embodiment of the present disclosure Figure 1 ; Figure 5 A schematic diagram of the structure of an amplifier in a bias circuit provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of the structure of the coupling module provided in the embodiment of the present disclosure Figure 1 ; Figure 7 A schematic diagram of the structure of the coupling module provided in the embodiment of the present disclosure Figure 2 ; Figure 8 A schematic diagram of the structure of the DC conversion module provided in the embodiment of the present disclosure Figure 1 ; Fig. 9 A schematic diagram of the structure of the DC conversion module provided in the embodiment of the present disclosure Figure 2 ; Fig.10A schematic diagram of the structure of the DC conversion module provided in the embodiment of the present disclosure Figure 3 ; Fig.11 Schematic diagram of the connection structure between the bias circuit and the amplifier provided in the embodiment of the present disclosure Figure 1 ; Fig.12 Schematic diagram of the connection structure between the bias circuit and the amplifier provided in the embodiment of the present disclosure Figure 2 ; Fig.13 A schematic diagram of an intermediate current and a bias current provided for an embodiment of the present disclosure; Fig.14 A schematic diagram of the structure of a power amplifier circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0017] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0018] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0020] Figure 1 An amplifier 200 and a bias circuit 101 in the technology are shown below. Figure 1 Taking the principle of bias circuit 101 controlling amplifier 200 in one technology as an example, the following is explained: It should be noted that the reference Figure 1The bias circuit 101 includes a bipolar transistor Q2 and resistors R11, R12 and R13. The bipolar transistor Q2 may also be other types of transistors, which is not limited here. Figure 1 The circuit system shown includes a current mirror, which includes a bipolar transistor Q2 and a bipolar transistor Q1 in the amplifier 200. Furthermore, the bias circuit 101 can apply a DC bias to the amplifier 200 by copying the current through the current mirror. The resistor R11 is connected in series between the power supply and the collector of the bipolar transistor Q2, and together with the bipolar transistor Q2, it forms a constant current source structure. The resistor R11 is used to generate a reference current Iref, which is used as a reference source of the current mirror and is mirror-copied to the bipolar transistor Q1 in the amplifier 200, thereby providing a stable bias current for the bipolar transistor Q1. The resistors R12 and R13 are used to adjust the current copy ratio between the reference current Iref in the bias circuit 101 and the working current Ic of the bipolar transistor Q1.

[0021] In the present disclosure, continue to refer to Figure 1 In order to ensure the accuracy of current copy, it is necessary to ensure Figure 1 The voltages of nodes A and B are consistent. Therefore, in the process of designing the bias circuit 101, the ratio of the resistors R12 and R13 between nodes A and B needs to be adjusted according to the current copy ratio. For example, the current Iref in the bias circuit 101 and the operating current Ic of the bipolar transistor Q1 are 1:20. Correspondingly, the ratio of the resistors R12 and R13 can be set to 20:1. At this time, the resistance of the resistor R13 close to the amplifier 200 is smaller, and the input signal may be Figure 1 The path S in the middle is bypassed to the ground, that is, the input signal is grounded in the order of node B, node C and bipolar transistor Q2, which will cause input signal loss. In addition, node B close to amplifier 200 is a low impedance node, which is more likely to couple power supply or substrate noise, adding additional noise sources. As a result, the noise figure (NF) of amplifier 200 decreases, seriously affecting the noise performance of amplifier 200. Especially when the input signal is a small signal, the noise performance has a greater impact on the overall performance of the amplifier.

[0022] Figure 2 and Figure 3 The embodiment of the present disclosure provides Figure 1 Schematic diagram of voltage variation of the amplifier 200 receiving different input signals, wherein the horizontal axis is time t, the unit is second (s), and the vertical axis is voltage U, the unit is volt (V). It should be noted that, Figure 2 and Figure 3 The DC bias voltage is proportional to the bias current. The DC bias voltage is Figure 1The control terminal (base) voltage of the bipolar transistor Q1 in the circuit. Figure 2 The input signal L1 is a small signal, that is, the input signal L1 has a relatively low power, and the power range may be between a few milliwatts and a few watts. Figure 3 The input signal L2 in is a large signal, that is, the input signal L1 has a relatively high power, and the power range can be between a few watts and a few kilowatts. Since the power is proportional to the square of the voltage swing, the voltage swing of the small signal input signal L1 is also smaller than the voltage swing of the large signal input signal L2.

[0023] In the embodiments of the present disclosure, reference Figure 1 , when the input signal is a small signal, Figure 2 The swing ratio of the input signal L1 Figure 3 The swing of input signal L2 is small, and the voltage value of the sum of input signal L1 and DC bias voltage is always greater than the turn-on voltage of bipolar transistor Q1. The swing of input signal L1 will not affect the working range of transistor. However, when the input signal is a large signal, such as Figure 3 As shown in the L3 area, the sum of the input signal L2 and the DC bias voltage is less than the turn-on voltage of the bipolar transistor Q1. In the process of amplifying the input signal L2, there will be a period of time when the bipolar transistor Q1 cannot be turned on. Therefore, the equivalent DC level of the overall input signal will be slightly raised, that is, the average voltage of the input signal L2 will be slightly raised, making Figure 1 The voltage at the middle point C rises, and then the reference current Iref decreases, thereby affecting the swing of the working current Ic of the bipolar transistor Q1 under large signals, and further having a greater impact on the linearity index of the amplifier 200.

[0024] Figure 4 1 is a schematic diagram of the structure of an optional bias circuit 100 provided in an embodiment of the present disclosure. The bias circuit 100 can be connected to an amplifier 200. The amplifier 200 can be any one of a class AB driver amplifier and a class B driver amplifier. The class AB driver amplifier and the class B driver amplifier can be used in a scenario where the input signal is a large signal, so the linearity index under the large signal is concerned.

[0025] In the embodiments of the present disclosure, reference Figure 4, the amplifier 200 may include a bipolar junction transistor (BJT) Q1. The bipolar transistor Q1 may be an amplifying transistor of the amplifier 200. The bipolar transistor is a base current-controlled transistor, and its base input resistance is relatively small. Its operating current Ic is proportional to the base current and has an exponential relationship with the base voltage. Therefore, it is very sensitive to voltage changes and has high requirements for noise coefficient. For example, the bipolar transistor Q1 may be a heterojunction bipolar transistor (HBT) or a homojunction bipolar transistor. Among them, the base current of the heterojunction bipolar transistor is relatively low, which reduces the base current shot noise (ShotNoise) and the base resistance thermal noise (Johnson Noise), and can significantly optimize the noise performance of small signals. The breakdown voltage of the heterojunction bipolar transistor can reach more than 15V, supporting a higher voltage swing, thereby reducing large signal clipping distortion and improving linearity indicators.

[0026] In the embodiments of the present disclosure, reference Figure 4 The amplifier 200 is used to receive and amplify an input signal and generate an output signal. The bias circuit 100 can output a bias current to the bipolar transistor Q1 of the amplifier 200. The bias circuit 100 includes a coupling module 10, a DC conversion module 20, and a current copy module 30. The bias circuit 100 can control the operating current of the bipolar transistor Q1 in the amplifier 200 by adjusting the bias current, thereby adjusting the linearity and other parameters of the amplifier 200.

[0027] In the embodiments of the present disclosure, reference Figure 4 , the coupling module 10 is connected to the output end of the amplifier 200. The coupling module 10 is configured to sample the voltage at the output end of the amplifier 200 to generate a sampling voltage. The sampling voltage may be an AC voltage. That is, the coupling module 10 may sample the output signal of the amplifier 200, thereby monitoring the power and / or swing change of the input signal through the change of the output signal.

[0028] The sampling voltage can feed back the amplitude change of the output voltage at the output end of the amplifier 200. The amplitude of the output voltage at the output end of the amplifier 200 is positively correlated with the amplitude of the input signal, and the amplitude of the output voltage at the output end of the amplifier 200 can reflect the amplitude of the input signal.

[0029] Meanwhile, the coupling module 10 is connected to the output end of the amplifier 200 , and the coupling module 10 does not contact the input end of the amplifier 200 . Therefore, the coupling module 10 will not affect the input signal received by the input end of the amplifier 200 .

[0030] In addition, the amplifier 200 amplifies the power of the input signal, so the amplitude of the output voltage at the output end of the amplifier 200 is larger than the amplitude of the input signal. Compared with sampling the input signal, the embodiment of the present disclosure samples the output signal, which can improve the sampling accuracy.

[0031] In the embodiments of the present disclosure, reference Figure 4 , the bias circuit 100 also includes a DC conversion module 20. The DC conversion module 20 is connected to the output end of the coupling module 10. The DC conversion module 20 is configured to receive a sampled voltage and convert the sampled voltage into a DC intermediate current. For example, the DC conversion module 20 may include a transistor, the sampled voltage may be a control terminal voltage of the transistor, and the intermediate current may be a drain current of the transistor. The bipolar transistor Q1 is a current-controlled device, and the DC conversion module 20 converts the sampled voltage into a DC intermediate current, so as to facilitate the subsequent conversion of the intermediate current into a bias current for controlling the bipolar transistor Q1.

[0032] In the embodiments of the present disclosure, reference Figure 4 , the bias circuit 100 also includes a current copy module 30. The current copy module 30 is respectively connected to the bipolar transistor Q1 and the DC conversion module 20. The current copy module 30 is configured to receive an intermediate current, and copy the intermediate current in proportion to a bias current, and output the bias current to the input end of the bipolar transistor Q1. For example, the current copy module 30 may include a current mirror. The current mirror can copy the intermediate current in proportion to a bias current. By proportionally copying the intermediate current through the current copy module 30, there is no need for the DC conversion module 20 to directly output a bias current that meets the requirements, thereby avoiding the device area of ​​the DC conversion module 20 being too large, reducing the integration area, and reducing power consumption.

[0033] When the amplitude (voltage value) of the input signal increases, the amplitude of the sampling voltage increases accordingly, the intermediate current increases accordingly, the bias current increases, and the DC bias voltage (control terminal voltage) of the bipolar transistor Q1 increases, so that the sum of the input signal and the DC bias voltage is always greater than the turn-on voltage of the bipolar transistor Q1, and the bipolar transistor Q1 is always turned on. Therefore, the operating current Ic of the bipolar transistor Q1 increases, thereby improving the linearity index of the amplifier.

[0034] Figure 5 is a schematic diagram of a circuit connection relationship between an optional bias circuit 100 and an amplifier 200 provided in an embodiment of the present disclosure. It should be noted that: Figure 5 The amplifier 200 illustrated in the example is a cascode structure, and the amplifier 200 includes a bipolar transistor Q1 and a transistor Mb. The amplifier 200 may also be a common source structure, a common gate structure, etc., which is not limited here. Figure 5The transistor Mb shown is described by taking an NMOS (N-Metal-Oxide-Semiconductor) as an example, and the transistor Mb may also be a bipolar transistor (BJT) or other types of transistors, which is not limited here.

[0035] In the embodiments of the present disclosure, reference Figure 5 , Figure 5 Inductor L1 and capacitor C12 form an output matching circuit of amplifier 200, which is used to match the output impedance of amplifier 200. Capacitor C12 can isolate the output signal from bias circuit 100. "In" is the input terminal of amplifier 200; "Out" is the output terminal of amplifier 200. "Vb1" is used to provide a bias voltage to transistor Mb. Transistor Mb and bipolar transistor Q1 form a common source and common gate structure to improve the output impedance of amplifier 200, so that amplifier 200 has better constant current characteristics.

[0036] It should also be noted that the reference Figure 4 and Figure 5 The connection node between the current copy module 30 and the amplifier 200 is located between the capacitor C11 and the bipolar transistor Q1 to prevent the capacitor C11 from filtering out the DC component in the bias current. The connection node between the coupling module 10 and the amplifier 200 is located between the capacitor C12 and the bipolar transistor Q1, and the sampling voltage of the coupling module 10 can retain the DC component of the voltage at the output end of the amplifier 200.

[0037] In the embodiments of the present disclosure, reference Figure 5 , the bias circuit 100 can sample the output end of the amplifier 200, and adjust the bias current output to the amplifier 200 based on the sampling result. The value of the bias current can be calculated and simulated according to the swing required by the linearity index of the actual output of the amplifier 200. The sampling result can be the voltage (i.e., the sampling voltage) at the output end of the amplifier 200, and the sampling result can feedback the power of the input signal. In other words, the bias circuit 100 can adjust the bias current output to the amplifier 200 based on the feedback of the output signal of the amplifier 200. For example, the bias circuit 100 can increase the bias current as the power of the input signal increases. In this way, the bias circuit 100 of the embodiment of the present disclosure can increase the bias current as the power of the input signal increases, and then, the sum of the DC bias voltage and the input signal voltage is greater than the turn-on voltage of the bipolar transistor Q1, thereby increasing the swing of the working current Ic of the bipolar transistor Q1, and then improving the linearity of the amplifier 200.

[0038] Figure 6 is a schematic diagram of the structure of an optional coupling module 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 6The directional coupler 110 shown in FIG. 1 is a four-port directional coupler. The directional coupler 110 may be of other types, which is not limited here.

[0039] In some embodiments, reference Figure 6 , the coupling module 10 may be a directional coupler 110. The directional coupler 110 is generally composed of a through line (main line) 111 and a coupled line (sub-line) 112. The input port P1 of the directional coupler 110 may be connected to Figure 1 The collector of the bipolar transistor Q1 of the amplifier 200, the output signal enters the directional coupler 110 through the input port P1. The output port P2 of the directional coupler 110 can be connected to the output terminal Out of the amplifier 200, and the output signal is output from the output port P2 to the next stage circuit after passing through the coupling amplifier 200. The coupling port P3 of the directional coupler 110 is connected to the DC conversion module 20, which is used to extract and output the coupled signal from the output signal. The isolation port P4 of the directional coupler 110 is used to reduce signal reflection and interference. For example, the isolation port P4 can be connected to loads such as resistors and capacitors. In this way, the directional coupler 110 can couple the output signal of the output terminal of the amplifier 200 to the coupling line 112 according to a certain proportion, and then the directional coupler 110 can process the coupled signal in the coupling line 112, generate a sampling voltage and output it to the DC conversion module 20. The directional coupler 110 realizes energy transfer through the electromagnetic field interaction between the through line 111 and the coupled line 112 , and the attenuation and interference of the output signal of the through line (main line) 111 during the sampling process are extremely small.

[0040] Figure 7 is a schematic diagram of the structure of an optional coupling module 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 7 The third voltage-dividing element 11 and the fourth voltage-dividing element 12 shown in the figure are both resistors. The third voltage-dividing element 11 and the fourth voltage-dividing element 12 may also be capacitors, which is not limited here.

[0041] In some embodiments, reference Figure 7 , the coupling module 10 may include a third voltage divider element 11 and a fourth voltage divider element 12. The third voltage divider element 11 and the fourth voltage divider element 12 are connected in series between the output terminal Out of the amplifier and the ground. The connection node D of the third voltage divider element 11 and the fourth voltage divider element 12 outputs the sampled voltage. For example, the third voltage divider element 11 may include a resistor R11, and the fourth voltage divider element 12 may include a resistor R12. In this way, the third voltage divider element 11 and the fourth voltage divider element 12 can sample the voltage of the output terminal Out of the amplifier by voltage division, and sample the voltage swing of the output terminal Out of the amplifier.

[0042] In some embodiments of the present disclosure, reference Figure 7, the resistance values ​​of the third voltage divider element 11 and the fourth voltage divider element 12 are both greater than 10 kilo-ohms. Thus, when the third voltage divider element 11 and the fourth voltage divider element 12 are used for voltage acquisition in the embodiment of the present disclosure, the current leakage is small, the power loss can be effectively reduced, and the resolution requirement of the detection circuit is reduced, making the detection circuit design more convenient.

[0043] Figure 8 and Fig. 9 is a schematic diagram of the structure of an optional DC conversion module 20 provided in an embodiment of the present disclosure. It should be noted that: Figure 8 and Fig. 9 The transistors M1 to M3 shown are all described by taking bipolar transistors (BJT) as an example, the first end of the transistors M1 to M3 is the collector, the second end of the transistors M0 to Mn is the emitter, and the control end of the transistors M0 to M3 is the base. The transistors M0 to M3 can also be other types of transistors such as NMOS tubes (N-Metal-Oxide-Semiconductor), which is not limited here. Figure 8 and Fig. 9 The node D in Figure 7 The third voltage dividing element 11 and the connection node of the third voltage dividing element 11 can be regarded as the output end of the coupling module 10. Figure 8 and Fig. 9 The node D in can also be Figure 6 P3 port.

[0044] In some embodiments of the present disclosure, reference Figure 8, the DC conversion module 20 includes a first voltage divider element 21, a second voltage divider element 22, a first capacitor C1, a tail current generating unit 23, a first transistor M1, a second transistor M2 and a third transistor M3. The first voltage divider element 21, the second voltage divider element 22 and the first capacitor C1 are sequentially connected in series between the output end and the ground of the coupling module 10, and the first capacitor C1 is grounded. The control end of the first transistor M1 is connected to the node E1 between the coupling module 10 and the first voltage divider element 21. The control end of the second transistor M2 is connected to the node E2 between the first voltage divider element 21 and the second voltage divider element 22. The control end of the third transistor M3 is connected to the node E3 between the second voltage divider element 22 and the first capacitor C1. In this way, the first voltage divider element 21 and the second voltage divider element 22 divide the sampling voltage. The DC conversion module 20 can control the AC voltage swing and DC voltage of nodes E1, E2, and E3 by controlling the voltage division ratio of the first voltage divider element 21 and the second voltage divider element 22, and then adjust the conduction degree of the first transistor M1, the second transistor M2, and the third transistor M3. Thus, the greater the conduction degree of the first transistor M1 and the third transistor M3, the greater the shunting ratio of the first transistor M1 and the third transistor M3 to the tail current Iee, and then the current value of the output intermediate current will increase. In other words, as the sampling voltage increases, the greater the shunting ratio of the first transistor M1 and the third transistor M3 to the tail current Iee, the intermediate current will also increase accordingly.

[0045] In the embodiments of the present disclosure, reference Figure 8 The first capacitor C1 is located between the second voltage dividing element 22 and the ground terminal. Therefore, at the same time, the first capacitor C1 can prevent the DC component of the sampled voltage from leaking from the ground terminal, thereby ensuring the accuracy of the intermediate current.

[0046] In the embodiments of the present disclosure, reference Figure 8, the DC conversion module 20 also includes a third resistor R3, a fourth resistor R4 and a second capacitor C2. The tail current generating unit 23 is used to provide a stable working current (tail current Iee). The first ends of the first transistor M1, the second transistor M2 and the third transistor M3 are all connected to the output end of the tail current generating unit 23, and receive the tail current Iee generated by the tail current generating unit 23. The first end of the second transistor M2 is respectively connected to the first end of the third resistor R3 and the first end of the second capacitor C2. The second end of the third resistor R3 is connected to the power supply end. The first end of the first transistor M1 and the first end of the third transistor M3 are both connected to the first end of the fourth resistor R4 and the second end of the second capacitor C2. The second end of the fourth resistor R4 is used to output the intermediate current. For example, the ratio of the equivalent size of the first transistor M1, the second transistor M2 and the third transistor M3 is 1:5:1. When the input signal is a small signal, the first transistor M1, the second transistor M2 and the third transistor M3 can shunt the tail current Iee at a ratio of 1:5:1. At this time, the intermediate current of the first transistor M1 and the third transistor M3 is 2 / 7Iee. In this way, the first transistor M1, the second transistor M2 and the third transistor M3 can distribute the tail current Iee generated by the tail current generating unit 23 according to the received control voltage. The second end of the first transistor M1 and the second end of the third transistor M3 are connected to the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the current copy module. The second end of the first transistor M1 and the third transistor M3 can output the intermediate current to the current copy module.

[0047] Furthermore, as the amplitude of the sampling voltage increases, the increase in the AC swing of the node E2 is half of that of the node E1. That is, as the amplitude of the sampling voltage increases, the increase in the AC swing of the first transistor M1 will be larger than that of the first transistor M1 of the second transistor M2, and the intermediate current output by the first transistor M1 and the third transistor M3 will be divided into more tail current Iee. In this way, when the amplitude of the sampling voltage gradually increases, the DC conversion module 20 can use the difference in the increase in the swing of the AC voltage of the node E1 and the node E2 to increase the diversion ratio of the first transistor M1 and the third transistor M3 to the tail current Iee, thereby increasing the current value of the output intermediate current.

[0048] It should be noted that the voltage division ratio of the first voltage divider element 21 and the second voltage divider element 22, as well as the equivalent size ratio of the first transistor M1, the second transistor M2 and the third transistor M3 can be designed according to actual needs, and are not limited here. The sizes of the first transistor M1 and the third transistor M3 can be different, and are not limited here.

[0049] In some embodiments, reference Figure 8, the first voltage-dividing element 21 and the second voltage-dividing element 22 are both resistors. For example, the first voltage-dividing element 21 includes a first resistor R1. The second voltage-dividing element 22 includes a second resistor R2. In this way, the DC component of the sampling voltage can be used as a bias voltage of the DC conversion module 20 and provided to the transistors M1, M2 and M3 in the DC conversion module 20. Therefore, the present disclosure does not need to additionally set a device for providing a bias voltage to the transistors M1, M2 and M3 in the DC conversion module 20, further reducing the area of ​​the bias circuit 100, improving the integration, and reducing energy consumption.

[0050] In other embodiments, reference Fig. 9 , the first voltage divider element 21 and the second voltage divider element 22 are both capacitors. The first voltage divider element 21 may include a capacitor C21. The second voltage divider element 22 may include a capacitor C22. The control terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are connected to the second bias current Ib. In this way, the second bias current Ib can provide a DC bias to the transistors M1, M2, and M3 in the DC conversion module 20.

[0051] In some embodiments, reference Figure 8 , the tail current generating unit 23 includes a first current mirror 231. The resistor R31 of the first current mirror 231 can generate a reference current Iref2. The input transistor M41 and the output transistor M42 copy the reference current Iref2 to generate a tail current Iee. The second ends of the transistors M1, M2 and M3 can all be connected to the collector of the output transistor M42. The input transistor M41 and the output transistor M42 can be any type of transistors, and are not limited here.

[0052] In other embodiments, reference Fig. 9 , the tail current generating unit 23 includes a current source 232. In this way, the current source 232 can directly provide the tail current Iee to the transistors M1, M2 and M3.

[0053] Figure 8 and Fig. 9 The detection circuit shown has a simple structure, low power consumption and high sensitivity, and can effectively improve the performance of the amplifier.

[0054] Fig.10 It is a schematic structural diagram of another optional DC conversion module 20 provided in an embodiment of the present disclosure.

[0055] In other embodiments of the present disclosure, refer to Fig.10The DC conversion module 20 includes a root mean square detector 210 and a voltage-to-current unit 220. The root mean square detector 210 is configured to receive a sampled voltage, and convert the sampled voltage into a DC voltage and output it. The voltage-to-current unit 220 is connected to the output end of the root mean square detector 210, and is configured to receive a DC voltage and convert the DC voltage into an intermediate current.

[0056] In the embodiments of the present disclosure, reference Fig.10 , the root mean square detector 210 may include an operational amplifier OP and a diode D1. The cathode of the diode D1 and the positive input terminal of the operational amplifier OP are connected to the output terminal D of the coupling module. The reverse input terminal of the operational amplifier OP is grounded. The operational amplifier OP is used to amplify the sampled voltage, and the diode D1 is used to detect the sampled voltage. In this way, the root mean square detector 210 can accurately measure the root mean square value of the sampled voltage and convert it into a stable DC voltage output.

[0057] In the embodiments of the present disclosure, reference Fig.10 , the voltage-to-current unit 220 may include a transistor M21. The output end of the operational amplifier OP is connected to the control end of the transistor M21. The first end of the transistor M21 outputs a bias current, and the second end of the transistor M21 is grounded. In this way, the DC voltage output by the RMS detector 210 provides a bias for the transistor M21, so that the conduction degree of the transistor M21 is different, thereby adjusting the intermediate current output by the transistor M21.

[0058] Fig.11 and Fig.12 is a schematic diagram of a circuit connection structure of an optional bias circuit 100 and an amplifier 200 provided in an embodiment of the present disclosure, Fig.11 and Fig.12 The structure of the current copy module 30 is illustrated in more detail. It should be noted that: Fig.11 and Fig.12 The intermediate coupling module 10 and the DC conversion module 20 can be understood with reference to the above embodiments, and will not be described in detail here. Fig.11 and Fig.12 The transistor M31 is the input transistor of the second current mirror 31, and the transistor M32 is the output transistor of the second current mirror 31. It should be noted that the current amplification ratio of the second current mirror 31 can be adjusted by adjusting parameters such as the width-to-length ratio (W / L) of the transistors M31 and M32.

[0059] In some embodiments of the present disclosure, reference Fig.11The current copy module 30 includes a second current mirror 31 and a fifth resistor R5. The input end of the second current mirror 31 receives the intermediate current, and the output end of the second current mirror 31 outputs the bias current of the mirror. In this way, as the amplitude of the input signal increases, the magnitude of the intermediate current increases, and the magnitude of the bias current increases. Thus, the swing of the operating current of the amplifier 200 can be increased, and the linearity index of the amplifier 200 can be improved.

[0060] In the embodiments of the present disclosure, reference Fig.11 , the fifth resistor R5 is located between the output end of the second current mirror 31 and the input end of the bipolar transistor Q1. In this solution, the resistance setting of the fifth resistor R5 is relatively free and is not limited by the mirror ratio of the second current mirror 31, so the resistance of the fifth resistor R5 can be greater than 10kΩ. In this way, when the input signal is a small signal, the bias circuit 100 of the embodiment of the present disclosure can prevent the input signal from being bypassed and grounded from the output end of the bias circuit 100, and can effectively prevent the current of the bipolar transistor Q1 from leaking through the bias circuit 100, avoiding input signal loss, and further improving the noise performance of the amplifier 200. In addition, there is a DC conversion module between the transistor M31 and the ground, which can also reduce current leakage.

[0061] In other embodiments of the present disclosure, refer to Fig.12 , the current copy module 30 also includes a fourth transistor M4 and a sixth resistor R6. The output end of the second current mirror 31 is respectively connected to the first end of the fourth transistor M4, the first end of the fifth resistor R5, and the first end of the sixth resistor R6. The second end of the fourth transistor M4 is grounded. The control end of the fourth transistor M4 is connected to the second end of the sixth resistor R6. The second end of the fifth resistor R5 is connected to the control end of the bipolar transistor Q1. In this way, as the amplitude of the input signal increases, the magnitude of the intermediate current increases, and the magnitude of the bias current increases. Thus, the output swing of the amplifier 200 can be increased, and the linearity index of the amplifier 200 can be improved. At the same time, the fifth resistor R5 and the sixth resistor R6 can shunt the bias current, and the current copy module 30 can adjust the bias current by adjusting the ratio of the fifth resistor R5 and the sixth resistor R6. In addition, the fourth transistor M4 is connected in series to the output end of the transistor M32 of the second current mirror 31, which improves the output impedance of the second current mirror 31, so that the second current mirror 31 has a better constant current characteristic.

[0062] In some embodiments of the present disclosure, reference Fig.12 The ratio of the fifth resistor R5 to the sixth resistor R6 is inversely proportional to the amplification factor of the second current mirror 31. In this way, the present disclosure can further improve the amplification factor of the second current mirror 31 by adjusting the resistance ratio of the fifth resistor R5 to the sixth resistor R6.

[0063] It should be noted that the ratio of the sixth resistor R6 to the fifth resistor R5 can be less than 20. The resistance value of the fifth resistor R5 can be designed according to actual needs. For example, the fifth resistor R5 can be in the order of kilo-ohms. In this way, when the input signal is a small signal, the bias circuit 100 of the embodiment of the present disclosure can prevent the input signal from being bypassed and grounded at the output end of the bias circuit 100, and can effectively prevent the current of the bipolar transistor Q1 from leaking through the bias circuit 100, thereby avoiding input signal loss, and further improving the noise performance of the amplifier 200. In addition, there is a DC conversion module between the transistor M31 and the ground, which can also reduce current leakage.

[0064] Fig.13 is a schematic diagram of an optional intermediate current and bias current provided in an embodiment of the present disclosure. It should be noted that: Fig.13 L4 is a curve showing a change in bias current and the power of the input signal, and L5 is a curve showing a change in the intermediate current and the power of the input signal.

[0065] In the present disclosure, Fig.13 As shown, as the power of the input signal increases, the power of the input signal gradually increases, and the intermediate current output by the DC conversion module 20 gradually increases as shown in L5. That is, as the power of the input signal increases, the amplitude (voltage value) of the input signal increases, the amplitude of the output signal increases, and the amplitude of the sampling voltage increases; furthermore, the intermediate current is positively correlated with the sampling voltage, and the magnitude of the intermediate current also increases.

[0066] In the present disclosure, Fig.13 As shown, as the power of the input signal increases, the amplitude of the input signal gradually increases, and the bias current output by the current copy module 30 gradually increases as shown in L4. In this way, as the amplitude (voltage value) of the input signal increases, the magnitude of the intermediate current increases, and the magnitude of the bias current increases; and the operating current of the bipolar transistor Q1 in the amplifier 200 is positively correlated with the magnitude of the bias current. When the swing of the input signal increases, the swing of the operating current of the bipolar transistor Q1 increases, thereby improving the linearity index of the amplifier 200.

[0067] Fig.13 The slope of L4 and L6 is greater than that of other regions; the slope of L5 and L7 is greater than that of other regions, which means that when the power of the input signal is within this range, the sensitivity of the bias circuit adaptation is higher. The slope of L4 is greater than that of L5, which means that the mirror ratio of the second current mirror is larger, and the intermediate current is amplified during the mirroring, which improves the sensitivity of the adaptation.

[0068] Fig.14 is a schematic diagram of an optional power amplifier circuit provided in an embodiment of the present disclosure, with reference to Fig.14The present disclosure also provides a power amplifier circuit 300. The power amplifier circuit 300 includes a bipolar transistor Q1 and the bias circuit 100 in the above embodiment. The bipolar transistor Q1 is an amplifying transistor of the power amplifier circuit 300. The control end of the bipolar transistor Q1 is connected to the output end of the bias circuit to receive the bias current output by the bias circuit 100.

[0069] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0070] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0071] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An adaptive bias circuit, characterized in that: Applied to an amplifier, the amplifier comprising a bipolar transistor; The bias circuit comprises: A coupling module, connected to the output end of the amplifier, configured to sample the voltage of the output end of the amplifier to generate a sampling voltage, wherein the sampling voltage is an AC voltage; a DC conversion module, connected to the output end of the coupling module, configured to receive the sampled voltage and convert the sampled voltage into a DC intermediate current; wherein the intermediate current is positively correlated with the sampled voltage; The current copy module is respectively connected to the bipolar transistor and the DC conversion module, and is configured to receive the intermediate current, copy the intermediate current in proportion to a bias current, and output the bias current to the input end of the bipolar transistor.

2. The bias circuit according to claim 1, characterized in that: The DC conversion module comprises: A first voltage-dividing element, a second voltage-dividing element and a first capacitor, wherein the first voltage-dividing element, the second voltage-dividing element and the first capacitor are sequentially connected in series between an output end of the coupling module and a ground, and the first capacitor is grounded; A tail current generating unit configured to generate a stable tail current; A first transistor, a second transistor and a third transistor, wherein the control end of the first transistor is connected to a node between the coupling module and the first voltage divider element; the control end of the second transistor is connected to a node between the first voltage divider element and the second voltage divider element; the control end of the third transistor is connected to a node between the second voltage divider element and the first capacitor; the first ends of the first transistor, the second transistor and the third transistor are all connected to the output end of the tail current generating unit for receiving the tail current; the second end of the first transistor and the second end of the third transistor are connected together for outputting the intermediate current.

3. The bias circuit according to claim 2, characterized in that: The first voltage dividing element and the second voltage dividing element are both resistors; or, The first voltage-dividing element and the second voltage-dividing element are both capacitors, and the control ends of the first transistor, the second transistor and the third transistor are also connected to a second bias current.

4. The bias circuit according to claim 3, characterized in that: The DC conversion module further includes: a third resistor, a fourth resistor and a second capacitor; wherein, The first end of the second transistor is connected to the first end of the third resistor and the first end of the second capacitor respectively; the second end of the third resistor is connected to the power supply end; The first end of the first transistor and the first end of the third transistor are both connected to the first end of the fourth resistor and the second end of the second capacitor; the second end of the fourth resistor is connected to the current copy module for outputting the intermediate current.

5. The bias circuit according to claim 2, wherein: The tail current generating unit includes: a first current mirror and / or a current source.

6. The bias circuit according to claim 1, wherein: The DC conversion module comprises: A root mean square detector, connected to the output end of the coupling module, configured to receive the sampled voltage, convert the sampled voltage into a direct current voltage and output it; The voltage-to-current unit is connected to the output end of the root mean square detector and is configured to receive the DC voltage and convert the DC voltage into the intermediate current.

7. The bias circuit according to claim 1, wherein: The coupling module is a directional coupler; or, The coupling module includes: a third voltage dividing element and a fourth voltage dividing element; wherein, The third voltage dividing element and the fourth voltage dividing element are connected in series between the output terminal of the amplifier and the ground, and a connection node between the third voltage dividing element and the fourth voltage dividing element outputs the sampling voltage.

8. The bias circuit according to claim 7, characterized in that: The third voltage-dividing element and the fourth voltage-dividing element are both resistors; or, the third voltage-dividing element and the fourth voltage-dividing element are both capacitors.

9. The bias circuit according to claim 8, characterized in that: The resistance values ​​of the third voltage-dividing element and the fourth voltage-dividing element are both greater than 10 kilo-ohms.

10. The bias circuit according to claim 1, wherein: The current copy module includes: A second current mirror, the input end of which receives the intermediate current and the output end of which outputs the bias current; A fifth resistor is located between the output end of the second current mirror and the input end of the bipolar transistor; and a resistance value of the fifth resistor is greater than 10 kilo-ohms.

11. The bias circuit according to claim 10, characterized in that: The current copy module further includes: a fourth transistor and a sixth resistor; wherein, The output end of the second current mirror is also connected to the first end of the fourth transistor, the first end of the fifth resistor, and the first end of the sixth resistor respectively; The second end of the fourth transistor is grounded; the control end of the fourth transistor is connected to the second end of the sixth resistor; The second end of the fifth resistor is connected to the input end of the bipolar transistor.

12. The bias circuit according to claim 11, characterized in that: The ratio of the fifth resistor to the sixth resistor is inversely proportional to the gain of the second current mirror.

13. The bias circuit according to claim 1, wherein: The bipolar transistor is a heterojunction bipolar transistor; the amplifier is a class AB driver amplifier or a class B driver amplifier.

14. A power amplifier circuit, characterized in that: include: A bipolar transistor and a bias circuit as claimed in any one of claims 1 to 13; wherein: The control end of the bipolar transistor receives the bias current output by the bias circuit.

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