Capacitance digital conversion method and circuit, touch screen system and electronic equipment

Abstract

The invention provides a capacitance digital conversion method and circuit, a touch screen system and electronic equipment. The method comprises the steps that a capacitance-to-voltage converter receives an initial capacitance signal sent by a touch sensor and converts the initial capacitance signal into a voltage analog signal, and the voltage analog signal corresponds to the capacitance value of the touch sensor; a first converter calculating a high bit of a digital value based on the voltage analog signal in a coarse quantization manner; a second converter calculates the low bits of the digital value in a fine quantized manner based on the residual component; wherein the second converter comprises a scaling type analog-to-digital conversion circuit; combination logic circuitry combines the high bits of the digital value and the low bits of the digital value to generate a digital value. According to the embodiment of the invention, weight matching and calibration are not needed, so that the complexity of the capacitance digital conversion circuit is reduced, the area of a chip is reduced, the converters are adopted in a segmented manner, the appropriate conversion range and conversion precision are obtained, and the conversion energy efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a capacitance-to-digital conversion method, circuit, touch screen system and electronic equipment. Background Art

[0002] Capacitance-to-digital conversion circuit (capacitance sensor) is based on the classic analog-to-digital converter, combined with capacitance-voltage and other pre-converters to complete capacitance-to-digital conversion. Its commonly used structures include successive approximation-register ADC (SAR ADC), Sigma-Delta analog-to-digital conversion circuit (SDADC), and so on. Successive approximation-register ADC (SARADC) has the characteristics of fast speed and high energy efficiency, but its accuracy is limited and the signal-to-noise ratio is low. Sigma-Delta analog-to-digital conversion circuit (SD ADC) has high accuracy, but slow speed and low energy efficiency. As for analog-to-digital conversion circuits (ADC) of other structures, for example, pipeline analog-to-digital converters (Pipeline ADC), flash analog-to-digital converters (Flash ADC), etc., the speed is far beyond the requirements of capacitance sensors, but its power consumption is relatively large and the accuracy is low, which still cannot meet the needs. Therefore, there is an urgent need for a capacitance-to-digital converter to solve the above problems. Summary of the invention

[0003] In view of at least one of the above technical problems existing in the prior art, the present application is proposed. According to one aspect of the present application, a capacitance-to-digital conversion method is provided, the method comprising:

[0004] The capacitance-to-voltage converter receives an initial capacitance signal sent by the touch sensor, and converts the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to a capacitance value of the touch sensor;

[0005] The first converter roughly calculates the high bits of the digital value based on the voltage analog signal;

[0006] The second converter calculates the lower bits of the digital value in fine quantization based on the residual component; wherein the second converter includes a scaling analog-to-digital conversion circuit;

[0007] The combinational logic circuit combines the upper bits of the digital value with the lower bits of the digital value to generate a digital value.

[0008] The capacitance-to-digital conversion method of the embodiment of the present application converts an initial capacitance signal into a voltage analog signal, and the first converter and the second converter respectively perform coarse quantization digital conversion and fine quantization digital conversion on the voltage analog signal sent by the capacitance-to-voltage converter to obtain the high bit and the low bit of the digital value to generate a digital value. Since the first converter does not need to perform weight matching and calibration, the complexity of the capacitance-to-digital conversion circuit is reduced, and the chip area is reduced. Moreover, according to the signal characteristics of the capacitance-to-digital conversion circuit, a suitable conversion circuit is adopted in segments to obtain an appropriate conversion range and conversion accuracy trade-off, thereby improving conversion energy efficiency.

[0009] Another aspect of the present application provides a capacitance-to-digital conversion circuit with a hybrid architecture, which is used to implement the capacitance-to-digital conversion method as described above. The capacitance-to-digital conversion circuit includes:

[0010] A capacitance-to-voltage converter, configured to receive an initial capacitance signal sent by the touch sensor and convert the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to a capacitance value of the touch sensor;

[0011] The analog-to-digital converter includes a first converter and a second converter, wherein the first converter is used to roughly quantize the high bits of the digital value based on the voltage analog signal; the second converter is used to receive the residual component sent by the first converter, and finely quantize the low bits of the digital value based on the residual component signal; wherein the second converter includes a scaling analog-to-digital conversion circuit;

[0012] A combinational logic circuit that combines the upper and lower bits of a digital value to generate a digital value.

[0013] According to another aspect of the embodiments of the present application, a touch screen system is provided. The touch screen system includes the capacitance-to-digital conversion circuit with the hybrid architecture as described above.

[0014] Another aspect of the present application provides an electronic device, wherein the system includes:

[0015] A memory and a processor, wherein the memory stores a computer program to be executed by the processor, and when the computer program is executed by the processor, the processor executes the capacitance-to-digital converter with the hybrid architecture as described above.

[0016] On another aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the processor executes the capacitance-to-digital converter with the hybrid architecture as described above.

[0017] The capacitive digital circuit, touch screen system, electronic device and storage medium with a hybrid architecture according to the embodiments of the present application can implement the aforementioned capacitive digital conversion method, and therefore have the same advantages as the aforementioned capacitive digital conversion method.

[0018] The capacitance-to-digital conversion circuit with a hybrid architecture of the embodiment of the present application has a capacitance-to-digital conversion circuit, method and touch screen system with a hybrid architecture. By converting an initial capacitance signal into a voltage analog signal, the first converter and the second converter respectively perform coarse quantization digital conversion and fine quantization digital conversion on the voltage analog signal sent by the capacitance-to-voltage converter to obtain the high bit and the low bit of the digital value to generate a digital value. Since the first converter does not need to perform weight matching and calibration, the complexity of the capacitance-to-digital conversion circuit is reduced, and the area of ​​the chip is reduced. Moreover, according to the signal characteristics of the capacitance-to-digital conversion circuit, a suitable conversion circuit is adopted in segments to obtain an appropriate conversion range and conversion accuracy trade-off, thereby improving conversion energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 A schematic diagram showing a capacitance-to-digital conversion method according to an embodiment of the present application is shown;

[0021] Figure 2 A schematic flow chart showing the low-bit conversion of a digital value by the second converter according to an embodiment of the present application;

[0022] Figure 3 A schematic flowchart of step S202 according to an embodiment of the present application is shown;

[0023] Figure 4 A schematic flowchart of step S301 according to an embodiment of the present application is shown;

[0024] Figure 5 A schematic flowchart showing step S301 according to another embodiment of the present application is shown;

[0025] Figure 6 A schematic diagram showing a change in capacitance of a capacitance-to-digital conversion circuit when a touch behavior occurs according to an embodiment of the present application;

[0026] Figure 7 A schematic flow chart showing a capacitance-to-digital conversion method according to yet another embodiment of the present application;

[0027] Figure 8 A schematic diagram showing a schematic diagram of a working process of a capacitance-to-digital conversion circuit according to an embodiment of the present application;

[0028] Fig. 9 A schematic block diagram of a capacitance-to-digital conversion circuit with a hybrid architecture according to an embodiment of the present application is shown;

[0029] Fig.10 A schematic block diagram of a touch screen system according to an embodiment of the present application is shown;

[0030] Fig.11 A schematic block diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] An analog-to-digital converter (ADC) can convert an analog signal - that is, an actual signal such as temperature, pressure, voltage, current, distance, or light intensity - into a digital representation of that signal. The system can then process, control, calculate, transmit, or store this digital representation. The conversion process of an analog-to-digital converter (ADC) can be: sampling the analog waveform at uniform time intervals and assigning a digital value to each sample. The digital value is displayed at the output of the converter in a binary coded format. This value is obtained by dividing the sampled analog input voltage by the reference voltage and multiplying it by the number of digital codes. The resolution of the converter is set by the number of binary bits in the output code. For a general analog-to-digital converter (ADC), the digital code it outputs represents the weight, and the digital code needs to be scaled strictly by 2 from high to low. For example Figure 3 , which is a schematic diagram of the digital code scaling process output by an analog-to-digital converter (ADC).

[0033] If the weight is not accurate, the output digital code will also be inaccurate. For example, for a 3-bit analog-to-digital converter (ADC), if the highest bit is much larger, then there will be a large section of missing code near the half of the full swing. If the highest bit is much smaller, then there will be a large section of code overlap near the half of the full swing. Similarly, if the weight of the second highest bit is not accurate, the weight deviation is too much, which will also cause the conversion waveform to be distorted.

[0034] In view of the above problem, although measures can be taken from aspects such as analog-to-digital converter (ADC) circuit calibration and circuit layout design to reduce this distortion, it increases complexity and comes at the expense of power consumption and circuit board area.

[0035] In one application scenario, a capacitance-to-digital conversion circuit includes a metal sheet covered on an insulating layer, which itself has a certain capacitance. The metal sheet is equivalent to the upper plate of the capacitor, and the earth is equivalent to the lower plate of the capacitor. Since the human body is a conductor and has an electric potential, when the human body approaches the capacitance-to-digital conversion circuit, the superposition of capacitance values ​​can be detected at the metal sheet end; at the same time, environmental factors such as temperature, humidity, and material aging can also cause capacitance value fluctuations. Generally, the capacitance value change caused by touch behavior is much smaller than the capacitance value change caused by the environment, and is also much smaller than the capacitance value of the entire capacitance-to-digital conversion circuit. For example, a capacitance-to-digital conversion circuit is distributed with a metal sheet with a diameter of several millimeters to several centimeters, and a ground wire is surrounded around the metal sheet, and its capacitance is approximately between 10pF and 100pF. When the human body approaches the capacitance-to-digital conversion circuit, its capacitance will change from tens of fF to hundreds of fF. Environmental changes will also bring about capacitance value changes of hundreds of fF to several pF. Among them, the signal change speed caused by the proximity of the conductor is the fastest, and the amount is still small, requiring high recognition speed and accuracy. Therefore, a high-precision capacitance-to-digital conversion circuit is required. Based on at least one of the above technical problems, the present application provides a capacitance digital conversion method, the method comprising: a capacitance voltage converter receives an initial capacitance signal sent by a touch sensor, and converts the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to the capacitance value of the touch sensor; a first converter roughly calculates the high bit of a digital value based on the voltage analog signal; a second converter finely calculates the low bit of the digital value based on a residual component; wherein the second converter includes a scaling analog-to-digital conversion circuit; and a combinational logic circuit combines the high bit of the digital value with the low bit of the digital value to generate a digital value. The capacitance digital conversion method of the embodiment of the present application converts the initial capacitance signal into a voltage analog signal, and the first converter and the second converter respectively perform a coarse quantization digital conversion and a fine quantization digital conversion on the voltage analog signal sent by the capacitance voltage converter to obtain the high bit and the low bit of the digital value to generate a digital value. Since the first converter does not need to perform weight matching and calibration, the complexity of the capacitance digital conversion circuit is reduced, and the chip area is reduced. Moreover, according to the signal characteristics of the capacitance digital conversion circuit, a suitable conversion circuit is adopted in segments to obtain an appropriate conversion range and conversion accuracy trade-off, thereby improving the conversion energy efficiency.

[0036] Figure 1 A schematic diagram showing a capacitance-to-digital conversion method according to an embodiment of the present application is shown; Figure 1As shown, the capacitance-to-digital conversion method 100 according to the embodiment of the present application may include step S101, step S102, step S103, and step S104:

[0037] In step S101 , the capacitance-to-voltage converter receives an initial capacitance signal sent by a touch sensor, and converts the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to a capacitance value of the touch sensor.

[0038] In step S102 , the first converter roughly calculates the upper bits of the digital value based on the voltage analog signal.

[0039] The first converter may include a successive-approximation-register ADC (SAR ADC) or a flash ADC or other low-precision and high-speed analog-to-digital conversion circuit.

[0040] The following embodiment of the present application is described by taking the first converter being a successive approximation analog-to-digital conversion circuit 201 as an example.

[0041] In one embodiment of the present application, the first converter generates a reference voltage (Cbaseline) according to the power supply voltage. The reference voltage of the analog-to-digital converter (ADC) refers to the starting point of its input voltage range. It is used to determine the conversion relationship between the analog input voltage and the digital output value of the analog-to-digital converter (ADC). The reference voltage is generally a fixed reference voltage, which can be a certain voltage value or a voltage range. The reference voltage can affect the conversion accuracy of the analog-to-digital converter (ADC). Generally speaking, the higher the reference voltage, the higher the conversion accuracy of the analog-to-digital converter (ADC). This is because the higher the reference voltage, the smaller the range corresponding to each digital quantity, so that the change of the input signal can be more accurately represented.

[0042] In step S103 , a second converter calculates low bits of the digital value in fine quantization based on the residual component; wherein the second converter includes a scaling analog-to-digital conversion circuit.

[0043] The second converter may include a zoom ADC. Since the second converter is used to calculate the lower bits of the digital value in fine quantization, the second converter uses a zoom ADC with high precision.

[0044] In step S104 , the combinational logic circuit combines the upper bits of the digital value with the lower bits of the digital value to generate a digital value.

[0045] In some examples, the digital value may be divided into a high bit and a low bit. In other words, the bit string of the digital value DV may include a high bit and a low bit.

[0046] In one embodiment of the present application, Figure 2 As shown, the method further includes step S201 and step S202:

[0047] In step S201, when the capacitance-to-digital converter is powered on, the second converter performs a first fine-quantization low-bit conversion of the digital value according to the residual component;

[0048] In step S202, the second converter determines whether the size of the lower bits of the digital value meets a preset condition, and updates the lower bits of the digital value if the preset condition is met.

[0049] The preset condition includes that the lower bit of the digital value is close to the critical value of the reference voltage. For example, if the reference voltage range is 1V-5V, then its critical value is 1V and 5V. When the lower bit of the digital value is 1.2V or 4.9V, it can be regarded as close to the critical value of the reference voltage.

[0050] In one embodiment of the present application, Figure 3 As shown, in step S202, the second converter updates the low bit of the digital value when a preset condition is met, including:

[0051] In step S301, the first converter notifies the first converter to adjust the reference voltage according to the reference voltage critical value to which the lower bit of the digital value approaches;

[0052] In step S302, the second converter re-obtains the residual component according to the adjusted reference voltage;

[0053] In step S303, the second converter updates the lower bits of the digital value according to the reacquired residual component;

[0054] In step S304, the process returns to re-determine whether the low-order value of the updated digital value meets a preset condition.

[0055] In the embodiment of the present application, since the lower bits of the digital value are calculated based on the residual component, after the reference voltage is adjusted, the residual component also changes accordingly, and therefore the lower bits of the digital value need to be recalculated based on the changed residual component.

[0056] It is worth noting that the voltage analog signal minus the amount converted by the SAR ADC is the residual, which is processed by the zoom ADC to form the low bit of the digital value. Therefore, the weight of the SAR ADC does not need to be very accurate, as long as most of the values ​​are roughly subtracted.

[0057] In one example, if Figure 4 As shown, the first converter in step S301 adjusts the reference voltage, including:

[0058] Step S401: determining the amplitude of the reference voltage reduction or increase according to the capacitance value change of the initial capacitance signal, so that the capacitance value change of the initial capacitance signal is within the adjusted reference voltage range.

[0059] In one embodiment of the present application, the number of high bits of digital value and the number of low bits of digital value are determined respectively according to at least the conversion capability of the first converter and the conversion capability of the second converter. First, the number of high bits of digital value can be determined at least according to the conversion capability of the first converter. For example, when the first converter is capable of performing 8-bit analog-to-digital conversion, the high bits can include 8 bits. Secondly, the number of low bits of digital value can be determined at least according to the conversion capability of the second converter. For example, when the second converter is capable of performing 4-bit analog-to-digital conversion, the low bits can include 4 bits. According to the above example, the digital value DV can include a bit string of up to 12 bits. As described above, the analog-to-digital converter can perform analog-to-digital conversion at high speed and has high resolution. Therefore, the first converter generating the high bits can adopt an analog-to-digital conversion scheme with relatively high speed, and the second converter generating the low bits can adopt an analog-to-digital conversion scheme with relatively high precision.

[0060] Among them, Figure 6 , which is a schematic diagram of the change in capacitance of the capacitance-to-digital conversion circuit when a touch occurs. Figure 6 It can be seen that the reference voltage is a voltage range, and the voltage range of the reference voltage includes a minimum value (ie, a first critical value) and a maximum value (ie, a second critical value), and the first critical value is lower than the second critical value.

[0061] In another example, Figure 5 As shown, the first converter in step S301 adjusts the reference voltage, including:

[0062] Step S501: when the lower bit of the digital value approaches the first critical value, the first converter reduces the reference voltage by at least one amplitude;

[0063] Step S502: when the low-order value of the digital value approaches the second critical value, the first converter increases the reference voltage by at least one amplitude.

[0064] For example, when the low bit value of the digital value is 20% lower than the reference voltage, it can be considered close to the first critical value; when the low bit value of the digital value is 60% higher than the reference voltage, it can be considered close to the second critical value.

[0065] Assuming that the digital representation supported by the first converter is 8 bits, and the total capacitance of its capacitive elements is 1PF, the capacitance of a single capacitive element is 0.125PF. When adjusting the reference voltage, one amplitude is 0.125PF. For example, when the first critical value corresponds to 0.375PF, the low bit of the digital value is close to the first critical value, and the difference is not large, one amplitude of the first critical value can be adjusted, that is, the reference voltage is correspondingly lowered by 0.125PF, and the adjusted first critical value is 0.25PF; if lowering one amplitude cannot cover the low bit of the digital value, two amplitudes can be adjusted, and the adjusted first critical value corresponds to 0.375PF. For another example, when the second critical value corresponds to 0.75PF, the low bit of the digital value is close to the second critical value, one amplitude can be increased, and the adjusted second critical value is 0.875PF; if the increased second critical value cannot cover the low bit of the digital value, two amplitudes can be adjusted, and the adjusted second amplitude corresponds to 1PF. And so on.

[0066] The embodiment of the present application adopts a capacitance-to-digital conversion circuit with a hybrid architecture. Usually, the capacitance change caused by touch behavior is much smaller than the capacitance change caused by the environment, and is also much smaller than the overall capacitance value of the entire capacitance-to-digital conversion circuit. In addition, the touch behavior is judged based on the fluctuation shape and has nothing to do with the absolute size of the capacitance value waveform. Therefore, the weight accuracy requirement of the high position of the converter can be reduced, that is, the capacitance value of the capacitance-to-digital conversion circuit can be subtracted by a substantial amount, leaving only the waveform within the fluctuation range for accurate conversion, so as to improve the conversion efficiency without affecting the final conversion result.

[0067] The capacitance digital conversion circuit (capacitor digital conversion, CDC) architecture used in the embodiment of the present application adopts a structure combining a successive approximation analog-to-digital conversion circuit (SAR ADC) and a zoom analog-to-digital conversion circuit (Zoom ADC). The embodiment of the present application adopts a successive approximation analog-to-digital conversion circuit (SAR ADC) to convert the high bits of the digital value to obtain a reference voltage (Cbaseline), that is, to generate a reference voltage (Cbaseline) corresponding to a rough capacitance value, and then the zoom analog-to-digital conversion circuit (Zoom ADC) converts the changes in the environment and touch into the low bits of the digital value. It is worth noting that the capacitance digital conversion circuit (capacitor digital conversion, CDC) of the embodiment of the present application needs to make the change in the zoom analog-to-digital conversion circuit (Zoom ADC) sufficient to cover the change in capacitance value caused by the environment throughout the product life cycle.

[0068] The capacitance-to-digital conversion method of the embodiment of the present application converts an initial capacitance signal into a voltage analog signal, and the first converter and the second converter respectively perform coarse quantization digital conversion and fine quantization digital conversion on the voltage analog signal sent by the capacitance-to-voltage converter to obtain the high bit and the low bit of the digital value to generate a digital value. Since the first converter does not need to perform weight matching and calibration, the complexity of the capacitance-to-digital conversion circuit is reduced, and the chip area is reduced. Moreover, according to the signal characteristics of the capacitance-to-digital conversion circuit, a suitable conversion circuit is adopted in segments to obtain an appropriate conversion range and conversion accuracy trade-off, thereby improving conversion energy efficiency.

[0069] like Figure 7 , which is a schematic flow chart of a capacitance-to-digital conversion method according to another embodiment of the present application. The capacitance-to-digital conversion method 700 according to the embodiment of the present application may include the following steps S701, S702, S703, S704, S705, and S707;

[0070] In step S701 , the capacitance-to-digital conversion circuit is initialized to operate.

[0071] Here, the initialization of the capacitance-to-digital conversion circuit refers to an initialization operation performed on the capacitance-to-digital conversion circuit when it leaves the factory. Generally speaking, the capacitance-to-digital conversion circuit is initialized only once.

[0072] In step S702 , a successive approximation analog-to-digital conversion circuit (SAR ADC) generates a reference voltage according to a power supply voltage VDD.

[0073] Here, only a successive approximation analog-to-digital converter (SAR ADC) is used as an example for introduction. In specific implementation, other high-speed and low-precision analog-to-digital converters may be used, such as a flash analog-to-digital converter (Flash ADC).

[0074] In step S703, the zoom ADC converter performs a first analog-to-digital conversion.

[0075] Here, the first conversion of the zoom ADC converter refers to the first analog-to-digital conversion performed by the zoom ADC converter each time the capacitor-to-digital converter circuit is powered on and used during the use of the capacitor-to-digital converter circuit.

[0076] In step S704 , the zoom ADC circuit refreshes the lower bits of the output digital value.

[0077] In step S705 , the zoom ADC circuit determines whether the low bit of the digital value is close to the reference voltage critical value; if yes, step S706 is executed; otherwise, step S707 is executed.

[0078] For example, it can be set to be 70 which is higher than the highest critical value of the reference voltage, and regarded as close to the highest critical value of the reference voltage. In this case, step S706 can be executed.

[0079] In step S706, the zoom ADC circuit refreshes the lower bits of the output digital value, and the process returns to step S704.

[0080] In step S707 , the zoom ADC maintains the output digital value at a low level, and the process returns to step S704 .

[0081] Those skilled in the art should know that the zoom analog-to-digital conversion circuit (Zoom ADC) is an analog-to-digital converter (ADC) structure formed by combining a high-bit SAR ADC and a low-bit SD ADC. Since the capacitance change caused by the environment is significantly greater than the capacitance change caused by the touch behavior, the embodiment of the present application improves the processing method of the zoom analog-to-digital conversion circuit (Zoom ADC). After the zoom analog-to-digital conversion circuit (Zoom ADC) completes the first conversion, the detection of the touch behavior is completely handed over to the SD ADC part of the zoom analog-to-digital conversion circuit (Zoom ADC) for processing, and the conversion range of the SD ADC of the zoom analog-to-digital conversion circuit (Zoom ADC) is required to be sufficient to cover the capacitance fluctuation range caused by the touch behavior. Only when the conversion range of the SD ADC of the zoom ADC is close to the edge of the conversion range, such as when it reaches 20% of the lowest critical value of the reference voltage or 80% of the maximum critical value of the reference voltage, the value of the SAR ADC part of the zoom ADC is readjusted once, so that the entire zoom ADC is an analog-to-digital converter (ADC) structure composed of a high-bit SAR ADC and a low-bit SD ADC.

[0082] like Figure 8 FIG. 1 is a schematic diagram of the working process of the capacitance-to-digital conversion circuit of the embodiment of the present application. The shaded portion represents the conversion portion of Zoom / SD. As the environment changes and the Zoom / SAR value is adjusted, the conversion range of Zoom / SD will move up and down accordingly.

[0083] The embodiment of the present application processes the capacitance in segments through two converters, so that the three parts of the capacitance value (the range gradually decreases, the speed gradually increases, and the accuracy requirement gradually increases) are properly processed. This can achieve:

[0084] (1) Reduce chip area. Since the first converter in the highest stage does not need weight matching, it does not require complex layout matching drawing and calibration circuits, saving a portion of the chip (i.e., circuit board) area.

[0085] (2) Improve energy efficiency. Based on the signal characteristics of the capacitive sensor, the converter is used in segments to obtain the appropriate conversion range and conversion accuracy trade-off. For example, the operating frequency of the SD ADC, which has relatively high power consumption, is reduced (SAR only needs to be initialized once at the factory, and Zoom / SAR depends on the speed of environmental changes). SD only needs to convert a very small range, so the clock frequency can be reduced, and power consumption is also reduced accordingly.

[0086] Fig. 9 A schematic diagram of a capacitance-to-digital conversion circuit with a hybrid architecture according to an embodiment of the present application is shown; Figures 1 to 8 The capacitance-to-digital conversion method in any example. Fig. 9 As shown, a capacitance-to-digital conversion circuit 900 with a hybrid architecture according to an embodiment of the present application may include a capacitance-to-voltage converter 10 , an analog-to-digital converter 20 , and a combinational logic circuit 30 .

[0087] In one embodiment of the present application, the capacitance-to-voltage converter 10 is used to receive an initial capacitance signal sent by a touch sensor and convert the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to the capacitance value of the touch sensor.

[0088] In one embodiment of the present application, the analog-to-digital converter 20 is used to perform coarse quantization digital conversion and fine quantization digital conversion on the voltage analog signal sent by the capacitor-to-voltage converter to generate a digital value.

[0089] In some examples, the digital value may be divided into a high bit and a low bit. In other words, the bit string of the digital value DV may include a high bit and a low bit.

[0090] In one embodiment of the present application, the analog-to-digital converter 20 includes a first converter and a second converter:

[0091] The first converter is used to roughly calculate a high bit of a digital value based on the voltage analog signal.

[0092] The second converter is used to receive the residual component sent by the first converter, and calculate the low bit of the digital value in a fine quantized manner based on the residual component signal.

[0093] The second converter may include a zoom analog-to-digital conversion circuit (Zoom ADC) 202. Since the second converter is used to calculate the lower bits of the digital value in fine quantization, the second converter adopts a high-precision analog-to-digital converter.

[0094] The first converter may include a successive-approximation-register ADC (SAR ADC) 201 or a low-precision and high-speed analog-to-digital conversion circuit such as a flash analog-to-digital converter (Flash ADC).

[0095] In view of the signal characteristics of the capacitance-to-digital conversion circuit (also referred to as a capacitance sensor), the embodiment of the present application divides the digital-to-analog converter into two sections, respectively adopting a successive approximation analog-to-digital conversion circuit (SAR ADC) architecture and a zoom analog-to-digital conversion circuit (Zoom ADC) architecture.

[0096] In one embodiment of the present application, the combinational logic circuit 30 is used to combine the upper bits and the lower bits of the digital value to generate a digital value.

[0097] In some embodiments, the upper bits and lower bits of the digital value may be generated sequentially, that is, after the first converter generates the upper bits of the digital value, the second converter generates the lower bits according to the residual component.

[0098] Then, the combinatorial logic circuit 30 may receive the upper bits generated by the first converter and the lower bits generated by the second analog-to-digital converter. The combinatorial logic circuit 30 performs arithmetic operations and / or logic operations on the upper bits and the lower bits to generate a digital value.

[0099] The present application also provides a touch screen system, such as Fig.10 As shown, the touch screen system 1000 includes the capacitance-to-digital conversion circuit 900 with the hybrid architecture as described above.

[0100] Combine the following Fig.11 The electronic device of the present application is described, wherein: Fig.11 A schematic block diagram of an electronic device 1100 according to an embodiment of the present application is shown. The electronic device 1100 includes the touch screen system 1000 as described above.

[0101] like Fig.11 As shown, the electronic device 1100 also includes: one or more memories 1101 and one or more processors 1102, and the memory 1101 stores a computer program executed by the processor 1102, and when the computer program is executed by the processor 1102, the processor 1102 executes the capacitance-to-digital conversion method described above.

[0102] The electronic device 1100 may be part or all of a computer device that can implement the capacitance-to-digital conversion method through software, hardware, or a combination of software and hardware.

[0103] like Fig.11 As shown, the electronic device 1100 includes one or more memories 1101, one or more processors 1102, a display (not shown), and a communication interface, etc. These components are interconnected through a bus system and / or other forms of connection mechanisms (not shown). It should be noted that Fig.11 The components and structures of the electronic device 1100 shown are merely exemplary and non-limiting. The electronic device 1100 may also have other components and structures as required.

[0104] The memory 1101 is used to store various data and executable program instructions generated during the operation of the related method, such as for storing various application programs or algorithms for implementing various specific functions. It can include one or more computer program products, and the computer program product can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0105] The processor 1102 may be a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other form of processing unit having data processing capabilities and / or instruction execution capabilities, and may be other components in the electronic device 1100 to perform the desired functions.

[0106] In one example, the electronic device 1100 also includes an output device that can output various information (such as images or sounds) to the outside (such as a user), and can include one or more of a display device, a speaker, and the like.

[0107] The communication interface can be an interface of any currently known communication protocol, such as a wired interface or a wireless interface, wherein the communication interface may include one or more serial ports, USB interfaces, Ethernet ports, WiFi, wired networks, DVI interfaces, device integrated interconnect modules or other suitable ports, interfaces, or connections.

[0108] In addition, according to an embodiment of the present application, a storage medium is also provided, on which program instructions are stored, and when the program instructions are run by a computer or a processor, the corresponding steps of the capacitance digital conversion method of the embodiment of the present application are used. The storage medium may include, for example, a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, or any combination of the above storage media.

[0109] The capacitive digital circuit, touch screen system, electronic device and storage medium with a hybrid architecture according to the embodiments of the present application can implement the aforementioned capacitive digital conversion method, and therefore have the same advantages as the aforementioned capacitive digital conversion method.

[0110] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0111] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0112] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0113] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0114] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0115] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0116] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0117] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some modules according to the embodiments of the present application. The application can also be implemented as a device program (e.g., computer program and computer program product) for executing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0118] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0119] The above is only a specific implementation or description of a specific implementation of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A capacitance-to-digital conversion method, applied to a capacitance-to-digital conversion circuit, characterized in that: The method comprises: The capacitance-to-voltage converter receives an initial capacitance signal sent by the touch sensor, and converts the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to a capacitance value of the touch sensor; The first converter roughly calculates the high bits of the digital value based on the voltage analog signal; The second converter calculates the lower bits of the digital value in fine quantization based on the residual component; wherein the second converter includes a scaling analog-to-digital conversion circuit; The combinational logic circuit combines the upper bits of the digital value with the lower bits of the digital value to generate a digital value.

2. The method according to claim 1, characterized in that in, The first converter includes a successive approximation analog-to-digital conversion circuit or a flash analog-to-digital converter.

3. The method according to claim 1, characterized in that: in, The first converter generates a reference voltage according to a power supply voltage.

4. The method according to claim 3, characterized in that: The method further comprises: When the capacitance-to-digital converter is powered on, the second converter performs a first fine-quantization low-bit conversion of the digital value according to the residual component; The second converter determines whether the size of the lower bits of the digital value meets a preset condition, and updates the lower bits of the digital value if the preset condition is met.

5. The method according to claim 4, characterized in that in, The preset condition includes that a lower bit of the digital value is close to a reference voltage critical value.

6. The method according to claim 5, characterized in that When a preset condition is met, the second converter updates the lower bit of the digital value, including: The first converter notifies the first converter to adjust the reference voltage according to the reference voltage critical value that the low bit of the digital value is close to; The second converter re-obtains the residual component according to the adjusted reference voltage; The second converter updates the lower bits of the digital value according to the reacquired residual component; Returns whether the low-order value of the updated digital value meets the preset conditions.

7. The method according to claim 6, characterized in that The first converter adjusts the reference voltage, comprising: The amplitude of the reference voltage reduction or increase is determined according to the capacitance value change of the initial capacitance signal, so that the capacitance value change of the initial capacitance signal is within the adjusted reference voltage range.

8. The method according to claim 6, characterized in that The reference voltage critical value includes a first critical value and a second critical value, and the first critical value is lower than the second critical value; the first converter adjusts the reference voltage, including: When the low bit of the digital value approaches the first critical value, the first converter reduces the reference voltage by at least one amplitude; when the low bit of the digital value approaches the second critical value, the first converter increases the reference voltage by at least one amplitude.

9. A capacitance-to-digital conversion circuit with a hybrid architecture, characterized in that: Used to implement the capacitance-to-digital conversion method according to any one of claims 1 to 8, the capacitance-to-digital conversion circuit comprising: A capacitance-to-voltage converter, configured to receive an initial capacitance signal sent by the touch sensor and convert the initial capacitance signal into a voltage analog signal, wherein the voltage analog signal corresponds to a capacitance value of the touch sensor; The analog-to-digital converter includes a first converter and a second converter, wherein the first converter is used to roughly quantize the high bits of the digital value based on the voltage analog signal; the second converter is used to receive the residual component sent by the first converter, and finely quantize the low bits of the digital value based on the residual component signal; wherein the second converter includes a scaling analog-to-digital conversion circuit; A combinational logic circuit that combines the upper and lower bits of a digital value to generate a digital value. 10 . A touch screen system, comprising the capacitance-to-digital conversion circuit with a hybrid architecture according to claim 9 .

11. An electronic device, characterized in that: The electronic device comprises the touch screen system as claimed in claim 10; the electronic device further comprises: A memory and a processor, wherein the memory stores a computer program executed by the processor, and when the computer program is executed by the processor, the processor executes the capacitance-to-digital conversion method according to any one of claims 1 to 8.

12. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the processor executes the capacitance-to-digital conversion method according to any one of claims 1 to 8.

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