Very-low-frequency demodulation method and system for two-way cache half-speed parallel processing

Abstract

The invention discloses a very low frequency demodulation method and system for two-way cache half-speed parallel processing, and relates to the field of signal processing, and the method comprises the steps: converting a very low frequency minimum frequency shift keying signal into a first-way signal and a second-way signal according to the high and low levels of a local baud rate signal, writing the first path of signal into a first memory under the synchronous control of the local baud rate signal, and writing the second path of signal into a second memory under the synchronous control of the local baud rate signal; under the synchronous control of the local baud rate signal, reading out the first path of signal from the first memory and carrying out first frequency domain conversion processing to obtain a first frequency component, and under the synchronous control of the local baud rate signal, reading out the second path of signal from the second memory and carrying out second frequency domain conversion processing to obtain a second frequency component; and performing parallel-serial conversion on the first frequency component and the second frequency component under the synchronous control of the local baud rate signal to obtain a serial demodulation output signal. By implementing the method, the timeliness of demodulating the signal in the very low frequency communication system is improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular to a very low frequency demodulation method and system for dual-path buffer half-speed parallel processing. Background Art

[0002] The VLF communication system operates in the 3-30kHz frequency band and has the characteristics of strong penetration, low attenuation, and long transmission distance. It plays an important role in communication applications in special environments such as underwater and underground. Due to the limited bandwidth resources in the VLF band, frequency shift keying modulation technology is widely used.

[0003] In the related art, the receiving end of the very low frequency communication system uses frequency domain transformation technology to demodulate the frequency shift keying signal. This technology performs frequency domain transformation operation on the received signal and analyzes the frequency components of the signal to complete the demodulation.

[0004] However, as the baud rate of the communication system increases, the computational speed of the frequency domain transform cannot keep up with the signal input rate, resulting in untimely processing of the received signal and affecting the real-time performance of the system. Summary of the invention

[0005] The present application provides a very low frequency demodulation method and system for dual-path buffer half-speed parallel processing, which are used to improve the timeliness of demodulation signals in a very low frequency communication system.

[0006] In the first aspect, the present application provides a very low frequency demodulation method with dual-path cache and half-speed parallel processing, which is applied to a very low frequency demodulation system, and the method includes: converting a very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of a local baud rate signal, wherein when the local baud rate signal is at a high level, the very low frequency minimum shift keying signal is converted into the first signal, and when the local baud rate signal is at a low level, the very low frequency minimum shift keying signal is converted into the second signal; writing the first signal into a first memory under the synchronous control of the local baud rate signal, and writing the second signal into a second memory under the synchronous control of the local baud rate signal; reading the first signal from the first memory under the synchronous control of the local baud rate signal and performing a first frequency domain transformation processing to obtain a first frequency component, reading the second signal from the second memory under the synchronous control of the local baud rate signal and performing a second frequency domain transformation processing to obtain a second frequency component; and performing parallel-to-serial conversion on the first frequency component and the second frequency component under the synchronous control of the local baud rate signal to obtain a serial demodulation output signal.

[0007] By adopting the above technical scheme, the very low frequency minimum shift keying signal is converted into the first signal and the second signal according to the high and low levels of the local baud rate signal, thereby realizing the serial-to-parallel conversion and shunting processing of the signal, converting the serial signal into two parallel data streams that can be processed at half speed, writing the two signals into different memories under the synchronous control of the local baud rate signal, and then performing frequency domain transformation processing. The processed frequency components can be converted from parallel to serial to obtain a serial demodulation output signal under the synchronous control of the local baud rate signal, thereby ensuring the timing timeliness and data integrity of the entire demodulation process, effectively improving the demodulation efficiency and accuracy, and realizing stable demodulation of the very low frequency minimum shift keying signal.

[0008] In combination with some embodiments of the first aspect, in some embodiments, before the step of converting the very low frequency minimum shift keying signal into the first signal and the second signal according to the high and low levels of the local baud rate signal, the method also includes: performing synchronization processing on the received very low frequency minimum shift keying signal to obtain a synchronization processing result; generating a local baud rate signal according to the synchronization processing result, and calculating frequency domain transformation parameters according to the local baud rate signal, the frequency domain transformation parameters including sampling rate and transformation length.

[0009] By adopting the above technical scheme, the received very low frequency minimum shift keying signal is synchronously processed to obtain a synchronous processing result. The local baud rate signal generated thereby can control the rhythm of subsequent data processing. The calculated frequency domain transformation parameters can provide a suitable sampling rate and transformation length for the frequency domain transformation processing, thereby improving the adaptability of signal processing, ensuring accurate demodulation under different signal conditions, and further improving the reliability and stability of the demodulation method, so that the entire demodulation system can better cope with various situations and effectively reduce the probability of demodulation errors caused by inappropriate parameters.

[0010] In combination with some embodiments of the first aspect, in some embodiments, the step of reading out the first signal from the first memory under the synchronous control of the local baud rate signal and performing a first frequency domain transformation processing to obtain a first frequency component, and reading out the second signal from the second memory under the synchronous control of the local baud rate signal and performing a second frequency domain transformation processing to obtain a second frequency component, specifically includes: reading out the first signal from the first memory under the synchronous control after the local baud rate signal is divided into two, and performing a first frequency domain transformation processing on the first signal to obtain the first frequency component; reading out the second signal from the second memory under the synchronous control after the local baud rate signal is divided into two, and performing a second frequency domain transformation processing on the second signal to obtain the second frequency component; determining the frequency corresponding to the maximum amplitude in the first frequency component as f0, and determining the frequency corresponding to the maximum amplitude in the second frequency component as f1.

[0011] By adopting the above technical solution, the signal is read from the memory and frequency domain transformation is performed under synchronous control after the local baud rate signal is divided into two parts. The clock control after the two-part frequency division enables the two signals to be processed alternately to form a pipeline structure, which effectively solves the problem of insufficient frequency domain transformation time, and determines that the frequencies corresponding to the maximum amplitude values ​​in the frequency components are f0 and f1, which can accurately obtain key frequency information, help to accurately determine the original data bit value, improve the accuracy of demodulation, and make the demodulation result more consistent with the actual signal situation, thereby better restoring the information carried by the original signal.

[0012] In combination with some embodiments of the first aspect, in some embodiments, the step of performing parallel-to-serial conversion on the first frequency component and the second frequency component under the synchronous control of the local baud rate signal to obtain a serial demodulation output signal specifically includes: generating a demodulation decision result according to f0 in the first frequency component and f1 in the second frequency component under the synchronous control of the local baud rate signal, wherein the demodulation value corresponding to f0 is 0, and the demodulation value corresponding to f1 is 1; and merging the demodulation decision results in a chronological order to obtain the serial demodulation output signal.

[0013] By adopting the above technical solution, under the synchronous control of the local baud rate signal, the demodulation judgment result is generated according to f0 in the first frequency component and f1 in the second frequency component, and the corresponding relationship between f0 and f1 and the demodulation value ensures the accuracy of the judgment. The judgment results are combined in time sequence to obtain a serial demodulation output signal, restore the original data time sequence, and improve the quality of the demodulation output signal.

[0014] In combination with some embodiments of the first aspect, in some embodiments, the first memory and the second memory write signals at the local baud rate signal frequency, and read signals at half the local baud rate signal frequency.

[0015] By adopting the above technical solution, the first and second memories are written at the local baud rate signal frequency and read at half the frequency. The writing frequency ensures that the signal is stored in time to avoid loss, and the reading frequency realizes caching to solve the rate mismatch problem.

[0016] In combination with some embodiments of the first aspect, in some embodiments, the first signal is read out from the first memory under the synchronous control of the local baud rate signal and a first frequency domain transformation is performed to obtain a first frequency component, and the second signal is read out from the second memory under the synchronous control of the local baud rate signal and a second frequency domain transformation is performed to obtain a second frequency component. The parameter determination method of the frequency domain transformation processing includes: determining the transformation time of each frequency domain as half of the period of the local baud rate signal according to the local baud rate signal; determining the sampling rate and transformation length that satisfy the ratio of the sampling rate to the transformation length equal to half of the frequency of the local baud rate signal according to the transformation time; and performing frequency domain transformation processing on the first signal and the second signal respectively according to the sampling rate and transformation length.

[0017] By adopting the above technical solution, the frequency domain transformation time is determined to be half of the period according to the local baud rate signal, and time resources are reasonably allocated to ensure timely processing. The adaptive sampling rate and transformation length are determined accordingly to ensure that the frequency domain transformation is effective and accurate. These parameters are used to process the two signals and accurately obtain the frequency components, laying the foundation for accurate demodulation, improving the accuracy of frequency analysis, enhancing the adaptability to different signal characteristics, and making the demodulation results more in line with the actual signals.

[0018] In combination with some embodiments of the first aspect, in some embodiments, the depth of the first memory and the depth of the second memory are both the transformation length.

[0019] By adopting the above technical solution, the depth of the first and second memories is made equal to the transformation length, and the amount of data read from the memory is precisely matched with the transformation requirements, thereby avoiding inaccurate processing due to data problems.

[0020] In a second aspect, an embodiment of the present application provides a very low frequency demodulation system, which includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to enable the very low frequency demodulation system to perform the method described in the first aspect and any possible implementation method of the first aspect.

[0021] In a third aspect, an embodiment of the present application provides a computer program product comprising instructions. When the above-mentioned computer program product runs on a very low frequency demodulation system, the above-mentioned very low frequency demodulation system executes the method described in the first aspect and any possible implementation method of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions. When the instructions are executed on a very low frequency demodulation system, the very low frequency demodulation system executes the method described in the first aspect and any possible implementation manner of the first aspect.

[0023] It can be understood that the very low frequency demodulation system provided in the second aspect, the computer program product provided in the third aspect, and the computer storage medium provided in the fourth aspect are all used to execute the method provided in the embodiment of the present application. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method, which will not be repeated here.

[0024] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. The present application realizes serial-to-parallel conversion and shunting processing of signals by converting a very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of a local baud rate signal, converts a serial signal into two parallel data streams that can be processed at half speed, writes the two signals into different memories under the synchronous control of a local baud rate signal, and then performs frequency domain transformation processing. The processed frequency components can be converted from parallel to serial to obtain a serial demodulated output signal under the synchronous control of a local baud rate signal, thereby ensuring the timing timeliness and data integrity of the entire demodulation process, effectively improving the demodulation efficiency and accuracy, and realizing stable demodulation of very low frequency minimum shift keying signals.

[0025] 2. The present application obtains a synchronization processing result by performing synchronization processing on the received very low frequency minimum shift keying signal. The local baud rate signal generated thereby can control the rhythm of subsequent data processing. The calculated frequency domain transformation parameters can provide a suitable sampling rate and transformation length for the frequency domain transformation processing, thereby improving the adaptability of signal processing, ensuring accurate demodulation under different signal conditions, and further improving the reliability and stability of the demodulation method, so that the entire demodulation system can better cope with various situations and effectively reduce the probability of demodulation errors caused by inappropriate parameters.

[0026] 3. The present application reads out the signal from the memory and performs frequency domain transformation processing under synchronous control after the local baud rate signal is divided into two parts. The clock control after the two-division allows the two signals to be processed alternately to form a pipeline structure, effectively solving the problem of insufficient frequency domain transformation time, and determining the frequencies corresponding to the maximum amplitude values ​​in the frequency components as f0 and f1. It can accurately obtain key frequency information, help to accurately determine the original data bit value, improve the accuracy of demodulation, and make the demodulation result more consistent with the actual signal situation, thereby better restoring the information carried by the original signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1It is a flowchart of a very low frequency demodulation method of dual-path buffer half-speed parallel processing in an embodiment of the present application; Figure 2 is another flowchart of a very low frequency demodulation method for dual-path buffer half-speed parallel processing in an embodiment of the present application; Figure 3 It is a schematic diagram of a physical device structure of a very low frequency demodulation system in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be used as limitations to the present application. As used in the specification of the present application, the singular expressions "one", "a kind of", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear indication to the contrary in the context. It should also be understood that the term "and / or" used in the present application refers to any or all possible combinations comprising one or more of the listed items.

[0029] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0030] For ease of understanding, the following is a description of the process of the method provided by this implementation. Figure 1 , is a flow chart of a very low frequency demodulation method with dual-path cache and half-speed parallel processing in an embodiment of the present application.

[0031] S101. Convert a very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of a local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is at a high level, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is at a low level.

[0032] Among them, the very low frequency minimum frequency shift keying signal refers to a digital modulation signal operating in the 3-30kHz frequency band, using two specific frequencies to represent the digital "0" and "1" respectively. The local baud rate signal fb refers to the reference clock obtained after frame header synchronization with the same rate as the transmitting end, which is used to control the rhythm of data processing. The first signal represents the data stream sampled during the high level of fb. The second signal represents the data stream sampled during the low level of fb. Serial-to-parallel conversion refers to the process of distributing the continuous modulation signal to two parallel channels according to the high and low level timing of fb.

[0033] This step is executed after the frame header synchronization is completed, and is used to realize the serial-to-parallel conversion and shunt processing of the signal. Specifically, the system shunts the input very low frequency minimum frequency shift keying signal according to the high and low level states of the local baud rate signal fb. When fb is high, the input signal is directed to the first channel; when fb is low, the input signal is directed to the second channel. This shunt mechanism converts the serial signal that originally needs to be processed at the fb rate into two parallel data streams that can be processed at the fb / 2 rate, creating conditions for subsequent half-speed processing.

[0034] In some embodiments, serial-to-parallel conversion can be implemented in a variety of ways: Optionally, a circuit based on a D flip-flop is used for implementation, including: configuring two D flip-flops to sample data during high and low levels respectively; using the rising edge of the fb signal to trigger the first D flip-flop and the falling edge to trigger the second D flip-flop; obtaining two data streams respectively through the output buffer. Optionally, a multiplexer is used for implementation, including: configuring a 1:2 distributor circuit; connecting the fb signal to the selection control terminal; turning on the first output when fb is high and the second output when fb is low; buffering and shaping the output signal. It is understandable that other circuit structures can also be used to implement the serial-to-parallel conversion function, which is not limited here.

[0035] S102: write the first signal into a first memory under the synchronous control of the local baud rate signal, and write the second signal into a second memory under the synchronous control of the local baud rate signal.

[0036] The first memory fifo1 and the second memory fifo2 refer to first-in-first-out storage units for caching data, and their depth is equal to the frequency domain transformation length n. The write operation refers to storing the shunted signal into the corresponding memory under the control of fb. Synchronous control means using the clock edge of fb to trigger data writing to ensure the accuracy of the write timing. The memory depth is equal to the transformation length to ensure the complete data sample required for a frequency domain transformation.

[0037] This step is performed after the serial-to-parallel conversion is completed to achieve cache storage of two signals. Specifically, when fb is high, the system writes the first signal into fifo1; when fb is low, the second signal is written into fifo2. The writing process uses the fb rate, while the subsequent reading uses the fb / 2 rate. This difference in writing and reading rates realizes the data cache function. The write operation of each memory is strictly carried out according to the timing of fb to ensure the continuity and integrity of the data.

[0038] In some embodiments, data caching can be implemented in a variety of ways: Optionally, an asynchronous FIFO structure is used, including: configuring two FIFO memories with independent read and write clocks; connecting fb to the write clock terminal; setting a write address counter; monitoring the FIFO status flag to control data writing. Optionally, a dual-port RAM structure is used, including: configuring two dual-port RAM units; using fb to drive the write address counter; resetting when the count value reaches n; controlling the timing of data writing through write enable. It is understandable that other storage structures can also be used to implement the data caching function, which is not limited here.

[0039] S103, under the synchronous control of the local baud rate signal, read out the first signal from the first memory and perform a first frequency domain transformation process to obtain a first frequency component, and under the synchronous control of the local baud rate signal, read out the second signal from the second memory and perform a second frequency domain transformation process to obtain a second frequency component.

[0040] Among them, frequency domain transformation processing refers to the mathematical operation process of converting time domain signals into frequency domain representation, which is implemented by fast Fourier transform. Frequency component refers to the n frequency components with unequal amplitudes obtained after transformation, where the amplitude corresponding to the fi-th frequency component is ai. Synchronous control means using the clock after the local baud rate signal fb is divided by two to control the data readout and processing timing. The first and second frequency domain transformation processing correspond to the independent processing processes of the two signals respectively, and the processing parameters include the sampling rate fc and the transformation length n, which satisfy the relationship of fc / n=fb / 2. The read operation refers to the process of retrieving data from the memory at a rate of fb / 2.

[0041] This step is executed after the two signals have completed caching, realizing half-speed parallel frequency domain processing. Specifically, the system divides the local baud rate signal fb into two to obtain a processing clock with a frequency of fb / 2, and controls the readout and transformation processing of the two signals. When one signal is undergoing frequency domain transformation, the other signal is undergoing data acquisition, forming an alternating processing pipeline structure. Each time, n data points are taken for FFT operation to obtain n frequency components. This half-speed processing mechanism decomposes the operation that originally needs to be processed at the fb rate into two parallel operations at the fb / 2 rate, solving the problem of insufficient frequency domain transformation time.

[0042] In some embodiments, half-speed frequency domain processing can be implemented in a variety of ways: Optionally, a hardware FFT processor is used for implementation, including: configuring a dedicated FFT processor chip; setting processing parameters fc and n; sending memory output data to the FFT processor; reading the spectrum result after processing is completed; and performing amplitude calculation on the spectrum data. Optionally, a software FFT algorithm is used for implementation, including: configuring a DSP processor; loading a base-2 FFT program; reading an n-point data sequence from the memory; performing an FFT operation to obtain a complex spectrum; and calculating the amplitude of each frequency component. It is understandable that other algorithms or processors can also be used to implement the frequency domain transformation function, which is not limited here.

[0043] S104, performing parallel-to-serial conversion on the first frequency component and the second frequency component under synchronous control of the local baud rate signal to obtain a serial demodulation output signal.

[0044] Among them, parallel-to-serial conversion refers to the process of recombining two parallel frequency components into a single data stream. The serial demodulation output signal refers to the bit stream reorganized according to the timing of the original data, where frequency f0 corresponds to the demodulation value 0 and frequency f1 corresponds to the demodulation value 1. Local baud rate signal synchronization control means using the clock edge of fb to trigger data conversion and output. The frequency component refers to the characteristic frequency obtained after frequency domain transformation, which is used to determine the bit value of the original data.

[0045] This step is performed after completing the two-way frequency domain transformation processing to achieve the reorganization output of the demodulation result. Specifically, the system processes the two frequency components alternately according to the rhythm of the local baud rate signal fb. In each cycle of fb, the corresponding frequency components are converted into digital bit values ​​and output in a timing order. This process recombines the parallel data of the two channels at the rate of fb / 2 into a serial data stream at the rate of fb, restoring the timing relationship of the original data.

[0046] In some embodiments, parallel-to-serial conversion can be implemented in a variety of ways: Optionally, a multiplexer can be used to implement the function, including: configuring a 2:1 digital multiplexer; connecting two frequency components to the data input terminal; using fb to control channel selection; configuring a latch at the output terminal; and outputting serial data in a time sequence. Optionally, a shift register can be used to implement the function, including: configuring a dual-port shift register; loading the first data at a high level of fb; loading the second data at a low level of fb; using fb to drive the shift operation; and obtaining the data stream from the serial output terminal. It is understandable that other circuit structures can also be used to implement the parallel-to-serial conversion function, which is not limited here.

[0047] The following is a more detailed description of the process of the method provided by this implementation. Figure 2 , is another flow chart of the very low frequency demodulation method with dual-path cache and half-speed parallel processing in an embodiment of the present application.

[0048] S201, performing synchronization processing on a received very low frequency minimum shift keying signal to obtain a synchronization processing result.

[0049] Very low frequency minimum shift keying signal is a digital modulation signal operating in the 3-30kHz frequency band, using two frequencies f0 and f1 to represent the digital 0 and 1 respectively. Synchronous processing is a signal processing technology used to extract timing information from the received signal to ensure that the data transmission rhythm of the receiving end is consistent with that of the transmitting end. The result of the synchronous processing contains bit synchronization and frame synchronization information. Bit synchronization is used to determine the sampling time of each bit, and frame synchronization is used to determine the starting position of the data frame.

[0050] In this step, the system first digitally samples the received VLF minimum frequency shift keying signal, and then extracts the timing characteristics of the signal through correlation operations or envelope detection. In specific implementation, the zero-crossing detection method can be used to detect the jump point of the signal, and the time interval between adjacent jump points can be counted to establish a time histogram. By analyzing the peak position of the time histogram, the bit period information of the signal can be obtained. At the same time, by detecting a specific synchronization header sequence, the boundary of the data frame is determined. The final output synchronization processing result contains bit clock recovery information and frame synchronization mark information.

[0051] S202: Generate a local baud rate signal according to the synchronization processing result, and calculate frequency domain transformation parameters according to the local baud rate signal, where the frequency domain transformation parameters include a sampling rate and a transformation length.

[0052] The local baud rate signal is a clock signal related to the data transmission rate and is used to control the sampling and processing of data. The frequency domain transformation parameters are the key parameters required for frequency domain analysis, including the sampling rate (i.e., the number of sampling points per unit time) and the transformation length (i.e., the number of data points processed in one transformation).

[0053] In this step, the system generates a square wave clock signal with the same baud rate frequency as the received signal as the local baud rate signal according to the synchronization processing result obtained in step S201. Then, based on the period of the local baud rate signal, the appropriate sampling rate and transformation length are calculated. The selection of the sampling rate must satisfy the Nyquist sampling theorem, that is, at least twice the highest signal frequency. The transformation length needs to make a trade-off between time resolution and frequency resolution, and is generally selected as an integer multiple of the ratio of the sampling rate to the local baud rate signal frequency.

[0054] S203, converting the very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of the local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is at a high level, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is at a low level.

[0055] The first signal and the second signal are very low frequency minimum frequency shift keying signals after shunting, corresponding to the signal segments during the high level and low level of the local baud rate signal respectively. High and low levels refer to the two logical states of digital signals, with high level usually represented as "1" and low level represented as "0".

[0056] In this step, the system implements signal shunting by judging the level state of the local baud rate signal. When the local baud rate signal is at a high level, the very low frequency minimum frequency shift keying signal sampling value of this period is output to the first channel; when the local baud rate signal is at a low level, the very low frequency minimum frequency shift keying signal sampling value of this period is output to the second channel. This shunting method can be implemented by a digital switch or a multiplexer, and the control signal is the local baud rate signal.

[0057] S204, writing the first signal into a first memory under the synchronous control of the local baud rate signal, and writing the second signal into a second memory under the synchronous control of the local baud rate signal.

[0058] The first memory and the second memory (fifo1 and fifo2) are two independent first-in-first-out cache units, and their depth is equal to the transformation length n. The write operation refers to storing data in the storage unit in sequence under the synchronous control of the local baud rate signal fb. The synchronous control is specifically manifested as using the rising edge or falling edge of the local baud rate signal fb to trigger the data write action. The first signal and the second signal are two digital signal streams obtained in the previous step according to the high and low level shunting of fb.

[0059] In the specific implementation process, the first signal is written to fifo1 during the period when fb is high, and the second signal is written to fifo2 during the period when fb is low. The write clock of both memories uses fb, and the write address is generated by the modulo-n counter. The write enable signal of each memory is controlled by the level state of fb: when fb is high, fifo1 write enable is valid, and when fb is low, fifo2 write enable is valid. When the write address count reaches n-1, it automatically returns to zero, forming a cyclic writing process. The data bit width of the memory needs to meet the signal quantization accuracy requirements, and usually adopts a 12-bit or 16-bit structure. This dual fifo structure realizes the signal caching and diversion functions, providing data support for subsequent parallel processing.

[0060] S205 , reading the first signal from the first memory under synchronous control after the local baud rate signal is divided into two, and performing a first frequency domain transformation process on the first signal to obtain the first frequency component.

[0061] Frequency division by two means reducing the signal frequency to half of the original frequency. The implementation method is to divide the local baud rate signal fb by 2 to obtain a new clock signal with a frequency of fb / 2. Frequency domain transformation processing is a mathematical operation process that converts time domain sampling data into frequency domain representation. It is implemented using fast Fourier transform (FFT). The first frequency component refers to the n frequency components obtained after the FFT operation. Each component contains amplitude and phase information.

[0062] In this step, first use a D flip-flop to divide fb by two to obtain a readout clock with a frequency of fb / 2. Under the control of this readout clock, n data points are read out from fifo1 for a complete FFT operation. The parameters of FFT are set as: sampling rate fc, transform length n. FFT calculation obtains n frequency components, ranging from 0 to fc / 2, and the frequency resolution is fc / n. Each frequency component fi corresponds to an amplitude value ai, and the value range of i is 1 to n. These frequency components constitute the spectral characteristics of the first signal, which is used for subsequent frequency identification. The entire processing process is carried out at a rhythm of fb / 2 to ensure that there is enough time to complete the FFT operation.

[0063] S206. Read the second signal from the second memory under synchronous control after the local baud rate signal is divided into two, and perform a second frequency domain transformation on the second signal to obtain the second frequency component. The first memory and the second memory write signals at the frequency of the local baud rate signal and read signals at half the frequency of the local baud rate signal. The depths of the first memory and the second memory are both the transformation length.

[0064] This step involves the frequency domain transformation processing of the second signal and the read and write timing control of the memory. The memory depth refers to the data storage capacity of fifo1 and fifo2, which is equal to the FFT transformation length n. The write and read operations are performed at the frequencies of fb and fb / 2 respectively, forming a rate ratio of 2:1 and realizing a half-speed processing mechanism. The second frequency component has the same data structure as the first frequency component and also contains n frequency component information.

[0065] During the implementation process, the data reading and FFT processing of fifo2 use the same control logic as fifo1, but the timing is staggered by half a cycle. When one signal is undergoing FFT operation, the other signal is undergoing data acquisition, and the two processes are performed alternately to form a pipeline structure. The read address of each memory is generated by a modulo-n counter driven by the fb / 2 clock, and it restarts from 0 when the read address reaches n-1. The result of the FFT operation is n complex frequency components, where the i-th frequency component corresponds to a frequency of i×fc / nHz and an amplitude of ai. This double-buffered half-speed parallel processing mechanism effectively solves the problem of insufficient FFT operation time at high baud rates and improves the real-time processing capability of the system.

[0066] S207 , determining that the frequency corresponding to the maximum amplitude in the first frequency component is f0 , and determining that the frequency corresponding to the maximum amplitude in the second frequency component is f1 .

[0067] The frequency component is the spectrum information obtained after the FFT transformation. Each component contains a frequency value and a corresponding amplitude value. The maximum amplitude value refers to the component with the highest amplitude among the n frequency components, and its corresponding frequency is the characteristic frequency to be detected. f0 and f1 represent the characteristic frequencies detected in the first and second signals, respectively, and are used for subsequent demodulation decisions. For example, in the n=2048-point FFT result, if the amplitude of a frequency component is significantly higher than that of other components, then this frequency is the characteristic frequency to be detected.

[0068] In the specific implementation process, the amplitude values ​​of the n frequency components of the first FFT result are compared one by one. Set an initial maximum amplitude value amax=0, and compare the amplitude value of each component with amax in turn. If the current component amplitude is greater than amax, update the amax value and record the corresponding frequency value. After the comparison is completed, the recorded frequency is f0. The second FFT result is processed in the same way to obtain f1. In order to improve the detection reliability, it is also necessary to set the amplitude threshold value, and only the amplitude exceeding the threshold is involved in the maximum value comparison. The resolution of frequency detection is determined by the FFT parameters, and the interval between adjacent frequency components is fc / nHz.

[0069] S208 , generating a demodulation decision result according to f0 in the first frequency component and f1 in the second frequency component under synchronous control of the local baud rate signal, wherein the demodulation value corresponding to f0 is 0, and the demodulation value corresponding to f1 is 1.

[0070] Demodulation decision is the process of converting the detected characteristic frequency into digital bits. The synchronous control of the local baud rate signal ensures that the decision is made at the right time. The demodulation values ​​0 and 1 are the two basic states in digital communication, corresponding to the detected f0 and f1 frequencies respectively. The decision result is a binary decision output within each code element period, which needs to be generated in a timing sequence under the control of the baud rate signal.

[0071] The specific implementation process of this step is as follows: First, establish the frequency decision threshold, and record the two frequencies used in FSK modulation as F0 and F1 respectively. When the detected f0 is close to F0 (the frequency deviation is within the preset range), the demodulation value 0 is output; when f0 is close to F1, the demodulation value 1 is output. Similarly, when f1 is close to F0, 0 is output, and when it is close to F1, 1 is output. The decision process is triggered on the rising edge of the local baud rate signal fb to ensure that the decision result is synchronized with the data clock. The decision result is latched by a D flip-flop to avoid glitch interference. The decision circuit can be implemented with combinational logic, including a frequency comparator and a decision logic.

[0072] S209: Combine the demodulation decision results in a time sequence to obtain the serial demodulation output signal.

[0073] The serial demodulation output signal refers to the process of recombining the judgment results of two parallel processing into a single serial data stream. The timing sequence refers to the rearrangement of the data bits according to the time sequence of the original data. The merging operation requires precise control of the alternating output timing of the two data to ensure that data bits are not lost or repeated.

[0074] In the implementation process, a 2:1 digital multiplexer is used to complete the parallel-to-serial conversion. The two data input terminals of the multiplexer are connected to the two judgment results respectively, and the selection signal uses the local baud rate signal fb. When fb is high, the first judgment result is selected, and when fb is low, the second judgment result is selected. The output end obtains a complete serial data stream with a data rate of fb. To ensure that the output data is synchronized with the original data, a D flip-flop can be added at the output end, and the output data is latched using the rising edge of fb. In addition, a buffer circuit needs to be designed to smooth out the glitches that may be generated during data switching and improve the quality of the output signal. The entire parallel-to-serial conversion process is strictly controlled according to the timing to ensure the integrity and accuracy of the demodulated output signal.

[0075] The parameter determination method of the frequency domain transformation processing includes: determining the transformation time of each frequency domain according to the local baud rate signal as half of the period of the local baud rate signal; According to the conversion time, determining a sampling rate and a conversion length that satisfy a ratio of the sampling rate to the conversion length equal to half of the frequency of the local baud rate signal; The first signal and the second signal are respectively subjected to frequency domain transformation processing according to the sampling rate and the transformation length.

[0076] The local baud rate signal is the system's reference clock, and its period T=1 / fb determines the basic timing of data processing. The transformation time refers to the time window required to complete a frequency domain transformation, which is T / 2 in this design. The sampling rate fc is the number of sampling points per unit time, and the transformation length n is the number of data points processed by an FFT. The ratio of the two, fc / n, represents the time resolution of the FFT operation. Frequency domain transformation processing is a mathematical operation process that converts time domain signals to frequency domain, which is implemented using the FFT algorithm. For example, when fb=100Hz, the transformation time is 5ms. If fc=1024Hz is selected, then n=2048 points satisfy the relationship fc / n=fb / 2.

[0077] The first step is to determine the conversion time based on the local baud rate signal fb. Due to the dual-channel alternating processing mechanism, the processing time of each signal is half of the baud rate period, that is, T / 2. This time window must meet the frequency resolution requirements and ensure that the processing is completed before the next data arrives. In the specific implementation, fb is used for two-way frequency division to obtain the processing clock to control the start and end of the FFT operation.

[0078] The second step is to determine the sampling rate fc and the transform length n. These two parameters must satisfy the relationship fc / n=fb / 2. When selecting parameters, first determine the minimum value of the sampling rate fc based on the signal bandwidth to satisfy the Nyquist sampling theorem. Then calculate the transform length n=2fc / fb that satisfies the relationship. To facilitate FFT implementation, n is taken as an integer power of 2. For example, if the highest signal frequency is 400Hz, then fc is at least 800Hz, and can actually be 1024Hz. When fb=100Hz, n=2048 points can be obtained.

[0079] The third step is to use the determined parameters to perform frequency domain transformation processing. For the first signal, n data points are collected during the high level of fb, and the FFT operation is completed during the low level of the next cycle; for the second signal, data is collected during the low level of fb, and the FFT operation is completed during the high level of the next cycle. The two-way processing is performed alternately without interfering with each other. The FFT operation uses a fast algorithm of base-2, and the data storage uses in-situ operation to save storage space. The operation result contains n complex frequency components, and the frequency resolution is fc / nHz.

[0080] The following describes the very low frequency demodulation system in the embodiment of the present invention from the perspective of hardware processing. Figure 3 , is a schematic diagram of a physical device structure of a very low frequency demodulation system in an embodiment of the present application.

[0081] It should be noted that Figure 3 The structure of the very low frequency demodulation system shown is only an example and shall not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0082] like Figure 3 As shown, the VLF demodulation system includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 302 or the program loaded from the storage part 308 to the random access memory (RAM) 303, such as executing the method described in the above embodiment. In the RAM 303, various programs and data required for system operation are also stored. The CPU 301, the ROM 302 and the RAM 303 are connected to each other through the bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0083] The following components are connected to the I / O interface 305: an input section 306 including an audio input device, a button switch, etc.; an output section 307 including a liquid crystal display (LCD) and an audio output device, an indicator light, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. A removable medium 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 310 as needed so that a computer program read therefrom is installed into the storage section 308 as needed.

[0084] In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 309, and / or installed from a removable medium 311. When the computer program is executed by the central processing unit (CPU) 301, various functions defined in the present invention are performed.

[0085] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus, or device.

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. Each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings.

[0087] Specifically, the VLF demodulation system of this embodiment includes a processor and a memory. The memory stores a computer program. When the computer program is executed by the processor, the VLF demodulation method of dual-path cache half-speed parallel processing provided in the above embodiment is implemented.

[0088] As another aspect, the present invention further provides a computer-readable storage medium, which may be included in the very low frequency demodulation system described in the above embodiment; or may exist independently without being assembled into the very low frequency demodulation system. The above storage medium carries one or more computer programs, and when the above one or more computer programs are executed by a processor of the very low frequency demodulation system, the very low frequency demodulation system implements the very low frequency demodulation method of dual-path buffer half-speed parallel processing provided in the above embodiment.

[0089] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0090] As used in the above embodiments, the term "when..." may be interpreted to mean "if..." or "after..." or "in response to determining..." or "in response to detecting...", depending on the context. Similarly, the phrases "upon determining..." or "if (the stated condition or event) is detected" may be interpreted to mean "if determining..." or "in response to determining..." or "upon detecting (the stated condition or event)" or "in response to detecting (the stated condition or event)", depending on the context.

[0091] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

Claims

1. A dual-path buffer half-speed parallel processing very low frequency demodulation method, characterized in that: Applied to a very low frequency demodulation system, the method comprises: Converting a very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of the local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is at a high level, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is at a low level; Writing the first signal into a first memory under the synchronous control of the local baud rate signal, and writing the second signal into a second memory under the synchronous control of the local baud rate signal; Under the synchronous control of the local baud rate signal, the first signal is read out from the first memory and subjected to a first frequency domain transformation process to obtain a first frequency component, and under the synchronous control of the local baud rate signal, the second signal is read out from the second memory and subjected to a second frequency domain transformation process to obtain a second frequency component; The first frequency component and the second frequency component are converted into serial-parallel under the synchronous control of the local baud rate signal to obtain a serial demodulation output signal.

2. The method according to claim 1, characterized in that Before the step of converting the very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of the local baud rate signal, the method further includes: Performing synchronization processing on the received very low frequency minimum frequency shift keying signal to obtain a synchronization processing result; A local baud rate signal is generated according to the synchronization processing result, and frequency domain transformation parameters are calculated according to the local baud rate signal, wherein the frequency domain transformation parameters include a sampling rate and a transformation length.

3. The method according to claim 1, characterized in that The steps of reading out the first signal from the first memory under the synchronous control of the local baud rate signal and performing a first frequency domain transformation process to obtain a first frequency component, and reading out the second signal from the second memory under the synchronous control of the local baud rate signal and performing a second frequency domain transformation process to obtain a second frequency component specifically include: Reading the first signal from the first memory under synchronous control after the local baud rate signal is divided into two, and performing a first frequency domain transformation process on the first signal to obtain the first frequency component; Reading the second signal from the second memory under synchronous control after the local baud rate signal is divided into two, and performing a second frequency domain transformation process on the second signal to obtain the second frequency component; The frequency corresponding to the maximum amplitude in the first frequency component is determined to be f0, and the frequency corresponding to the maximum amplitude in the second frequency component is determined to be f1.

4. The method according to claim 1, characterized in that The step of performing parallel-to-serial conversion on the first frequency component and the second frequency component under the synchronous control of the local baud rate signal to obtain a serial demodulation output signal specifically includes: Under the synchronous control of the local baud rate signal, a demodulation decision result is generated according to f0 in the first frequency component and f1 in the second frequency component, wherein the demodulation value corresponding to f0 is 0, and the demodulation value corresponding to f1 is 1; The demodulation decision results are combined in a time sequence to obtain the serial demodulation output signal.

5. The method according to claim 1, characterized in that The first memory and the second memory write signals at the frequency of the local baud rate signal and read signals at half the frequency of the local baud rate signal.

6. The method according to claim 1, characterized in that In the steps of reading out the first signal from the first memory under the synchronous control of the local baud rate signal and performing a first frequency domain transformation process to obtain a first frequency component, and reading out the second signal from the second memory under the synchronous control of the local baud rate signal and performing a second frequency domain transformation process to obtain a second frequency component, the method for determining the parameters of the frequency domain transformation process includes: Determine, according to the local baud rate signal, that the frequency domain conversion time of each channel is half of the period of the local baud rate signal; According to the conversion time, determining a sampling rate and a conversion length that satisfy a ratio of the sampling rate to the conversion length equal to half of the frequency of the local baud rate signal; The first signal and the second signal are respectively subjected to frequency domain transformation processing according to the sampling rate and transformation length.

7. The method according to claim 2, characterized in that The depths of the first memory and the second memory are both the transformation length.

8. A very low frequency demodulation system, characterized in that: The very low frequency demodulation system comprises: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code comprises computer instructions, and the one or more processors call the computer instructions to enable the very low frequency demodulation system to execute the method as described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on a very low frequency demodulation system, the very low frequency demodulation system is caused to execute the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that When the computer program product runs on a very low frequency demodulation system, the very low frequency demodulation system is caused to perform the method according to any one of claims 1 to 7.

Images