LED driving circuit and method

Abstract

The invention discloses an LED driving circuit and method. The LED driving circuit comprises a pulse width modulation (PWM) signal detection module which is configured to generate a power supply voltage control signal of which the pulse width is not less than a preset time length based on a PWM control signal; the power supply voltage control module is configured to generate a switch tube control signal based on the power supply voltage control signal and is used for controlling the on-off of a power switch tube, and the power supply voltage of the LED load is related to the on-off of the power switch tube; and the PWM dimming control module is configured to generate a dimming control signal based on the PWM control signal and is used for controlling the on-off of a dimming switch tube, and the dimming switch tube is used for adjusting the brightness of the LED load.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to an LED driving circuit and method. Background Art

[0002] In the Light Emitting Diode (LED) drive, pulse width modulation (PWM) dimming technology is widely used in modern lighting and display devices due to its high efficiency and flexibility. By adjusting the duty cycle of the pulse, PWM dimming can achieve basic brightness control. As users' requirements for light quality and visual experience continue to increase, PWM deep dimming has emerged as a more sophisticated control method, which achieves more sophisticated brightness control by increasing the frequency or reducing the duty cycle. As the frequency increases or the duty cycle decreases, the pulse width of PWM dimming will gradually decrease, causing the power supply of the LED to gradually become distorted, and the linearity of PWM dimming will deteriorate sharply, affecting the dimming effect. Summary of the invention

[0003] According to an embodiment of the present invention, the LED driving circuit includes: a PWM signal detection module, which is configured to generate a power supply voltage control signal with a pulse width not less than a preset duration based on a PWM control signal; a power supply voltage control module, which is configured to generate a switch tube control signal based on the power supply voltage control signal, for controlling the on-off of the power switch tube, wherein the power supply voltage of the LED load is related to the on-off of the power switch tube; and a PWM dimming control module, which is configured to generate a dimming control signal based on the PWM control signal, for controlling the on-off of the dimming switch tube, wherein the dimming switch tube is used to adjust the brightness of the LED load.

[0004] According to an embodiment of the present invention, the LED driving method includes: receiving a PWM control signal, generating a power supply voltage control signal with a pulse width not less than a preset duration based on the PWM control signal; generating a switch tube control signal based on the power supply voltage control signal, for controlling the on-off of the power switch tube, wherein the power supply voltage of the LED load is related to the on-off of the power switch tube; and generating a dimming control signal based on the PWM control signal, for controlling the on-off of the dimming switch tube, wherein the dimming switch tube is used to adjust the brightness of the LED load. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0006] Figure 1 The schematic diagram of the structure of the traditional LED driving circuit is shown;

[0007] Figure 2 Shown based on Figure 1 Specific waveform diagram of PWM traditional dimming technology;

[0008] Figure 3 Shown based on Figure 1 Specific waveform diagram of PWM deep dimming technology;

[0009] Figure 4 A schematic structural diagram of an LED driving circuit according to an embodiment of the present invention is shown;

[0010] Figure 5 Shown based on Figure 4 Specific waveform diagram;

[0011] FIG. 6A to FIG. 6D Four structural schematic diagrams of a PWM signal detection module according to an embodiment of the present invention are shown;

[0012] Figure 7 A schematic flow chart of an LED driving method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0013] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid unnecessary ambiguity to the present invention.

[0014] Figure 1 FIG. 1 shows a schematic diagram of the structure of a conventional LED driving circuit. Figure 1 As shown in FIG. 1 , the conventional LED driving circuit includes an oscillator, a gate driving unit, a PWM dimming control module, an inductor L, a power switch tube M1, a dimming switch tube M2, a diode D, and an output capacitor Cout. Figure 1 As shown, the oscillator generates a clock signal based on the PWM control signal, and the gate drive unit generates a switch control signal Gate based on the PWM control signal and the clock signal, which is used to control the on and off of the power switch M1; the PWM dimming control module generates a dimming control signal based on the PWM control signal, which is used to control the on and off of the dimming switch M2. Figure 1In the boost architecture, the inductor L, the power switch tube M1, the diode D and the output capacitor Cout form a boost architecture. Vin is the input voltage. The boost architecture converts the low voltage input voltage Vin into a high voltage Vout based on the switch tube control signal and then uses the high voltage Vout as the LED load (i.e. Figure 1 The functions of each component in the boost architecture are as follows: the inductor L stores energy during the charging phase and releases the stored energy during the discharging phase to increase the output voltage; the power switch tube M1 controls the flow of current, and the switching frequency and duty cycle corresponding to the on and off of M1 directly affect the size of Vout; the diode D is used to prevent the current from flowing in the reverse direction; the output capacitor Cout is used to smooth Vout and reduce voltage fluctuations, while supplying power to the LED load during the charging phase. The dimming switch tube M2 is used to adjust the brightness of the LED load, and the specific switching frequency and duty cycle of M2 are used to adjust the average current of the LED load to achieve PWM dimming.

[0015] Figure 2 Shown based on Figure 1 Specific waveform diagram of the traditional PWM dimming technology. Figure 2 The waveform diagram includes the signal waveforms of the PWM control signal, the clock signal clk output by the oscillator, the switch control signal Gate output by the gate drive unit, the inductor current I_L of the inductor L, the power supply voltage Vout, and the load current ILED flowing through the LED load. Figure 2 As shown, in the traditional PWM dimming technology, the duty cycle of the PWM control signal is relatively large, and even the PWM control signal with the minimum pulse width can enable the controller to output a clock signal clk and a switch control signal Gate with multiple signal cycles. Figure 2 The generation process of each signal in includes: when the PWM control signal is at a high level, the gate drive unit is enabled, the oscillator is synchronously controlled to work, and the oscillator outputs a clock signal clk with a constant frequency, which determines the operating frequency of the Gate of the gate drive unit; when the Gate is at a high level, M1 is turned on, the inductor L is charged to store energy, and when the Gate is at a low level, M1 is turned off, and the inductor L releases energy to supply power to the output capacitor Cout and the load; the power supply voltage Vout smoothes the waveform through the output capacitor Cout, and there is ripple on Vout due to the charging of the inductor and the discharging of the load; the waveform of the load current ILED passing through the LED load corresponds to the PWM control signal, and the average current of ILED can be adjusted by adjusting the duty cycle of the PWM control signal, thereby realizing the brightness control of the LED load.

[0016] PWM deep dimming technology achieves the effect of stable output of low-brightness light by increasing the frequency of the PWM control signal or reducing the duty cycle of the PWM control signal. However, as the frequency of the PWM control signal increases or the duty cycle decreases, the pulse width of the PWM control signal decreases, resulting in the energy stored in the inductor L being unable to provide a stable output current. Figure 3 Shown based on Figure 1 The specific waveform diagram of PWM deep dimming technology. Figure 2 and Figure 3 , Figure 3 The pulse width of the PWM control signal is significantly smaller than Figure 2 The pulse width of the PWM control signal. Figure 3 As shown in the figure, when the pulse width of the PWM control signal is small enough to only support the output of one clock cycle of the clock signal clk and the switch control signal Gate, the boost architecture completes only one energy conversion within one cycle of the PWM control signal, and the energy consumed by the LED load is greater than the energy stored in the inductor L, resulting in insufficient energy in the output capacitor Cout until it is completely consumed, causing the supply voltage Vout and the load current ILED to gradually become distorted until the LED load turns off. The linearity of the PWM deep dimming deteriorates sharply, affecting the dimming effect.

[0017] Taking into account the problem of gradual distortion of power supply in current PWM deep dimming, an LED driving circuit and method according to an embodiment of the present invention are proposed, wherein the LED load is dimmed based on a PWM control signal, and a power supply voltage control signal is generated based on the PWM control signal to control the power supply voltage of the LED load. Since the pulse width of the power supply voltage control signal is not less than the preset duration, the LED load can be stably powered, thereby ensuring a stable dimming effect.

[0018] Figure 4 FIG. 2 shows a schematic diagram of the structure of an LED driving circuit according to an embodiment of the present invention. Figure 4 As shown, the LED driving circuit 400 according to the embodiment of the present invention includes a PWM signal detection module 401, a power supply voltage control module 402 (including an oscillator and a gate drive unit), a PWM dimming control module 403, an inductor L, a power switch tube M1, a dimming switch tube M2, a diode D and an output capacitor Cout. Figure 4 As shown, the inductor L, the power switch tube M1, the diode D and the output capacitor Cout form a boost architecture. The power switch tube M1 is turned on and off based on the switch tube control signal, so that the boost architecture converts the low voltage input voltage Vin into a high voltage Vout and then uses the high voltage Vout as the power supply voltage of the LED load (illustrated as LED, such as an LED light string including one or more LED monomers). The magnitude of the power supply voltage is related to the on and off of the power switch tube M1. It can be understood that Figure 4The boost architecture is only an example. It is based on the structure of the on-off output supply voltage of the power switch tube M1. Figure 4 In addition to the boost architecture in , you can also choose other architectures such as buck-boost. Figure 4 As shown, the dimming switch tube M2 is connected in series to the current path of the LED load, and the switching frequency and duty cycle of the dimming control tube M2 are used to adjust the average current of the LED load to adjust the brightness of the LED load.

[0019] exist Figure 4 In the embodiment, the PWM signal detection module 401 is configured to generate a power supply voltage control signal with a pulse width not less than a preset duration based on the PWM control signal; the power supply voltage control module 402 is configured to generate a switch tube control signal based on the power supply voltage control signal, which is used to control the on-off of the power switch tube M1, wherein the power supply voltage of the LED load is related to the on-off of the power switch tube M1; the PWM dimming control module 403 is configured to generate a dimming control signal based on the PWM control signal, which is used to control the on-off of the dimming switch tube M2, wherein the dimming switch tube M2 is used to adjust the brightness of the LED load. Figure 4 As shown, the PWM signal detection module 401 generates a power supply voltage control signal based on the PWM control signal, the power supply voltage control module 402 generates a switch tube control signal based on the power supply voltage control signal, and the power switch tube M1 is turned on and off based on the switch tube control signal, so that the boost architecture outputs Vout corresponding to the switch tube control signal, and the PWM dimming control module 403 generates a dimming control signal based on the PWM control signal, and the dimming switch tube M2 is turned on and off based on the dimming control signal, so that an average current corresponding to the dimming control signal is generated in the current path of the LED load, and the average current is related to the brightness of the LED load.

[0020] exist Figure 4In the embodiment, the PWM signal detection module 401 generates a power supply voltage control signal based on the PWM control signal, and the pulse width of the power supply voltage control signal is not less than the preset duration. The setting of the preset duration is to ensure that the subsequent power supply voltage control module 402 generates a switch tube control signal according to the power supply voltage control signal, and when the power switch tube acts based on the switch tube control signal, the power supply voltage is relatively stable and maintained in a stable voltage range, for example, not less than a preset voltage, so that the power supply voltage can provide stable power to the LED load. Therefore, regardless of the pulse width of the PWM control signal, it is necessary to ensure that the pulse width of the power supply voltage control signal is not less than the preset duration. In some special cases, such as in the PWM deep dimming scene, the duty cycle of the PWM control signal is relatively small, the pulse width of the power supply voltage control signal is relatively large, and the preset duration is usually greater than the pulse width of the PWM control signal. If the pulse width of the PWM control signal is greater than the preset duration, the pulse width of the supply voltage control signal may be equal to the pulse width of the PWM control signal.

[0021] In some embodiments, the PWM signal detection module 401 is further configured to: use the pulse start time of the PWM control signal as the pulse start time of the power supply voltage control signal to generate the power supply voltage control signal. Specifically, assuming that the pulse levels of the PWM control signal and the power supply voltage control signal are both high, when the actual levels of the PWM control signal and the power supply voltage control signal are both low, when the PWM control signal changes from a low level to a high level, the power supply voltage control signal changes from a low level to a high level, and when the high level of the power supply voltage control signal is maintained for a time period not less than a preset time period, the power supply voltage control signal changes from a high level to a low level, so that the pulse width of the power supply voltage control signal is not less than the preset time period.

[0022] Figure 5 Shown based on Figure 4 Specific waveform diagram. Figure 5As shown, taking the oscillator's duty cycle of 50% and the preset duration of 2.5 clock signal cycles of the oscillator as an example, the PWM signal detection module 401 generates a power supply voltage control signal based on the PWM control signal. When the PWM control signal changes from a low level to a high level, the power supply voltage control signal changes from a low level to a high level; after the power supply voltage control signal maintains a high level for a preset duration (such as 2.5 clock signal cycles, that is, the pulse width reaches 2.5 clock signal cycles), it changes from a high level to a low level. The power supply voltage control module 402 works based on the power supply voltage control signal, wherein the clock signal clk output by the oscillator and the switch tube control signal Gate output by the gate drive unit have the same shape and both correspond to the pulse width of the power supply voltage control signal, and the current I_L of the inductor L and the power supply voltage Vout both correspond to the switch tube control signal Gate. The PWM dimming control module 403 generates a dimming control signal based on the PWM control signal, and the dimming switch tube M2 adjusts the brightness of the LED load based on the dimming control signal, and the load current ILED of the LED load corresponds to the PWM control signal.

[0023] Different preset durations can be set for LED drive circuits with different parameters and dimming requirements. The preset duration should be set appropriately. A too short preset duration cannot completely solve the power supply instability problem when the PWM control signal pulse width is small. A too long preset duration may cause excessive residual energy in the LED drive circuit and trigger the protection mechanism of the LED drive circuit.

[0024] According to the LED driving circuit of the embodiment of the present invention, the control signals of dimming and power supply of the LED driving circuit are separated, the dimming is realized based on the PWM control signal, and the power supply is realized based on the power supply voltage control signal, so that the power supply voltage of the LED driving circuit is stabilized within a voltage range by the power supply voltage control signal with a larger pulse width, and the LED load can be stably powered, thereby ensuring a stable dimming effect.

[0025] FIG. 6A to FIG. 6D Four structural schematic diagrams of the PWM signal detection module according to the embodiment of the present invention are shown. The following takes the case where the pulses of each signal are at a high level and the effective level of each circuit end is at a high level as an example to analyze the specific structure, and the analysis of other cases (the pulses of any signal are at a low level and the effective level of the circuit end of any unit is at a low level) is similar.

[0026] like Fig. 6AAs shown, in some specific embodiments, the PWM signal detection module 401 includes: an operation unit, configured to generate a power supply voltage control signal based on the PWM control signal and the timing signal, and the pulse width of the power supply voltage control signal is a larger value between the pulse width of the PWM control signal and the pulse width of the timing signal; a clock unit, configured to generate a clock signal based on the power supply voltage control signal; and a timing unit, configured to generate a timing signal based on the clock signal, and the pulse width of the timing signal is a preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal.

[0027] exist Fig. 6A In the embodiment, the operation unit can be specifically configured to generate a power supply voltage control signal by performing a logical OR operation on the PWM control signal and the timing signal; and the clock unit can be further configured to generate a clock pulse of the clock signal when the power supply voltage control signal is at a high level. At this time, for the operation unit, regardless of the level of the timing signal, as long as the PWM control signal changes from a low level to a high level, the operation unit will output a high-level power supply voltage control signal. The high-level power supply voltage control signal will trigger the clock unit, so that the clock unit generates a clock pulse of the clock signal when the power supply voltage control signal is at a high level, and the clock unit will not generate a clock pulse when the power supply voltage control signal is at a low level. The clock unit can be implemented by an oscillator.

[0028] exist Fig. 6A In the embodiment, the timing unit outputs a timing signal based on the clock signal. Specifically, when the clock signal changes from a low level to a high level, the timing signal changes from a low level to a high level, and when the duration of the timing signal being at a high level reaches a preset duration, the timing signal changes from a high level to a low level. When the timing signal changes from a low level to a high level, the timing unit starts timing the pulse width of the timing signal from zero, and the preset duration can be set based on the duty cycle, the number of pulses, or the number of signal cycles of the clock signal output by the clock unit (i.e., the timing unit is further configured to generate a timing signal by counting the changing edges of the clock pulses of the clock signal). For example, if the preset duration is set to 3 clock pulses, then when the clock signal is monitored to change from a high level to a low level for the third time (i.e., when the falling edge of the third clock signal pulse appears), it is considered that the preset duration has been reached. For another example, if it is set to 3 signal cycles, then when the clock signal is monitored to change from a low level to a high level for the fourth time (i.e., the third signal cycle ends and the fourth signal cycle begins), it is considered that the preset duration has been reached. The preset duration of the timing signal is usually greater than a preset number of signal cycles of the clock signal, and the preset number is a positive integer and can be set according to actual conditions.

[0029] exist Fig. 6AIn the embodiment, the operation unit performs a logical OR operation on the timing signal and the PWM control signal, so that the pulse width of the power supply voltage control signal is the larger value of the pulse widths of the PWM control signal and the timing signal. When the pulse width of the PWM control signal is less than the preset duration, the pulse width of the power supply voltage control signal is the preset duration. When the pulse width of the PWM control signal is not less than the preset duration, the pulse width of the power supply voltage control signal is the same as the pulse width of the PWM control signal.

[0030] In some embodiments, the enable end of the timing unit receives a power supply voltage control signal or a constant level signal. The pulse level of the power supply voltage control signal (i.e., the level at which the pulse is located) or the level of the constant level signal is the effective level of the enable end. The timing unit works when the signal level at the enable end is the effective level. To ensure that the timing unit in this embodiment outputs accurate and complete pulses of the timing signal, the time period during which the signal received by the enable end of the timing unit is at the effective level should cover the time period of the pulse of the timing signal. This structure is applied to the case where the pulse width of the PWM control signal is small, usually less than the preset duration, and the pulse width of the output power supply voltage control signal is the preset duration.

[0031] In some embodiments, when the enable end of the timing unit receives a constant level signal (assuming that the enable end is valid at a high level and the constant level signal is at a high level), the timing unit always remains in a working state, and once the clock unit sends a clock pulse of a clock signal to the timing unit, the timing unit can generate a timing signal based on the clock pulse. The operation unit starts to output a high-level power supply voltage control signal when the PWM control signal is at a high level, the clock unit generates a clock pulse of the clock signal when the power supply voltage control signal is at a high level, the timing unit generates a timing signal based on the clock pulse, and the operation unit outputs a high-level power supply voltage control signal when at least one of the timing signal and the PWM control signal is at a high level. Since the pulse width of the timing signal is a preset duration, even if the pulse width of the PWM control signal is less than the preset duration, under the action of the timing signal, the pulse width of the power supply voltage control signal output by the operation unit will reach the preset duration.

[0032] In some embodiments, the situation in which the enable end of the timing unit receives the power supply voltage control signal is similar to receiving the constant level signal. The operation unit starts to output a high-level power supply voltage control signal when the PWM control signal is at a high level, the clock unit generates a clock pulse of the clock signal when the power supply voltage control signal is at a high level, the timing unit generates a timing signal based on the clock pulse when the power supply voltage control signal is at a high level, and the operation unit outputs a high-level power supply voltage control signal when at least one of the timing signal and the PWM control signal is at a high level. Since the pulse width of the timing signal is a preset duration, even if the pulse width of the PWM control signal is less than the preset duration, under the action of the timing signal, the pulse width of the power supply voltage control signal output by the operation unit will reach the preset duration.

[0033] like Figure 6B As shown, compared Fig. 6A In some embodiments, the PWM signal detection module 401 further includes: a signal latch unit, configured to generate a latch signal based on the timing signal and the PWM control signal, the pulse width of the latch signal is a preset duration, the enable end of the timing unit receives the latch signal, and the pulse level of the latch signal is the effective level of the enable end. For example, the signal latch unit is further configured to: use the pulse start time of the PWM control signal as the pulse start time of the latch signal, and use the pulse end time of the timing signal as the pulse end time of the latch signal to generate the latch signal. Therefore, when the PWM control signal changes from a low level to a high level, the latch signal changes from a low level to a high level, and when the timing signal changes from a high level to a low level, the latch signal changes from a high level to a low level, the enable end of the timing unit changes from a valid level to an invalid level, and the timing unit stops working. Regardless of the relationship between the pulse width of the PWM control signal and the preset duration, the pulse of the latch signal can only be generated when the pulse of the PWM control signal appears. Therefore, the enabling of the timing unit by the latch signal ensures that within a signal cycle of the PWM control signal, the power supply voltage control signal output by the timing unit includes a complete pulse with a pulse width of the preset duration and only includes this one pulse.

[0034] In some specific embodiments, the signal latch unit may include: a reset subunit, configured to generate a reset signal in the form of a pulse when the timing signal indicates that the pulse width of the timing signal reaches a preset duration (for example, the timing signal changes from a high level to a low level); a latch subunit, configured to generate a latch signal based on a PWM control signal, and reset the latch signal based on the reset signal. Specifically, when the reset end of the latch subunit is at a high level, the latch signal remains at a low level, and when the reset end of the latch subunit is at a low level, the latch signal is output based on the signal at the latch end, that is, if the signal at the latch end changes from a low level to a high level, a high-level latch signal is output, and the high level will be maintained until the reset end changes from a low level to a high level, and the latch signal is reset to a low level.

[0035] Specifically, when the timing signal changes from a high level to a low level, that is, the pulse width of the timing signal reaches a preset duration, the reset subunit generates a reset signal in the form of a short pulse, and the reset end of the latch subunit receives the reset signal. When the reset signal changes from a low level to a high level, the latch signal is reset to a low level. Since the reset signal is a pulse with a very short pulse width (for example, a duty cycle of 5% or 2%), the reset signal will soon change from a high level to a low level again, and then the latch subunit will change according to the signal at the latch end.

[0036] like Figure 6C As shown, in some embodiments, the PWM signal detection module 401 includes: a signal latch unit, configured to generate a latch signal based on a timing signal and a PWM control signal; a clock unit, configured to generate a clock signal based on the latch signal; and a timing unit, configured to generate a timing signal based on the clock signal, the pulse width of the latch signal and the pulse width of the timing signal are both preset durations, the preset duration is greater than a preset number of signal cycles of the clock signal, and the timing signal or the latch signal is used as a power supply voltage control signal. Figure 6C In the PWM signal detection module 401 shown, the timing signal and the latch signal have the same signal waveform and a pulse width of a preset duration. Either one of the two can be selected as the power supply voltage control signal, and the pulse width of the power supply voltage control signal is also a preset duration.

[0037] exist Figure 6C In some embodiments, the signal latch unit is further configured to: use the pulse start time of the PWM control signal as the pulse start time of the latch signal, and use the pulse end time of the timing signal as the pulse end time of the latch signal to generate a latch signal.

[0038] In some specific embodiments, the signal latch unit may include: a reset subunit, configured to generate a reset signal in the form of a pulse when the timing signal indicates that the pulse width of the timing signal reaches a preset duration; a latch subunit, configured to generate a latch signal based on a PWM control signal, and reset the latch signal based on the reset signal.

[0039] like Fig.6D As shown, in some embodiments, the PWM signal detection module 401 includes: a signal latch unit, configured to generate a latch signal based on a timing signal and a PWM control signal; an operation unit, configured to generate a power supply voltage control signal based on a PWM control signal and a latch signal; a clock unit, configured to generate a clock signal based on a latch signal or a power supply voltage control signal; and a timing unit, configured to generate a timing signal based on a clock signal, wherein the pulse width of the latch signal and the pulse width of the timing signal are both preset durations, the preset duration is greater than a preset number of signal cycles of the clock signal, and the pulse width of the power supply voltage control signal is the larger value of the pulse width of the PWM control signal and the pulse width of the latch signal. Specifically, the input end of the clock unit receives a latch signal or a power supply voltage control signal, and the clock unit generates a clock signal with continuous pulses when the signal at the input end changes from a low level to a high level. As shown Fig.6D In the PWM signal detection module 401 shown, the timing signal and the latch signal have the same signal waveform and the pulse width is a preset duration, and the pulse width of the supply voltage control signal is not less than the pulse width of the latch signal.

[0040] exist Fig.6D In some embodiments, the signal latch unit is further configured to: use the pulse start time of the PWM control signal as the pulse start time of the latch signal, and use the pulse end time of the timing signal as the pulse end time of the latch signal to generate a latch signal. In some specific embodiments, the signal latch unit may include: a reset subunit, configured to generate a reset signal in the form of a pulse when the timing signal indicates that the pulse width of the timing signal reaches a preset duration; a latch subunit, configured to generate a latch signal based on the PWM control signal, and reset the latch signal based on the reset signal.

[0041] like Figure 6C and Fig.6D In the PWM signal detection module 401 shown, the enable terminal of the timing unit receives any one of the latch signal, the power supply voltage control signal or the constant level signal. The pulse level of the latch signal, the pulse level of the power supply voltage control signal and the level of the constant level signal correspond to the effective level of the enable terminal. Fig. 6A and Figure 6B similar, Figure 6C and Fig.6DIn the case where the enable end of the timing unit receives a power supply voltage control signal or a constant level signal, it is usually applied to the case where the pulse width of the PWM control signal is small, usually less than the preset duration. At this time, the pulse widths of the timing signal, the latch signal, and the power supply voltage control signal are all the preset duration; when the enable end of the timing unit receives a latch signal, the pulse widths of the timing signal and the latch signal are both the preset duration, and the pulse width of the power supply voltage control signal is the larger pulse width of the latch signal and the PWM control signal.

[0042] exist FIG. 6A to FIG. 6D In the clock unit, timing unit, operation unit, and signal latch unit, FIG. 6A to FIG. 6D The connection relationships shown in the figure are not exactly the same, resulting in different signal inputs or signal outputs, but for the units with the same name in each figure, their internal signal processing logic is the same and does not change with the change of external signals. For example, when the clock unit generates a clock signal based on a latch signal or a power supply voltage control signal, the signal processing logic inside the clock unit is: when the input signal is in a valid level state (the valid level state corresponds to the pulse level of the input signal), the clock pulse of the clock signal is output; for another example, the timing unit generates a timing signal based on the clock signal, and the signal processing logic inside the timing unit is: when the enable end level is valid, the changing edges of the continuous pulses of the clock signal are counted; for another example, the signal latch unit generates a latch signal based on the PWM control signal and the timing signal, and the internal signal processing logic is: the pulse start time of the PWM control signal is used as the starting time. The latch signal is generated by taking the pulse start time of the latch signal and the pulse end time of the timing signal as the pulse end time of the latch signal; for another example, the operation unit generates the power supply voltage control signal based on the PWM control signal and the timing signal or the latch signal, and the signal processing logic inside the operation unit is: taking the pulse start time of the PWM control signal as the pulse start time of the power supply voltage control signal, and taking the later of the two pulse end times of the PWM control signal and another input signal as the pulse end time of the power supply voltage control signal, so that the pulse width of the power supply voltage control signal is the larger value of the pulse width of the PWM control signal and the other input signal. When the pulses of the two input signals and the pulses of the power supply voltage control signal are both high levels, the operation unit can be implemented by a logic or operation unit, and when the pulses of the two input signals and the pulses of the power supply voltage control signal are both low levels, the operation unit can be implemented by a logic and operation unit. Similarly, in other cases, the operation unit can select a specific logic circuit to implement according to the specific signal state.

[0043] Based on the above description, if the supply voltage control module 402 includes an oscillator, the oscillator can be reused in the PWM signal detection module 401 as a clock unit. In addition, an AND operation unit can be provided between the clock unit and the timing unit, and the AND operation unit can be configured to perform a logic AND operation on the clock signal and the supply voltage control signal, or can be configured to perform a logic AND operation on the clock signal and the latch signal, and the result of the logic AND operation will be sent to the timing unit, so that the timing unit generates a timing signal based on the output result of the AND operation unit.

[0044] Figure 7 FIG. 2 shows a schematic flow chart of an LED driving method according to an embodiment of the present invention. Figure 7 As shown, the LED driving method according to an embodiment of the present invention includes: receiving a PWM control signal, and generating a power supply voltage control signal with a pulse width not less than a preset duration based on the PWM control signal (S701); generating a switch tube control signal based on the power supply voltage control signal, for controlling the on-off of the power switch tube (S702), wherein the power supply voltage of the LED load is related to the on-off of the power switch tube; and generating a dimming control signal based on the PWM control signal, for controlling the on-off of the dimming switch tube, wherein the dimming switch tube is used to adjust the brightness of the LED load (S703).

[0045] In some embodiments, the process of generating a power supply voltage control signal (S701) includes: generating a power supply voltage control signal by using a pulse start time of a PWM control signal as a pulse start time of the power supply voltage control signal.

[0046] In some embodiments, generating a power supply voltage control signal process (S701) includes: generating a power supply voltage control signal based on a PWM control signal and a timing signal, wherein a pulse width of the power supply voltage control signal is a larger value between a pulse width of the PWM control signal and a pulse width of the timing signal, the timing signal is generated based on a clock signal, the clock signal is generated based on the power supply voltage control signal, and the pulse width of the timing signal is a preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal.

[0047] In some embodiments, generating a power supply voltage control signal process (S701) includes: generating a latch signal based on a timing signal and a PWM control signal; generating a clock signal based on the latch signal; and generating a timing signal based on the clock signal, wherein a pulse width of the latch signal and a pulse width of the timing signal are both preset durations, the preset duration is greater than a preset number of signal cycles of the clock signal, and the timing signal or the latch signal is used as the power supply voltage control signal.

[0048] In some embodiments, generating a power supply voltage control signal process (S701) includes: generating a latch signal based on a timing signal and a PWM control signal; generating a power supply voltage control signal based on a PWM control signal and a latch signal; generating a clock signal based on the latch signal or the power supply voltage control signal; and generating a timing signal based on the clock signal, wherein a pulse width of the latch signal and a pulse width of the timing signal are both preset durations, the preset duration is greater than a preset number of signal cycles of the clock signal, and a pulse width of the power supply voltage control signal is a larger value between a pulse width of the PWM control signal and a pulse width of the latch signal.

[0049] The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the system and method according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0050] The present invention can be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithms described in the specific embodiments can be modified, and the system architecture does not depart from the basic spirit of the present invention. Therefore, the current embodiments are regarded as exemplary and non-restrictive in all aspects, and the scope of the present invention is defined by the appended claims rather than the above description, and all changes falling within the meaning and equivalent scope of the claims are thus included in the scope of the present invention.

Claims

1. An LED driving circuit, comprising: A pulse width modulation (PWM) signal detection module is configured to generate a power supply voltage control signal with a pulse width not less than a preset duration based on the PWM control signal; a power supply voltage control module, configured to generate a switch tube control signal based on the power supply voltage control signal, for controlling the on-off of the power switch tube, wherein the power supply voltage of the LED load is related to the on-off of the power switch tube; and The PWM dimming control module is configured to generate a dimming control signal based on the PWM control signal, so as to control the on and off of the dimming switch tube, wherein the dimming switch tube is used to adjust the brightness of the LED load.

2. The LED driving circuit according to claim 1, wherein: The PWM signal detection module is further configured as follows: The power supply voltage control signal is generated by taking the pulse start time of the PWM control signal as the pulse start time of the power supply voltage control signal.

3. The LED driving circuit according to claim 2, wherein: The PWM signal detection module comprises: an operation unit configured to generate the supply voltage control signal based on the PWM control signal and the timing signal, wherein the pulse width of the supply voltage control signal is a larger value between the pulse width of the PWM control signal and the pulse width of the timing signal; a clock unit configured to generate a clock signal based on the supply voltage control signal; and The timing unit is configured to generate the timing signal based on the clock signal, the pulse width of the timing signal is the preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal.

4. The LED driving circuit according to claim 3, wherein: The operation unit is further configured to generate the supply voltage control signal by performing a logic OR operation on the PWM control signal and the timing signal; and The clock unit is further configured to generate a clock pulse of the clock signal when the supply voltage control signal is at a high level.

5. The LED driving circuit according to claim 3, wherein: The enable terminal of the timing unit receives the supply voltage control signal or the constant level signal.

6. The LED driving circuit according to claim 3, wherein: The PWM signal detection module also includes: a signal latch unit, configured to generate a latch signal based on the timing signal and the PWM control signal, wherein the pulse width of the latch signal is the preset duration, The enable terminal of the timing unit receives the latch signal.

7. The LED driving circuit according to claim 2, wherein: The PWM signal detection module comprises: a signal latch unit configured to generate a latch signal based on a timing signal and the PWM control signal; a clock unit configured to generate a clock signal based on the latch signal; and a timing unit, configured to generate the timing signal based on the clock signal, The pulse width of the latch signal and the pulse width of the timing signal are both the preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal. The timing signal or the latch signal serves as the supply voltage control signal.

8. The LED driving circuit according to claim 2, wherein: The PWM signal detection module comprises: a signal latch unit configured to generate a latch signal based on a timing signal and the PWM control signal; an operation unit, configured to generate the supply voltage control signal based on the PWM control signal and the latch signal; a clock unit configured to generate a clock signal based on the latch signal or the supply voltage control signal; and a timing unit, configured to generate the timing signal based on the clock signal, The pulse width of the latch signal and the pulse width of the timing signal are both the preset duration, the preset duration is greater than a preset number of signal cycles of the clock signal, and the pulse width of the power supply voltage control signal is the larger value of the pulse width of the PWM control signal and the pulse width of the latch signal.

9. The LED driving circuit according to claim 7 or 8, wherein: The enable terminal of the timing unit receives any one of the latch signal, the supply voltage control signal or the constant level signal.

10. The LED driving circuit according to any one of claims 6 to 8, wherein: The signal latch unit is further configured as: The latch signal is generated by taking the pulse start time of the PWM control signal as the pulse start time of the latch signal and taking the pulse end time of the timing signal as the pulse end time of the latch signal.

11. A LED driving method, comprising: Receiving a PWM control signal, and generating a power supply voltage control signal with a pulse width not less than a preset duration based on the PWM control signal; generating a switch tube control signal based on the power supply voltage control signal, for controlling the on-off of the power switch tube, wherein the power supply voltage of the LED load is related to the on-off of the power switch tube; and A dimming control signal is generated based on the PWM control signal to control the on and off of a dimming switch tube, wherein the dimming switch tube is used to adjust the brightness of the LED load.

12. The LED driving method according to claim 11, wherein: Generating the supply voltage control signal processing includes: The power supply voltage control signal is generated by taking the pulse start time of the PWM control signal as the pulse start time of the power supply voltage control signal.

13. The LED driving method according to claim 12, wherein: Generating the supply voltage control signal processing includes: generating the supply voltage control signal based on the PWM control signal and the timing signal, Among them, the pulse width of the power supply voltage control signal is the larger value of the pulse width of the PWM control signal and the pulse width of the timing signal, the timing signal is generated based on the clock signal, the clock signal is generated based on the power supply voltage control signal, and the pulse width of the timing signal is the preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal.

14. The LED driving method according to claim 12, wherein: Generating the supply voltage control signal processing includes: generating a latch signal based on a timing signal and the PWM control signal; generating a clock signal based on the latch signal; and Generating the timing signal based on the clock signal, The pulse width of the latch signal and the pulse width of the timing signal are both the preset duration, and the preset duration is greater than a preset number of signal cycles of the clock signal. The timing signal or the latch signal serves as the supply voltage control signal.

15. The LED driving method according to claim 12, wherein: Generating the supply voltage control signal processing includes: generating a latch signal based on a timing signal and the PWM control signal; generating the supply voltage control signal based on the PWM control signal and the latch signal; generating a clock signal based on the latch signal or the supply voltage control signal; and generating the timing signal based on the clock signal, The pulse width of the latch signal and the pulse width of the timing signal are both the preset duration, the preset duration is greater than a preset number of signal cycles of the clock signal, and the pulse width of the power supply voltage control signal is the larger value of the pulse width of the PWM control signal and the pulse width of the latch signal.

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