Capacitorless dynamic random access memory and method of manufacturing and use thereof

Abstract

This invention discloses a capacitor-free dynamic random access memory (DRAM), its fabrication method, and its applications. The capacitor-free DRAM of this invention comprises a bottom gate dielectric layer, a first bottom gate electrode, a second bottom gate electrode, a source electrode, a first active layer, a source-drain composite electrode, a second active layer, a drain electrode, a water-oxygen barrier layer, a top gate dielectric layer, a top gate electrode, and a memory node. The surface of the second active layer has several columnar protrusions. The capacitor-free DRAM of this invention has advantages such as high storage density, extremely fast read speed, long retention time, low power consumption, and low production cost. Furthermore, its simple structure and fabrication process make it suitable for large-scale industrial production and application.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a capacitor-free dynamic random access memory, its fabrication method, and its applications. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of random access memory that uses dynamic storage cells. It is primarily used as the main memory of a computer to store running programs and data. Currently, commonly used DRAMs are made of silicon-based materials. However, due to the silicon-based 1T1C cell structure, large capacitors occupy most of the space in the DRAM chip, thus limiting further increases in storage density. Furthermore, silicon-based DRAM also suffers from short retention times and high production costs, making it difficult to meet the growing demands of practical applications.

[0003] Therefore, developing a dynamic random access memory with high storage density, long retention time, and low production cost is of great significance. Summary of the Invention

[0004] The purpose of this invention is to provide a capacitor-free dynamic random access memory, its preparation method, and its application.

[0005] The technical solution adopted in this invention is:

[0006] A capacitor-free dynamic random access memory, comprising:

[0007] Bottom gate dielectric layer;

[0008] The first bottom gate electrode and the second bottom gate electrode are disposed at different positions on the same surface of the bottom gate dielectric layer;

[0009] The first active layer and the second active layer are disposed at different positions on the other surface of the bottom gate dielectric layer. The first active layer corresponds to the first bottom gate electrode, and the second active layer corresponds to the second bottom gate electrode. The surface of the second active layer is distributed with several columnar protrusions.

[0010] The source electrode, the source-drain composite electrode, and the drain electrode are disposed on the side of the bottom gate dielectric layer away from the first bottom gate electrode and the second bottom gate electrode. The source electrode is in contact with the first active layer, the source-drain composite electrode is in contact with the first active layer and the second active layer, and the drain electrode is in contact with the second active layer.

[0011] A water-oxygen barrier layer covers the surfaces of the source electrode, the first active layer, the source-drain composite electrode, the second active layer, and the drain electrode.

[0012] Top grid dielectric layer, covering the surface of the water and oxygen barrier layer;

[0013] The top gate electrode is located on the side of the top gate dielectric layer that is away from the water and oxygen barrier layer, and the top gate electrode corresponds to the second active layer.

[0014] The storage node is connected to the source electrode at one end and to the top gate electrode at the other end.

[0015] Note: The capacitorless dynamic random access memory of the present invention integrates a read transistor and a write transistor. The first bottom gate electrode, the bottom gate dielectric layer, the first active layer, the source electrode, the source-drain composite electrode, the water-oxygen barrier layer, and the top gate dielectric layer constitute the write transistor. The second bottom gate electrode, the bottom gate dielectric layer, the second active layer, the source-drain composite electrode, the drain electrode, the water-oxygen barrier layer, the top gate dielectric layer, and the top gate electrode constitute the read transistor.

[0016] Preferably, the composition of the bottom gate dielectric layer includes at least one of Al2O3, ZrO2, HfO2, TiO2, and Sc2O3.

[0017] Preferably, the thickness of the bottom gate dielectric layer is 10 nm to 60 nm.

[0018] Preferably, the composition of the first bottom gate electrode includes at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0019] Preferably, the thickness of the first bottom gate electrode is 20 nm to 80 nm.

[0020] Preferably, the composition of the second bottom gate electrode includes at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0021] Preferably, the thickness of the second bottom gate electrode is 40 nm to 100 nm.

[0022] Preferably, the composition of the first active layer includes at least one of indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium oxide (In2O3), and indium gallium zinc oxide (IGZO).

[0023] Preferably, the thickness of the first active layer is 10 nm to 60 nm.

[0024] Preferably, the composition of the second active layer includes at least one of indium tin zinc oxide, indium tin oxide, indium oxide, and indium gallium zinc oxide.

[0025] Preferably, the thickness of the second active layer is 30nm to 160nm (this thickness includes the height of the columnar protrusions), and the height of the columnar protrusions distributed on the surface is 20nm to 100nm.

[0026] Preferably, the columnar protrusions are arranged in an array.

[0027] Preferably, the source electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0028] Preferably, the thickness of the source electrode is 50 nm to 200 nm.

[0029] Preferably, the source-drain composite electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0030] Preferably, the thickness of the source-drain composite electrode is 50 nm to 200 nm.

[0031] Preferably, the drain electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0032] Preferably, the thickness of the drain electrode is 50 nm to 200 nm.

[0033] Preferably, the water-oxygen barrier layer comprises at least one of fluorinated organic compounds and organosiloxanes.

[0034] More preferably, the water-oxygen barrier layer is composed of octadecyltriethoxysilane.

[0035] Preferably, the thickness of the water-oxygen barrier layer is 2nm to 50nm.

[0036] Preferably, the composition of the top gate dielectric layer includes at least one of Al2O3, ZrO2, HfO2, TiO2, and Sc2O3.

[0037] Preferably, the thickness of the top gate dielectric layer is 30nm to 100nm.

[0038] Preferably, the top gate electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0039] Preferably, the thickness of the top gate electrode is 100nm to 200nm.

[0040] Preferably, the composition of the storage node includes at least one of Al-Nd alloy, Al, Ti, Ni, and ITO.

[0041] Preferably, the thickness of the storage node is 40nm to 400nm.

[0042] Preferably, the capacitor-free dynamic random access memory further includes a substrate.

[0043] Preferably, the substrate is one of a glass substrate, a single-crystal silicon substrate, or a flexible polymer substrate.

[0044] A method for fabricating a capacitor-free dynamic random access memory as described above includes the following steps:

[0045] 1) A first bottom gate electrode and a second bottom gate electrode are formed on one side of the substrate, and then a bottom gate dielectric layer is formed;

[0046] 2) A first active layer and a second active layer are formed on the surface of the bottom gate dielectric layer;

[0047] 3) A source electrode, a source-drain composite electrode, and a drain electrode are formed on the surface of the bottom gate dielectric layer;

[0048] 4) A water-oxygen barrier layer is formed on the surface of the source electrode, the first active layer, the source-drain composite electrode, the second active layer, and the drain electrode.

[0049] 5) A top grid dielectric layer is formed on the surface of the water-oxygen barrier layer;

[0050] 6) A top gate electrode is formed on the surface of the top gate dielectric layer, and then a storage node connecting the source electrode and the top gate electrode is formed to obtain a capacitor-free dynamic random access memory.

[0051] An electronic product comprising the aforementioned capacitorless dynamic random access memory.

[0052] The working principle of the capacitorless dynamic random access memory of the present invention is as follows: The first bottom gate electrode of the capacitorless dynamic random access memory is connected to the write word line (WWL), the second bottom gate electrode is connected to the read word line (RWL), the source-drain composite electrode is connected to the bit line (BL), and the drain electrode is connected to ground (GND). During reading and writing, RWL maintains a constant voltage drive, and the oxide capacitor C of the read transistor is... OX,Tr As a storage capacitor, RWL maintains a constant voltage drive. When WWL is turned on, charge from BL is injected into the storage node (SN region) to realize data writing. When WWL is turned off, charge flows into BL through the active layer of the read transistor and reads data through signal amplification. By using transistors with active layers containing columnar bump structures (i.e., read transistors), the gate control capability of read transistors is improved while the number of bit lines is reduced. This improves the read speed, reduces the power consumption of 2T0CDRAM, and increases the integration density of storage cells.

[0053] The beneficial effects of the present invention are: the capacitor-free dynamic random access memory of the present invention has the advantages of high storage density, extremely fast read speed, long retention time, low power consumption, and low production cost, and its structure and manufacturing process are simple, making it suitable for large-scale industrial production and application.

[0054] Specifically:

[0055] 1) The capacitorless dynamic random access memory of the present invention is provided with a transistor (i.e., a read transistor, which is composed of a second bottom gate electrode, a bottom gate dielectric layer, a second active layer, a source-drain composite electrode, a drain electrode, a water-oxygen barrier layer, a top gate dielectric layer, and a top gate electrode) containing an active layer with a columnar protrusion structure. This transistor has extremely strong gate control capability and high on-state current, which is beneficial for fast reading of memory devices and the distinction between data "0" and "1". In addition, it also reduces the power consumption of 2T0C DRAM and increases the integration density of memory cells.

[0056] 2) The capacitorless dynamic random access memory of the present invention is provided with a water and oxygen barrier layer, which can not only block water and oxygen, but also effectively avoid the impact of subsequent processes on the columnar protrusion structure of the second active layer. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the capacitorless dynamic random access memory of the present invention.

[0058] Figure 2 This is a top view of the second active layer in the capacitorless dynamic random access memory of the present invention.

[0059] Figure 3 This is a circuit diagram of the capacitorless dynamic random access memory of the present invention.

[0060] Explanation of reference numerals in the attached diagram: 10, bottom gate dielectric layer; 20, first bottom gate electrode; 30, second bottom gate electrode; 40, first active layer; 50, second active layer; 60, source electrode; 70, source-drain composite electrode; 80, drain electrode; 90, water and oxygen barrier layer; 100, top gate dielectric layer; 110, top gate electrode; 120, memory node; WWL, write word line; RWL, read word line; BL, bit line; GND, ground line.

[0061] Figure 4 The transfer characteristic curve of the write transistor in the capacitorless dynamic random access memory of the embodiment is shown.

[0062] Figure 5 The transfer characteristic curve of the read transistor in the capacitorless dynamic random access memory of the embodiment is shown.

[0063] Figure 6 The curves show the transfer characteristics of the read transistors in a capacitor-free dynamic random access memory as a comparative example.

[0064] Figure 7 The retention time characteristic curve of the capacitorless dynamic random access memory device in the embodiment is shown. Detailed Implementation

[0065] The present invention will be further explained and described below with reference to specific embodiments.

[0066] Example:

[0067] A capacitor-free dynamic random access memory (structural diagram shown) Figure 1 As shown; the top view of the second active layer is as follows Figure 2 As shown; the circuit diagram is as follows. Figure 3 As shown, it consists of a bottom gate dielectric layer 10, a first bottom gate electrode 20, a second bottom gate electrode 30, a first active layer 40, a second active layer 50, a source electrode 60, a source-drain composite electrode 70, a drain electrode 80, a water and oxygen barrier layer 90, a top gate dielectric layer 100, a top gate electrode 110, and a storage node 120.

[0068] The bottom gate dielectric layer 10 is composed of Al2O3 and has a thickness of 60 nm;

[0069] The first bottom gate electrode 20 and the second bottom gate electrode 30 are disposed at different positions on the same surface of the bottom gate dielectric layer 10; the first bottom gate electrode 20 is composed of an Al-Nd alloy with a thickness of 60 nm; the second bottom gate electrode 30 is composed of an Al-Nd alloy with a thickness of 60 nm.

[0070] The first active layer 40 and the second active layer 50 are disposed at different positions on the other surface of the bottom gate dielectric layer 10. The first active layer 40 corresponds to the first bottom gate electrode 20, and the second active layer 50 corresponds to the second bottom gate electrode 30. The surface of the second active layer 50 is distributed with a plurality of columnar protrusions arranged in an array. The first active layer 40 is composed of indium tin zinc oxide (ITZO) and has a thickness of 20 nm. The second active layer 50 is composed of indium tin zinc oxide and has a thickness of 50 nm (including the height of the columnar protrusions). The height of the columnar protrusions distributed on the surface is 30 nm.

[0071] The source electrode 60, the source-drain composite electrode 70, and the drain electrode 80 are disposed on the side of the bottom gate dielectric layer 10 away from the first bottom gate electrode 20 and the second bottom gate electrode 30. The source electrode 60 is in contact with the first active layer 40, the source-drain composite electrode 70 is in contact with the first active layer 40 and the second active layer 50, and the drain electrode 80 is in contact with the second active layer 50. The source electrode 60 is composed of indium tin oxide (ITO) and has a thickness of 100 nm. The source-drain composite electrode 70 is composed of indium tin oxide (ITO) and has a thickness of 100 nm. The drain electrode 80 is composed of indium tin oxide (ITO) and has a thickness of 100 nm.

[0072] A water-oxygen barrier layer 90 covers the surfaces of the source electrode 60, the first active layer 40, the source-drain composite electrode 70, the second active layer 50, and the drain electrode 80; the water-oxygen barrier layer 90 is composed of octadecyltriethoxysilane and has a thickness of 5 nm.

[0073] The top gate dielectric layer 100 covers the surface of the water and oxygen barrier layer 90; the top gate dielectric layer 100 is composed of HfO2 and has a thickness of 100 nm.

[0074] The top gate electrode 110 is disposed on the side of the top gate dielectric layer 100 away from the water and oxygen barrier layer 90, and the top gate electrode 110 corresponds to the second active layer 50; the top gate electrode 110 is composed of ITO and has a thickness of 100 nm.

[0075] One end of the memory node 120 is connected to the source electrode 60, and the other end is connected to the top gate electrode 110; the memory node 120 is composed of indium tin oxide and has a thickness of 100 nm.

[0076] The first bottom gate electrode 20 is connected to the write word line (WWL), the second bottom gate electrode 30 is connected to the read word line (RWL), the source-drain composite electrode 70 is connected to the bit line (BL), and the drain electrode 80 is connected to the ground line (GND).

[0077] The fabrication method of the capacitor-free dynamic random access memory is as follows:

[0078] 1) The glass substrate was ultrasonically cleaned with deionized water and isopropanol for 15 min each, then placed in a vacuum oven at 90°C for 1 h, and then cooled. A 60 nm thick Al-Nd alloy film was deposited on one side of the substrate by magnetron sputtering. The first and second bottom gate electrodes were then patterned by ultraviolet lithography and reactive ion etching (RIE). An Al2O3 film was then deposited by atomic layer deposition, with the pressure in the deposition chamber controlled to be less than 20 Pa. Water and trimethylaluminum were circulated at 150°C, with each cycle lasting 8 s and each cycle depositing a thickness of 0.1 nm. The number of cycles was controlled to achieve a thickness of 60 nm for the Al2O3 film. The film was then heated at 200°C for 30 min (to remove any water molecules that may remain in the Al2O3 film) to form the bottom gate dielectric layer.

[0079] 2) The device with the prepared bottom gate dielectric layer is coated with photoresist, exposed with photolithography pattern, and stripped with a stripper solution. Then it is placed in a magnetron sputtering chamber, where polycrystalline ITO targets are sputtered simultaneously with DC power and polycrystalline ZnO targets are sputtered with RF power to deposit an ITZO thin film on the surface of the bottom gate dielectric layer. The DC sputtering power is controlled at 100W and the RF sputtering power is controlled at 130W. The gas pressure in the chamber is controlled at 0.5Pa during sputtering, and the volume ratio of argon to oxygen is controlled at 10:6. The sputtering temperature is room temperature. Then it is placed in acetone to remove the stripper and dried to complete the lift-off process, forming a first active layer with a thickness of 20nm and a second active layer with a thickness of 50nm (the surface is distributed with several columnar protrusions with a height of 30nm).

[0080] 3) The device with the first and second active layers prepared is coated with photoresist, exposed with photolithography pattern, and stripped with a stripper solution. Then it is placed in a magnetron sputtering chamber and an ITO target is sputtered to deposit an ITO film with a thickness of 100 nm on the surface of the bottom gate dielectric layer. The sputtering temperature is room temperature, the sputtering chamber pressure is set to 0.5 Pa, the volume ratio of argon to oxygen is controlled to 10:3, and the DC target sputtering power is 100 W. After removing the photoresist, it is placed on a heating stage and annealed at 350 °C for 3 h (to reduce defects in the active layer and improve crystal quality, while reducing contact resistance) to form the source electrode, source-drain composite electrode, and drain electrode.

[0081] 4) Place the device with the prepared source electrode, source-drain composite electrode and drain electrode into a ceramic boat, and load octadecyltriethoxysilane into another ceramic boat. Then place the two ceramic boats in the same sealed container and put them into a vacuum oven. Keep them at 120℃ for 1 hour, and then cool them down to 60℃ and keep them at 0.5 hours. A water and oxygen barrier layer with a thickness of 5 nm is formed on the surface of the source electrode, the first active layer, the source-drain composite electrode, the second active layer and the drain electrode.

[0082] 5) The device with the prepared water-oxygen barrier layer is placed on a patterned metal mask and fixed. Then, HfO2 target material is deposited on the surface of the water-oxygen barrier layer by magnetron sputtering with RF power supply to form a 100nm thick HfO2 film. The gas pressure in the sputtering chamber is controlled at 0.5Pa, the argon flow rate is controlled at 20sccm, the oxygen flow rate is controlled at 10sccm, the sputtering temperature is room temperature, and the sputtering power is set to 100W to form the top gate dielectric layer.

[0083] 6) The device with the prepared top gate dielectric layer is coated with photoresist, exposed with photolithographic patterns, and stripped with a stripper solution. It is then placed in a magnetron sputtering chamber and a 100 nm thick ITO film is deposited using DC sputtering to form the top gate electrode. The gas pressure in the sputtering chamber is controlled at 0.5 Pa, and sputtering is performed in a pure argon environment. The sputtering temperature is room temperature, and the sputtering power is set to 100 W. The photoresist is then removed, and a portion of the top gate dielectric layer and a portion of the water-oxygen barrier layer are selectively removed using a dry etching method to expose a portion of the source electrode. Patterned photoresist is then applied, and the device is placed in a magnetron sputtering chamber again. A 100 nm thick ITO film is deposited using a DC power supply on an ITO target. The sputtering temperature is room temperature, the sputtering chamber pressure is set to 0.5 Pa, the volume ratio of argon to oxygen is controlled at 10:3, and the DC target sputtering power is 100 W. The photoresist is then removed, forming a storage node connecting the source electrode and the top gate electrode, thus obtaining a capacitor-free dynamic random access memory.

[0084] Comparative example:

[0085] A capacitor-free dynamic random access memory device is identical to the capacitor-free dynamic random access memory of the embodiment, except that the second active layer 50 is adjusted to be an ITZO thin film with a thickness of 20 nm and a flat surface (without columnar protrusions).

[0086] Performance testing:

[0087] 1) The electrical performance of the write transistor and read transistor in the capacitor-free dynamic random access memory of the embodiment and the read transistor in the capacitor-free dynamic random access memory of the comparative example were tested using an Agilent B1500A semiconductor parameter analyzer. The resulting transfer characteristic curves are shown below. Figure 4 , Figure 5 and Figure 6 As shown.

[0088] Depend on Figure 4 It can be seen that the write transistor in the capacitorless dynamic random access memory of the embodiment has an extremely low off-state current (below 10). -13 A) The detection limit of the instrument was exceeded, and the switching current ratio reached 1×10⁻⁶. 9 Thanks to the extremely low off-state current, the charge retention time of the device is increased, thereby further improving the storage performance of the device.

[0089] Depend on Figure 5 and Figure 6 It can be known that:

[0090] a) The subthreshold swing of the read transistor in the capacitorless dynamic random access memory of the embodiment is 142mV / dec, which is lower than the subthreshold swing of 191mV / dec of the read transistor in the capacitorless dynamic random access memory of the comparative example. This shows that by setting columnar protrusions on the surface of the second active layer, the transistor can have stronger gate control capability.

[0091] b) The read transistor mobility in the capacitorless dynamic random access memory of the embodiment is 21.85 cm⁻¹. 2 / V·s, higher than the 16.24cm mobility of the read transistor in the comparative capacitorless DRAM. 2 / V·s indicates that by setting columnar protrusions on the surface of the second active layer, more induced electric field can be generated, enabling the second active layer to generate more carrier channels, thereby improving the transistor mobility.

[0092] 2) The storage performance of the capacitorless dynamic random access memory device in this embodiment was tested using an Agilent B1500A semiconductor parameter analyzer. The resulting retention time characteristic curve is shown below. Figure 7 As shown.

[0093] Depend on Figure 7Known to: The capacitorless dynamic random access memory device in the embodiment can achieve a retention time of more than 35 seconds without a capacitor, when ΔV is defined. sn When the effective retention time is 0.1V, the retention time of the device can reach 2s, which is far higher than the current millisecond standard of traditional 1T1C. In contrast, the read current of the capacitorless dynamic random access memory in the comparison is too small to meet the standard of the memory device. This shows that the high drive current and strong gate control capability of the capacitorless dynamic random access memory device in the embodiment improve the effective read window of the device, thereby improving the read performance of the memory device.

[0094] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A capacitor-free dynamic random access memory, characterized in that, The components include: Bottom gate dielectric layer; The first bottom gate electrode and the second bottom gate electrode are disposed at different positions on the same surface of the bottom gate dielectric layer; The first active layer and the second active layer are disposed at different positions on the other surface of the bottom gate dielectric layer. The first active layer corresponds to the first bottom gate electrode, and the second active layer corresponds to the second bottom gate electrode. The surface of the second active layer is distributed with several columnar protrusions. The source electrode, the source-drain composite electrode, and the drain electrode are disposed on the side of the bottom gate dielectric layer away from the first bottom gate electrode and the second bottom gate electrode. The source electrode is in contact with the first active layer, the source-drain composite electrode is in contact with the first active layer and the second active layer, and the drain electrode is in contact with the second active layer. A water-oxygen barrier layer covers the surfaces of the source electrode, the first active layer, the source-drain composite electrode, the second active layer, and the drain electrode. Top grid dielectric layer, covering the surface of the water and oxygen barrier layer; The top gate electrode is located on the side of the top gate dielectric layer that is away from the water and oxygen barrier layer, and the top gate electrode corresponds to the second active layer. The storage node is connected to the source electrode at one end and to the top gate electrode at the other end.

2. The capacitor-free dynamic random access memory according to claim 1, characterized in that: The bottom gate dielectric layer comprises at least one of Al2O3, ZrO2, HfO2, TiO2, and Sc2O3; the top gate dielectric layer comprises at least one of Al2O3, ZrO2, HfO2, TiO2, and Sc2O3.

3. The capacitor-free dynamic random access memory according to claim 1 or 2, characterized in that: The thickness of the bottom gate dielectric layer is 10nm to 60nm; the thickness of the top gate dielectric layer is 30nm to 100nm.

4. The capacitor-free dynamic random access memory according to claim 1, characterized in that: The first active layer comprises at least one of indium tin zinc oxide, indium tin oxide, indium oxide, and indium gallium zinc oxide; The second active layer comprises at least one of indium tin zinc oxide, indium tin oxide, indium oxide, and indium gallium zinc oxide.

5. The capacitor-free dynamic random access memory according to claim 1 or 4, characterized in that: The thickness of the first active layer is 10nm to 60nm; the thickness of the second active layer is 30nm to 160nm, and the height of the columnar protrusions distributed on the surface is 20nm to 100nm.

6. The capacitor-free dynamic random access memory according to any one of claims 1, 2 and 4, characterized in that: The water-oxygen barrier layer comprises at least one of fluorinated organic compounds and organosiloxanes; the thickness of the water-oxygen barrier layer is 2 nm to 50 nm.

7. The capacitor-free dynamic random access memory according to any one of claims 1, 2 and 4, characterized in that: The first bottom gate electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the first bottom gate electrode is 20 nm to 80 nm. The second bottom gate electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the second bottom gate electrode is 40 nm to 100 nm. The source electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the source electrode is 50 nm to 200 nm. The source-drain composite electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the source-drain composite electrode is 50 nm to 200 nm. The drain electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the drain electrode is 50 nm to 200 nm. The top gate electrode comprises at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the top gate electrode is 100 nm to 200 nm.

8. The capacitor-free dynamic random access memory according to any one of claims 1, 2 and 4, characterized in that: The memory node is composed of at least one of Al-Nd alloy, Al, Ti, Ni, and ITO; the thickness of the memory node is 40 nm to 400 nm.

9. A method for fabricating a capacitor-free dynamic random access memory as described in any one of claims 1 to 8, characterized in that, Includes the following steps: 1) A first bottom gate electrode and a second bottom gate electrode are formed on one side of the substrate, and then a bottom gate dielectric layer is formed; 2) A first active layer and a second active layer are formed on the surface of the bottom gate dielectric layer; 3) A source electrode, a source-drain composite electrode, and a drain electrode are formed on the surface of the bottom gate dielectric layer; 4) A water-oxygen barrier layer is formed on the surface of the source electrode, the first active layer, the source-drain composite electrode, the second active layer, and the drain electrode. 5) A top grid dielectric layer is formed on the surface of the water-oxygen barrier layer; 6) A top gate electrode is formed on the surface of the top gate dielectric layer, and then a storage node connecting the source electrode and the top gate electrode is formed to obtain a capacitor-free dynamic random access memory.

10. An electronic product, characterized in that, It includes the capacitor-free dynamic random access memory according to any one of claims 1 to 8.

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