Semiconductor memory device, method of manufacturing same, and electronic system including same

Abstract

A semiconductor memory device including three-dimensionally arranged memory cells, a method of manufacturing the same, and an electronic system including the same are provided. The semiconductor memory device includes: a first stack structure including first gate electrodes sequentially stacked and spaced apart from each other; a second stacked structure on the first stacked structure and including second gate electrodes sequentially stacked and spaced apart from each other; and a channel structure extending in a vertical direction and passing through the first and second stacked structures, in which the channel structure includes a channel layer and a data storage layer, the channel layer including a first pillar portion intersecting the first gate electrode, a second pillar portion intersecting the second gate electrode, and a horizontal portion extending along a plane intersecting the vertical direction, the horizontal portion connects the first pillar portion and the second pillar portion, and the data storage layer extends along an outer side of the channel layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority from Korean Patent Application No. 10-2023-0153592 filed in the Korean Intellectual Property Office on November 8, 2023, and all rights and benefits derived therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device, a method for manufacturing the semiconductor memory device, and an electronic system including the semiconductor memory device, and more particularly, to a semiconductor memory device including three-dimensionally arranged memory cells, a method for manufacturing the semiconductor memory device, and an electronic system including the semiconductor memory device. Background Art

[0004] Since a semiconductor memory device capable of storing high-capacity data is required in an electronic system, a method capable of increasing the data storage capacity of the semiconductor memory device has been studied. As one of the methods capable of increasing the data storage capacity of the semiconductor memory device, a semiconductor memory device including memory cells arranged three-dimensionally rather than two-dimensionally has been proposed. Summary of the invention

[0005] Some example embodiments of the present disclosure provide a semiconductor memory device having improved reliability.

[0006] Some example embodiments of the present disclosure provide methods for manufacturing a semiconductor memory device having improved reliability.

[0007] Some example embodiments of the present disclosure provide electronic systems including semiconductor memory devices having improved reliability.

[0008] Example embodiments of the present disclosure are not limited to those mentioned above, and some example embodiments of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0009] According to an example embodiment of the present invention, a semiconductor memory device includes: a first stacking structure, which includes a plurality of first gate electrodes stacked sequentially and spaced apart from each other; a second stacking structure, which is located on the first stacking structure, the second stacking structure includes a plurality of second gate electrodes stacked sequentially and spaced apart from each other; and a channel structure, which extends in a vertical direction to pass through the first stacking structure and the second stacking structure, wherein the channel structure includes a channel layer and a data storage layer, the channel layer includes a first column portion intersecting the plurality of first gate electrodes, a second column portion intersecting the plurality of second gate electrodes, and a horizontal portion extending along a plane intersecting the vertical direction, the horizontal portion connecting the first column portion and the second column portion, and the data storage layer extending along an outer side of the channel layer.

[0010] According to an example embodiment of the inventive concept, a semiconductor memory device includes: a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate; a first stacked structure located on the peripheral circuit structure, the first stacked structure including a plurality of first gate electrodes stacked sequentially and spaced apart from each other; a second stacked structure located between the peripheral circuit structure and the first stacked structure, the second stacked structure including a plurality of second gate electrodes stacked sequentially and spaced apart from each other; a channel layer extending in a vertical direction and passing through the first stacked structure and the second stacked structure, the channel layer including a first semiconductor layer intersecting the plurality of first gate electrodes and a second semiconductor layer intersecting the plurality of second gate electrodes a body layer; a data storage layer, which includes a first dielectric layer inserted between the first stack structure and the first semiconductor layer and a second dielectric layer inserted between the second stack structure and the second semiconductor layer; a source structure, which is connected to the first semiconductor layer on the first stack structure; and a bit line, which is connected to the second semiconductor layer and is located between the peripheral circuit structure and the second stack structure, wherein the width of the first semiconductor layer decreases as the first semiconductor layer points to the second stack structure, the width of the second semiconductor layer decreases as the second semiconductor layer points to the first stack structure, and the second semiconductor layer includes a horizontal portion, the horizontal portion extends along a plane intersecting the vertical direction and is connected to the first semiconductor layer.

[0011] According to an example embodiment of the present invention, an electronic system includes: a mainboard; a semiconductor memory device including a peripheral circuit structure and a unit structure sequentially stacked on the mainboard; and a controller located on the mainboard and electrically connected to the semiconductor memory device, wherein the unit structure includes a first stacking structure, a second stacking structure between the peripheral circuit structure and the first stacking structure, and a channel structure, the first stacking structure includes a plurality of first gate electrodes sequentially stacked and spaced apart from each other, the second stacking structure includes a plurality of second gate electrodes sequentially stacked and spaced apart from each other, the channel structure extends in a vertical direction and passes through the first stacking structure and the second stacking structure, and wherein the channel structure includes a channel layer, the channel layer includes a first column portion intersecting the plurality of first gate electrodes, a second column portion intersecting the plurality of second gate electrodes, and a horizontal portion extending along a plane intersecting the vertical direction, the horizontal portion connecting the first column portion with the second column portion, and a data storage layer extending along an outer side of the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the inventive concept will become more apparent by describing in detail some example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0014] Figure 2 is a circuit diagram illustrating a semiconductor memory device according to example embodiments.

[0015] Figure 3 is a layout diagram illustrating a semiconductor memory device according to example embodiments.

[0016] Figure 4 is along Figure 3 A cross-sectional view taken along line AA.

[0017] Figure 5 It is shown Figure 4 Magnified view of region R1.

[0018] Figure 6 It is shown Figure 4 An enlarged view of region R2.

[0019] Figure 7 It is shown Figure 4 An enlarged view of region R3.

[0020] Figure 8 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments.

[0021] Fig. 9 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments.

[0022] Fig.10 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments.

[0023] Fig.11 and Fig.12 It is shown Fig.10 Various magnified views of region R4.

[0024] Fig.13 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments.

[0025] Figures 14 to 17 It is shown Fig.13 Various magnified views of region R4.

[0026] Figures 18 to 34 are diagrams illustrating intermediate steps describing a method of manufacturing a semiconductor memory device according to example embodiments.

[0027] Figure 35 to Figure 39 are diagrams illustrating intermediate steps describing a method of manufacturing a semiconductor memory device according to example embodiments.

[0028] Figure 40 to Figure 42 are diagrams illustrating intermediate steps describing a method of manufacturing a semiconductor memory device according to example embodiments.

[0029] Figures 43 to 51 2 are diagrams illustrating intermediate steps of a method of manufacturing a semiconductor memory device according to some embodiments.

[0030] Figure 52 to Figure 57 are diagrams illustrating intermediate steps describing a method of manufacturing a semiconductor memory device according to example embodiments.

[0031] Fig.58 is a block diagram illustrating an electronic system according to example embodiments.

[0032] Fig.59 is an example perspective diagram illustrating an electronic system according to example embodiments.

[0033] Fig.60 is along Fig.59 Schematic cross-sectional view taken along line II. DETAILED DESCRIPTION

[0034] It will be understood that although the terms "first", "second", "upper", "lower", etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the technical spirit of the present disclosure, the first element or component discussed below may be referred to as the second element or component.

[0035] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0036] In the following, reference will be made to Figures 1 to 17 A semiconductor memory device according to some example embodiments of the present disclosure is described.

[0037] Figure 1 is a block diagram illustrating a semiconductor memory device 10 according to example embodiments.

[0038] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through the bit lines BL, the word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. For example, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0039] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and may transmit and receive data DATA to and from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generating circuit for generating various voltages for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0040] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels supplied to the word lines WL and the bit lines BL.

[0041] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0042] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. For example, when a program operation is performed, the page buffer 35 may operate as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. Meanwhile, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to read out the data DATA stored in the memory cell array 20.

[0043] Figure 2 is a circuit diagram illustrating a semiconductor memory device according to example embodiments.

[0044] Reference Figure 2 , a memory cell array (eg, Figure 1 20) includes a common source line CSL, a plurality of bit lines BL and a plurality of cell strings CSTR.

[0045] A plurality of bit lines BL may be arranged two-dimensionally on a plane including a first direction X and a second direction Y. For example, the bit lines BL may extend in the second direction Y, respectively, and may be spaced apart from each other and then arranged along the first direction X. A plurality of cell strings CSTR may be connected to the corresponding bit lines BL in parallel, respectively. The cell strings CSTR may be connected in common to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0046] Each of the cell strings CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each of the memory cell transistors MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series in a vertical direction (hereinafter, referred to as a third direction Z) intersecting the first direction X and the second direction Y.

[0047] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2m, and a string selection line SSL may be provided between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL11 to WL1n and WL21 to WL2m may be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0048] Figure 3 is a layout diagram illustrating a semiconductor memory device according to example embodiments. Figure 4 is along Figure 3 A cross-sectional view taken along line AA. Figure 5 It is shown Figure 4 Magnified view of region R1. Figure 6 It is shown Figure 4 An enlarged view of region R2. Figure 7 It is shown Figure 4 An enlarged view of region R3.

[0049] Reference Figures 3 to 7 , a semiconductor memory device according to example embodiments includes a memory cell structure CELL and a peripheral circuit structure PERI.

[0050] The memory cell structure CELL may include a cell array area CA, an extension area EA, and an outer area PA.

[0051] A memory cell array (eg, Figure 1 20) may be formed in the cell array region CA. For example, a source structure 102, a channel structure CH, gate electrodes 112 and 117, and a bit line BL, which will be described later, may be disposed on the cell array region CA.

[0052] The extension area EA may be disposed near the cell array area CA. For example, the extension area EA may be adjacent to the cell array area CA in the first direction X. Gate electrodes 112 and 117 to be described later may be stacked on the extension area EA in a stepped shape.

[0053] The outer area PA may be a peripheral area surrounding the cell array area CA and the extension area EA. For example, the outer area PA may be adjacent to the cell array area CA and / or the extension area EA in the first direction X and the second direction Y. A conductive pad 390 to be described later may be provided in the outer area PA.

[0054] The memory cell structure CELL may include a source structure 102, a first stacked structure SS1, a first interlayer insulating layer 142, a second stacked structure SS2, a second interlayer insulating layer 144, a channel structure CH, a cutting structure WC, a first gate contact 162, a second gate contact 163, a first unit wiring structure 380, a second unit wiring structure 180, first through-pieces 164 and 165, second through-pieces 166 and 167, and a conductive pad 390.

[0055] The first stacked structure SS1 may be disposed in the cell array area CA and the extension area EA. The first stacked structure SS1 may include a plurality of first mold insulating layers 110 and a plurality of first gate electrodes 112 alternately stacked along a third direction Z. Each of the first mold insulating layers 110 and each of the first gate electrodes 112 may have a layered structure extending along a plane (e.g., an XY plane) intersecting the third direction Z. The first gate electrodes 112 may be sequentially stacked along the third direction Z by being spaced apart from each other by the first mold insulating layers 110. The number and shape of the first mold insulating layers 110 and the first gate electrodes 112 are not limited to the example shown.

[0056] The first interlayer insulating layer 142 may cover the first stacked structure SS1. The first interlayer insulating layer 142 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0057] The second stacked structure SS2 may be disposed in the cell array area CA and the extension area EA. The second stacked structure SS2 may be stacked on the first stacked structure SS1. For example, the second stacked structure SS2 may be formed on the lower surface of the first stacked structure SS1 and the lower surface of the first interlayer insulating layer 142. The second stacked structure SS2 may include a plurality of second molded insulating layers 115 and a plurality of second gate electrodes 117 alternately stacked along a third direction Z. Each of the second molded insulating layers 115 and each of the second gate electrodes 117 may have a layered structure extending along a plane (e.g., an XY plane) intersecting the third direction Z. The second gate electrodes 117 may be sequentially stacked along the third direction Z by being spaced apart from each other via the second molded insulating layers 115. The number and shape of the second molded insulating layers 115 and the second gate electrodes 117 are not limited to the examples shown.

[0058] The second interlayer insulating layer 144 may cover the second stacked structure SS2. For example, the second interlayer insulating layer 144 may be formed on the lower surface of the first stacked structure SS1 and the lower surface of the first interlayer insulating layer 142. The second interlayer insulating layer 144 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0059] In some example embodiments, the first gate electrode 112 may include a plurality of first word lines (eg, Figure 2 WL11 to WL1n) and ground select lines (e.g., Figure 2 of GSL).

[0060] In some example embodiments, the second gate electrode 117 may include a plurality of second word lines (eg, Figure 2 WL21 to WL2m) and string selection lines (e.g., Figure 2 SSL).

[0061] The gate electrodes 112 and 117 may include a conductive material, for example, a semiconductor material such as silicon or a metal (e.g., tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni)), but are not limited thereto. For example, each of the gate electrodes 112 and 117 may include at least one of tungsten (W), molybdenum (Mo), or ruthenium (Ru). For another example, each of the gate electrodes 112 and 117 may include polysilicon.

[0062] The mold insulating layers 110 and 115 may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but are not limited thereto. For example, each of the mold insulating layers 110 and 115 may include a silicon oxide layer.

[0063] In some example embodiments, the first stack structure SS1 may include a plurality of stacks S11, S12, and S13. For example, the first stack structure SS1 may include a first stack S11, a second stack S12, and a third stack S13 sequentially stacked on an upper surface of the second stack structure SS2. The stacks S11, S12, and S13 of the first stack structure SS1 may include a plurality of first mold insulation layers 110 and a plurality of first gate electrodes 112 alternately stacked. Although it is shown that three stacks S11, S12, and S13 are stacked on the second stack structure SS2, this is only an example, and the number of stacks S11, S12, and S13 may vary.

[0064] The channel structure CH may be disposed in the cell array area CA. The channel structure CH may extend along the third direction Z to pass through the first stacked structure SS1 and the second stacked structure SS2. For example, the channel structure CH may be a pillar-type (e.g., cylindrical) structure extending along the third direction Z. The channel structure CH may intersect the plurality of gate electrodes 112 and 117.

[0065] In some example embodiments, the plurality of channel structures CH may be arranged in a zigzag form. Figure 3 As shown, a plurality of channel structures CH may be arranged alternately with each other in the first direction X and the second direction Y. Such channel structures CH may further improve the integration of the semiconductor memory device. The number and arrangement of the channel structures CH are not limited to the example shown.

[0066] In some example embodiments, the channel structure CH may have a tapered shape toward the second stack structure SS2 in each of the stack members S11, S12, and S13 of the first stack structure SS1. Figure 4 As shown, in each of the stacks S11, S12, and S13 of the first stack structure SS1, the width of the channel structure CH may decrease as the channel structure is directed toward the second stack structure SS2. This may be because the etching process for forming the channel structure CH with respect to the corresponding stacks S11, S12, and S13 of the first stack structure SS1 is performed in a direction directed toward the second stack structure SS2 (e.g., -Z direction).

[0067] In some example embodiments, the channel structure CH may have a step difference between the stacks S11, S12, and S13 of the first stack structure SS1. For example, in a boundary surface between the first stack S11 and the second stack S12, the width of the upper portion of the channel structure CH in the first stack S11 may be greater than the width of the lower portion of the channel structure CH in the second stack S12. In addition, in a boundary surface between the second stack S12 and the third stack S13, the width of the upper portion of the channel structure CH in the second stack S12 may be greater than the width of the lower portion of the channel structure CH in the third stack S13.

[0068] The channel structure CH may have a structure in which a portion of the first stack structure SS1 and a portion of the second stack structure SS2 are joined to each other. For example, a first channel hole CHh1 extending along the third direction Z to pass through the first stack structure SS1 may be formed. The channel structure CH in the first stack structure SS1 may be formed in the first channel hole CHh1. In addition, a second channel hole CHh2 extending along the third direction Z to pass through the second stack structure SS2 and expose the channel structure CH in the first stack structure SS1 may be formed. The channel structure CH in the second stack structure SS2 may be formed in the second channel hole CHh2 so that it can be joined to the channel structure CH in the first stack structure SS1.

[0069] The channel structure CH may include a channel layer 130 , a data storage layer 132 , a first filling insulating layer 134 , a second filling insulating layer 135 , a first channel pad 136 , and a second channel pad 137 .

[0070] The channel layer 130 may extend along the third direction Z to pass through the first stacked structure SS1 and the second stacked structure SS2. The channel layer 130 may include a first semiconductor layer 1301 and a second semiconductor layer 1302. The first semiconductor layer 1301 may intersect the plurality of first gate electrodes 112. The second semiconductor layer 1302 may intersect the plurality of second gate electrodes 117. The first semiconductor layer 1301 and the second semiconductor layer 1302 may be connected to each other.

[0071] In some example embodiments, the first semiconductor layer 1301 may have a tapered shape toward the second stack structure SS2 in each of the stack members S11, S12, and S13 of the first stack structure SS1. Figure 5 As shown, as the first semiconductor layer 1301 points toward the second stack structure SS2, the width of the first semiconductor layer 1301 may decrease. This may be due to the etching process for forming the first channel hole CHh1 with respect to the corresponding stack members S11, S12 and S13 of the first stack structure SS1 being performed in a direction (e.g., -Z direction) pointing toward the second stack structure SS2.

[0072] In some example embodiments, the second semiconductor layer 1302 may have a tapered shape toward the first stacked structure SS1. Figure 5 As shown, as the second semiconductor layer 1302 points toward the first stacked structure SS1, the width of the second semiconductor layer 1302 may decrease. This may be because the etching process for forming the second channel hole CHh2 for the second stacked structure SS2 is performed in a direction (eg, Z direction) pointing toward the first stacked structure SS1.

[0073] The first semiconductor layer 1301 and the second semiconductor layer 1302 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon (polysilicon), an organic semiconductor material, or a carbon nanostructure, but are not limited thereto. Figure 4 and Figure 5 , a boundary between the first semiconductor layer 1301 and the second semiconductor layer 1302 is shown in FIG. 1 , but this is merely an example, and the boundary between the first semiconductor layer 1301 and the second semiconductor layer 1302 may not exist.

[0074] In some example embodiments, the first semiconductor layer 1301 may include a first pillar portion 1301a. The first pillar portion 1301a may extend along the third direction Z to intersect the plurality of first gate electrodes 112. For example, the first pillar portion 1301a may be cylindrical extending along the third direction Z.

[0075] In some example embodiments, the second semiconductor layer 1302 may include a second pillar portion 1302a and a first horizontal portion 1302b. The second pillar portion 1302a may extend along the third direction Z to intersect with the plurality of second gate electrodes 117. For example, the second pillar portion 1302a may be cylindrical extending along the third direction Z. The first horizontal portion 1302b may extend from the upper portion of the second pillar portion 1302a along a plane (e.g., an XY plane) intersecting the third direction Z. For example, the first horizontal portion 1302b may be a plate-shaped (e.g., a circular plate-shaped) for blocking or closing the upper portion of the cylindrical second pillar portion 1302a. That is, the second semiconductor layer 1302 including the second pillar portion 1302a and the first horizontal portion 1302b may have a cup shape. The first horizontal portion 1302b may be connected to the first semiconductor layer 1301. For example, the upper surface of the first horizontal portion 1302b may protrude upward from the lowermost surface of the first pillar portion 1301a. Therefore, the second semiconductor layer 1302 may be bonded to the first semiconductor layer 1301 .

[0076] The data storage layer 132 may be inserted between the stacked structures SS1 and SS2 and the channel layer 130. For example, the data storage layer 132 may extend along the outer side of the channel layer 130. The data storage layer 132 may include a first dielectric layer 1321 and a second dielectric layer 1322. The first dielectric layer 1321 may be inserted between the first semiconductor layer 1301 and the first stacked structure SS1. For example, the first dielectric layer 1321 may extend to conform along the outline of the first channel hole CHh1, and the first semiconductor layer 1301 may extend to conform on the first dielectric layer 1321. The second dielectric layer 1322 may be inserted between the second semiconductor layer 1302 and the second stacked structure SS2. For example, the second dielectric layer 1322 may extend to conform along the outline of the second channel hole CHh2, and the second semiconductor layer 1302 may extend to conform on the second dielectric layer 1322.

[0077] The second semiconductor layer 1302 may be connected to the first semiconductor layer 1301 by passing through the second dielectric layer 1322. For example, a connection hole 1302h extending in the third direction Z to pass through an upper portion of the second dielectric layer 1322 and expose a lower portion of the first semiconductor layer 1301 may be formed. The second semiconductor layer 1302 may be formed in the connection hole 1302h and thus bonded to the first semiconductor layer 1301. Therefore, the channel layer 130 may have a structure in which the first semiconductor layer 1301 and the second semiconductor layer 1302 are bonded to each other.

[0078] Each of the first dielectric layer 1321 and the second dielectric layer 1322 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or a combination thereof.

[0079] In some example embodiments, each of the first dielectric layer 1321 and the second dielectric layer 1322 may be formed of a plurality of layers. For example, the first dielectric layer 1321 may include a first tunneling insulating layer 1321a, a first charge storage layer 1321b, and a first blocking insulating layer 1321c sequentially stacked on the outer side of the first semiconductor layer 1301. For example, the second dielectric layer 1322 may include a second tunneling insulating layer 1322a, a second charge storage layer 1322b, and a second blocking insulating layer 1322c sequentially stacked on the outer side of the second semiconductor layer 1302.

[0080] Each of the first tunnel insulating layer 1321a and the second tunnel insulating layer 1322a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 )). Each of the first charge storage layer 1321b and the second charge storage layer 1322b may include, for example, silicon nitride. Each of the first blocking insulating layer 1321c and the second blocking insulating layer 1322c may include, for example, silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 )).

[0081] In some example embodiments, an upper portion of the second dielectric layer 1322 may protrude upward from a boundary surface between the first and second stacked structures SS1 and SS2. For example, an upper surface of the second blocking insulating layer 1322c may be formed higher than a boundary surface between the first and second stacked structures SS1 and SS2.

[0082] In some example embodiments, the first charge storage layer 1321b and the second charge storage layer 1322b may be separated from each other. Figure 5 As shown, an upper portion of the second blocking insulating layer 1322c may extend along a plane (e.g., an XY plane) intersecting the third direction Z. In this case, the first charge storage layer 1321b and the second charge storage layer 1322b may be separated from each other by the second blocking insulating layer 1322c. In some example embodiments, an upper portion of the second charge storage layer 1322b may extend along a plane (e.g., an XY plane) intersecting the third direction Z.

[0083] The first filling insulating layer 134 may be formed to fill at least a portion of the inside of the first semiconductor layer 1301. For example, the first filling insulating layer 134 may fill at least a portion of a region of the first channel hole CHh1 remaining after the first dielectric layer 1321 and the first semiconductor layer 1301 are filled. The first filling insulating layer 134 may include, for example, silicon oxide, but is not limited thereto.

[0084] The second filling insulating layer 135 may be formed to fill at least a portion of the inside of the second semiconductor layer 1302. For example, the second filling insulating layer 135 may fill at least a portion of a region of the second channel hole CHh2 remaining after filling the second dielectric layer 1322 and the second semiconductor layer 1302. The second filling insulating layer 135 may include, for example, silicon oxide, but is not limited thereto.

[0085] In some example embodiments, the first filling insulating layer 134 and the second filling insulating layer 135 may be separated by the first horizontal portion 1302b. For example, the first horizontal portion 1302b may extend between the first filling insulating layer 134 and the second filling insulating layer 135 along a plane (eg, an XY plane) intersecting the third direction Z.

[0086] The first channel pad 136 may be connected to one end of the channel layer 130. Figure 6As shown, the first channel pad 136 may be formed on the first filling insulating layer 134 and thus connected to the upper portion of the first semiconductor layer 1301. Although the first channel pad 136 is shown only as being in contact with the inner side of the first semiconductor layer 1301, this is only an example, and the first channel pad 136 may be in contact with the upper surface of the first semiconductor layer 1301. The first channel pad 136 may include a conductive material, for example, polysilicon doped with impurities or metal, but is not limited thereto. In some example embodiments, the first channel pad 136 may be omitted.

[0087] The second channel pad 137 may be connected to the other end of the channel layer 130. Figure 7 As shown, the second channel pad 137 may be formed below the second filling insulating layer 135 and thus connected to the lower portion of the second semiconductor layer 1302. Although the second channel pad 137 is shown as being in contact with the inner side of the second semiconductor layer 1302, this is merely an example, and the second channel pad 137 may be in contact with the lower surface of the second semiconductor layer 1302. The second channel pad 137 may include a conductive material, for example, polysilicon doped with impurities or metals, but is not limited thereto. In some embodiments, the second channel pad 137 may be omitted.

[0088] In some example embodiments, a dummy channel structure DCH may be formed in the extension area EA The dummy channel structure DCH may extend in the third direction Z to pass through at least a portion of the first stack structure SS1 and / or at least a portion of the second stack structure SS2 .

[0089] The dummy channel structure DCH may be formed at the same level as the channel structure CH, or may be formed at a different level from the channel structure CH. For example, when the dummy channel structure DCH is formed at the same level as the channel structure CH, the dummy channel structure DCH may include the channel layer 130, the data storage layer 132, the first filling insulating layer 134, the second filling insulating layer 135, the first channel pad 136, and the second channel pad 137 as described above. For another example, when the dummy channel structure DCH is formed at a level different from that of the channel structure CH, the dummy channel structure DCH may be filled with an insulating material and / or a conductive material. The size of the dummy channel structure DCH may be the same as that of the channel structure CH, or may be different from that of the channel structure CH. In some example embodiments, the size of the dummy channel structure DCH may be larger than that of the channel structure CH.

[0090] The cutting structure WC may extend along the first direction X to cut the first stack structure SS1 and the second stack structure SS2. In addition, the plurality of cutting structures WC may be spaced apart from each other and extend in parallel with each other along the first direction X. The first stack structure SS1 and the second stack structure SS2 may be divided by the plurality of cutting structures WC to form a plurality of memory cell blocks (e.g., Figure 1For example, two adjacent cutting structures WC may define one memory cell block therebetween. A plurality of channel structures CH may be disposed in each memory cell block defined by the cutting structures WC.

[0091] In some example embodiments, the cutting structure WC may include an insulating material. For example, the cutting structure WC may include at least one of silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0092] In some example embodiments, the string separation pattern SC may be formed in the second stack structure SS2. The string separation pattern SC may extend along the first direction X to cut the string selection line ( Figure 2 SSL; for example, a gate electrode disposed at the lowermost portion of the second gate electrode 117). Each of the memory cell blocks defined by the cutting structure WC may be divided by the string separation pattern SC to form a plurality of string regions. For example, the string separation pattern SC may define two string regions in one memory cell block. The string separation pattern SC may include at least one of an insulating material (for example, silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto).

[0093] The source structure 102 may be disposed in the cell array region CA. The source structure 102 may be stacked on the first stacked structure SS1. For example, the source structure 102 may be formed on the upper surface of the first interlayer insulating layer 142 of the cell array region CA. The source structure 102 may be connected to one end of the channel layer 130. For example, Figure 6 As shown, the source structure 102 may contact an upper end of the first semiconductor layer 1301 and / or the first channel pad 136 .

[0094] The source structure 102 may include a conductive material, such as polysilicon doped with impurities, a metal, or a metal silicide, but is not limited thereto. For example, the source structure 102 may include polysilicon (poly-Si) doped with n-type impurities (e.g., phosphorus (P) or arsenic (As)). According to some example embodiments, the source structure 102 may be provided as a common source line (e.g., Figure 2 of CSL).

[0095] In some example embodiments, the third interlayer insulating layer 104 may be formed near the source structure 102. The third interlayer insulating layer 104 may form an insulating region near the source structure 102 over the extension area EA and the outer area PA. For example, the third interlayer insulating layer 104 may be formed on the upper surface of the first interlayer insulating layer 142 of the extension area EA and the outer area PA. The third interlayer insulating layer 104 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0096] The first gate contact 162 may be disposed in the extension area EA. The first gate contact 162 may be connected to the first gate electrode 112. For example, the first gate electrode 112 of the extension area EA may be stacked in a step shape on the upper surface of the second stacked structure SS2. Each of the plurality of first gate contacts 162 may extend along the third direction Z to pass through the third interlayer dielectric layer 104 and the first interlayer dielectric layer 142, and may be connected to the first gate electrode 112 corresponding thereto in the extension area EA. In some example embodiments, as the first gate contact 162 points to the second interlayer insulating layer 144, the width of the first gate contact 162 may decrease.

[0097] The second gate contact 163 may be disposed in the extension area EA. The second gate contact 163 may be connected to the second gate electrode 117. For example, the second gate electrode 117 of the extension area EA may be stacked in a step shape on the lower surface of the first stacked structure SS1. Each of the plurality of second gate contacts 163 may extend along the third direction Z to pass through the second interlayer insulating layer 144, and may be connected to the second gate electrode 117 corresponding thereto in the extension area EA. In some example embodiments, as the second gate contact 163 points to the first interlayer insulating layer 142, the width of the second gate contact 163 may decrease.

[0098] The first unit wiring structure 380 may be formed on the upper surface of the first stacked structure SS1. For example, a first inter-wiring insulating layer 340 covering the source structure 102 and the third interlayer insulating layer 104 may be formed, and the first unit wiring structure 380 may be formed in the first inter-wiring insulating layer 340. The first unit wiring structure 380 may be electrically connected to the source structure 102 and / or the first gate contact 162. The number and arrangement of the first unit wiring structures 380 are shown only as examples and are not limited thereto.

[0099] The second unit wiring structure 180 may be formed on the lower surface of the second stacked structure SS2. For example, a second inter-wiring insulating layer 146 covering the second interlayer insulating layer 144 may be formed, and the second unit wiring structure 180 may be formed in the second inter-wiring insulating layer 146. The second unit wiring structure 180 may be electrically connected to the channel structure CH and / or the second gate contact 163. Figure 4 The number and arrangement of the second unit wiring structures 180 shown in FIG. 1 are merely examples and are not limited thereto.

[0100] In some example embodiments, the second unit wiring structure 180 may include a bit line BL. The bit line BL may extend along the second direction Y and thus be connected to a plurality of channel structures CH arranged along the second direction Y. For example, a bit line contact 161 may be formed in the second interlayer insulating layer 144. The bit line contact 161 may be connected to the other end of the channel layer 130. For example, Figure 7 As shown, the bit line contact 161 may contact the lower end of the second semiconductor layer 1302 and / or the second channel pad 137. The bit line BL may be electrically connected to the channel structure CH through the bit line contact 161. The plurality of bit lines BL may be spaced apart from each other and extend in parallel with each other along the second direction Y.

[0101] The first through-holes 164 and 165 and the second through-holes 166 and 167 may be disposed in the outer area PA. The first through-holes 164 and 165 and the second through-holes 166 and 167 may extend in the third direction Z and thus electrically connect the first unit wiring structure 380 with the second unit wiring structure 180 .

[0102] In some embodiments, the first vias 164 and 165 may be referred to as first and second contact plugs 164 and 165 , respectively, and the second vias 166 and 167 may be referred to as third and fourth contact plugs 166 and 167 , respectively.

[0103] The first contact plug 164 and the third contact plug 166 may be disposed on a side of the first stacked structure SS1. For example, the first contact plug 164 and the third contact plug 166 may extend along the third direction Z to pass through the third interlayer insulating layer 104 and the first interlayer insulating layer 142. In some example embodiments, as the first contact plug 164 and the third contact plug 166 point toward the second interlayer insulating layer 144, the widths of the first contact plug 164 and the third contact plug 166 may decrease, respectively.

[0104] The second contact plug 165 and the fourth contact plug 167 may be disposed on the side of the second stacked structure SS2. The second contact plug 165 may be connected to the first contact plug 164, and the fourth contact plug 167 may be connected to the third contact plug 166. For example, the second contact plug 165 may be connected to the first contact plug 164 by passing through the second interlayer insulating layer 144, and the fourth contact plug 167 may be connected to the third contact plug 166 by passing through the second interlayer insulating layer 144. In some example embodiments, as the second contact plug 165 and the fourth contact plug 167 point to the first interlayer insulating layer 142, the widths of the second contact plug 165 and the fourth contact plug 167 may be reduced.

[0105] The conductive pad 390 may be disposed in the outer region PA. The conductive pad 390 may be formed on the first unit wiring structure 380. For example, the conductive pad 390 may be formed in the first inter-wiring insulating layer 340. The conductive pad 390 may be electrically connected to the peripheral circuit structure PERI through the second through-vias 166 and 167.

[0106] The peripheral circuit structure PERI may include a peripheral circuit substrate 200 , a peripheral circuit element PT, and a peripheral circuit wiring structure 280 .

[0107] The peripheral circuit substrate 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some example embodiments, the peripheral circuit substrate 200 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0108] The peripheral circuit element PT may be formed on the peripheral circuit substrate 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Figure 1 30). For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 37), a row decoder (e.g., Figure 1 33) and page buffers (e.g., Figure 1 35). In the following description, the surface of the peripheral circuit substrate 200 on which the peripheral circuit element PT is disposed may be referred to as the front side of the peripheral circuit substrate 200. Conversely, the surface of the peripheral circuit substrate 200 opposite to the front side of the peripheral circuit substrate 200 may be referred to as the rear side of the peripheral circuit substrate 200.

[0109] The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element PT may include various passive elements such as capacitors, resistors, and inductors, and various active elements such as transistors.

[0110] The peripheral circuit wiring structure 280 may be formed on the peripheral circuit element PT. For example, the third inter-wiring insulating layer 240 may be formed on the front side of the peripheral circuit substrate 200, and the peripheral circuit wiring structure 280 may be formed in the third inter-wiring insulating layer 240. The peripheral circuit wiring structure 280 may be electrically connected to the peripheral circuit element PT. Figure 3 The number and arrangement of the peripheral circuit wiring structures 280 shown in FIG. 2 are merely examples and are not limited thereto.

[0111] In some example embodiments, the memory cell structure CELL may be stacked on the peripheral circuit structure PERI. For example, the memory cell structure CELL may be stacked on the third inter-wiring insulating layer 240.

[0112] In some example embodiments, the second stack structure SS2 may be interposed between the peripheral circuit structure PERI and the first stack structure SS1. For example, a lower surface of the second stack structure SS2 may face the front side of the peripheral circuit substrate 200.

[0113] The semiconductor memory device according to some example embodiments may have a chip-to-chip (C2C) structure. The C2C structure refers to manufacturing an upper chip including a memory cell structure CELL on a first wafer, manufacturing a lower chip including a peripheral circuit structure PERI on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method.

[0114] For example, the bonding method may refer to a method for electrically connecting the first bonding metal 190 formed on the uppermost metal layer of the upper chip to the second bonding metal 290 formed on the uppermost metal layer of the lower chip. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is merely an example, and the first bonding metal 190 and the second bonding metal 290 may be formed of various other metals such as aluminum (Al) or tungsten (W).

[0115] Since the first bonding metal 190 and the second bonding metal 290 are bonded to each other, the second cell wiring structure 180 may be electrically connected to the peripheral circuit wiring structure 280. Therefore, the source structure 102, the gate electrodes 112 and 117, and / or the bit line BL may be electrically connected to the peripheral circuit element PT.

[0116] As semiconductor memory devices including memory cells arranged three-dimensionally are highly integrated, the aspect ratio (AR) of a channel structure extending in a vertical direction continues to increase. Therefore, a high-quality channel structure is required to satisfy required performance even with a high aspect ratio.

[0117] The semiconductor memory device according to some example embodiments may have a structure in which the channel structure CH in the first stacked structure SS1 and the channel structure CH in the second stacked structure SS2 as described above are bonded to each other. That is, the channel structure CH in the first stacked structure SS1 and the channel structure CH in the second stacked structure SS2 may be formed in separate steps and bonded to each other. Therefore, a channel structure having an improved aspect ratio while mitigating or preventing quality degradation may be provided.

[0118] In addition, in the semiconductor memory device according to some example embodiments, the channel layer 130 of the channel structure CH may have a structure in which the first semiconductor layer 1301 and the second semiconductor layer 1302 formed in different directions are bonded to each other. For example, as described above, the first semiconductor layer 1301 may be formed based on an etching process performed in a direction (e.g., -Z direction) from the first stacked structure SS1 toward the second stacked structure SS2, and the second semiconductor layer 1302 may be formed based on an etching process performed in a direction (e.g., Z direction) from the second stacked structure SS2 toward the first stacked structure SS1. Therefore, both ends of the channel structure CH may be provided in a large area. For example, a first channel pad 136 connected to the upper end of the first semiconductor layer 1301 and a second channel pad 137 connected to the lower end of the second semiconductor layer 1302 may be provided in a large area. As a result, a channel structure CH having improved connectivity with both the source structure 102 and the bit line BL may be provided.

[0119] Figure 8 is a cross-sectional view showing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 7 Redundant parts of those parts described.

[0120] Reference Figure 8 , in the semiconductor memory device according to example embodiments, the cutting structure WC may include a first cutting pattern WC1 and a second cutting pattern WC2.

[0121] The first cutting pattern WC1 may extend along the first direction X to cut the first stack structure SS1. The second cutting pattern WC2 may extend along the first direction X to cut the second stack structure SS2. The first cutting pattern WC1 and the second cutting pattern WC2 may be connected to each other in the third direction Z.

[0122] The first cutting pattern WC1 may have a tapered shape toward the second stacked structure SS2. For example, as the first cutting pattern WC1 points toward the second stacked structure SS2, the width of the first cutting pattern WC1 may decrease. This may be due to the fact that the etching process for forming the first cutting pattern WC1 is performed in a direction (e.g., -Z direction) toward the second stacked structure SS2.

[0123] The second cutting pattern WC2 may have a tapered shape toward the first stacked structure SS1. For example, as the second cutting pattern WC2 points toward the first stacked structure SS1, the width of the second cutting pattern WC2 may decrease. This may be due to the fact that the etching process for forming the second cutting pattern WC2 is performed in a direction (e.g., Z direction) toward the first stacked structure SS1.

[0124] Fig. 9is a cross-sectional view showing a semiconductor memory device according to some embodiments. Figures 1 to 7 Redundant parts of those parts described.

[0125] Reference Fig. 9 , in the semiconductor memory device according to example embodiments, the second stack structure SS2 may include a plurality of stacks S21 and S22 .

[0126] For example, the second stack structure SS2 may include a fourth stack S21 and a fifth stack S22 sequentially stacked on the lower surface of the first stack structure SS1. Each of the stacks S21 and S22 of the second stack structure SS2 may include a plurality of second mold insulating layers 115 and a plurality of second gate electrodes 117 alternately stacked. Although it is shown that only two stacks S21 and S22 are stacked on the first stack structure SS1, this is only an example, and the number of stacks S21 and S22 may be variously modified.

[0127] In some example embodiments, in each of the stacks S21 and S22 of the second stacked structure SS2, the channel structure CH may have a tapered shape toward the first stacked structure SS1. For example, as shown in the figure, in each of the stacks S21 and S22 of the second stacked structure SS2, as the channel structure CH points toward the first stacked structure SS1, the width of the channel structure CH may decrease. This may be due to the fact that the etching process for the corresponding stacks S21 and S22 of the second stacked structure SS2 for forming the channel structure CH is performed in a direction (e.g., Z direction) toward the first stacked structure SS1.

[0128] In some example embodiments, the channel structure CH may have a step difference between the stacks S21 and S22 of the second stack structure SS2. For example, on a boundary surface between the fourth stack S21 and the fifth stack S22, a width of a lower portion of the channel structure CH in the fourth stack S21 may be greater than a width of an upper portion of the channel structure CH in the fifth stack S22.

[0129] Fig.10 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments. Fig.11 and Fig.12 It is shown Fig.10 For ease of description, the above reference will be briefly described or omitted. Figures 1 to 7 Redundant parts of those parts described.

[0130] Reference Figures 10 to 12 , the semiconductor memory device according to example embodiments may further include a pad insulating layer 170 .

[0131] The pad insulating layer 170 may be interposed between the first and second stacked structures SS1 and SS2. The pad insulating layer 170 may include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0132] The pad insulating layer 170 may include a pad hole 170h inserted between the first channel hole CHh1 and the second channel hole CHh2. The pad hole 170h may connect the first channel hole CHh1 with the second channel hole CHh2. The pad hole 170h may be wider than the first channel hole CHh1 and the second channel hole CHh2. For example, on the boundary surface between the first stacked structure SS1 and the pad insulating layer 170, the width W3 of the pad hole 170h may be greater than the width W1 of the first channel hole CHh1. For example, on the boundary surface between the second stacked structure SS2 and the pad insulating layer 170, the width W3 of the pad hole 170h may be greater than the width W2 of the second channel hole CHh2.

[0133] The second semiconductor layer 1302 may be connected to the first semiconductor layer 1301 by passing through the second dielectric layer 1322 and the first dielectric layer 1321. For example, the connection hole 1302h may extend in the third direction Z to pass through the upper portion of the second dielectric layer 1322 and the lower portion of the first dielectric layer 1321, and may expose the lower portion of the first semiconductor layer 1301. The second semiconductor layer 1302 may be formed in the connection hole 1302h to be bonded to the first semiconductor layer 1301.

[0134] In some example embodiments, the first mold insulating layer 110 and the second mold insulating layer 115 adjacent to the pad insulating layer 170 may be formed to be thinner than the pad insulating layer 170. For example, a thickness T1 of the first mold insulating layer 110 adjacent to the pad insulating layer 170 and a thickness T2 of the second mold insulating layer 115 adjacent to the pad insulating layer 170 may be smaller than a thickness T3 of the pad insulating layer 170. In this case, a connection failure of the channel layer 130 due to the distance between the first gate electrode 112 and the second gate electrode 117 may be avoided.

[0135] In some example embodiments, first and second contact pads 174 and 176 may be formed in the pad insulating layer 170. The first contact pad 174 may be inserted between the first and second contact plugs 164 and 165, and the second contact pad 176 may be inserted between the third and fourth contact plugs 166 and 167. The first contact pad 174 may connect the first and second contact plugs 164 and 165, and the second contact pad 176 may connect the third and fourth contact plugs 166 and 167. The first contact pad 174 may be wider than the first and second contact plugs 164 and 165, and the second contact pad 176 may be wider than the third and fourth contact plugs 166 and 167. The first and second contact pads 174 and 176 may mitigate or prevent the occurrence of connection failures of the first through-holes 164 and 165 and the second through-holes 166 and 167 due to misalignment or the like.

[0136] Reference Fig.10 and Fig.11 In the semiconductor memory device according to example embodiments, the first semiconductor layer 1301 may further include a first pad portion 1301c. The first pad portion 1301c may be formed in the pad hole 170h. The first pad portion 1301c may extend along a plane (e.g., an XY plane) intersecting the third direction Z. For example, a lower portion of the first dielectric layer 1321 may extend to conform along a contour of the pad hole 170h, and the first pad portion 1301c may fill at least a portion of a region of the pad hole 170h that remains after the first dielectric layer 1321 is filled.

[0137] In some example embodiments, the second semiconductor layer 1302 may be connected to the first pad portion 1301c. In the pad insulating layer 170, at a plane intersecting the vertical direction, the width of the first pad portion 1301c may be greater than the width of the second semiconductor layer 1302. For example, the upper surface of the first horizontal portion 1302b may protrude upward from the lowermost surface of the first pad portion 1301c. In some example embodiments, the second column portion 1302a may pass through the first pad portion 1301c. For example, the upper surface of the first horizontal portion 1302b may protrude upward from the upper surface of the first pad portion 1301c. The first pad portion 1301c may mitigate or prevent the occurrence of a connection failure of the channel layer 130 due to misalignment, etc. In some example embodiments, the width of the first pad portion 1301c is greater than the width of the first column portion 1301a.

[0138] Reference Fig.10 and Fig.12In the semiconductor memory device according to example embodiments, the second semiconductor layer 1302 may further include a second pad portion 1302c. The second pad portion 1302c may be formed in the pad hole 170h. The second pad portion 1302c may extend along a plane (e.g., an XY plane) intersecting the third direction Z. For example, an upper portion of the second dielectric layer 1322 may extend to conform along the contour of the pad hole 170h, and the second pad portion 1302c may fill at least a portion of a region of the pad hole 170h that remains after the second dielectric layer 1322 is filled.

[0139] In some example embodiments, the first semiconductor layer 1301 may include a first pillar portion 1301a and a second horizontal portion 1301b. The second horizontal portion 1301b may extend from a lower portion of the first pillar portion 1301a along a plane (e.g., an XY plane) intersecting the third direction Z. For example, the second horizontal portion 1301b may have a plate shape (e.g., a disk shape) for blocking the lower portion of the cylindrical first pillar portion 1301a. That is, the first semiconductor layer 1301 including the first pillar portion 1301a and the second horizontal portion 1301b may have a cup shape.

[0140] In some example embodiments, the second pillar portion 1302a may pass through the second pad portion 1302c. For example, the upper surface of the first horizontal portion 1302b may protrude upward from the upper surface of the second pad portion 1302c. In some example embodiments, the second semiconductor layer 1302 may be connected to the second horizontal portion 1301b. For example, the upper surface of the first horizontal portion 1302b may protrude upward from the lowermost surface of the second horizontal portion 1301b. The second pad portion 1302c may reduce or prevent the occurrence of a connection failure of the channel layer 130 due to misalignment, etc.

[0141] Fig.13 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments. Figures 14 to 17 It is shown Fig.13 For ease of description, the above reference will be briefly described or omitted. Figures 1 to 12 Redundant parts of those parts described.

[0142] Reference Figures 13 to 17 , the semiconductor memory device according to some embodiments may further include a dummy gate electrode 119 .

[0143] The dummy gate electrode 119 may be formed in the pad insulating layer 170. The dummy gate electrode 119 may be spaced apart from the first gate electrode 112 by the first mold insulating layer 110, and may be spaced apart from the second gate electrode 117 by the second mold insulating layer 115. A portion of the channel layer 130 may intersect the dummy gate electrode 119. The dummy gate electrode 119 may include a conductive material, for example, a metal such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon, but is not limited thereto.

[0144] The dummy gate electrode 119 may include a pad hole 170h inserted between the first channel hole CHh1 and the second channel hole CHh2. Figures 10 to 12 The pad holes are similar, so their detailed description will be omitted.

[0145] Reference Fig.13 and Fig.14 In the semiconductor memory device according to the example embodiment, the first semiconductor layer 1301 may further include a first pad portion 1301c. Fig.10 and Fig.11 The described pad portion is similar, so a detailed description thereof will be omitted.

[0146] Reference Fig.13 and Fig.15 In the semiconductor memory device according to the example embodiment, the second semiconductor layer 1302 may further include a second pad portion 1302c. Fig.10 and Fig.12 The pad portion is similar, so a detailed description thereof will be omitted.

[0147] Reference Fig.13 , Fig.16 and Fig.17 , in a semiconductor memory device according to some example embodiments, the dummy gate electrode 119 may include a plurality of dummy word lines 1191 to 1193 that are spaced apart from each other and sequentially stacked.

[0148] For example, the dummy word lines 1191 to 1193 may be sequentially stacked by being spaced apart from each other by the first mold insulating layer 110. The number and shapes of the dummy word lines 1191 to 1193 are not limited to those shown.

[0149] In some example embodiments, the pad hole 170 h may connect the first channel hole CHh1 with the second channel hole CHh2 by passing through the dummy word lines 1191 to 1193 .

[0150] In some example embodiments, Fig.16As shown, the first semiconductor layer 1301 may include a first extension 1301d in the dummy word lines 1191 to 1193. The first extension 1301d may be formed in the pad hole 170h. For example, the lower portion of the first dielectric layer 1321 may extend to conform to the contour of the pad hole 170h, and the first extension 1301d may extend to conform to the contour of the first dielectric layer 1321 in the pad hole 170h.

[0151] In some example embodiments, Fig.17 As shown, the second semiconductor layer 1302 may further include a second extension 1302d in the dummy word lines 1191 to 1193. The second extension 1302d may be formed in the pad hole 170h. For example, the upper portion of the second dielectric layer 1322 may extend to conform to the contour of the pad hole 170h, and the second extension 1302d may extend to conform to the contour of the second dielectric layer 1322 in the pad hole 170h.

[0152] In the following, reference will be made to Figures 1 to 57 A method of manufacturing a semiconductor memory device according to some example embodiments is described.

[0153] Figures 18 to 34 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 17 Those redundant parts of the description.

[0154] Reference Fig.18 , a first molding member pS11 , a first interlayer insulating layer 142 , and a first preliminary channel pCH11 are formed on the base substrate 100 .

[0155] The base substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some example embodiments, the base substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0156] The first molding member pS11 may include a plurality of first molding insulating layers 110 and a plurality of first molding sacrificial layers 111 alternately stacked. The first molding sacrificial layers 111 may include a material having an etching selectivity relative to the first molding insulating layers 110. For example, the first molding insulating layer 110 may include a silicon oxide layer, and the first molding sacrificial layer 111 may include a silicon nitride layer. The first molding member pS11 in the extension area EA may be patterned into a step shape. Therefore, the first molding sacrificial layers 111 of the first molding member pS11 may be stacked in a step shape. The first interlayer insulating layer 142 may be formed to cover the first molding member pS11.

[0157] The first preliminary channel pCH11 may pass through the first molding member pS11 in the cell array region CA. The first preliminary channel pCH11 may include a material having an etch selectivity with respect to the first mold insulating layer 110 and the first mold sacrificial layer 111. For example, the first preliminary channel pCH11 may include polysilicon (poly-Si).

[0158] Reference Fig.19 , a second molding member pS12 , a second preliminary channel pCH12 , a third molding member pS13 , and a third preliminary channel pCH13 are formed on the first molding member pS11 and the first preliminary channel pCH11 .

[0159] The second molding member pS12 and the third molding member pS13 may include a plurality of first molding insulating layers 110 and a plurality of first molding sacrificial layers 111 alternately stacked. The formation of the second molding member pS12 and the third molding member pS13 may be similar to the formation of the first molding member pS11, and thus a detailed description thereof is omitted. Thus, a first preliminary stack structure pSS1 including the first molding member pS11, the second molding member pS12, and the third molding member pS13 may be formed.

[0160] The second preliminary channel pCH12 may pass through the second molding member pS12 in the cell array region CA, and the third preliminary channel pCH13 may pass through the third molding member pS13 in the cell array region CA. In addition, the second preliminary channel pCH12 may be connected to the first preliminary channel pCH11, and the third preliminary channel pCH13 may be connected to the second preliminary channel pCH12. The formation of the second preliminary channel pCH12 and the third preliminary channel pCH13 may be similar to the formation of the first preliminary channel pCH11, and thus a detailed description thereof is omitted.

[0161] Reference Fig. 20 , a channel layer 130 , a data storage layer 132 , a first filling insulation layer 134 , and a first channel pad 136 are formed in the first preliminary stacked structure pSS1 .

[0162] For example, the first preliminary channel pCH11, the second preliminary channel pCH12, and the third preliminary channel pCH13 in the first preliminary stack structure pSS1 may be selectively removed. Subsequently, a data storage layer 132, a channel layer 130, a first filling insulating layer 134, and a first channel pad 136 may be sequentially formed in the region where the first preliminary channel pCH11, the second preliminary channel pCH12, and the third preliminary channel pCH13 are removed.

[0163] Reference Fig.21 , a source structure 102 and a third interlayer insulating layer 104 are formed on the first interlayer insulating layer 142 .

[0164] A source structure 102 may be formed on the first interlayer insulating layer 142 of the cell array area CA. The source structure 102 may contact one end of the channel layer 130 and / or the first channel pad 136. A third interlayer insulating layer 104 may be formed on the first interlayer insulating layer 142 of the extension area EA and the outer area PA.

[0165] Reference Fig. 22 , the memory cell structure CELL is attached to the carrier substrate 400 .

[0166] For example, the carrier substrate 400 may be attached onto the source structure 102 and the third interlayer insulating layer 104. The memory cell structure CELL to which the carrier substrate 400 is attached may be reversed.

[0167] Reference Fig.23 and Fig.24 , a second preliminary stacked structure pSS2 and a second interlayer insulating layer 144 are formed on the first preliminary stacked structure pSS1 and the first interlayer insulating layer 142. For reference, Fig.24 It is shown Fig.23 Magnified view of region R1.

[0168] For example, the base substrate 100 may be removed. Then, a second initial stack structure pSS2 may be formed on the upper surface of the first initial stack structure pSS1 and the upper surface of the first interlayer insulating layer 142. The second initial stack structure pSS2 may include a plurality of second molded insulating layers 115 and a plurality of second molded sacrificial layers 116 that are alternately stacked. The second molded sacrificial layers 116 may include a material having an etching selectivity relative to the second molded insulating layers 115. For example, the second molded insulating layer 115 may include a silicon oxide layer, and the second molded sacrificial layer 116 may include a silicon nitride layer. The second initial stack structure pSS2 in the extension area EA may be patterned into a step shape. Therefore, the second molded sacrificial layers 116 of the second initial stack structure pSS2 may be stacked in a step shape. A second interlayer insulating layer 144 may be formed to cover the second initial stack structure pSS2.

[0169] Reference Fig.25 and Fig.26 , a second channel hole CHh2 is formed in the second preliminary stack structure pSS2. For reference, Fig.26 It is shown Fig.25 Magnified view of region R1.

[0170] The second channel hole CHh2 may pass through the second preliminary stacked structure pSS2. For example, the lower surface of the second channel hole CHh2 may be formed to be lower than the boundary surface between the first preliminary stacked structure pSS1 and the second preliminary stacked structure pSS2. Although the second horizontal portion 1301b of the first semiconductor layer 1301 is shown as being completely removed via the second channel hole CHh2, this is merely an example, and after forming the second channel hole CHh2, at least a portion of the second horizontal portion 1301b may remain.

[0171] Reference Fig. 27 , a second dielectric layer 1322 and a sacrificial semiconductor layer 130S are sequentially formed in the second channel hole CHh2.

[0172] The sacrificial semiconductor layer 130S may extend to conform to the contour of the second dielectric layer 1322. The sacrificial semiconductor layer 130S may include, for example, a semiconductor material such as single crystal silicon, polysilicon, an organic semiconductor material, or a carbon nanostructure, but is not limited thereto.

[0173] Reference Fig.28 A connection hole 1302h exposing the first semiconductor layer 1301 is formed in the second channel hole CHh2.

[0174] The connection hole 1302h may expose the upper portion of the first semiconductor layer 1301 by passing through the lower portion of the second dielectric layer 1322. For example, the connection hole 1302h may expose the first pillar portion 1301a. The sacrificial semiconductor layer 130S may be provided as a protective layer for protecting the second dielectric layer 1322 in the process of forming the connection hole 1302h.

[0175] Reference Fig.29 , a second semiconductor layer 1302 is formed in the connection hole 1302h.

[0176] Thus, a second semiconductor layer 1302 bonded to the first semiconductor layer 1301 may be formed. In some example embodiments, the second semiconductor layer 1302 may extend to conform to the contour of the connection hole 1302h. Thus, a second semiconductor layer 1302 including a second pillar portion 1302a and a first horizontal portion 1302b may be formed. In addition, a channel layer 130 including the first semiconductor layer 1301 and the second semiconductor layer 1302 may be formed.

[0177] Reference Fig.30 , a second filling insulating layer 135 and a second channel pad 137 are sequentially formed on the channel layer 130. A channel structure CH including the channel layer 130, the data storage layer 132, the first filling insulating layer 134, the second filling insulating layer 135, the first channel pad 136 and the second channel pad 137 may be formed.

[0178] Reference Fig.31 , a cutting region WCh for cutting the first preliminary stack structure pSS1 and the second preliminary stack structure pSS2 is formed.

[0179] Reference Fig.32 , forming a plurality of gate electrodes 112 and 117.

[0180] For example, the mold sacrificial layers 111 and 116 exposed by the cutting region WCh may be selectively removed. Then, gate electrodes 112 and 117 may be formed, replacing the regions where the mold sacrificial layers 111 and 116 are removed. Thus, a first stacked structure SS1 including a plurality of first gate electrodes 112 and a second stacked structure SS2 including a plurality of second gate electrodes 117 may be formed. After forming the plurality of gate electrodes 112 and 117, a cutting structure WC filling the cutting region WCh may be formed.

[0181] Reference Fig.33 , a second inter-wiring insulating layer 146 , a second unit wiring structure 180 , and a first bonding metal 190 are formed on the second interlayer insulating layer 144 .

[0182] Reference Fig.34 , stacking the memory cell structure CELL on the peripheral circuit structure PERI.

[0183] For example, the first bonding metal 190 of the memory cell structure CELL may be bonded with the second bonding metal 290 of the peripheral circuit structure PERI. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method.

[0184] Next, refer to Figure 4 , a first inter-wiring insulating layer 340, a first unit wiring structure 380 and a conductive pad 390 are formed on the source structure 102 and the third interlayer insulating layer 104. Thus, the Figures 3 to 7 The semiconductor memory device.

[0185] Figure 35 to Figure 39 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 34 For reference, Fig.35 It shows the description Fig. 20 An illustration of the intermediate steps of the following steps.

[0186] Reference Fig.35 , a first cutting region WCh1 for cutting the first preliminary stack structure pSS1 is formed.

[0187] Reference Fig.36 , forming a plurality of first gate electrodes 112.

[0188] For example, the first mold sacrificial layer 111 exposed by the first cutting region WCh1 may be selectively removed. Then, the first gate electrode 112 may be formed, replacing the region where the first mold sacrificial layer 111 is removed. Thus, the first stacked structure SS1 including the plurality of first gate electrodes 112 may be formed. After the plurality of first gate electrodes 112 are formed, a first cutting pattern WC1 for filling the first cutting region WCh1 may be formed.

[0189] Reference Fig.37 , forming a source structure 102, a third interlayer insulating layer 104, a second preliminary stacked structure pSS2 and a channel structure CH. For example, the reference Figures 21 to 30 Describe the steps.

[0190] Reference Fig.38 , forming a second cutting region WCh2 for cutting the second preliminary stack structure pSS2.

[0191] Reference Fig.39 , forming a plurality of second gate electrodes 117.

[0192] For example, the second mold sacrificial layer 116 exposed by the second cutting region WCh2 may be selectively removed. Then, the second gate electrode 117 may be formed instead of the region where the second mold sacrificial layer 116 is removed. Thus, a second stacked structure SS2 including a plurality of second gate electrodes 117 may be formed. After forming the plurality of second gate electrodes 117, a second cutting pattern WC2 for filling the second cutting region WCh2 may be formed.

[0193] Then, you can execute the reference Fig.33 , Fig.34 and Figure 4 Therefore, it is possible to manufacture a reference Figure 8 A semiconductor memory device is described.

[0194] Figure 40 to Figure 42 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 34 For reference, Fig.40 It shows the description Fig.23 An illustration of the intermediate steps of the following steps.

[0195] Reference Fig.40 , a fourth molding member pS21, a second interlayer insulating layer 144, and a fourth preliminary channel pCH21 are formed on the first preliminary stacked structure pSS1.

[0196] The fourth molding pS21 may include a plurality of second molding insulating layers 115 and a plurality of second molding sacrificial layers 116 alternately stacked. The fourth molding pS21 in the extension area EA may be patterned into a step shape. A second interlayer insulating layer 144 may be formed to cover the fourth molding pS21.

[0197] The fourth preliminary channel pCH21 may pass through the fourth molding member pS21 in the cell array region CA. The fourth preliminary channel pCH21 may include a material having an etch selectivity with respect to the second mold insulating layer 115 and the second mold sacrificial layer 116. For example, the fourth preliminary channel pCH21 may include polysilicon (poly-Si).

[0198] Reference Fig.41 , a fifth molding member pS22 and a fifth preliminary channel pCH22 are formed on the fourth molding member pS21 and the fourth preliminary channel pCH21.

[0199] The fifth molding member pS22 may include a plurality of second molding insulating layers 115 and a plurality of second molding sacrificial layers 116 alternately stacked. The formation of the fifth molding member pS22 may be similar to the formation of the fourth molding member pS21, and thus a detailed description thereof will be omitted. Thus, a second preliminary stack structure pSS2 including the fourth molding member pS21 and the fifth molding member pS22 may be formed.

[0200] The fifth preliminary channel pCH22 may pass through the fifth molding member pS22 in the cell array region CA. In addition, the fifth preliminary channel pCH22 may be connected to the fourth preliminary channel pCH21. The formation of the fifth preliminary channel pCH22 may be similar to that of the fourth preliminary channel pCH21, and thus a detailed description thereof will be omitted.

[0201] Reference Fig.42 , the fourth preliminary channel pCH21 and the fifth preliminary channel pCH22 are selectively removed. Thus, a second channel hole CHh2 passing through the second preliminary stack structure pSS2 may be formed.

[0202] Then, you can execute the reference Figures 27 to 34 and Figure 4 Therefore, it is possible to manufacture a reference Fig. 9 A semiconductor memory device is described.

[0203] Figures 43 to 51 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 34 Redundant parts of those parts described.

[0204] Reference Fig.43 and Fig.44, a pad insulating layer 170, a sacrificial pad 172, a first preliminary stack structure pSS1, a first interlayer insulating layer 142, a first preliminary channel pCH11, a second preliminary channel pCH12, and a third preliminary channel pCH13 are formed on the base substrate 100. For reference, Fig.44 It is shown Fig.43 An enlarged view of region R4.

[0205] A pad insulating layer 170 may be formed on the base substrate 100. A sacrificial pad 172 may be formed in the pad insulating layer 170 of the cell array area CA. In some example embodiments, a first contact pad 174 and a second contact pad 176 may be further formed in the pad insulating layer 170 of the outer area PA.

[0206] A first preliminary stack structure pSS1 , a first interlayer insulating layer 142 , a first preliminary channel pCH11 , a second preliminary channel pCH12 , and a third preliminary channel pCH13 may be formed on the pad insulating layer 170 .

[0207] Reference Fig.45 , forming a first channel hole CHh1 and a pad hole 170h.

[0208] For example, the first preliminary channel pCH11 , the second preliminary channel pCH12 , the third preliminary channel pCH13 , and the sacrificial pad 172 may be selectively removed.

[0209] Reference Fig.46 , a first dielectric layer 1321 and a first semiconductor layer 1301 are formed in the first channel hole CHh1 and the pad hole 170h. For example, the following may be performed: Fig. 20 Thus, the first semiconductor layer 1301 including the first pillar portion 1301a, the second horizontal portion 1301b, and the first pad portion 1301c may be formed.

[0210] Reference Fig.47 , a second preliminary stack structure pSS2 is formed on the pad insulating layer 170. For example, the following may be performed: Figure 21 to Figure 23 Describe the steps.

[0211] Reference Fig.48 , a second channel hole CHh2 is formed in the second preliminary stack structure pSS2.

[0212] The second channel hole CHh2 may penetrate the second preliminary stack structure pSS2. For example, the second channel hole CHh2 may expose the first dielectric layer 1321 in the pad hole 170h.

[0213] Reference Fig.49 , a second dielectric layer 1322 and a sacrificial semiconductor layer 130S are sequentially formed in the second channel hole CHh2.

[0214] Reference Fig.50 A connection hole 1302h exposing the first semiconductor layer 1301 is formed in the second channel hole CHh2.

[0215] The connection hole 1302h may expose an upper portion of the first semiconductor layer 1301 by passing through a lower portion of the second dielectric layer 1322 and an upper portion of the first dielectric layer 1321. For example, the connection hole 1302h may expose the first pillar portion 1301a and the first pad portion 1301c.

[0216] Reference Fig.51 , a second semiconductor layer 1302 is formed in the connection hole 1302h.

[0217] Then, you can execute the reference Figure 30 to Figure 34 and Figure 4 Therefore, it is possible to manufacture a reference Fig.10 and Fig.11 A semiconductor memory device is described.

[0218] Figure 52 to Figure 57 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment. For ease of description, the above references will be briefly described or omitted. Figures 1 to 51 For reference, Fig.52 It shows the description Fig. 22 An illustration of the intermediate steps of the following steps.

[0219] Reference Fig.52 and Fig.53 A pad insulating layer 170 , a sacrificial pad 172 , a second preliminary stack structure pSS2 , and a second interlayer insulating layer 144 are formed on the first preliminary stack structure pSS1 and the first interlayer insulating layer 142 .

[0220] For example, the base substrate 100 may be removed. A pad insulating layer 170 and a sacrificial pad 172 may be formed on an upper surface of the first preliminary stacked structure pSS1 and an upper surface of the first interlayer insulating layer 142. In some example embodiments, a first contact pad 174 and a second contact pad 176 may also be formed in the pad insulating layer 170 of the outer area PA.

[0221] A second preliminary stack structure pSS2 and a second interlayer insulating layer 144 may be formed on the pad insulating layer 170 .

[0222] Reference Fig.54 , forming a second channel hole CHh2 and a pad hole 170h.

[0223] For example, a second channel hole CHh2 for exposing the sacrificial pad 172 by passing through the second preliminary stack structure pSS2 may be formed. Subsequently, the sacrificial pad 172 exposed by the second channel hole CHh2 may be selectively removed.

[0224] Reference Fig.55 , a second dielectric layer 1322 and a sacrificial semiconductor layer 130S are formed in the second channel hole CHh2 and the pad hole 170h.

[0225] Reference Fig.56 A connection hole 1302h for exposing the first semiconductor layer 1301 is formed in the second channel hole CHh2.

[0226] The connection hole 1302h may expose the upper portion of the first semiconductor layer 1301 by passing through the lower portion of the second dielectric layer 1322 and the upper portion of the first dielectric layer 1321. For example, the connection hole 1302h may expose the second horizontal portion 1301b. In some example embodiments, the portion of the sacrificial semiconductor layer 130S remaining in the pad hole 170h may form the second pad portion 1302c.

[0227] Reference Fig.57 , a second semiconductor layer 1302 is formed in the connection hole 1302h.

[0228] Then, you can execute the above reference Figure 30 to Figure 34 and Figure 4 As a result, the above-mentioned steps can be manufactured Fig.10 and Fig.12 A semiconductor memory device is described.

[0229] In the following, reference will be made to Figures 1 to 60 An electronic system including a semiconductor memory device according to some example embodiments is described.

[0230] Fig.58 is a block diagram illustrating an electronic system according to example embodiments. Fig.59 is a perspective view illustrating an electronic system according to example embodiments. Fig.60 is along Fig.59 For the sake of convenience, the reference will be briefly described or omitted. Figures 1 to 37 The redundant part of the above part.

[0231] Reference Fig.58, an electronic system 1000 according to example embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a memory device including one or more semiconductor memory devices 1100 or an electronic device including a memory device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0232] The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), and may include, for example, a reference Figures 1 to 17 At least one of the semiconductor memory devices described herein. The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 110F.

[0233] The first structure 1100F may include a decoder circuit 1110 (eg, Figure 1 , a row decoder 33), a page buffer 1120 (eg, Figure 1 110 and logic circuit 1130 (eg, Figure 1 For example, the first structure 1100F may correspond to the control logic 37 of the reference Figures 1 to 17 Describe the peripheral circuit structure PERI.

[0234] The second structure 1100S may include the Figure 2 The common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR described above may be connected to the decoder circuit 1110 through word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell string CSTR may be connected to the page buffer 1120 through the bit lines BL. For example, the second structure 1100S may correspond to the reference Figures 1 to 17 The memory cell structure CELL is described.

[0235] In some embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S.

[0236] In some example embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through the second connection line 1125 .

[0237] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Figure 1The input / output pad 1101 of the control logic 37) communicates with the controller 1200. The input / output pad 1101 may correspond to the reference Figures 1 to 17 The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S. For example, the connection line 1135 may correspond to the reference Figures 1 to 17 Second feedthroughs 166 and 167 are described.

[0238] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0239] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written to the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be sent through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0240] Reference Fig.59 and Fig.60 , an electronic system 2000 according to some embodiments may include a main board 2001, a main controller 2002 packaged on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed in the main board 2001.

[0241] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may perform communication with the external host according to any one of interfaces such as a universal serial bus (USB), a peripheral component interconnect high speed (PCI-Express), a serial advanced technology attachment (SATA), and M-PHy for universal flash memory (UFS). In some embodiments, the electronic system 2000 may be operated by power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0242] The main controller 2002 may write data into or read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0243] The DRAM 2004 may be a buffer memory for alleviating a speed difference between the semiconductor package 2003 as a data storage space and an external host. In addition, the DRAM 2004 included in the electronic system 2000 may operate as a high-speed cache memory and may provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0244] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 for electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 on the package substrate 2100 and the connection structure 2400.

[0245] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.58 Input / output pad 1101.

[0246] In some example embodiments, the connection structure 2400 may be a bonding wire for electrically connecting the input / output pad 2210 with the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV) instead of the connection structure 2400 by a bonding wire manner.

[0247] In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in one package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be packaged on a separate interposer substrate different from the main board 2001, and the main controller 2002 may be connected to the semiconductor chip 2200 through a wire formed in the interposer substrate.

[0248] In some example embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body portion 2120, a lower pad 2125 disposed on a lower surface of the package substrate body portion 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the upper pad 2130 with the lower pad 2125 inside the package substrate body portion 2120. The package upper pad 2130 may be electrically connected to the connection structure 2400. Fig.59 As shown, the lower pad 2125 may be connected to the wiring pattern 2005 of the main board 2001 of the electronic system 2000 through the conductive connector 2800 .

[0249] In an electronic system according to some example embodiments, each of the semiconductor chips 2200 may include a reference Figures 1 to 17 For example, the semiconductor chip 2200 may include a memory cell structure CELL and a peripheral circuit structure PERI. Illustratively, the memory cell structure CELL may include reference Figures 3 to 7The first stack structure SS1, the second stack structure SS2, the channel structure CH, the cutting structure WC, the bit lines BL, the first through-holes 164 and 165, and the second through-holes 166 and 167 are described.

[0250] Any functional blocks shown in the figure and described above may be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0251] Although the present invention has been specifically shown and described with reference to some exemplary embodiments of the present invention, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present invention as defined by the appended claims. It is intended that the present exemplary embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present invention.

Claims

1. A semiconductor memory device, comprising: A first stacked structure including a plurality of first gate electrodes sequentially stacked and spaced apart from each other; a second stacked structure located on the first stacked structure, the second stacked structure comprising a plurality of second gate electrodes sequentially stacked and spaced apart from each other; as well as a channel structure extending in a vertical direction to pass through the first stacked structure and the second stacked structure, Wherein, the channel structure comprises: a channel layer including a first column portion intersecting the plurality of first gate electrodes, a second column portion intersecting the plurality of second gate electrodes, and a horizontal portion extending along a plane intersecting the vertical direction, the horizontal portion connecting the first column portion and the second column portion, and The data storage layer extends along the outer side of the channel layer.

2. The semiconductor memory device according to claim 1, wherein: As the first pillar portion points toward the second stack structure, the width of the first pillar portion decreases, and As the second pillar portion points toward the first stack structure, a width of the second pillar portion decreases.

3. The semiconductor memory device according to claim 1, wherein: The plurality of first gate electrodes are stacked in a step shape on an upper surface of the second stack structure, and The plurality of second gate electrodes are stacked in a step shape on a lower surface of the first stack structure.

4. The semiconductor memory device according to claim 1, wherein: The first stacking structure includes a first stacking member and a second stacking member, wherein the first stacking member and the second stacking member are sequentially stacked on the second stacking structure, Each of the first stack and the second stack includes the plurality of first gate electrodes, and At a boundary surface between the first stack and the second stack, a width of the channel structure in the first stack is greater than a width of the channel structure in the second stack.

5. The semiconductor memory device according to claim 1, wherein: The channel structure further includes: A first filling insulating layer at least partially fills the interior of the first column portion; and a second filling insulating layer at least partially filling the interior of the second column portion; and The horizontal portion separates the first filling insulating layer from the second filling insulating layer.

6. The semiconductor memory device according to claim 5, wherein: The channel structure further includes: a first trench pad connected to one end of the first pillar portion on the first filling insulating layer; and A second trench pad is connected to one end of the second pillar portion on the second filling insulating layer.

7. The semiconductor memory device according to claim 1, wherein: The data storage layer comprises: a first dielectric layer including a first tunneling insulating layer, a first charge storage layer, and a first blocking insulating layer sequentially stacked on an outer side of the first pillar portion; and a second dielectric layer including a second tunneling insulating layer, a second charge storage layer, and a second blocking insulating layer sequentially stacked on an outer side of the second pillar portion, and The second blocking insulating layer separates the first charge storage layer from the second charge storage layer.

8. The semiconductor memory device according to claim 1, further comprising: a pad insulating layer interposed between the first stacked structure and the second stacked structure, The channel layer further includes a pad portion extending in the pad insulating layer along a plane intersecting the vertical direction. The width of the pad portion is greater than the width of the first column portion, and The second pillar portion is connected to the pad portion.

9. The semiconductor memory device according to claim 1, further comprising: a source structure connected to the first pillar portion on the first stacked structure; as well as A bit line is connected to the second pillar portion on the second stack structure.

10. The semiconductor memory device according to claim 1, further comprising: A peripheral circuit structure comprising a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate, Wherein, the second stacking structure is inserted between the first stacking structure and the peripheral circuit structure.

11. A semiconductor memory device comprising: A peripheral circuit structure, comprising a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate; A first stacked structure, which is located on the peripheral circuit structure, the first stacked structure comprising a plurality of first gate electrodes sequentially stacked and spaced apart from each other; A second stacked structure, located between the peripheral circuit structure and the first stacked structure, the second stacked structure comprising a plurality of second gate electrodes sequentially stacked and spaced apart from each other; a channel layer extending in a vertical direction and passing through the first stacked structure and the second stacked structure, the channel layer comprising a first semiconductor layer intersecting the plurality of first gate electrodes and a second semiconductor layer intersecting the plurality of second gate electrodes; The data storage layer includes: a first dielectric layer interposed between the first stacked structure and the first semiconductor layer, and a second dielectric layer interposed between the second stacked structure and the second semiconductor layer; a source structure connected to the first semiconductor layer on the first stacked structure; and a bit line connected to the second semiconductor layer and located between the peripheral circuit structure and the second stacked structure, As the first semiconductor layer points toward the second stacked structure, the width of the first semiconductor layer decreases. As the second semiconductor layer is directed toward the first stacked structure, the width of the second semiconductor layer decreases, and The second semiconductor layer includes a horizontal portion extending along a plane intersecting the vertical direction and connected to the first semiconductor layer.

12. The semiconductor memory device according to claim 11, wherein: The horizontal portion is in the first stacking structure.

13. The semiconductor memory device according to claim 11, further comprising: a pad insulating layer interposed between the first stacked structure and the second stacked structure, wherein the first semiconductor layer includes a pad portion extending along a plane intersecting the vertical direction in the pad insulating layer, On the plane, the width of the pad portion is greater than the width of the second semiconductor layer, and The second semiconductor layer is connected to the pad portion.

14. The semiconductor memory device according to claim 11, wherein: Each of the first semiconductor layer and the second semiconductor layer includes a polycrystalline silicon (poly-Si) layer.

15. The semiconductor memory device according to claim 11, wherein: Each of the first dielectric layer and the second dielectric layer includes a tunneling insulating layer, a charge storage layer, and a blocking insulating layer sequentially stacked on an outer side of the channel layer.

16. The semiconductor memory device according to claim 15, wherein: Each of the tunnel insulating layer and the blocking insulating layer includes a silicon oxide layer, and The charge storage layer includes a silicon nitride layer.

17. The semiconductor memory device according to claim 11, further comprising: a cutting structure, wherein the cutting structure extends along a first horizontal direction intersecting the vertical direction, and the cutting structure cuts the first stacking structure and the second stacking structure, The bit line extends in a second horizontal direction intersecting the vertical direction and the first horizontal direction.

18. The semiconductor memory device according to claim 11, further comprising: a first contact plug extending along the vertical direction on one side of the first stack structure; as well as A second contact plug extends along the vertical direction on one side of the second stack structure, the second contact plug electrically connecting the peripheral circuit structure and the first contact plug.

19. An electronic system comprising: Motherboard; A semiconductor memory device comprising a peripheral circuit structure and a unit structure sequentially stacked on the main board; as well as a controller located on the main board and electrically connected to the semiconductor memory device, Wherein, the unit structure comprises: a first stacked structure including a plurality of first gate electrodes sequentially stacked and spaced apart from each other, a second stacked structure located between the peripheral circuit structure and the first stacked structure, the second stacked structure comprising a plurality of second gate electrodes sequentially stacked and spaced apart from each other, and a channel structure extending in a vertical direction and passing through the first stacking structure and the second stacking structure, and Wherein, the channel structure comprises: a channel layer including a first column portion intersecting the plurality of first gate electrodes, a second column portion intersecting the plurality of second gate electrodes, and a horizontal portion extending along a plane intersecting the vertical direction, the horizontal portion connecting the first column portion and the second column portion, and The data storage layer extends along the outer side of the channel layer.

20. The semiconductor memory device according to claim 19, wherein: As the first pillar portion points toward the second stack structure, the width of the first pillar portion decreases, and As the second pillar portion points toward the first stack structure, a width of the second pillar portion decreases.

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