Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. In the semiconductor device, a first HKMG transistor having a first threshold voltage forms a first memory cell, a second HKMG transistor having a second threshold voltage forms a second memory cell, and the first memory cell and the second memory cell are connected by using the difference between the first threshold voltage and the second threshold voltage. The first storage unit and the second storage unit can form different conduction states, and 0 / 1 state reading is achieved. Manufacturing of the first HKMG transistor and the second HKMG transistor is compatible with an HKMG technology, the first HKMG transistor and the second HKMG transistor can be formed together with other devices of an HKMG technology platform, the integration density of the semiconductor device can be improved, the technology difficulty can be reduced, the first HKMG transistor and the second HKMG transistor do not adopt floating gate type gate structures, the operation voltage is low, and the manufacturing cost is low. And the method can be compatible with low-voltage device (such as logic device) processes.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a semiconductor memory device that can be rewritten multiple times electronically. Current EEPROM devices use a floating gate tunnel oxide layer transistor structure to form a storage unit. Under the action of an external strong electric field, bidirectional electron flow is achieved between the drain and the floating gate, thereby realizing the control of the storage unit.

[0003] In addition, with the development of manufacturing technology and the reduction of critical dimensions, the HKMG (high dielectric constant gate dielectric and metal gate) process has the advantages of reducing gate dielectric leakage current and avoiding polysilicon gate depletion effect, and has been applied to CMOS integrated circuit manufacturing.

[0004] However, the above-mentioned structure of the EEPROM device makes it difficult to be compatible with the HKMG process, which increases the process difficulty and reduces the integration density. In addition, since the control gate needs to be connected to a high voltage (usually not less than 12V) when writing to form a strong positive electric field between the floating gate and the drain to allow electrons to enter the floating gate from the drain through the tunnel oxide layer, the existing structure of the EEPROM device is also incompatible with the low-voltage device process. Summary of the invention

[0005] In order to solve the problem that the current memory device using a floating gate tunnel oxide layer transistor structure is incompatible with the HKMG process and the low voltage device process, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device.

[0006] In one aspect, the present invention provides a semiconductor device, comprising:

[0007] A substrate, the substrate comprising a first conductivity type doped region;

[0008] at least one first HKMG transistor having a first threshold voltage, formed on a surface of a corresponding first conductivity type doped region, wherein a gate and a source / drain region of the first HKMG transistor are of a second conductivity type; and

[0009] At least one second HKMG transistor with a second threshold voltage is formed on the surface of the corresponding first conductivity type doped region, the gate of the second HKMG transistor has the first conductivity type and the source and drain regions have the second conductivity type;

[0010] The first HKMG transistor forms a first storage unit, the second HKMG transistor forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage to achieve 0 / 1 state readout.

[0011] Optionally, the substrate has a first conductivity type doping or a second conductivity type doping, and the first conductivity type doping region is formed by the substrate or by a well region formed in the substrate.

[0012] Optionally, the difference between the first threshold voltage and the second threshold voltage is (1±x)V, where x is a value greater than 0 and less than 1.

[0013] Optionally, the first threshold voltage is less than the second threshold voltage.

[0014] Optionally, the gate of the first HKMG transistor includes a second conductivity type work function adjustment layer and an electrode material layer stacked on the second conductivity type work function adjustment layer.

[0015] Optionally, the gate of the second HKMG transistor includes a first conductivity type work function adjustment layer and an electrode material layer stacked on the first conductivity type work function adjustment layer.

[0016] Optionally, at least one pair of adjacent first HKMG transistors and second HKMG transistors shares the same first conductivity type doping region.

[0017] Optionally, at least one pair of adjacent first HKMG transistors and second HKMG transistors share the same source and drain region; or at least one pair of adjacent first HKMG transistors and second HKMG transistors do not share the same source and drain region.

[0018] Optionally, the semiconductor device further includes a logic transistor formed on the surface of the substrate, and the logic transistor has a HKMG gate structure.

[0019] In another aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0020] providing a substrate, the substrate comprising a first conductivity type doped region; and

[0021] At least one first HKMG transistor and at least one second HKMG transistor are formed on the surface of the first conductive type doped region, so that the gate and source-drain region of the first HKMG transistor are of the second conductive type, and the gate of the second HKMG transistor has the first conductive type and the source-drain region has the second conductive type, wherein the first HKMG transistor has a first threshold voltage and forms a first storage unit, and the second HKMG transistor has a second threshold voltage and forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, so as to realize 0 / 1 state readout.

[0022] Optionally, forming at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductive type doped region includes:

[0023] A first dummy gate and a second dummy gate are formed on the surface of the first conductive type doped region respectively, and sidewalls, corresponding source and drain regions, and an interlayer dielectric layer are formed on both sides of the first dummy gate and the second dummy gate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first dummy gate and the second dummy gate;

[0024] removing the first dummy gate and forming a first groove at the position of the first dummy gate;

[0025] Forming a first gate dielectric layer and a second conductive type work function adjustment layer on the inner wall of the first groove, and filling the inner wall with electrode material, wherein the first gate dielectric layer includes a high dielectric constant material;

[0026] Performing a planarization process to expose the upper surface of the interlayer dielectric layer, the remaining conductive material in the first groove and the second conductive type work function adjustment layer form the gate of the first HKMG transistor, and the source and drain regions on both sides of the first groove are the source and drain regions of the first HKMG transistor;

[0027] removing the second dummy gate and forming a second groove at the position of the second dummy gate;

[0028] forming a second gate dielectric layer and a first conductivity type work function adjustment layer on the inner wall of the second groove, and filling the electrode material, wherein the second gate dielectric layer comprises a high dielectric constant material; and

[0029] A planarization process is performed to expose the upper surface of the interlayer dielectric layer, the remaining conductive material in the second groove and the first conductive type work function adjustment layer form the gate of the second HKMG transistor, and the source and drain regions on both sides of the second groove are the source and drain regions of the second HKMG transistor.

[0030] In the semiconductor device and the method for manufacturing the semiconductor device provided by the present invention, a first HKMG transistor having a first threshold voltage forms a first storage unit, and a second HKMG transistor having a second threshold voltage forms a second storage unit. By utilizing the difference between the first threshold voltage and the second threshold voltage, the first storage unit and the second storage unit can form different conduction states to achieve 0 / 1 state readout. The manufacturing of the first HKMG transistor and the second HKMG transistor is compatible with the HKMG process and can be formed together with other devices of the HKMG process platform, which helps to improve the integration density of the semiconductor device and reduce the process difficulty. Moreover, the first HKMG transistor and the second HKMG transistor do not use a floating gate structure, and the operating voltage is low, which can be compatible with the process of low-voltage devices (such as logic devices). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 2 It is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention.

[0033] Figure 3 1 is a schematic plan view of a first storage unit and a second storage unit in one embodiment of the present invention.

[0034] Figure 4 4 is a circuit diagram of a first storage unit and a second storage unit in one embodiment of the present invention.

[0035] Figure 5 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0036] FIG. 6A to FIG. 6E It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The semiconductor device and the manufacturing method of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the drawings in the specification are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0038] The following first refers to Figures 1 to 4 A semiconductor device according to an embodiment of the present invention is described.

[0039] Reference Figure 1 and Figure 2 In an embodiment of the present invention, the semiconductor device includes a substrate 100, and the substrate 100 includes a first conductive type doped region.

[0040] The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or may be other substrates known to those skilled in the art for carrying semiconductor devices. In the following description, the substrate 100 is, for example, a silicon substrate. Certain doping ions may be implanted into the substrate 100 according to design requirements to adjust electrical parameters, and an isolation structure (e.g., shallow trench isolation (STI) and / or deep trench isolation (DTI)) may be formed in the substrate 100.

[0041] The substrate 100 may have a first conductivity type doping or a second conductivity type doping. In one embodiment, the first conductivity type doping region is formed by the substrate 100 having the first conductivity type doping. However, the first conductivity type doping region may also be formed by a well region (such as Figure 1 and Figure 2 The P-well (PW) shown is formed.

[0042] like Figure 1 and Figure 2 As shown, the semiconductor device further includes at least one first HKMG transistor 10 and at least one second HKMG transistor 20, wherein the first HKMG transistor 10 has a first threshold voltage (Vth1), and the second HKMG transistor 20 has a second threshold voltage (Vth2). "HKMG" indicates that the first HKMG transistor 10 and the second HKMG transistor 20 use a gate dielectric layer containing a high dielectric constant material (High k, k represents a dielectric constant) and a metal gate structure.

[0043] The first conductivity type may be P type or N type, where P type is opposite to N type. In the case where the substrate 100 is a silicon substrate, the dopant used to form the N type doping includes, for example, phosphorus (P) or arsenic (As), and the dopant used to form the P type doping includes, for example, boron (B) or boron difluoride (BF2).

[0044] like Figure 1 As shown, in one embodiment, at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 may share the same P-well (i.e., share the same first conductivity type doping region), i.e., at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 are formed on the same P-well surface. In another embodiment, the first HKMG transistor 10 and the second HKMG transistor 20 are formed on different P-well surfaces, respectively.

[0045] The first HKMG transistor 10 and the second HKMG transistor 20 each include a gate and source / drain regions (eg, Figure 1 and Figure 2 A first gate dielectric layer 111 may be provided between the gate of the first HKMG transistor 10 and the substrate 100, and a second gate dielectric layer 113 may be provided between the gate of the second HKMG transistor 20 and the substrate 100. The first gate dielectric layer 111 and the second gate dielectric layer 113 may include, for example, a high dielectric constant material. The dielectric constant of the high dielectric constant material is, for example, greater than the dielectric constant of silicon oxide. The high dielectric constant material may include, for example, at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Si3N4, TiO2 and nitride oxide.

[0046] like Figure 1 As shown, in one embodiment, at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 share the same source and drain region. As an example, the first HKMG transistor 10 and the second HKMG transistor 20 share a drain region. However, the present invention is not limited thereto. Figure 2 As shown, in some other embodiments, the source and drain regions of at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 are not shared, and are isolated by a shallow trench isolation (STI) structure.

[0047] The conductivity type of the source and drain regions of the first HKMG transistor 10 and the second HKMG transistor 20 is opposite to that of the first conductivity type doped region, that is, the second conductivity type. Figure 1 and Figure 2 As shown, taking the first conductivity type as P type and the second conductivity type as N type as an example, the first HKMG transistor 10 and the second HKMG transistor 20 are N-channel transistors, and the source and drain regions are N-type doped. In another embodiment, the first conductivity type is N type and the second conductivity type is P type, the first HKMG transistor 10 and the second HKMG transistor 20 are P-channel transistors, and the source and drain regions are P-type doped.

[0048] In the embodiment of the present invention, the gate conductivity types of the first HKMG transistor 10 and the second HKMG transistor 20 are different. Figure 1 and Figure 2 The gate of the second HKMG transistor 20 (denoted as “NMG”) is, for example, an N-type. Figure 1 and Figure 2Expressed as "PMG") is, for example, of the P type. As an example, the gate of the first HKMG transistor 10 may include an N-type work function adjustment layer and an electrode material layer stacked on the N-type work function adjustment layer, and the gate of the second HKMG transistor 20 may include a P-type work function adjustment layer and an electrode material layer stacked on the P-type work function adjustment layer. By selecting the N-type work function adjustment layer and the P-type work function adjustment layer, the gate conduction types and work functions of the first HKMG transistor 10 and the second HKMG transistor 20 can be made different, so that the threshold voltages are different. The N-type work function adjustment layer is, for example, TiAl, the P-type work function adjustment layer is, for example, TiN, and the electrode material layer includes, for example, Al.

[0049] In this embodiment, the gate of the second HKMG transistor 20 formed on the surface of the first conductive type doped region is of the second conductive type, the same as the conductive type of the first conductive type doped region, and the second threshold voltage (Vth2) of the second HKMG transistor 20 is greater than the first threshold voltage (Vth1) of the first HKMG transistor 10, that is, Vth1 < Vth2. As an example, the difference between the first threshold voltage and the second threshold voltage is (1 ± x)V, where x is a value greater than 0 and less than 1, that is, the difference between the first threshold voltage and the second threshold voltage is, for example, about 1V.

[0050] In the embodiment of the present invention, by using the threshold voltage difference between the first HKMG transistor 10 and the second HKMG transistor 20, the first storage unit is formed by the first HKMG transistor 10, and the second storage unit is formed by the second HKMG transistor 20, and the ROM (Read Only Memory) function can be realized. The first storage unit and the second storage unit can form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, so as to realize the readout of the 0 / 1 state (referring to the binary symbols 0 and 1).

[0051] Refer to Figure 3 and Figure 4In one embodiment, the drain terminal (D) of the first HKMG transistor 10 and the second HKMG transistor 20 are shared and the gates are connected, so that the drain terminal voltage and the gate voltage are the same, and the gate voltage and the drain terminal voltage are both VDD, for example, and VDD is 0.8V to 1.2V, for example. The first HKMG transistor 10 and the second HKMG transistor 20 jointly form a storage bit; wherein the first storage unit formed by the first HKMG transistor 10 has a first state reading point N1 (i.e., Node1) located at the source terminal (S) of the first HKMG transistor 10, and the first state reading point N1 is used to read 1, for example, and the second storage unit formed by the second HKMG transistor 20 has a second state reading point N2 (i.e., Node2) located at the source terminal of the second HKMG transistor 20, and the second state reading point N2 is used to read 0, for example, and the corresponding reading point can be selected as needed. Since the first threshold voltage (Vth1) of the first HKMG transistor 10 is lower than the second threshold voltage (Vth2) of the second HKMG transistor 20, when the gate voltage VDD is greater than Vth1 and less than Vth2, the first HKMG transistor 10 is turned on and the second HKMG transistor 20 is not turned on. By detecting the source current or voltage of the first HKMG transistor 10, a first state signal (for example, 1) can be obtained. When the gate voltage VDD is greater than Vth2, both the first HKMG transistor 10 and the second HKMG transistor 20 are turned on. By detecting the source current or voltage of the second HKMG transistor 20, a second state signal (for example, 0) can be obtained.

[0052] However, the present invention is not limited to Figure 3 and Figure 4 In the case shown, for example, in another embodiment, the source and drain of the first HKMG transistor 10 and the second HKMG transistor 20 are independently controlled, and the gates can also be independently controlled. When reading the signal, the drain and gate of the first HKMG transistor 10 and the second HKMG transistor 20 can be connected to VDD, and the source voltage or current of the first HKMG transistor 10 and the second HKMG transistor 20 can be detected respectively under the corresponding gate voltage to obtain the corresponding state signal.

[0053] The first HKMG transistor 10 and the second HKMG transistor 20 can be formed by HKMG process, and thus are compatible with HKMG process, and no additional process steps need to be introduced, so they can be integrated with other devices made by HKMG process platform on the same substrate 100. As an example, in one embodiment, in addition to the first HKMG transistor 10 and the second HKMG transistor 20, the semiconductor device may also include a logic transistor formed on the surface of the substrate 100, and the logic transistor may, for example, use a HKMG gate structure, but is not limited thereto, and the logic transistor may also use a non-HKMG gate structure, and the non-HKMG gate structure may, for example, include a gate oxide layer and a polysilicon gate formed on the gate oxide layer. In addition, the first HKMG transistor 10 and the second HKMG transistor 20 do not use a floating gate type gate structure, and the operating voltage is low, which can be compatible with low-voltage device processes. The semiconductor device is, for example, a semiconductor chip or module. Due to the strong compatibility, it helps to improve the integration density of semiconductor devices and reduce the process difficulty.

[0054] An embodiment of the present invention further relates to a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device described in the above embodiment.

[0055] Reference Figure 5 and Fig. 6A According to an embodiment of the present invention, first, step S1 is performed to provide a substrate 100, wherein the substrate 100 includes a first conductive type doping region. The substrate 100 is, for example, a silicon substrate. The substrate 100 may have a first conductive type doping region or a second conductive type doping region. The first conductive type doping region may be formed by the substrate 100, or the first conductive type doping region may be formed by a well region formed in the substrate 100. As an example, the first conductive type is a P type, and the first conductive type doping region is a P well (PW) formed in the substrate 100.

[0056] According to an embodiment of the present invention, step S2 is then performed to form at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductive type doped region, so that the gate and source-drain region of the first HKMG transistor are of the second conductive type, and the gate of the second HKMG transistor has the first conductive type and the source-drain region has the second conductive type, wherein the first HKMG transistor has a first threshold voltage and forms a first storage unit, the second HKMG transistor has a second threshold voltage and forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state readout.

[0057] As an example, step S2 may include the following process.

[0058] First, refer to Fig. 6A A first dummy gate DG1 and a second dummy gate DG2 are formed on the surface of the corresponding first conductive type doping region, and a sidewall SP and a source and drain region (such as Fig. 6A As an example, the first conductive type doped region is a P-well (PW), and the first dummy gate DG1 and the second dummy gate DG2 are formed on the same P-well surface. The first dummy gate DG1 and the second dummy gate DG2 are, for example, polysilicon, and an oxide layer may be formed between them and the substrate 100.

[0059] Afterwards, refer to Figure 6B The second dummy gate DG2 is protected by a mask (not shown), and the first dummy gate DG1 is removed by etching to form a first groove T1 at the position of the first dummy gate DG1. The oxide layer under the first dummy gate DG1 can also be removed.

[0060] Next, refer to Figure 6C , a first gate dielectric layer 111 and a second conductive type work function adjustment layer 113 are formed on the inner wall of the first groove T1, and an electrode material 115 is filled, and then a planarization process is performed to expose the upper surface of the interlayer dielectric layer 120. The remaining electrode material 115 and the second conductive type work function adjustment layer 113 in the first groove T1 form the gate of the first HKMG transistor 10, and the source and drain regions on both sides of the gate are the source and drain regions of the first HKMG transistor 10. The gate of the first HKMG transistor 10 and the source and drain regions on both sides thereof have a second conductive type (such as N type), Figure 6C The gate of the first HKMG transistor 10 is represented by "NMG". The first gate dielectric layer 111 includes a high dielectric constant material. The second conductive type work function adjustment layer 113 is, for example, an N-type work function adjustment layer, for example, TiAl. The electrode material 115 includes, for example, Al.

[0061] Afterwards, refer to Fig.6D , a mask (not shown) is used to protect the gate of the first HKMG transistor 10, and the second dummy gate DG2 is removed by etching, and a second groove T2 is formed at the position of the second dummy gate DG2. The oxide layer under the second dummy gate DG2 can also be removed.

[0062] Next, refer to Fig. 6E, a second gate dielectric layer 112 and a first conductive type work function adjustment layer 114 are formed on the inner wall of the second groove T2, and an electrode material 116 is filled, and then a planarization process is performed to expose the upper surface of the interlayer dielectric layer 120. The remaining conductive material in the second groove T2 and the first conductive type work function adjustment layer 114 form the gate of the second HKMG transistor 20, and the source and drain regions on both sides of the gate are the source and drain regions of the second HKMG transistor 20. The gate of the second HKMG transistor 20 has a first conductive type (such as a P type), Fig. 6E In the figure, PMG is used to represent that the source and drain regions of the second HKMG transistor 20 have the second conductivity type. The second gate dielectric layer 112 includes a high dielectric constant material. The first conductivity type work function adjustment layer 114 is, for example, a P-type work function adjustment layer, such as TiN. The electrode material 116 includes, for example, Al.

[0063] The gate conductivity types of the first HKMG transistor 10 and the second HKMG transistor 20 formed by the above process are different, and thus the work functions are also different. The first HKMG transistor 10 and the second HKMG transistor 20 have different threshold voltages, and form a first storage unit and a second storage unit respectively. By using the difference in threshold voltages of the first HKMG transistor 10 and the second HKMG transistor 20, the first storage unit and the second storage unit can form different conduction states, thereby realizing 0 / 1 state readout. In the embodiment of the present invention, the fabrication of the first HKMG transistor 10 and the second HKMG transistor 20 is compatible with the HKMG process, and the first HKMG transistor 10 and the second HKMG transistor 20 can be formed together with other devices of the HKMG process platform, which helps to improve the integration density of semiconductor devices and reduce the process difficulty. Moreover, the first HKMG transistor 10 and the second HKMG transistor 20 do not use a floating gate structure, and the operating voltage is low, which can be compatible with the process of low-voltage devices (such as logic devices).

[0064] It should be noted that the embodiments in this specification are described in a progressive manner, and each part focuses on the differences from other embodiments. The relevant parts can be understood by reference.

[0065] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a first conductivity type doped region; At least one first HKMG transistor with a first threshold voltage is formed on the surface of the corresponding first conductivity type doped region, and the gate and source and drain regions of the first HKMG transistor are of the second conductivity type; as well as At least one second HKMG transistor with a second threshold voltage is formed on the surface of the corresponding first conductivity type doped region, the gate of the second HKMG transistor has the first conductivity type and the source and drain regions have the second conductivity type; The first HKMG transistor forms a first storage unit, the second HKMG transistor forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage to achieve 0 / 1 state readout.

2. The semiconductor device according to claim 1, wherein The substrate has a first conductivity type doping or a second conductivity type doping, and the first conductivity type doping region is formed by the substrate or by a well region formed in the substrate.

3. The semiconductor device according to claim 1, wherein The difference between the first threshold voltage and the second threshold voltage is (1±x)V, where x is a value greater than 0 and less than 1.

4. The semiconductor device according to claim 1, wherein The first threshold voltage is lower than the second threshold voltage.

5. The semiconductor device according to claim 1, wherein: The gate of the first HKMG transistor includes a second conductivity type work function adjustment layer and an electrode material layer stacked on the second conductivity type work function adjustment layer.

6. The semiconductor device according to claim 1, wherein: The gate of the second HKMG transistor includes a first conductivity type work function adjustment layer and an electrode material layer stacked on the first conductivity type work function adjustment layer.

7. The semiconductor device according to claim 1, wherein: At least one pair of adjacent first HKMG transistors and second HKMG transistors shares the same first conductivity type doping region.

8. The semiconductor device according to claim 1, wherein At least one pair of adjacent first HKMG transistors and second HKMG transistors share the same source and drain region; or at least one pair of adjacent first HKMG transistors and second HKMG transistors do not share the same source and drain region.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The invention also includes a logic transistor formed on the surface of the substrate, wherein the logic transistor has a HKMG gate structure.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a first conductivity type doped region; as well as At least one first HKMG transistor and at least one second HKMG transistor are formed on the surface of the first conductive type doped region, so that the gate and source-drain region of the first HKMG transistor are of the second conductive type, and the gate of the second HKMG transistor has the first conductive type and the source-drain region has the second conductive type, wherein the first HKMG transistor has a first threshold voltage and forms a first storage unit, and the second HKMG transistor has a second threshold voltage and forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, so as to realize 0 / 1 state readout.

11. The method according to claim 10, characterized in that: Forming at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductive type doped region includes: A first dummy gate and a second dummy gate are formed on the surface of the first conductive type doped region respectively, and sidewalls, corresponding source and drain regions, and an interlayer dielectric layer are formed on both sides of the first dummy gate and the second dummy gate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first dummy gate and the second dummy gate; removing the first dummy gate and forming a first groove at the position of the first dummy gate; Forming a first gate dielectric layer and a second conductive type work function adjustment layer on the inner wall of the first groove, and filling the inner wall with electrode material, wherein the first gate dielectric layer includes a high dielectric constant material; Performing a planarization process to expose the upper surface of the interlayer dielectric layer, the remaining conductive material in the first groove and the second conductive type work function adjustment layer form the gate of the first HKMG transistor, and the source and drain regions on both sides of the first groove are the source and drain regions of the first HKMG transistor; removing the second dummy gate and forming a second groove at the position of the second dummy gate; forming a second gate dielectric layer and a first conductivity type work function adjustment layer on the inner wall of the second groove, and filling the electrode material, wherein the second gate dielectric layer comprises a high dielectric constant material; and A planarization process is performed to expose the upper surface of the interlayer dielectric layer, the remaining conductive material in the second groove and the first conductive type work function adjustment layer form the gate of the second HKMG transistor, and the source and drain regions on both sides of the second groove are the source and drain regions of the second HKMG transistor.

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