Gate-controlled enhanced asymmetric bidirectional thyristor electrostatic discharge protection device and its fabrication method

Abstract

This invention discloses a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method; a first NBL region is provided in the substrate P-Sub; a first annular HVNW region and first to second P-Epi regions are provided above the NBL region; a first to fourth PW region and a first to third NW region are provided above the HVNW region and the P-Epi region; a first P+ implantation region is provided in the first PW region; a first strip polysilicon gate, a second P+ implantation region, a second strip polysilicon gate, a first N+ implantation region and a third P+ implantation region are provided in the second PW region; a second N+ implantation region is provided in the second NW region; a third strip polysilicon gate, a fourth P+ implantation region, a fourth strip polysilicon gate, a third N+ implantation region and a fifth P+ implantation region are provided in the third PW region; a fourth N+ implantation region is provided in the third NW region; and a sixth P+ implantation region is provided in the fourth PW region. This invention constitutes a gate-controlled enhanced asymmetric bidirectional thyristor, in which a polysilicon gate is embedded in the N+ injection region, enhancing the gate control effect and reducing the emission efficiency of parasitic NPN, thereby improving the sustaining voltage.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection for semiconductor devices, and particularly to a gate-controlled enhancement-type asymmetric bidirectional thyristor ESD protection device and its fabrication method. Background Technology

[0002] With continuous societal progress and advancements in science and technology, the development of integrated circuits (ICs) has progressed from submicron to deep submicron and has entered the nanometer scale. As semiconductor processes continue to evolve, chip sizes are shrinking, and the number of transistors that can be integrated per unit chip area is increasing, making chips more sensitive to electrostatic discharge (ESD). The accumulation of electrostatic charge is ubiquitous and widespread in all aspects of daily life. Therefore, more and more IC designers are focusing on ESD protection for semiconductors. Data shows that ESD-induced failures in integrated circuits and microelectronic products cause hundreds of billions of dollars in economic losses annually, reflecting the importance of ESD protection in electronic product design. This problem is particularly pronounced in high-voltage applications, where high operating voltages present a series of challenges for ESD design, requiring ESD protection devices to have fast turn-on speeds, high holding voltages, and high failure currents.

[0003] Currently, traditional silicon controlled rectifiers (SCRs) suffer from numerous problems in practical applications. When an ESD pulse reaches the anode of a traditional SCR, the device forms a positive feedback loop composed of parasitic PNP and NPN transistors under the avalanche effect to release electrostatic current, resulting in a low sustaining voltage. However, in high-voltage applications, due to the high operating voltage of the chip, the excessively low sustaining voltage of a traditional SCR can easily cause latch-up, potentially burning out the entire chip. Furthermore, because the reverse path of a traditional SCR is equivalent to a forward-biased diode, it cannot be used in bidirectional applications. These drawbacks prevent traditional SCRs from effectively protecting the internal core circuitry of the chip.

[0004] The structure and equivalent circuit of a traditional silicon controlled rectifier (SCR) are as follows: Figure 1 As shown. When the anode of the device faces an ESD impact, an avalanche breakdown effect occurs between its anode NW and cathode PW, generating a large number of avalanche carriers that enter the cathode PW of the device and cross the parasitic resistance R. P1A voltage drop is generated, thus turning on the parasitic NPN transistor composed of cathode N+, PW, and NW. When NW and PW are reverse biased, the parasitic PNP transistor composed of anode P+, ​​anode PW, and cathode PW operates in the saturation region. When the NPN and PNP parasitic transistors enter the saturation region, the conventional SCR is fully turned on, forming a low-resistance PNPN path to release electrostatic current, at which point the thyristor path is fully turned on. At this time, the conventional SCR exhibits negative resistance, resulting in a phenomenon where the current continuously increases while the voltage decreases. However, the sustaining voltage of the device is usually low. When the normal operating voltage of the protected chip is higher than the sustaining voltage of the device, a latch-up effect can easily occur, burning out the chip. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention, based on research on asymmetric bidirectional thyristors, provides a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic discharge protection device with simple structure, high failure current, and high sustaining voltage, and also provides its fabrication method.

[0006] The technical solution of the present invention to solve the above problems is: a gate-controlled enhancement type asymmetric bidirectional thyristor electrostatic discharge (ESD) device, characterized in that: it includes a substrate P-Sub; the substrate P-Sub has a first NBL region; and a first annular HVNW region and a first to a second P-Epi region are provided above the NBL region. The HVNW region and P-Epi are arranged from bottom to top and from left to right as follows: first PW region, first NW region, second PW region, second NW region, third PW region, third NW region, fourth PW region, first field oxygen isolation region, first P+ implantation region, second field oxygen isolation region, first multi-strip polysilicon gate, second P+ implantation region, second strip polysilicon gate, first N+ implantation region, third P+ implantation region, third field oxygen isolation region, second N+ implantation region, fourth field oxygen isolation region, third strip polysilicon gate, fourth P+ implantation region, fourth strip polysilicon gate, third N+ implantation region, fifth P+ implantation region, fifth field oxygen isolation region, fourth N+ implantation region, sixth field oxygen isolation region, sixth P+ implantation region, and seventh field oxygen isolation region. The first P+ implantation region is located in the first PW region; the first strip-shaped polysilicon gate, the second P+ implantation region, the second strip-shaped polysilicon gate, the first N+ implantation region, and the third P+ implantation region are located in the second PW region; the second N+ implantation region is located in the second NW region; the third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth strip-shaped polysilicon gate, the third N+ implantation region, and the fifth P+ implantation region are located in the third PW region; the fourth N+ implantation region is located in the third NW region; and the sixth P+ implantation region is located in the fourth PW region. The first P+ implantation region, the first strip-shaped polysilicon gate, the second P+ implantation region, the second strip-shaped polysilicon gate, the first N+ implantation region, and the sixth P+ implantation region are connected as the cathode of the device; the third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth strip-shaped polysilicon gate, and the third N+ implantation region are connected as the anode of the device.

[0007] In the aforementioned gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device, when ESD stress reaches the anode and the cathode is grounded, avalanche breakdown occurs in the second NW region, the first HVNW region, the second PW region, and the first P-Epi region. This immediately activates the parasitic PNP1 transistor formed by the second PW region, the first P-Epi region, the second NW region, the first HVNW region, the third PW region, and the second P-Epi region; and the parasitic NPN1 transistor formed by the first N+ injection region, the second PW region, the first P-Epi region, the first HVNW region, and the second NW region. The base region of the NPN1 transistor is connected to the parasitic resistor R. P1 It is connected to the second P+ injection region and led out to the cathode from the second P+ injection region. When ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW region, the first HVNW region, the third PW region, and the second P-Epi region undergo avalanche breakdown, and then conduction occurs in the parasitic PNP2 transistor formed by the third PW region, the second P-Epi region, the third NW region, the first HVNW region, and the fourth PW region; the parasitic NPN2 transistor formed by the third N+ injection region, the third PW region, the second P-Epi region, the third NW region, and the first HVNW region; the base region of the NPN2 transistor is connected to the parasitic resistor R. P2 The electrode is connected to the fourth P+ injection region and led out to the anode from the fourth P+ injection region. This forms a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device. By segmenting the first and third N+ injection regions and embedding a polysilicon gate, a strip-shaped polysilicon gate is formed, thereby enhancing the gate control effect. The gate electric field drives the current to a deeper path, improving the robustness of the device. In addition, the segmentation of the emitter N+ injection region reduces the emitter efficiency of the parasitic NPN and improves the sustaining voltage of the device.

[0008] A method for fabricating a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device includes the following steps:

[0009] Step 1: Form the NBL region, P-Epi region, and ring-shaped HVNW region in the P-Sub substrate;

[0010] Step 2: Form the first to seventh field oxygen isolation regions on the P-Sub substrate using photolithography;

[0011] Step 3: Using photolithography, the first to third NW regions are sequentially formed in the first HVNW region;

[0012] Step 4: Using photolithography, the first to fourth PW regions are sequentially formed in P-Sub and P-Epi;

[0013] Step 5: Form the first strip polysilicon gate and the second strip polysilicon gate in the second PW region, and form the third strip polysilicon gate and the fourth strip polysilicon gate in the third PW region.

[0014] Step 6: Using photolithography, a first P+ implantation region is formed in the first PW region, a second and a third P+ implantation region are formed in the second PW region, a fourth and a fifth P+ implantation region are formed in the third PW region, and a sixth P+ implantation region is formed in the fourth PW region.

[0015] Step 7: By photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region is formed in the second NW region, a third N+ implantation region is formed in the third PW region, and a fourth N+ implantation region is formed in the third NW region.

[0016] The technical solution of the present invention to solve the above problems is:

[0017] 1. This invention constitutes a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device. By segmenting the emitter N+ injection region of the forward and reverse thyristor paths, the area of ​​the emitter N+ injection region and the emission efficiency of the parasitic NPN transistor are reduced, thereby suppressing the positive feedback effect of the thyristor. This method does not require additional chip area or the introduction of special layers, and is fully compatible with traditional CMOS processes, effectively improving the device's holding voltage.

[0018] 2. This invention enhances the gate's control over the SCR current by segmenting the N+ injection regions of the emitters of the forward and reverse SCRs and embedding polysilicon gates. This concentrates the surface parasitic current path with the main SCR current path, thereby extending the SCR current path and effectively improving the device's sustaining voltage. Furthermore, the presence of an electric field direction below the gate, aligned with the current path, allows the SCR current to flow into a deeper path, increasing the current release capacity per unit area and effectively improving the device's robustness and failure current.

[0019] 3. The process used in this invention is simple, requiring no additional special layers, and the implementation is straightforward. Segmenting the emitter N+ injection region and embedding the gate can be achieved using EDA software without violating the design rules in the process documentation. Furthermore, this structure allows for modulation of the emitter N+ injection region segmentation ratio according to different voltage domain requirements, thereby meeting the voltage maintenance requirements and effectively protecting the core chip from external electrostatic discharge (ESD) shocks. Attached Figure Description

[0020] Figure 1 The diagram shows a cross-sectional view and an equivalent circuit diagram of a traditional silicon controlled rectifier (SCR) structure.

[0021] Figure 2This is a cross-sectional view and circuit connection diagram of the gate-controlled effect enhanced asymmetric bidirectional thyristor structure in an embodiment of the present invention.

[0022] Figure 3 This is a three-dimensional structural diagram of the gate-controlled effect enhanced asymmetric bidirectional thyristor structure in an embodiment of the present invention.

[0023] Figure 4 This is the equivalent circuit of the gate-controlled effect enhanced asymmetric bidirectional thyristor structure used for ESD protection in the embodiments of the present invention, i.e., the ESD current release path.

[0024] Figure 5 This is a top view of the gate-controlled effect enhanced asymmetric bidirectional thyristor structure in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] like Figures 1-5 As shown, a gate-controlled effect enhanced asymmetric bidirectional thyristor structure is characterized by:

[0027] The substrate includes a P-Sub 101; a first NBL region 201 is provided in the P-Sub 101; a first annular HVNW region 301, a first P-Epi region 401, and a second P-Epi region 402 are provided above the NBL region; a first PW region 501, a second PW region 502, a third PW region 503, a fourth PW region 504, a first NW region 601, a second NW region 602, and a third NW region 603 are provided above the HVNW region and the P-Epi region; a first P+ implantation region 701 is provided in the first PW region 501; and a first P+ implantation region 701 is provided in the second PW region 502. From left to right, the following structures are arranged in sequence: a first strip polysilicon gate 1001, a second P+ implantation region 702, a first N+ implantation region 801, and a third P+ implantation region 703; a second N+ implantation region 802 is provided in the second NW region 602; from left to right, the following structures are arranged in the third PW region 503: a third strip polysilicon gate 1003, a fourth P+ implantation region 704, a fourth strip polysilicon gate 1003, and a third N+ implantation region 803; a fourth N+ implantation region 804 is provided in the third NW region 603; and a sixth P+ implantation region 706 is provided in the fourth PW region 504.

[0028] The first P+ implantation region 701 is connected to the first upper metal layer 101 of the upper metal layer through a contact hole. The first strip polysilicon gate 1001 is connected to the second upper metal layer 102 of the upper metal layer through a contact hole. The second P+ implantation region 702 is connected to the third upper metal layer 103 of the upper metal layer through a contact hole. The second strip polysilicon gate 1002 is connected to the fourth upper metal layer 104 of the upper metal layer through a contact hole. The first N+ implantation region 801 is connected to the first upper metal layer 104 of the upper metal layer through a contact hole. The hole is connected to the fifth upper metal layer 105 of the upper metal layer. The sixth P+ injection region 706 is connected to the tenth upper metal layer 110 of the upper metal layer through the contact hole. The first upper metal layer 101, the second upper metal layer 102, the third upper metal layer 103, the fourth upper metal layer 104, the fifth upper metal layer 105, and the tenth upper metal layer 110 of the upper metal layer are connected to the first upper metal layer 301 of the lower metal layer through the contact hole 1201, and are used as the anode of the device.

[0029] The third strip-shaped polysilicon gate 1003 is connected to the sixth upper metal layer 106 of the upper metal layer through a contact hole. The fourth P+ implantation region 803 is connected to the seventh upper metal layer 107 of the upper metal layer through a contact hole. The fourth strip-shaped polysilicon gate 1004 is connected to the eighth upper metal layer 108 of the upper metal layer through a contact hole. The third N+ implantation region 803 is connected to the ninth upper metal layer 109 of the upper metal layer through a contact hole. The sixth upper metal layer 106, the seventh upper metal layer 107, the eighth upper metal layer 108, and the ninth upper metal layer 109 of the upper metal layer are connected to the second upper metal layer 302 of the lower metal layer through the contact hole 1202, and serve as the cathode of the device.

[0030] A method for fabricating a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device includes the following steps:

[0031] Step 1: Form a first NBL region 201, a first annular HVNW region 301, a first P-Epi region 401, and a second P-Epi region 402 in the substrate P-Sub101. Specifically:

[0032] The first NBL region 201, the first annular HVNW region 301, the first P-Epi region 401, and the second P-Epi region 402 are fabricated on the surface of the substrate P-Sub101. A silicon dioxide thin film is then formed by thermal oxidation to mitigate stress damage caused by silicon nitride formation in subsequent process steps. A silicon nitride layer is deposited using LPCVD technology as a stop layer for CMP in subsequent process steps.

[0033] Photoresist is uniformly applied to the wafer, and then exposed and developed. This step defines shallow trench isolation (STI). Silicon nitride, silicon dioxide, and the isolation trenches are then etched to remove the photoresist layer. A layer of silicon dioxide is deposited using LPCVD, followed by chemical mechanical polishing until the silicon nitride thin film layer is reached. Finally, the silicon nitride thin film layer is removed using hot phosphoric acid wet etching.

[0034] Step 2: Using photolithography, form the first field oxygen isolation region 901, the second field oxygen isolation region 902, the third field oxygen isolation region 903, the fourth field oxygen isolation region 904, the fifth field oxygen isolation region 905, the sixth field oxygen isolation region 906, and the seventh field oxygen isolation region 907 on the substrate P-Sub101. Specifically:

[0035] Using LOCOS isolation technology, a silicon dioxide thin film is grown using thermal oxidation as a buffer layer. Then, silicon nitride is deposited using LPCVD technology. Photoresist is applied to the wafer, and photolithography is used to define the first LOCOS isolation region 901, the second LOCOS isolation region 902, the third LOCOS isolation region 903, the fourth LOCOS isolation region 904, the fifth LOCOS isolation region 905, the sixth LOCOS isolation region 906, and the seventh LOCOS isolation region 907. Reactive ions then etch away the silicon nitride in the first LOCOS isolation region 901, the second LOCOS isolation region 902, the third LOCOS isolation region 903, the fourth LOCOS isolation region 904, the fifth LOCOS isolation region 905, the sixth LOCOS isolation region 906, the seventh LOCOS isolation region 907, the eighth LOCOS isolation region 908, and the ninth LOCOS isolation region 909. Field implantation is then performed to prevent field activation.

[0036] Step 3: Using photolithography, a first PW region 501 and a fourth PW region 504 are formed on the substrate P-Sub101. A second PW region 502 and a third PW region 503 are sequentially formed in the first P-Epi region 401 and the second P-Epi region 402. A first NW region 601, a second NW region 602, and a third NW region 603 are sequentially formed in the first annular HVNW301. Specifically:

[0037] Photoresist is applied to the wafer to define the first PW region 501, the second PW region 502, the third PW region 503, and the fourth PW region 504. Then, high-energy boron ions are implanted to form lightly doped P-type regions, and the photoresist layer is removed.

[0038] Photoresist is applied to the wafer to define the first NW region 601, the second NW region 602, and the third NW region 603. Then, high-energy phosphorus ion implantation is performed to form local N-type regions, and the photoresist layer is removed.

[0039] Annealing is performed on the first PW region 501, the second PW region 502, the third PW region 503, the fourth PW region 504, the first NW region 601, the second NW region 602, and the third NW region 603 to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate the further diffusion of impurities using the RTP process.

[0040] Step 4: A first strip-shaped polysilicon gate 1001 and a second strip-shaped polysilicon gate 1002 are formed in the second P-Well region 502, and a third strip-shaped polysilicon gate 1003 and a fourth strip-shaped polysilicon gate 1004 are formed in the third P-Well region 503. Specifically:

[0041] The growth of a sacrificial oxide layer is used to capture defects on the silicon surface. Gate oxide layer growth, serving as the gate insulating layer for the transistor, involves depositing the first strip-shaped polysilicon gate 1001, the second strip-shaped polysilicon gate 1002, the third strip-shaped polysilicon gate 1003, and the fourth strip-shaped polysilicon gate 1004 using LPCVD. Photoresist is then used for molding, followed by polysilicon etching, requiring precise shaping of the polysilicon from the photoresist, and removal of the photoresist layer. Polysilicon oxidation serves as a buffer to isolate the polysilicon from the silicon nitride formed in subsequent steps. A layer of silicon nitride is deposited using LPCVD, followed by silicon nitride etching, leaving isolation sidewalls, and precise ion implantation to locate the transistor source and drain regions.

[0042] Step 5: Using photolithography, a first P+ implantation region 701 is formed in the first PW region 501, a second P+ implantation region 702 and a third P+ implantation region 703 are formed in the second PW region 502, a fourth P+ implantation region 704 and a fifth P+ implantation region 705 are formed in the third PW region 503, and a sixth P+ implantation region 706 is formed in the fourth PW region 504. Specifically:

[0043] Photoresist formation is used to control ion implantation, shallow-depth, heavily doped boron ion implantation, removal of photoresist layer, and formation of the first P+ implantation region 701, the second P+ implantation region 702, the third P+ implantation region 703, the fourth P+ implantation region 704, the fifth P+ implantation region 705, and the sixth P+ implantation region 706.

[0044] Step Six: Using photolithography, a first N+ implantation region 801 is formed in the second PW region 502, a second N+ implantation region 802 is formed in the second NW region 602, a third N+ implantation region 803 is formed in the third PW region 503, and a fourth N+ implantation region 804 is formed in the third NW region 603. Specifically:

[0045] Photoresist formation is used to control ion implantation. Shallow-depth, heavily doped arsenic ion implantation removes the photoresist layer, forming the first N+ implantation region 801, the second N+ implantation region 802, the third N+ implantation region 803, and the fourth N+ implantation region 804.

[0046] This invention constitutes an asymmetric bidirectional thyristor structure with enhanced gate control effect, which can reduce emitter efficiency and enhance gate control effect by segmenting the N+ injection of the emitter and embedding it into the gate, such as... Figure 2 and Figure 3 As shown. This forms a gate-controlled enhancement-type asymmetric bidirectional thyristor rectifier, suppressing the positive feedback effect of the thyristor and achieving the purpose of improving the device's holding voltage; since there is an electric field direction below the gate in the same direction as the current path, the SCR current flows to a deeper path, improving the device's robustness and failure current. This invention uses a gate-controlled enhancement-type asymmetric bidirectional thyristor structure, as shown. Figure 4 and Figure 5 As shown. Specifically:

[0047] When ESD stress reaches the anode of the device and the cathode is grounded, avalanche breakdown occurs between the second NW region 602, the first HVNW region 301, the second PW region 502, and the first P-Epi region 401. This immediately activates the parasitic PNP1 transistor formed by the second PW region 502, the first P-Epi region 401, the second NW region 602, the first HVNW region 301, the third PW region 503, and the second P-Epi region 402; and the parasitic NPN1 transistor formed by the first N+ injection region 801, the second PW region 502, the first P-Epi region 401, the first HVNW region 301, and the second NW region 602. The base region of the NPN1 transistor is connected to the parasitic resistor R. P1 It is connected to the second P+ injection region 702 and led out to the cathode from the second P+ injection region 702. When ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW region 603, the first HVNW region 301, the third PW region 503, and the second P-Epi region 402 undergo avalanche breakdown, and then conduct the parasitic PNP2 transistor composed of the third PW region 503, the second P-Epi region 402, the third NW region 603, the first HVNW region 301, and the fourth PW region 504; the parasitic NPN2 transistor composed of the third N+ injection region 803, the third PW region 503, the second P-Epi region 402, the third NW region 603, and the first HVNW region 301; the base region of the NPN2 transistor is connected to the parasitic resistor R. P2The electrode is connected to the fourth P+ injection region 704 and led out to the anode from the fourth P+ injection region 704. This forms a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device. By segmenting the first N+ injection region 801 and the third N+ injection region 803 and embedding a polysilicon gate, a strip-shaped polysilicon gate is formed, thereby enhancing the gate control effect. The gate electric field drives the current to a deeper path, improving the robustness of the device. Furthermore, the segmentation of the emitter N+ reduces the emission efficiency of the parasitic NPN and improves the sustaining voltage of the device.

[0048] In summary, this invention provides a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method. The process is simple and does not require breaking process design rules. The fabricated ESD device is fully compatible with standard CMOS processes, requiring no masks outside of standard processes. This allows the ESD device to have a large holding voltage and a large failure current, effectively protecting the core chip under high voltage operation without latch-up risk, exhibiting high reliability and stability.

Claims

1. A gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that, include: Substrate P-Sub; The substrate P-Sub has a first NBL region; Above the NBL region are a first annular HVNW region, a first P-Epi region, and a second P-Epi region; Above the HVNW region, the first P-Epi region, and the second P-Epi region, from left to right, are sequentially arranged a first PW region, a first NW region, a second PW region, a second NW region, a third PW region, a third NW region, and a fourth PW region; above the substrate P-Sub, from left to right, are sequentially arranged a first field oxygen isolation region, a first P+ implantation region, a second field oxygen isolation region, a second P+ implantation region, a first N+ implantation region, a third P+ implantation region, a third field oxygen isolation region, a second N+ implantation region, a fourth field oxygen isolation region, a fourth P+ implantation region, a third N+ implantation region, a fifth P+ implantation region, a fifth field oxygen isolation region, a fourth N+ implantation region, a sixth field oxygen isolation region, a sixth P+ implantation region, and a seventh field oxygen isolation region; it also includes a first strip-shaped polysilicon gate, a second strip-shaped polysilicon gate, a third strip-shaped polysilicon gate, and a fourth strip-shaped polysilicon gate, wherein the first strip-shaped polysilicon gate is disposed between the second field oxygen isolation region and the second P+ implantation region, and the second... A strip-shaped polysilicon gate is disposed between the second P+ implantation region and the third P+ implantation region. The third strip-shaped polysilicon gate is disposed between the fourth field oxygen isolation region and the fourth P+ implantation region. The fourth strip-shaped polysilicon gate is disposed between the fourth P+ implantation region and the fifth P+ implantation region. The second strip-shaped polysilicon gate is embedded in a segmented first N+ implantation region, and the fourth strip-shaped polysilicon gate is embedded in a segmented third N+ implantation region. The first P+ implantation region is located in the first PW region. The first strip-shaped polysilicon gate, the second P+ implantation region, the second strip-shaped polysilicon gate, the first N+ implantation region, and the third P+ implantation region are located in the second PW region. The second N+ implantation region is located in the second NW region. The third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth strip-shaped polysilicon gate, the third N+ implantation region, and the fifth P+ implantation region are located in the third PW region. The fourth N+ implantation region is located in the third NW region. The sixth P+ implantation region is located in the fourth PW region. The first P+ implantation region, the first strip polysilicon gate, the second P+ implantation region, the second strip polysilicon gate, the first N+ implantation region, and the sixth P+ implantation region are connected to form the cathode of the device; The third strip polysilicon gate, the fourth P+ implantation region, the fourth strip polysilicon gate, and the third N+ implantation region are connected together to serve as the anode of the device.

2. The gate-controlled enhanced asymmetric bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, When ESD stress reaches the anode of the device and the cathode is grounded, avalanche breakdown occurs in the second NW region, the first HVNW region, the second PW region, and the first P-Epi region. This immediately activates the parasitic PNP1 transistor formed by the second PW region, the first P-Epi region, the second NW region, the first HVNW region, the third PW region, and the second P-Epi region; and the parasitic NPN1 transistor formed by the first N+ injection region, the second PW region, the first P-Epi region, the first HVNW region, and the second NW region. The base region of the NPN1 transistor is connected to the second P+ injection region through a parasitic resistor RP1, and is led out from the second P+ injection region. When ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW region, the first HVNW region, the third PW region, and the second P-Epi region undergo avalanche breakdown, and then conduction occurs in the parasitic PNP2 transistor formed by the third PW region, the second P-Epi region, the third NW region, the first HVNW region, and the fourth PW region; the parasitic NPN2 transistor formed by the third N+ injection region, the third PW region, the second P-Epi region, the first HVNW region, and the third NW region; the base region of the NPN2 transistor is connected to the fourth P+ injection region through the parasitic resistor RP2, and led out from the fourth P+ injection region to the anode.

3. The gate-controlled enhanced asymmetric bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, The first P+ implantation region is connected to the first metal layer of the upper metal layer through a contact hole; the first strip polysilicon gate is connected to the second metal layer of the upper metal layer through a contact hole; the second P+ implantation region is connected to the third metal layer of the upper metal layer through a contact hole; the second strip polysilicon gate is connected to the fourth metal layer of the upper metal layer through a contact hole; the first N+ implantation region is connected to the fifth metal layer of the upper metal layer through a contact hole; the sixth P+ implantation region is connected to the tenth metal layer of the upper metal layer through a contact hole; and the first, second, third, fourth, fifth, and tenth metal layers of the upper metal layer are connected to the first metal layer of the lower metal layer through the contact holes, serving as the anode of the device.

4. The gate-controlled enhanced asymmetric bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, The third strip-shaped polysilicon gate is connected to the sixth metal layer of the upper metal layer through a contact hole. The fourth P+ implantation region is connected to the seventh metal layer of the upper metal layer through a contact hole. The fourth strip-shaped polysilicon gate is connected to the eighth metal layer of the upper metal layer through a contact hole. The third N+ implantation region is connected to the ninth metal layer of the upper metal layer through a contact hole. The sixth, seventh, eighth, and ninth metal layers of the upper metal layer are connected to the second metal layer of the lower metal layer through the contact holes, serving as the cathode of the device.

5. A method for manufacturing a gate-controlled enhancement-type asymmetric bidirectional thyristor electrostatic discharge (ESD) device according to any one of claims 1-4, comprising the following steps: Step 1: Form the NBL region, P-Epi region, and ring-shaped HVNW region in the P-Sub substrate; Step 2: Form the first to seventh field oxygen isolation regions on the P-Epi substrate using photolithography; Step 3: Using photolithography, the first to third NW regions are sequentially formed in the first HVNW region; Step 4: Using photolithography, the first to fourth PW regions are sequentially formed in P-Sub and P-Epi; Step 5: Form the first strip polysilicon gate and the second strip polysilicon gate in the second PW region, and form the third strip polysilicon gate and the fourth strip polysilicon gate in the third PW region; Step 6: By photolithography, a first P+ implantation region is formed in the first PW region, a second and a third P+ implantation region are formed in the second PW region, a fourth and a fifth P+ implantation region are formed in the third PW region, and a sixth P+ implantation region is formed in the fourth PW region. Step 7: By photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region is formed in the second NW region, a third N+ implantation region is formed in the third PW region, and a fourth N+ implantation region is formed in the third NW region.

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