MIM-type gate GaN P-channel field-effect transistor and its fabrication method

Abstract

This invention discloses a MIM-type gate GaN P-channel field-effect transistor and its fabrication method. The device includes: a P-channel layer and a cap layer stacked sequentially from bottom to top; a gate groove extending to the P-channel layer is disposed on the upper surface of the cap layer; a first gate metal layer disposed in the gate groove and in Schottky contact with the P-channel layer; a source and a drain respectively disposed on opposite sides of the upper surface of the cap layer; an insulating gate dielectric layer disposed on the upper surface of the cap layer between the source and drain, and covering the upper surface of the first gate metal layer; and a second gate metal layer disposed on the upper surface of the gate dielectric layer and above the first gate metal layer. The gallium nitride P-channel field-effect transistor provided by this invention can avoid threshold voltage drift and reduce gate leakage current.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a MIM-type gate GaN P-channel field-effect transistor and its fabrication method. Background Technology

[0002] In modern digital integrated circuit design, complementary metal-oxide-semiconductor (CMOS) circuits occupy a central position. Their ability to integrate a large number of logic functions within a limited chip space has greatly driven the advancement of integrated circuits, propelling them towards greater complexity and functionality. Gallium nitride (GaN), a third-generation semiconductor, possesses significant advantages over silicon (Si), such as a much wider bandgap and higher breakdown field strength, making it a core material for radio frequency and power devices. CMOS circuits using all-GaN materials can overcome the parasitic effects inherent in co-packaging schemes between GaN devices and Si-based circuits, improving chip performance while fully leveraging the high breakdown voltage, stronger radiation resistance, and low switching losses of GaN devices. However, the current lack of high-performance GaN P-channel field-effect transistors hinders the design and development of all-GaN CMOS circuits.

[0003] Traditional gallium nitride (GaN) P-channel field-effect transistors (FETs) employ two gate structures: metal-oxide-semiconductor (MOS) and metal-semiconductor field-effect transistors (MES). In MOS structures, the oxide layer often contains a large amount of fixed charge. This charge accumulates over time, trapping holes or electrons, leading to threshold voltage drift and severely impacting device stability and lifetime. Furthermore, the subthreshold swing increases due to the greater oxide layer thickness in MOS structures. In contrast, MES-structured GaN P-channel FETs lack the shielding effect of an oxide dielectric layer, making it unable to effectively suppress gate leakage current. At high gate voltages, the increased gate leakage current further weakens the device's switching control capability, resulting in a less favorable on / off ratio compared to MOS structures. Therefore, researching and developing high-performance GaN P-channel FETs has become a key research focus both domestically and internationally. Achieving GaN P-channel FETs with high current on / off ratio, low subthreshold swing, and high stability is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This invention provides a MIM-type gate GaN P-channel field-effect transistor and its fabrication method, which can solve the problems of threshold voltage drift and gate leakage current in current gallium nitride P-channel field-effect transistors.

[0005] In a first aspect, an embodiment of the present invention provides a MIM-type gate GaN P-channel field-effect transistor, comprising:

[0006] The P-channel layer and the cap layer are stacked sequentially from bottom to top, and the upper surface of the cap layer is provided with a gate groove extending into the p-channel layer.

[0007] The first gate metal layer is disposed in the gate recess and is in contact with the p-channel Schottky layer;

[0008] The source and drain are respectively located on both sides of the upper surface of the cap layer;

[0009] An insulating gate dielectric layer is disposed on the upper surface of the cap layer and between the source and the drain, while also covering the upper surface of the first gate metal layer;

[0010] The second gate metal layer is disposed on the upper surface of the gate dielectric layer and is located above the first gate metal layer.

[0011] Secondly, embodiments of the present invention provide a method for fabricating a MIM-type gate GaN P-channel field-effect transistor, comprising:

[0012] Prepare p-channel layers and cap layers stacked sequentially from bottom to top;

[0013] The etching begins from the upper surface of the cap layer and extends to the gate recess in the p-channel layer;

[0014] Metals are deposited on both sides of the upper surface of the cap layer to form the source and drain electrodes;

[0015] A first gate metal layer is formed by depositing metal in the gate trench;

[0016] An insulating dielectric layer is deposited on the upper surface of the cap layer between the source and the drain and on the upper surface of the first gate metal layer to form a gate dielectric layer.

[0017] A second gate metal layer is formed by depositing metal on the upper surface of the gate dielectric layer above the first gate metal layer.

[0018] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: Because the gallium nitride P-channel field-effect transistor provided by the present invention has a gate with a metal-insulator-metal structure, the metal layer at the bottom layer in contact with the channel Schottky can deplete the two-dimensional hole gas at the p-GaN / AlGaN interface, realizing an enhancement-mode device. This avoids the threshold voltage drift problem caused by a large amount of fixed charge in the oxide layer of the MOS structure gallium nitride P-channel field-effect transistor under long-term operation, ensuring the stability and lifespan of the device. It also avoids the problem of increased subthreshold swing caused by a thicker oxide layer. The intermediate insulating layer acts as a shield to suppress gate leakage current, thus avoiding the problem of increased gate leakage current caused by the lack of electric field shielding in the dielectric layer under high gate voltage in the MES structure gallium nitride P-channel field-effect transistor, effectively improving the power conversion efficiency and lifespan of the device. Attached Figure Description

[0019] Figure 1 A schematic diagram of a MIM-type gate GaN P-channel field-effect transistor provided in an embodiment of the present invention;

[0020] Figure 2 A flowchart illustrating the fabrication method of a MIM-type gate GaN P-channel field-effect transistor provided in this embodiment of the invention;

[0021] Figures 3a-3e This is a schematic diagram illustrating the fabrication scenario of a MIM-type gate GaN P-channel field-effect transistor according to an embodiment of the present invention. Detailed Implementation

[0022] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0023] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0026] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0028] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0029] Figure 1 The diagram shown is a schematic diagram of a MIM-type gate GaN P-channel field-effect transistor provided in an embodiment of the present invention.

[0030] In one possible implementation, see Figure 1 A MIM-type gate GaN P-channel field-effect transistor may include a p-channel layer 1, a cap layer 2, a first gate metal layer 3, a source 4, a drain 5, a gate dielectric layer 6, and a second gate metal layer 7.

[0031] For example, see Figure 1The cap layer 2 can be disposed on the upper surface of the p-channel layer 1, and the upper surface of the cap layer 2 can have a gate groove extending to the p-channel layer 1. The first gate metal layer 3 can be disposed in the gate groove and make Schottky contact with the p-channel layer 1. The source 4 and drain 5 can be disposed on opposite sides of the upper surface of the cap layer 2, respectively. The insulating gate dielectric layer 6 can be disposed on the upper surface of the cap layer 2 between the source 4 and the drain 5, and cover the upper surface of the first gate metal layer 3. The second gate metal layer 7 can be disposed on the upper surface of the gate dielectric layer 6 above the gate groove (or the first gate metal layer 3).

[0032] In one example, the p-channel layer 1 can be a p-type GaN channel layer, and its doping ions can be Mg, with a doping concentration ranging from 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The thickness range can include 50nm to 100nm.

[0033] In one example, cap layer 2 can also be a p-type heavily doped GaN channel layer, with Mg as the dopant ion and a doping concentration ranging from 5 × 10⁻⁶. 19 ~1×10 20 cm -3 The thickness can range from 5nm to 30nm.

[0034] In one example, the material of the first gate metal layer 3 may include metals with low work functions such as W or Ti, and its thickness may range from 20 nm to 100 nm.

[0035] In one example, the source 4 and drain 5 can be made of Ni / Au multilayer metal. Ni metal has a high work function and can form an ohmic contact with the surface of cap layer 2, reducing the contact resistance between the metal and the semiconductor, reducing heat accumulation and power consumption. Au metal has good stability and conductivity and can prevent the oxidation of the underlying Ni metal.

[0036] In one example, the gate dielectric layer 6 is made of an insulator, which may include one or more of the following: SiO2, Al2O3, or SiN.

[0037] In traditional MOS structures, the gate Schottky metal needs to contact a wide-bandgap semiconductor layer with a high node constant, such as an AlGaN semiconductor layer, to reduce gate leakage current. However, direct contact between this semiconductor layer and the channel layer causes lattice mismatch, leading to performance degradation. This invention addresses this by sandwiching an insulating dielectric layer between two metal layers. This reduces gate leakage current using the gate dielectric layer while avoiding the lattice mismatch problem caused by growing an AlGaN barrier layer on the GaN channel layer.

[0038] For example, the thickness of the gate dielectric layer 6 may range from 5 nm to 100 nm.

[0039] A thicker gate dielectric layer reduces gate capacitance, decreases device gate control capability, and reduces transconductance; a thinner gate dielectric layer causes quantum tunneling and increases the difficulty of fabrication, leading to increased gate leakage current; while a gate dielectric layer 6 with a thickness within the above range can reduce gate parasitic capacitance, improve current on / off ratio, and reduce subthreshold swing while suppressing gate leakage current.

[0040] In one example, the material of the second gate metal layer 7 can be any metal, and its thickness can range from 10 nm to 1 μm.

[0041] In one possible implementation, see Figure 1 The gallium nitride P-channel field-effect transistor may also include a substrate layer 8, a buffer layer 9 and a barrier layer 10 stacked sequentially from bottom to top.

[0042] For example, see Figure 1 The p-channel layer 1 can be disposed on the upper surface of the barrier layer 10, that is, the upper surface of the barrier layer 10 is attached to the lower surface of the p-channel layer 1.

[0043] In one example, the material of substrate layer 8 may include Si, Al2O3, or SiC.

[0044] In one example, buffer layer 9 can be an undoped GaN layer with a thickness ranging from 1 to 10 μm.

[0045] In one example, the barrier layer 10 can be made of AlGaN with an Al composition of 10% to 30%, and its thickness can range from 10 to 30 nm.

[0046] Because the MIM-type GaN P-channel MOSFET provided by this invention has a gate with a metal-insulator-metal structure, the bottom metal layer in contact with the channel Schottky can deplete the two-dimensional hole gas at the p-GaN / AlGaN interface, realizing an enhancement-mode device. This avoids the threshold voltage drift problem caused by a large amount of fixed charge in the oxide layer of the MOS-structured GaN P-channel MOSFET under long-term operation, ensuring the stability and lifespan of the device. At the same time, it also avoids the problem of increased subthreshold swing caused by a thicker oxide layer. The middle insulating layer can play a shielding role to suppress gate leakage current, thereby avoiding the problem of increased gate leakage current caused by the lack of electric field shielding effect of the dielectric layer in the MES-structured GaN P-channel MOSFET under high gate voltage, effectively improving the power conversion efficiency and lifespan of the device.

[0047] Figure 2The diagram illustrates a method for fabricating a MIM-type gate GaN P-channel field-effect transistor according to an embodiment of the present invention. As an example and not a limitation, the method may include steps S201-S206, which are described below.

[0048] S201, prepare p-channel layer and cap layer stacked sequentially from bottom to top.

[0049] In one example, if the MIM-type gate GaN P-channel field-effect transistor also includes a substrate layer 8, a buffer layer 9, and a barrier layer 10, an epitaxial wafer comprising the substrate layer 8, buffer layer 9, barrier layer 10, p-channel layer 1, and cap layer 2 stacked sequentially from bottom to top can be integrally fabricated using epitaxial growth technology, resulting in the following: Figure 3a The structure shown.

[0050] For example, after the epitaxial wafer is prepared, it can be organically cleaned to remove the oxide layer on the surface, thereby reducing the interference of oxidation and contamination on subsequent device processes and the impact on device performance.

[0051] Specifically, firstly, the epitaxial wafer can be immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic contaminants from its surface. Next, it can be ultrasonically cleaned in an isopropanol solution for 5 minutes to effectively remove residual acetone. Then, the epitaxial wafer can be rinsed in deionized water to remove any remaining isopropanol. Finally, the surface can be dried with high-purity nitrogen to ensure no liquid residue remains. Alternatively, the epitaxial wafer can be placed in a 1:7 BOE solution for 30 seconds to remove the surface oxide layer, then rinsed with plenty of deionized water, and finally dried with high-purity nitrogen to complete the entire cleaning process.

[0052] S202, starting from the upper surface of the cap layer, is etched to extend into the gate groove in the p-channel layer.

[0053] In one example, spin coating, baking, exposure, and development operations can be sequentially performed on the upper surface of the cap layer 2 to define the area where the non-gate groove is located through photolithography. Then, inductively coupled plasma (ICP) dry etching technology is used to etch the area without photoresist coating, removing the cap layer 2 and part of the p-channel layer 1 to form the gate groove extending from the upper surface of the cap layer 2 into the p-channel layer 1. Afterward, the area can be cleaned with a stripping solution to remove residual photoresist, resulting in the desired shape. Figure 3b The structure shown.

[0054] S203 has metal deposited on both sides of the upper surface of the cap layer to form the source and drain electrodes.

[0055] In one example, the processes of spin coating, baking, exposure, and development can be performed on both sides of the upper surface of the cap layer 2 to define the regions where the source electrode 4 and drain electrode 5 are located using photolithography. Then, Ni / Au metal is sputtered onto the developed cap layer 2 surface using magnetron sputtering. Finally, residual resist and metal from other areas are removed using a stripping solution to obtain the desired result. Figure 3c The structure shown is illustrated. After metal deposition, a rapid thermal annealing process can be used to anneal the epitaxial wafer at 450°C for 5 minutes under a nitrogen atmosphere.

[0056] Annealing can reduce the influence of the gold-semiconductor interface state, allowing the source 4 and drain 5 to form good ohmic contacts with the cap layer 2, thereby reducing the contact resistance between the metal and the semiconductor.

[0057] Specifically, it can be Figure 3c The structure shown was annealed in a nitrogen atmosphere at 450°C for 5 minutes to form the gate trench, and then heated in a TMAH solution at 80°C for 10 minutes to repair the interface damage in the etched area.

[0058] S204, depositing metal in the gate trench to form a first gate metal layer.

[0059] In one example, a magnetron sputtering process can be used to sputter metal in the gate trench to form the first gate metal layer 3, resulting in... Figure 3d The structure shown.

[0060] S205, an insulating dielectric is deposited on the upper surface of the cap layer between the source and the drain and on the upper surface of the first gate metal layer to form a gate dielectric layer.

[0061] In one example, an insulating dielectric layer 6 can be formed by depositing an insulating dielectric layer on the upper surface of the cap layer 2 between the source 4 and the drain 5 and on the upper surface of the first gate metal layer 3 using the PEALD (Plasma Enhanced Atomic Layer Deposition) process, resulting in the following: Figure 3e The structure shown.

[0062] S206, deposit metal on the upper surface of the gate dielectric layer above the first gate metal layer to form a second gate metal layer.

[0063] In one example, similarly, photoresist can be applied, baked, exposed, and developed on the upper surface of the gate dielectric layer 6 above the first gate metal layer 3 to define the area where the gate groove is located using photolithography; then, metal is deposited using magnetron sputtering to form the second gate metal layer 7; finally, the layer is cleaned with a stripping solution to remove residual resist, and the metal in the non-gate electrode areas is stripped to obtain the desired result. Figure 1 The example shown is a gallium nitride P-channel field-effect transistor.

[0064] According to the fabrication method provided by the present invention, an enhancement-mode P-channel MOSFET with low gate leakage current and good operating stability can be fabricated. Furthermore, precise etching of the gate trench using an ICP dry etching process, followed by gate trench annealing and repair of the gate trench interface using a TMAH solution, can further improve interface quality and reduce gate leakage current.

[0065] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Claims

1. A MIM-type gate GaN P-channel field-effect transistor, characterized in that, include: A P-channel layer and a cap layer are stacked sequentially from bottom to top, and a gate groove extending into the P-channel layer is provided on the upper surface of the cap layer. A first gate metal layer is disposed in the gate recess and is in contact with the Schottky P-channel layer. The source and drain are respectively disposed on both sides of the upper surface of the cap layer; An insulating gate dielectric layer is disposed on the upper surface of the cap layer and between the source and the drain, while covering the upper surface of the first gate metal layer; A second gate metal layer is disposed on the upper surface of the gate dielectric layer and is located above the first gate metal layer.

2. The MIM-type gate GaN P-channel field-effect transistor according to claim 1, characterized in that, The GaN P-channel field-effect transistor further includes a substrate layer, a buffer layer, and a barrier layer stacked sequentially from bottom to top, with the upper surface of the barrier layer attached to the lower surface of the P-channel layer.

3. The MIM-type gate GaN P-channel field-effect transistor according to claim 1, characterized in that, The material of the first gate metal layer includes W and Ti.

4. The MIM-type gate GaN P-channel field-effect transistor according to claim 1, characterized in that, The material of the gate dielectric layer includes one or more of the following: SiO2, Al2O3, and SiN.

5. The MIM-type gate GaN P-channel field-effect transistor according to claim 1, characterized in that, The thickness range of the gate dielectric layer is 5 nm to 100 nm.

6. The MIM-type gate GaN P-channel field-effect transistor according to claim 1, characterized in that, The source and drain are made of Ni / Au multilayer metal.

7. A method for fabricating a MIM-type gate GaN P-channel field-effect transistor, characterized in that, include: Prepare a P-channel layer and a cap layer stacked sequentially from bottom to top; Etching begins from the upper surface of the cap layer and extends into the gate recess in the P-channel layer; Metal is deposited on both sides of the upper surface of the cap layer to form the source and drain electrodes; A first gate metal layer is formed by depositing metal in the gate recess; An insulating dielectric layer is deposited on the upper surface of the cap layer between the source and the drain and on the upper surface of the first gate metal layer to form a gate dielectric layer. A second gate metal layer is formed by depositing metal on the upper surface of the gate dielectric layer above the first gate metal layer.

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