LDMOS device and forming method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a forming method thereof. The LDMOS device comprises a substrate which comprises a front surface and a back surface which are oppositely distributed along a first direction; the body region is located in the substrate, and a groove is formed in the body region; the source electrode region is located in the body region, the source electrode region is distributed on the side wall of the groove and the bottom surface of the groove, the source electrode region comprises a body region contact region located on the bottom surface of the groove and a source electrode doping region distributed around the periphery of the body region contact region, and the source electrode doping region is in a bent shape and is continuously distributed on the side wall of the groove and a part of the bottom surface of the groove; the drift region is located in the substrate, the drift region is distributed on the outer side of the body region in the second direction, and the second direction perpendicularly intersects with the first direction; and a drain region in the drift region. According to the LDMOS device, the over-current capability of the LDMOS device can be ensured, and the specific on-resistance of the LDMOS device can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an LDMOS device and a forming method thereof. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) process technology is an advanced semiconductor manufacturing process that combines bipolar transistors, CMOS (complementary metal oxide semiconductor) and DMOS (double diffused metal oxide semiconductor) transistor technologies on a single chip. Bipolar transistors are mainly used for analog signal control, while CMOS and DMOS are used for digital signal control and high-power processing. Compared with traditional processes, BCD process technology reduces the number of components and the failure rate of connection failure by integrating three processes (i.e., bipolar transistor process, CMOS process and DMOS process) on a single chip. In addition, BCD process technology helps semiconductor devices dissipate heat more effectively and reduce reliability problems caused by excessive temperature. The BCD process reduces the interconnection length between internal device structures, reduces parasitic inductance, and thus reduces electromagnetic interference generated during high-frequency switching. In addition, BCD process technology also helps to achieve a smaller chip area.

[0003] The power output stage DMOS tube is the core of the BCD chip circuit, often occupying 1 / 2 to 2 / 3 of the entire chip area. It is the key to the entire integrated circuit. DMOS has a similar structure to CMOS devices, and also has electrodes such as source, drain, and gate, but the breakdown voltage at the drain end is high. There are two main types of DMOS, namely vertical double-diffused MOSFET (VDMOSFET) and lateral double-diffused MOSFET (LDMOSFET). LDMOS is widely used because it is more compatible with CMOS processes. LDMOS is a power device with a double diffusion structure that can withstand higher voltage and current than CMOS, while having lower on-resistance and switching loss. In theory, when the on-resistance is very small, the LDMOS device will provide a good switching characteristic, because the small on-resistance between the drain and the source will result in a larger output current, which can have a stronger driving capability. However, the current LDMOS device has a high on-resistance, which limits the improvement of the performance of the LDMOS device.

[0004] Therefore, how to reduce the specific on-resistance of the LDMOS device, thereby improving the switching characteristics of the LDMOS device to achieve improvement in the performance of the LDMOS device, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides an LDMOS device and a method for forming the same, which are used to reduce the on-resistance of the LDMOS device, thereby improving the switching characteristics of the LDMOS device, so as to improve the performance of the LDMOS device.

[0006] According to some embodiments, the present invention provides an LDMOS device, comprising: A substrate, comprising a front surface and a back surface that are oppositely distributed along a first direction; A body region, located in the substrate, wherein the body region has a groove; A source region, located in the body region, the source region comprising a body region contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body region contact region, the source doping region being in a bent shape and continuously distributed on the sidewall of the trench and a portion of the bottom surface of the trench; A drift region is located in the substrate, and the drift region is distributed outside the body region along a second direction, and the second direction intersects the first direction perpendicularly; The drain region is located in the drift region.

[0007] In some embodiments, the substrate and the body region both include first type dopant ions, the drift region and the drain region both include second type dopant ions, and the conductivity type of the first type dopant ions is opposite to the conductivity type of the second type dopant ions; The body contact region includes the first type of doping ions, and the source doping region includes the second type of doping ions.

[0008] In some embodiments, an angle between a sidewall of the trench and a bottom surface of the trench is an obtuse angle.

[0009] In some embodiments, a width of the trench is smaller than a width of the body region, and a depth of the trench is greater than a depth of the drain region and smaller than a depth of the body region.

[0010] In some embodiments, the width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

[0011] In some embodiments, it also includes: A gate structure is located on the front side of the substrate and is distributed between the drain region and the source region along the second direction, wherein the gate structure includes a gate dielectric layer covering the front side of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer.

[0012] In some embodiments, it also includes: An interlayer dielectric layer, covering the front surface of the substrate and filling the groove; A source lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the source region; a drain lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the drain region; A gate lead-out structure penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate structure.

[0013] In some embodiments, it also includes: A source contact layer, covering the surface of the source region and electrically connected to the source lead-out structure; A drain contact layer, covering the surface of the drain region and electrically connected to the drain lead-out structure; The gate contact layer covers the surface of the gate conductive layer and is electrically connected to the gate lead-out structure.

[0014] According to some other embodiments, the present invention further provides a method for forming an LDMOS device, comprising the following steps: Providing a substrate, the substrate comprising a front surface and a back surface that are oppositely distributed along a first direction; forming a body region and a drift region in the substrate, wherein the drift region is distributed outside the body region along a second direction, and the second direction intersects the first direction perpendicularly; forming a groove in the body region; A source region is formed on the sidewalls and the bottom surface of the trench, and a drain region is formed in the drift region, the source region includes a body region contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body region contact region, the source doping region is in a bent shape and is continuously distributed on the sidewalls and part of the bottom surface of the trench.

[0015] In some embodiments, the substrate includes first type doping ions; and the specific steps of forming a body region and a drift region in the substrate include: Implanting the first type of dopant ions into the substrate from the front surface of the substrate to form the body region, wherein the top surface of the body region is flush with the front surface of the substrate; Second type doping ions are injected into the substrate from the front side of the substrate to form the drift region, the top surface of the drift region is flush with the front side of the substrate, and the conductivity type of the first type doping ions is opposite to the conductivity type of the second type doping ions.

[0016] In some embodiments, the specific steps of forming the trench in the body region include: The body region is etched from the top surface of the body region using a photochemical etching process to form the groove.

[0017] In some embodiments, the step of etching the body region from the top surface of the body region to form the trench further includes: The etching parameters of the photochemical etching process are adjusted so that the angle between the sidewall of the formed groove and the bottom surface of the groove is an obtuse angle.

[0018] In some embodiments, the width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

[0019] In some embodiments, before forming a source region on the sidewalls of the trench and the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: The first type doping ions are implanted into the body region along the trench.

[0020] In some embodiments, the specific steps of forming a source region on the sidewalls of the trench and the bottom surface of the trench, and forming a drain region in the drift region include: The source region including the body contact region and the source doping region is formed on the sidewalls of the trench and the bottom surface of the trench, and the drain region is formed in the drift region, the body contact region includes the first type of doping ions, the source doping region includes the second type of doping ions, and the drain region includes the second type of doping ions.

[0021] In some embodiments, the front side of the substrate further has a gate structure distributed between the drain region and the source region along the second direction, the gate structure comprising a gate dielectric layer covering the front side of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer; after forming the source region on the sidewalls of the trench and the bottom surface of the trench, and forming the drain region in the drift region, the following steps are also included: A source contact layer electrically connected to the source region is formed on the surface of the source region, a drain contact layer electrically connected to the drain region is formed on the surface of the drain region, and a gate contact layer electrically connected to the gate conductive layer is formed on the surface of the gate conductive layer.

[0022] In some embodiments, after forming a source region on the sidewalls of the trench and the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: forming an interlayer dielectric layer covering the front surface of the substrate and filling the trench; A source lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the source contact layer, a drain lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the drain contact layer, and a gate lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate contact layer.

[0023] The LDMOS device and its formation method provided by the present invention are realized by arranging a groove in the body region and distributing the source region on the side wall and bottom surface of the groove, wherein the source region includes a body region contact region located on the bottom surface of the groove and a source doping region distributed around the periphery of the body region contact region, wherein the source doping region is in a bent shape and is continuously distributed on the side wall of the groove and part of the bottom surface of the groove, thereby realizing a three-dimensional structure of the LDMOS, and the bent source region can effectively increase the area of ​​the source region to ensure the overcurrent capacity of the LDMOS device. Moreover, since the area of ​​the source region can be increased by the groove, the overcurrent capacity of the LDMOS device can be ensured, and the distance between the source region and the drain region in the LDMOS device (i.e., the LDMOS pitch) can be reduced by reducing the size of the body region to reduce the specific on-resistance of the LDMOS device, thereby improving the performance of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic diagram of the structure of an LDMOS device in a specific embodiment of the present invention; Figure 2 is a schematic diagram of the structure of the body region and the source region in a specific implementation manner of the present invention; Figure 3 is a flow chart of a method for forming an LDMOS device in a specific embodiment of the present invention; Figure 4 is a schematic diagram of the structure after a body region and a drift region are formed in a substrate in a specific embodiment of the present invention; Figure 5 is a schematic diagram of a structure after a groove is formed in a body region in a specific embodiment of the present invention; Figure 6 is a schematic diagram of the structure after the source region and the drain region are formed in a specific embodiment of the present invention; Figure 7 is a schematic diagram of the structure after forming a source contact layer, a drain contact layer and a gate contact layer in a specific embodiment of the present invention; Figure 8 A schematic diagram of a structure after forming an interlayer dielectric layer in a specific embodiment of the present invention; Fig. 9 It is a schematic diagram of the structure after the source contact hole, the drain contact hole and the gate contact hole are formed in a specific embodiment of the present invention.

[0026] Description of Reference Numerals 10 substrate 11 Body Areas 12Drift Zone 13. Drain region 141 Body contact area 142 Source doping region 15 Grooves 16 Shallow Trench Isolation Structure 171 Gate dielectric layer 172 gate conductive layer 173Gate Isolation Layer 181 Source contact layer 182 drain contact layer 183 Gate contact layer 184 substrate contact layer 19 substrate contact area 20 interlayer dielectric layer 211 source lead structure 212 drain lead structure 213 Gate lead structure 214 substrate lead structure 221 source lead pad 222 drain lead pad 223 Gate lead pad 224 substrate lead pad 911 Source contact hole 912 drain contact hole 913 Gate contact hole 914 substrate contact hole DETAILED DESCRIPTION The specific implementation manner of the LDMOS device and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0027] This specific embodiment provides an LDMOS device, Figure 1 is a schematic diagram of the structure of an LDMOS device in a specific embodiment of the present invention, Figure 2 Schematic diagram of the structure of the body region and the source region in a specific embodiment of the present invention. Figure 1 and Figure 2 As shown, the LDMOS device comprises: The substrate 10 includes a front surface and a back surface that are oppositely distributed along a first direction D1; A body region 11 is located in the substrate 10, and a groove 15 is formed in the body region 11; A source region, located in the body region 11, the source region includes a body region contact region 141 located on the bottom surface of the trench 15 and a source doping region 142 distributed around the periphery of the body region contact region 141, the source doping region 142 is in a bent shape and is continuously distributed on the sidewall of the trench 15 and a portion of the bottom surface of the trench 15; A drift region 12 is located in the substrate 10 and is distributed outside the body region 11 along a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1; The drain region 13 is located in the drift region 12 .

[0028] For example, the substrate 10 is a silicon substrate. The substrate 10 has a plurality of active regions arranged at intervals, and adjacent active regions are isolated from each other by a shallow trench isolation structure 16, and each active region is used to form a unit structure in the LDMOS device. The multiple mentioned in this specific embodiment refers to more than two. In one example, the active region includes the body region 11 and the two drift regions 12 distributed on opposite sides of the body region 11 along the second direction D2, and the drain region 13 is provided in each drift region 12. The top surface of the body region 11 is flush with the front surface of the substrate 10. The groove 15 is recessed from the top surface of the body region 11 to the inside of the body region 11, and the groove 15 does not penetrate the body region 11 (for example, the groove 15 does not penetrate the body region 11 along both the first direction D1 and the second direction D2). The source region includes a body region contact region 141 located on the bottom surface of the groove 15 and a source doping region 142 distributed around the periphery of the body region contact region 141. The source doping region 142 is in a bent shape and is continuously distributed on the sidewall of the groove 15 and part of the bottom surface of the groove 15, so that the source region as a whole can be set in a bent shape through the recessed groove 15, so that the area of ​​the source region can be effectively increased to ensure the flow capacity of the LDMOS device. Moreover, since the groove can ensure the flow capacity of the LDMOS device by ensuring the area of ​​the source region, it is no longer limited by the minimum feature size of the photoresist in the ion implantation process, so that the size of the body region can be further reduced, so that the distance between the source region and the drain region in the LDMOS device (i.e., the LDMOS pitch) is reduced, so as to achieve the effect of reducing the on-resistance of the LDMOS device and improve the performance of the LDMOS device.

[0029] In some embodiments, the substrate 10 and the body region 11 both include first type doping ions, the drift region 12 and the drain region 13 both include second type doping ions, and the conductivity type of the first type doping ions is opposite to the conductivity type of the second type doping ions; The body contact region 141 includes the first type of doping ions, and the source doping region 142 includes the second type of doping ions.

[0030] Specifically, the source region includes the body region contact region 141 located on the bottom surface of the groove 15 and the source doping region 142 symmetrically distributed around the periphery of the body region contact region 141, and the source doping region 142 is continuously distributed on the sidewall of the groove 15 and part of the bottom surface of the groove 15, so that the source doping region 142 is bent. In one example, the body region contact region 141 is in contact with the source doping region 142. The body region contact region 141 and the body region 11 both include the first type of doping ions, and the doping concentration of the first type of doping ions in the body region contact region 141 is greater than the doping concentration of the first type of doping ions in the body region 11, that is, the body region contact region 141 is heavily doped, so that the body region contact region 141 can be used as the lead-out end of the body region 11 to reduce the contact resistance of the body region 11.

[0031] In one example, the first type of dopant ions are P-type ions, and the second type of dopant ions are N-type ions. In another example, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions.

[0032] In some embodiments, the angle between the sidewall of the groove 15 and the bottom surface of the groove 15 is an obtuse angle.

[0033] Specifically, the angle between the side wall of the groove 15 and the bottom surface of the groove 15 is an obtuse angle, that is, the angle between the side wall of the groove 15 and the bottom surface of the groove 15 is greater than 90 degrees. On the one hand, the tip discharge effect at the bottom corner of the groove 15 (that is, the connection between the side wall of the groove 15 and the bottom surface of the groove 15) can be reduced, thereby further improving the performance of the LDMOS device; on the other hand, it is also convenient to inject the second type of doping ions into the side wall and the bottom surface of the groove 15, thereby simplifying the operation of forming the source doping region 142, reducing the difference between the doping ion concentration in the source doping region 142 located on the side wall of the groove 15 and the doping ion concentration in the source doping region 142 located on the bottom surface of the groove 15, thereby further improving the performance of the LDMOS device.

[0034] In some embodiments, the width of the trench 15 is smaller than the width of the body region 11 , and the depth of the trench 15 is greater than the depth of the drain region 13 and smaller than the depth of the body region 11 .

[0035] In some embodiments, the width of the groove 15 is 0.3 μm to 0.4 μm, and the depth of the groove 15 is 1500 Å to 2500 Å.

[0036] Specifically, by setting the width of the groove 15 (e.g., the width of the groove 15 along the second direction D2) to 0.3 μm-0.4 μm, and the depth of the groove 15 (e.g., the depth of the groove 15 along the first direction D1) to 1500 Å-2500 Å, it can not only help to further reduce the size of the body region 11, so that the specific on-resistance of the LDMOS device is further reduced, but also meet the requirements of the groove etching and ion implantation process. In one example, the width of the groove 15 is 0.36 μm, and the depth of the groove 15 is 2000 Å.

[0037] In some embodiments, the LDMOS device further comprises: The gate structure is located on the front side of the substrate 10 and is distributed between the drain region 13 and the source region along the second direction D2. The gate structure includes a gate dielectric layer 171 covering the front side of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 covering the side walls of the gate dielectric layer 171 and the side walls of the gate conductive layer 172.

[0038] For example, the active region of the substrate 10 includes two gate structures distributed on opposite sides of the body region 11 along the second direction D2, and each gate structure is located between the source region and one of the drain regions 13 along the second direction D2. The gate structure includes a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 continuously covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172. In one example, the material of the gate dielectric layer 171 may be an oxide material, the material of the gate conductive layer 172 may be a polysilicon material, and the material of the gate isolation layer 173 may be any one of an oxide material and a nitride material, or a combination of the two.

[0039] In some embodiments, the LDMOS device further comprises: An interlayer dielectric layer 20 covers the front surface of the substrate 10 and fills the trench 15; A source lead-out structure 211, penetrating the interlayer dielectric layer 20 along the first direction D1 and electrically connected to the source region; A drain lead-out structure 212, penetrating the interlayer dielectric layer 20 along the first direction D1 and electrically connected to the drain region 13; The gate lead-out structure 213 penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the gate structure.

[0040] In some embodiments, the LDMOS device further comprises: A source contact layer 181, covering the surface of the source region and electrically connected to the source lead-out structure 211; A drain contact layer 182 covers the surface of the drain region 13 and is electrically connected to the drain lead-out structure 212; The gate contact layer 183 covers the surface of the gate conductive layer 172 and is electrically connected to the gate lead-out structure 213 .

[0041] For example, the substrate 10 further includes a substrate contact region 19, and the substrate contact region 19 includes the first type of doped ions, and the doping concentration of the first type of doped ions in the substrate contact region 19 is greater than that of the substrate 10. The substrate contact region 19 is electrically isolated from the drift region 12 by a shallow trench isolation structure 16. The LDMOS device further includes the source contact layer 181 continuously covering the body contact region 141 and the source doped region 142, the drain contact layer 182 covering the drain region 13, the gate contact layer 183 covering the gate conductive layer 172, and the substrate contact layer 184 covering the substrate contact region 19. In one example, the materials of the source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184 are all silicide materials. The interlayer dielectric layer 20 is located on the front surface of the substrate 10, and continuously covers the front surface of the substrate 10, the source contact layer 181, the drain contact layer 182, the gate contact layer 183 and the substrate contact layer 184, and the interlayer dielectric layer 20 fills the trench 15. In an example, the material of the interlayer dielectric layer 20 can be an insulating material such as oxide.

[0042] The LDMOS device also includes the source lead-out structure 211 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the source contact layer 181, the drain lead-out structure 212 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the drain contact layer 182, the gate lead-out structure 213 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the gate contact layer 183, and the substrate lead-out structure 214 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the substrate contact layer 184. The source contact layer 181 is used to reduce the contact resistance between the source lead-out structure 211 and the source region, the drain contact layer 182 is used to reduce the contact resistance between the drain lead-out structure 212 and the drain region 13, the gate contact layer 183 is used to reduce the contact resistance between the gate lead-out structure 213 and the gate conductive layer 172, and the substrate contact layer 184 is used to reduce the contact resistance between the substrate lead-out structure 214 and the substrate 10.

[0043] In one example, the LDMOS device also includes a source lead-out pad 221, a drain lead-out pad 222, a gate lead-out pad 223 and a substrate lead-out pad 224 located above the interlayer dielectric layer 20, the source lead-out pad 221 is electrically connected to the source lead-out structure 211, the drain lead-out pad 222 is electrically connected to the drain lead-out structure 212, the gate lead-out pad 223 is electrically connected to the gate lead-out structure 213, and the substrate lead-out pad 224 is electrically connected to the substrate lead-out structure 214.

[0044] The specific on-resistance of the LDMOS device is proportional to the distance (i.e., pitch) between the source lead-out structure 211 and the drain lead-out structure 212. By reducing the size of the body region 11, the distance between the source lead-out structure 211 and the drain lead-out structure 212 can be reduced, thereby reducing the specific on-resistance of the LDMOS device. However, as the size of the body region 11 is reduced, the size of the source region in the body region 11 will be reduced, which not only increases the process difficulty of forming the source region, but also affects the current capacity of the LDMOS device. In this specific embodiment, the groove 15 is formed in the body region 11, so that the source region is distributed on the side wall and bottom surface of the groove 15, so that the current capacity of the LDMOS device can be ensured while reducing the size of the body region 11 to reduce the specific on-resistance of the LDMOS device, thereby improving the overall performance of the LDMOS device.

[0045] This specific embodiment also provides a method for forming an LDMOS device. Figure 32 is a flow chart of a method for forming an LDMOS device in a specific embodiment of the present invention. The structure of the LDMOS device formed in this specific embodiment can be seen in FIG. Figure 1 and Figure 2 .like Figure 1-Figure 3 As shown, the method for forming the LDMOS device comprises the following steps: Step S31, providing a substrate 10, wherein the substrate 10 includes a front surface and a back surface that are relatively distributed along a first direction D1; Step S32, forming a body region 11 and a drift region 12 in the substrate 10, wherein the drift region 12 is distributed outside the body region 11 along a second direction D2, and the second direction D2 intersects the first direction D1 perpendicularly; Step S33, forming a trench 15 in the body region 11; Step S34, forming a source region on the sidewalls of the trench 15 and on the bottom surface of the trench 15, and forming a drain region 13 in the drift region 12, the source region includes a body contact region 141 located on the bottom surface of the trench 15 and a source doping region 142 distributed around the periphery of the body contact region 141, the source doping region 142 is in a bent shape and is continuously distributed on the sidewalls of the trench 15 and on part of the bottom surface of the trench 15.

[0046] Figure 4 1 is a schematic diagram of a structure after a body region and a drift region are formed in a substrate in a specific embodiment of the present invention. In some embodiments, the substrate 10 includes first type doping ions; the specific steps of forming a body region 11 and a drift region 12 in the substrate 10 include: Injecting the first type of dopant ions into the substrate 10 from the front surface of the substrate 10 to form the body region 11, wherein the top surface of the body region 11 is flush with the front surface of the substrate 10; The second type of dopant ions are injected into the substrate 10 from the front side of the substrate 10 to form the drift region 12. The top surface of the drift region 12 is flush with the front side of the substrate 10. The conductivity type of the first type of dopant ions is opposite to the conductivity type of the second type of dopant ions.

[0047] For example, after forming a plurality of active regions and the shallow trench isolation structure 16 for separating adjacent active regions in the substrate 10, a gate structure is formed above the active regions of the substrate 10, the gate structure comprising a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 continuously covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172. Next, the first type of dopant ions are injected into the substrate 10 from the front surface of the substrate 10, and the second type of dopant ions are injected into the substrate 10 from the front surface of the substrate 10 to form the body region 11 including the first type of dopant ions, and to form the drift region 12 including the second type of dopant ions, as shown in FIG. Figure 4 The order in which the body region 11 and the drift region 12 are formed can be adjusted according to actual needs.

[0048] Figure 5 1 is a schematic diagram of a structure after a groove is formed in the body region in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the groove 15 in the body region 11 include: The body region 11 is etched from the top surface of the body region 11 using a photochemical etching process to form the trench 15 .

[0049] Specifically, in order to reduce the specific on-resistance of the LDMOS device, the characteristic size of the body region 11 is reduced (for example, the width of the body region 11 along the second direction D2 is reduced), and the photochemical etching process can accurately form the groove 15 that meets the preset requirements (for example, morphology requirements and size requirements) in the smaller body region 11, thereby ensuring that the subsequent process of forming the source region in the groove 15 can proceed smoothly.

[0050] In some embodiments, the step of etching the body region 11 from the top surface of the body region 11 to form the trench 15 further includes: The etching parameters of the photochemical etching process are adjusted so that the angle β between the sidewall of the formed groove 15 and the bottom surface of the groove 15 is an obtuse angle.

[0051] Specifically, the angle β between the side wall of the groove 15 and the bottom surface of the groove 15 is an obtuse angle, that is, the angle β between the side wall of the groove 15 and the bottom surface of the groove 15 is greater than 90 degrees. On the one hand, the tip discharge effect at the bottom corner of the groove 15 (that is, the connection between the side wall of the groove 15 and the bottom surface of the groove 15) can be reduced, thereby further improving the performance of the LDMOS device; on the other hand, it is also convenient to implant the second type of doping ions into the side wall and the bottom surface of the groove 15, thereby simplifying the operation of forming the source doping region 142, reducing the difference between the doping ion concentration in the source doping region 142 located on the side wall of the groove 15 and the doping ion concentration in the source doping region 142 located on the bottom surface of the groove 15, thereby further improving the performance of the LDMOS device.

[0052] In some embodiments, the width of the groove 15 is 0.3 μm to 0.4 μm, and the depth of the groove 15 is 1500 Å to 2500 Å.

[0053] Specifically, by setting the width of the groove 15 (e.g., the width of the groove 15 along the second direction D2) to 0.3 μm-0.4 μm, and the depth of the groove 15 (e.g., the depth of the groove 15 along the first direction D1) to 1500 Å-2500 Å, it can not only help to further reduce the size of the body region 11, so that the specific on-resistance of the LDMOS device is further reduced, but also meet the requirements of the groove etching and ion implantation process. In one example, the width of the groove 15 is 0.36 μm, and the depth of the groove 15 is 2000 Å.

[0054] In some embodiments, before forming a source region on the sidewalls of the trench 15 and the bottom surface of the trench 15 and forming a drain region 13 in the drift region 12, the following steps are also included: The first type dopant ions are implanted into the body region 11 along the trench 15 .

[0055] Specifically, in the process of etching the body region 11 to form the groove 15, the etching process (such as a photochemical etching process) will affect the concentration and distribution of the first type of doped ions in the body region 11. In order to repair the influence of the groove etching process on the body region 11, before forming the source region on the side wall of the groove 15 and on the bottom surface of the groove 15, and forming the drain region 13 in the drift region 12, the first type of doped ions are injected into the body region 11 along the groove 15, thereby compensating for the influence of the etching process on the ion doping concentration and distribution in the body region 11.

[0056] Figure 6Schematic diagram of the structure after forming the source region and the drain region in a specific embodiment of the present invention. Figure 6 As shown, the specific steps of forming the source region on the sidewalls of the trench 15 and the bottom surface of the trench 15 and forming the drain region 13 in the drift region 12 include: The source region including the body contact region 141 and the source doping region 142 is formed on the sidewalls of the trench 15 and on the bottom surface of the trench 15, and the drain region 13 is formed in the drift region 12, the body contact region 141 includes the first type of doping ions, the source doping region 142 includes the second type of doping ions, and the drain region 13 includes the second type of doping ions.

[0057] In one example, the first type of doping ions are P-type ions, and the second type of doping ions are N-type ions. In another example, the first type of doping ions are N-type ions, and the second type of doping ions are P-type ions. For example, the substrate 10 and the body region 11 both include P-type ions, and the drift region 12 includes N-type ions. After forming the trench 15, N-type ions are implanted into the drift region 12, the substrate 10, the sidewalls of the trench 15, and a portion of the bottom surface of the trench 15 to form the drain region 13 in the drift region 12, the substrate 10, the substrate contact region 19 in the substrate 10, and the source doping region 142 on the sidewalls and a portion of the bottom surface of the trench 15. Afterwards, P-type ions are implanted into the bottom surface of the trench 15 to form the body region contact region 141. The implantation order of the N-type ions and the P-type ions can be adjusted according to actual needs.

[0058] Figure 7 1 is a schematic diagram of the structure after the source contact layer, the drain contact layer and the gate contact layer are formed in a specific embodiment of the present invention. In some embodiments, the front surface of the substrate 10 also has a gate structure distributed between the drain region 13 and the source region along the second direction D2, and the gate structure includes a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172; after forming the source region on the sidewalls of the trench 15 and the bottom surface of the trench 15, and forming the drain region 13 in the drift region 12, the following steps are also included: A source contact layer 181 electrically connected to the source region is formed on the surface of the source region, a drain contact layer 182 electrically connected to the drain region 13 is formed on the surface of the drain region 13, and a gate contact layer 183 electrically connected to the gate conductive layer 172 is formed on the surface of the gate conductive layer 172. Figure 7 shown.

[0059] Specifically, a metal material is deposited on the front surface of the substrate 10 and the surface of the source region, and a metal silicide layer covering the surface of the source region, the surface of the drain region 13, the surface of the gate conductive layer 172, and the surface of the substrate contact region 19 is formed by a heat treatment process, and the metal silicide layer located on the surface of the source region and electrically connected to the source region is used as the source contact layer 181, the metal silicide layer located on the surface of the drain region 13 and electrically connected to the drain region 13 is used as the drain contact layer 182, the metal silicide layer located on the surface of the gate conductive layer 172 and electrically connected to the gate conductive layer 172 is used as the gate contact layer 183, and the metal silicide layer located on the surface of the substrate contact region 19 and electrically connected to the substrate contact region 19 is used as the substrate contact layer 184. The source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184 are independent of each other. Figure 7 shown.

[0060] Figure 8 A schematic diagram of a structure after forming an interlayer dielectric layer in a specific embodiment of the present invention, Fig. 9 1 is a schematic diagram of the structure after forming the source contact hole, the drain contact hole and the gate contact hole in a specific embodiment of the present invention. In some embodiments, after forming the source region on the sidewall of the trench 15 and the bottom surface of the trench 15 and forming the drain region 13 in the drift region 12, the following steps are also included: An interlayer dielectric layer 20 is formed covering the front surface of the substrate 10 and filling the trench 15. Figure 8 As shown; A source lead-out structure 211 is formed which penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact and electrically connected with the source contact layer 181, a drain lead-out structure 212 is formed which penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact and electrically connected with the drain contact layer 182, and a gate lead-out structure 213 is formed which penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact and electrically connected with the gate contact layer 183. Figure 1 shown.

[0061] For example, an insulating material such as an oxide material is deposited on the front surface of the substrate 10 to form the interlayer dielectric layer 20 that continuously covers the front surface of the substrate 10, the source contact layer 181, the drain contact layer 182, the gate contact layer 183 and the substrate contact layer 184, and the interlayer dielectric layer 20 fills the trench 15. The interlayer dielectric layer 20 is etched to form a source contact hole 911 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the source contact layer 181, a drain contact hole 912 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the drain contact layer 182, a gate contact hole 913 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the gate contact layer 183, and a substrate contact hole 914 that penetrates the interlayer dielectric layer along the first direction D1 and exposes the substrate contact layer 184, as shown in FIG. Fig. 9 As shown. A metal material such as copper or tungsten is deposited to simultaneously form the source lead-out structure 211 filled in the source contact hole 911, the drain lead-out structure 212 filled in the drain contact hole 912, the gate lead-out structure 213 filled in the gate contact hole 913, and the substrate lead-out structure 214 filled in the substrate contact hole 914. Next, a source lead-out pad 221, a drain lead-out pad 222, a gate lead-out pad 223, and a substrate lead-out pad 224 are formed above the interlayer dielectric layer 20, the source lead-out pad 221 is electrically connected to the source lead-out structure 211, the drain lead-out pad 222 is electrically connected to the drain lead-out structure 212, the gate lead-out pad 223 is electrically connected to the gate lead-out structure 213, and the substrate lead-out pad 224 is electrically connected to the substrate lead-out structure 214, as shown. Figure 1 shown.

[0062] The LDMOS device and the method for forming the same provided in this specific embodiment realize a three-dimensional structure of the LDMOS by setting a groove in the body region and distributing the source region on the sidewall and bottom surface of the groove. The bent source region can effectively increase the area of ​​the source region to ensure the flow capacity of the LDMOS device. Moreover, since the area of ​​the source region can be increased by the groove, the flow capacity of the LDMOS device can be ensured while reducing the size of the body region to reduce the distance between the source region and the drain region (i.e., the LDMOS pitch) in the LDMOS device to reduce the specific on-resistance of the LDMOS device, thereby improving the performance of the LDMOS device.

[0063] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0064] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An LDMOS device, characterized in that: include: A substrate, comprising a front surface and a back surface that are oppositely distributed along a first direction; A body region, located in the substrate, wherein the body region has a groove; A source region, located in the body region, the source region comprising a body region contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body region contact region, the source doping region being in a bent shape and continuously distributed on the sidewall of the trench and a portion of the bottom surface of the trench; A drift region is located in the substrate, and the drift region is distributed outside the body region along a second direction, and the second direction intersects the first direction perpendicularly; The drain region is located in the drift region.

2. The LDMOS device according to claim 1, characterized in that: The substrate and the body region both include first-type doping ions, the drift region and the drain region both include second-type doping ions, and the conductivity type of the first-type doping ions is opposite to the conductivity type of the second-type doping ions; The body contact region includes the first type of doping ions, and the source doping region includes the second type of doping ions.

3. The LDMOS device according to claim 1, characterized in that: The included angle between the side wall of the groove and the bottom surface of the groove is an obtuse angle.

4. The LDMOS device according to claim 1, characterized in that: The width of the trench is smaller than the width of the body region, and the depth of the trench is greater than the depth of the drain region and smaller than the depth of the body region.

5. The LDMOS device according to claim 4, characterized in that: The width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

6. The LDMOS device according to claim 1, characterized in that: Also includes: A gate structure is located on the front side of the substrate and is distributed between the drain region and the source region along the second direction, wherein the gate structure includes a gate dielectric layer covering the front side of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer.

7. The LDMOS device according to claim 6, characterized in that: Also includes: An interlayer dielectric layer, covering the front surface of the substrate and filling the groove; A source lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the source region; a drain lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the drain region; A gate lead-out structure penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate structure.

8. The LDMOS device according to claim 7, characterized in that: Also includes: A source contact layer, covering the surface of the source region and electrically connected to the source lead-out structure; A drain contact layer, covering the surface of the drain region and electrically connected to the drain lead-out structure; The gate contact layer covers the surface of the gate conductive layer and is electrically connected to the gate lead-out structure.

9. A method for forming an LDMOS device, characterized in that: The steps include: Providing a substrate, the substrate comprising a front surface and a back surface that are oppositely distributed along a first direction; forming a body region and a drift region in the substrate, wherein the drift region is distributed outside the body region along a second direction, and the second direction intersects the first direction perpendicularly; forming a groove in the body region; A source region is formed on the sidewalls and the bottom surface of the trench, and a drain region is formed in the drift region, the source region includes a body region contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body region contact region, the source doping region is in a bent shape and is continuously distributed on the sidewalls and part of the bottom surface of the trench.

10. The method for forming an LDMOS device according to claim 9, characterized in that: The substrate includes first type doping ions; the specific steps of forming a body region and a drift region in the substrate include: Implanting the first type of dopant ions into the substrate from the front surface of the substrate to form the body region, wherein the top surface of the body region is flush with the front surface of the substrate; Second type doping ions are injected into the substrate from the front side of the substrate to form the drift region, the top surface of the drift region is flush with the front side of the substrate, and the conductivity type of the first type doping ions is opposite to the conductivity type of the second type doping ions.

11. The method for forming an LDMOS device according to claim 10, characterized in that: The specific steps of forming a trench in the body region include: The body region is etched from the top surface of the body region using a photochemical etching process to form the groove.

12. The method for forming an LDMOS device according to claim 11, characterized in that: The specific step of etching the body region from the top surface of the body region to form the groove further includes: The etching parameters of the photochemical etching process are adjusted so that the angle between the sidewall of the formed groove and the bottom surface of the groove is an obtuse angle.

13. The method for forming an LDMOS device according to claim 9, characterized in that: The width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

14. The method for forming an LDMOS device according to claim 10, characterized in that: Before forming a source region on the sidewalls of the trench and on the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: The first type doping ions are implanted into the body region along the trench.

15. The method for forming an LDMOS device according to claim 10, characterized in that: The specific steps of forming a source region on the sidewalls of the trench and on the bottom surface of the trench, and forming a drain region in the drift region include: The source region including the body contact region and the source doping region is formed on the sidewalls of the trench and the bottom surface of the trench, and the drain region is formed in the drift region, the body contact region includes the first type of doping ions, the source doping region includes the second type of doping ions, and the drain region includes the second type of doping ions.

16. The method for forming an LDMOS device according to claim 9, characterized in that: The front side of the substrate also has a gate structure distributed between the drain region and the source region along the second direction, the gate structure including a gate dielectric layer covering the front side of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer; after forming a source region on the sidewalls of the trench and the bottom surface of the trench, and forming a drain region in the drift region, the following steps are also included: A source contact layer electrically connected to the source region is formed on the surface of the source region, a drain contact layer electrically connected to the drain region is formed on the surface of the drain region, and a gate contact layer electrically connected to the gate conductive layer is formed on the surface of the gate conductive layer.

17. The method for forming an LDMOS device according to claim 16, wherein: After forming a source region on the sidewalls of the trench and on the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: forming an interlayer dielectric layer covering the front surface of the substrate and filling the trench; A source lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the source contact layer, a drain lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the drain contact layer, and a gate lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate contact layer.

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