A metasurface hetero-integrated silicon-based EUV detector design and a preparation method thereof

Abstract

The application discloses a kind of super surface hetero integrated silicon-based EUV detector design and preparation method thereof, the detector is based on super surface light field regulation and control ability and graphene / silicon hetero integrated " ultra shallow junction " characteristics, silicon nano column is lithographically etched on SOI, single-layer graphene is transferred to the top of silicon nano column by using " full dry transfer technology " to realize hetero integration, obtain Schottky barrier structure unit, overcome the key challenge of silicon-based EUV detector development (i.e., how to realize the efficient detection of extremely low transmission depth EUV band, and at the same time complete the effective extraction of light field (wave front) information). The application develops an integrated solution of EUV wave front information and direct " photoelectric " detection function, obtains a device prototype close to the theoretical performance limit, lays a foundation for developing a new type of EUV wave front detection system, and has important significance for developing new EUV detection system key components.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-nano manufacturing, and particularly relates to a metasurface hetero-integrated silicon-based EUV detector design and a preparation method thereof. BACKGROUND

[0002] Silicon-based extreme ultraviolet (EUV, 5-100 nm) photodetectors are widely used in equipment systems such as synchrotron radiation and free electron lasers. The EUV wavefront detector with high detection capability at a wavelength of 13.5 nm is a key sensing element of the workpiece table measurement and control subsystem of an EUV lithography machine, and is used for EUV beam imaging quality detection and wafer positioning. Existing commercialized silicon-based EUV detectors are mostly realized by co-packaging a fluorescent layer and a silicon-based CCD sensor or a “PureB” technology. The former converts incident EUV wavelengths into visible light by using a top fluorescent layer, and then indirectly realizes photodetection by using a bottom CCD, which has high requirements for packaging technology and density, material and process compatibility, and has high technical barriers and preparation costs. Moreover, the response time of such a system is usually difficult to achieve picosecond (ps) accuracy, which is one of the key factors restricting the workpiece table “overlay accuracy” to break through 0.5 nm (TSMC NXE: 3400B EUV lithography machine overlay accuracy ~ 1.8 nm). The latter is based on a “pure boron (PureB)” process to obtain a “super shallow junction” with a junction depth of ~ 10 nm, which can realize direct detection at a wavelength of 13.5 nm and faster response speed. However, the preparation is also complex, and in order to improve the response time and detection efficiency, the area of the device is usually large (to expand the width of the depletion region), which is not conducive to high-density pixel integration. In addition, in order to measure and analyze the deformation information (such as aberration and astigmatism) of the EUV beam modulated by the lens group, a Hartmann or Shack-Hartmann structure (usually a 2D hole array) is additionally integrated and packaged on the top of the above-mentioned detector to form a “wavefront detector”, which poses higher challenges to the preparation process and alignment accuracy. The design of the manufacturability of the metasurface hetero-integrated silicon-based EUV detector, the integrated integration scheme of the EUV wavefront information and the direct “optical-electric” detection function, and the development of the matching high-precision integration and preparation technology are of great significance for the development of new EUV detection system key components. SUMMARY

[0003] The application aims to provide a metasurface hetero-integrated silicon-based EUV detector design and a preparation method thereof.

[0004] The preparation method of the metasurface hetero-integrated silicon-based EUV detector provided by the application comprises the following specific steps:

[0005] (1) Pretreatment of the SOI substrate: immerse the SOI substrate in acetone for 15 min, then clean the SOI substrate in an IPA solution at 60 DEG C for 5 min, and then dry the SOI substrate by blowing N2;

[0006] (2) Preparation of the Si nanocolumn array: after the pretreatment, uniformly coat photoresist on the front surface of the SOI substrate, dry the photoresist at 100 DEG C for 90 s, and then form a circular array structure of the photoresist by electron beam lithography; use the photoresist as a mask, use HBr as an etching gas, and form a Si nanocolumn array metasurface structure by dry etching; spin-coat photoresist on the front surface of the substrate, and repeatedly perform the "lithography-etching" process to remove the edge Si and SiO2, and obtain a peripheral step structure;

[0007] (3) Gate epitaxy: spin-coat photoresist on the surface of the substrate, remove the peripheral photoresist by lithography and development, then epitaxially grow a layer of Si by MOCVD, then immerse the substrate in acetone solution for 10 s to lift off the surface photoresist, and obtain a gate structure;

[0008] (4) Manufacture of shallow trench isolation: spin-coat photoresist on the surface of the substrate, define a pattern by lithography and development, use the photoresist as a mask, and etch a trench structure by dry etching process, then deposit SiO2 by CVD method, immerse the substrate in acetone solution for 10 s to lift off the surface photoresist after the deposition is completed, and the trench is densely filled with SiO2 to form an isolation structure;

[0009] (5) Source and drain epitaxy: spin a layer of photoresist on the substrate surface, define the pattern by developing, then use MOCVD to epitaxially grow a highly doped N-type SiC epitaxial layer. After growth, immerse in acetone solution for 10 seconds to lift off the surface photoresist, forming heavily doped source and drain;

[0010] (6) "Gr / Si heterojunction" super surface integration: based on the full dry transfer technology, transfer single-layer graphene to the top of the silicon nanocolumn, conformally integrate (closely combine the sidewall and top) the "Gr / Si heterojunction" structure, obtain a Schottky barrier super unit, then use ion beam deposition process to deposit a layer of TaBO film on the surface of the single-layer graphene as an antireflection layer, and finally form a TaBO / Graphene / Si nanopillar super surface structure;

[0011] (7) Back thinning: spin a layer of photoresist on the back of the substrate, use the photoresist as a mask to remove the back Si layer by wet etching (KOH and IPA mixed solution) process. After etching, rinse with ultrapure water to remove the etching solution, then immerse in HF solution to remove a certain thickness of SiO2 layer. After etching, rinse with ultrapure water to remove the etching solution, and finally dry.

[0012] (8) Fabrication of back mirror: use ion beam deposition process to deposit Mo / Si multilayer film structure on the thinned area of the back of the substrate, forming a back Mo / Si mirror structure.

[0013] Further, the photoresist of step (1) can be PMMA, SU8, HSQ, ZEP, ARP, UV5, etc.

[0014] Further, the photoetching technology of step (1) can be optical lithography or electron beam lithography.

[0015] Further, the etching process of step (4) can be dry etching or wet etching.

[0016] Further, the transfer technology of step (6) can use full dry transfer technology or multi-step wet process.

[0017] Further, the wet etching of step (7) uses step etching, first etching off the excess Si layer, then etching off a certain thickness of buried oxide layer.

[0018] An ultrathin surface heterojunction integrated silicon-based EUV detector is prepared by the foregoing steps, and the detector structure is sequentially from top to bottom: TaBO antireflection layer (ARC), single-layer graphene, Si nanocolumn array, isolation layer, and back Mo / Si mirror.

[0019] Further, the mirror adopts a Mo / Si multilayer film structure.

[0020] Further, the Si nanocolumn array channel is doped with weak P type.

[0021] As described above, the super surface heterojunction integrated silicon-based EUV detector design and its preparation method have the following beneficial effects:

[0022] (1) The silicon nanocolumn array structure increases the "specific surface area" of the Gr / Si heterojunction structure, combines the optical trapping effect of the super surface, and enhances the absorption and photoelectric conversion capability of the light sensing unit for the incident light;

[0023] (2) The conformal integration of the single-layer graphene and the silicon nanocolumn constructs a Schottky barrier, realizes the full depletion of the silicon nanocolumn and the bottom thin layer, thereby reducing the dark current of the device while increasing the equivalent width of the depletion region, realizing the suppression of the heterojunction capacitance, and further reducing the RC constant to improve the response time (detection speed) of the device to meet the application in high-speed and high-frequency detection scenarios;

[0024] (3) The super surface has strong electromagnetic wave parameter control capability, and when the detector is working, the EUV light field information (such as wavefront information) detection function is implanted at the same time. That is, the super surface composed of a single-layer Gr / Si "super shallow junction" realizes the integration of the EUV wavefront information and the "light-electricity" direct conversion detection function;

[0025] (4) The detector adopts a full-depletion SOI substrate to construct a transistor structure, and places the "Gr / Si heterojunction" photodiode unit at the transistor gate position, which can use the transconductance characteristics (Id-Vg exponential relationship characteristics) of the transistor to internally amplify the photo-generated current of the gate photodiode, further improving the photoelectric conversion capability (responsivity and quantum efficiency) of the entire detection architecture;

[0026] (5) The "Gr / Si heterojunction" super surface can deposit a TaBO anti-reflection layer (ARC) on the top to reduce the reflection of the detector to the 13.5 nm EUV waveband. At the same time, the Mo / Si mirror structure deposited on the back of the light sensing area reflects the EUV light that has passed through the thin silicon channel layer (~ 30 nm) back again, enhancing the absorption characteristics of the super surface light sensing unit and further enhancing the quantum efficiency and photoelectric responsivity of the device. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The energy band structure of the single-layer graphene and the P-type silicon channel, and the energy band diagram of the Schottky barrier formed after the two are contacted;

[0028] Figure 2It is a schematic diagram of SOI substrate structure, and the three-layer structure is Si, SiO2 and Si respectively;

[0029] Figure 3 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the silicon nano column array structure prepared in the specific step (2) is shown.

[0030] Figure 4 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the gate formed by epitaxy in the specific step (3) is shown.

[0031] Figure 5 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the shallow trench isolation structure formed by etching groove and depositing SiO2 in the specific step (4) is shown.

[0032] Figure 6 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the heavily doped source and drain formed by epitaxy in the specific step (5) is shown.

[0033] Figure 7 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the "Gr / Si heterojunction" structure formed by transferring single layer graphene with Si nano column array structure by "full dry transfer technology" in the specific step (6) is shown.

[0034] Figure 8 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the structure after back thinning by wet etching process in the specific step (7) is shown.

[0035] Figure 9 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the mirror structure formed by depositing multilayer Mo / Si film by ion beam deposition process in the specific step (8) is shown.

[0036] Figure 10 It is a preparation method of super surface hetero integrated silicon based EUV detector, and the structure schematic diagram of the structure of depositing multilayer Mo / Si film by ion beam deposition process in the specific step (9) is shown. DETAILED DESCRIPTION

[0037] In order to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application will be described in detail below in combination with the drawings. It should be clear that the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0038] An ultrathin surface hetero-integrated silicon-based EUV detector, the detector structure from top to bottom in turn is: TaBO anti-reflection layer (ARC), single-layer graphene, Si nanocolumn array, isolation layer, mirror.

[0039] Further, the mirror adopts Mo / Si multilayer film structure.

[0040] Further, the Si nanocolumn array channel inside adopts weak P-type doping.

[0041] An ultrathin surface hetero-integrated silicon-based EUV detector preparation method, the preparation steps are as follows:

[0042] (1) spin coating photoresist on SOI substrate, using photolithography technology to expose photoresist film;

[0043] (2) After development, using dry etching technology to etch SOI substrate with photoresist as mask to obtain silicon nanocolumn array structure;

[0044] (3) using MOCVD method to epitaxially grow gate structure;

[0045] (4) using photolithography and etching process to define pattern, filling oxide in shallow trench to form shallow trench isolation (STI);

[0046] (5) using MOCVD method to epitaxially grow highly doped source and drain;

[0047] (6) based on dry transfer technology, transfer single-layer graphene to the top of silicon nanocolumn and deposit a layer of TaBO film using ion beam coating process;

[0048] (7) using wet etching process to thin the back of the device;

[0049] (8) using ion beam coating process, depositing back Mo / Si mirror.

[0050] Further, the photoresist of step (1) can be PMMA, SU8, HSQ, ZEP, ARP, UV5 and other types of photoresist materials;

[0051] Further, the photolithography technology of step (1) can be optical lithography or electron beam lithography;

[0052] Further, the etching process of step (4) can be dry etching or wet etching;

[0053] Further, the transfer technology of step (6) adopts full dry transfer technology or multi-step wet process;

[0054] Further, the wet etching in step (7) is to be carried out by step etching, i.e. first etching off the excess Si layer, and then etching off a certain thickness of the buried oxide layer.

[0055] Embodiment 1: A metasurface hetero-integrated silicon-based EUV detector

[0056] Step one: clean the SOI wafer, soak the SOI wafer in acetone for 15 min, then ultrasonic clean in 60℃ IPA solution for 5 min, and dry with N2.

[0057] Step two: spin a layer of 200 nm ARP6200 photoresist on the SOI substrate, and then perform multiple times of exposure-development-dry etching based on an electron beam exposure system and a plasma etching device to obtain a silicon nano-pillar array structure.

[0058] Step three: epitaxially grow a Si gate on the edge by MOCVD, then perform a shallow trench isolation process, etch a shallow trench structure by using Si3N4 as a hard mask and photolithography, then deposit SiO2 as an isolation layer in the trench by PECVD, and then planarize the SiO2 by chemical mechanical polishing.

[0059] Step four: epitaxially grow an N-type SiC high-density epitaxial layer as a source and a drain of the device by MOCVD.

[0060] Step five: based on a full-dry transfer technology, use a PDMS template as a "carrier" to cover the graphene, so as to obtain a graphene / PDMS stack structure, transfer it to the top of the silicon nano-pillar, release the PDMS, realize the common integration of graphene and silicon nano-pillar, obtain a Schottky barrier supercell, and deposit a layer of TaBO film as an antireflection layer.

[0061] Step six: thin the back of the device by a wet etching process, etch to the buried oxide layer by using KOH solution, and etch off a certain amount of SiO2 by using HF solution.

[0062] Step seven: use ion beam deposition (IBD) to deposit a multilayer Mo / Si film structure on the back of the device as a mirror.

[0063] The above specific embodiments, working principles and preparation methods further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating a metasurface heterogeneous integrated silicon-based EUV detector, characterized in that, The specific steps are as follows: SOI substrate pretreatment: Immerse the SOI substrate in acetone, then ultrasonically clean it with IPA solution at 60°C, and then dry it with N2. Fabrication of Si nanopillar array: After pretreatment, the SOI substrate is uniformly coated with photoresist on the front side. After drying at 100°C, a circular array structure of photoresist is formed by electron beam lithography. On the front side of the substrate, using photoresist as a mask and HBr as the etching gas, a Si nanopillar array metasurface structure is formed by dry etching. Photoresist is spin-coated on the front side of the substrate, and the "photolithography-etching" process is repeated to remove Si and SiO2 at the edges to obtain the peripheral step structure. Gate epitaxy: Photoresist is spin-coated on the substrate surface, photolithography and development are used to remove the outer photoresist, and then a layer of Si is epitaxially grown using MOCVD. After that, the substrate is immersed in acetone solution for 10 seconds to remove the surface photoresist and obtain the gate structure. Fabrication of shallow trench isolation: A layer of photoresist is spin-coated on the substrate surface and the pattern is defined by photolithography and development. The trench structure is formed by dry etching using the photoresist as a mask. Then, SiO2 is deposited by CVD. After deposition, the substrate is immersed in acetone solution for 10 seconds to remove the surface photoresist. The trench is densely filled with SiO2 to form an isolation structure. Source and drain epitaxy: A layer of photoresist is spin-coated on the substrate surface and the pattern is defined by photolithography and development. Then, an N-type SiC high-doped epitaxial layer is grown using MOCVD. After growth, the substrate is immersed in acetone solution for 10 seconds to remove the surface photoresist, forming heavily doped source and drain electrodes. "Gr / Si heterojunction" metasurface integration: Based on the all-dry transfer technology, monolayer graphene is transferred to the top of silicon nanopillars. The monolayer graphene and Si nanopillars are conformally integrated to form a "Gr / Si heterojunction" structure to obtain a Schottky barrier metaunit. Then, an ion beam deposition process is used to deposit a TaBO film on the surface of the monolayer graphene as an anti-reflection layer, finally forming a TaBO / Graphene / Si nanopillars metasurface structure. Backside thinning: A layer of photoresist is spin-coated on the backside of the substrate. Using the photoresist as a mask, a wet etching process is used to remove the backside Si layer. After etching, the substrate is rinsed in ultra-clean water to remove the etching solution. Then, it is placed in HF solution to remove a certain amount of SiO2 layer. After etching, the substrate is rinsed in ultra-clean water to remove the etching solution. Finally, it is dried. Fabrication of the back reflector: An ion beam deposition process is used to deposit a Mo / Si multilayer film structure in the thinned area on the back of the substrate to form the back Mo / Si reflector structure.

2. The method for fabricating a metasurface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that, After the pretreatment of the SOI substrate in the process of preparing the Si nanopillar array is completed, the photoresist is uniformly coated on the front side with PMMA, SU8, HSQ, ZEP, ARP and UV5 photoresist materials.

3. The metasurface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that, The Si nanopillar array channel is weakly doped with p-type.

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