Display device

Abstract

A display device includes: a substrate including a display area and a peripheral area surrounding the display area; a light emitting element disposed in the display area and a pixel circuit configured to drive the light emitting element; a fan-out wiring electrically connected to the pixel circuit and arranged in the peripheral area; a power input wiring and a power transfer wiring separated from each other in the peripheral area; and a connection member connected to the power input wiring through the first contact hole and to the power transfer wiring through the second contact hole. The connection member at least partially overlaps the fan-out wiring, and a center distance between the first contact holes is not constant.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0150296 filed in the Korean Intellectual Property Office on November 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device in which a high-quality image can be displayed. Background Art

[0004] Typically, a display device includes a light-emitting element and a pixel circuit for controlling an electrical signal applied to the light-emitting element. The pixel circuit includes a thin film transistor (TFT), a capacitor, and a plurality of wirings. The light-emitting element is configured to emit light in response to an electrical signal transmitted from the wiring.

[0005] For high integration and high reliability of such a display device, active research has been conducted on the arrangement of wirings and the like not only in a display region but also in a peripheral region around the display region. Summary of the invention

[0006] One or more embodiments include a display device with high reliability in which a high-quality image can be displayed. However, such technical features are examples, and one or more embodiments are not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area surrounding the display area; a light emitting element arranged in the display area and a pixel circuit configured to drive the light emitting element; a fan-out wiring electrically connected to the pixel circuit and arranged in the peripheral area; a power input wiring and a power transmission wiring separated from each other in the peripheral area; and a connection member connected to the power input wiring through a first contact hole and connected to the power transmission wiring through a second contact hole. The connection member at least partially overlaps the fan-out wiring, and the center distance between the first contact holes is not constant.

[0009] The center distance between the second contact holes may not be constant.

[0010] The first contact hole may include a 1-1 contact hole above the fan-out wiring and a 1-2 contact hole not above the fan-out wiring. A center distance between the 1-1 contact hole and the 1-2 contact hole adjacent to each other between which an edge of the fan-out wiring is located may be greater than a center distance between the 1-1 contact holes overlapping the fan-out wiring and adjacent to each other.

[0011] The number of the first contact holes and the number of the second contact holes may be different from each other.

[0012] The first contact hole may include a 1-1th contact hole above the fan-out wiring. The 1-1th contact hole may be retracted from an edge of the fan-out wiring at a specific interval in a plan view.

[0013] The pitch may be at least about 5 μm.

[0014] The pixel circuit may include: a first thin film transistor including a first semiconductor layer and a first gate electrode; and a second thin film transistor including a second semiconductor layer and a second gate electrode. The first semiconductor layer may be arranged on a layer different from a layer on which the second semiconductor layer is arranged.

[0015] At least some of the fan-out wirings may be arranged on the same layer as a layer on which the first gate electrode is arranged.

[0016] The connection member may be arranged on the same layer as a layer on which the second gate electrode is arranged.

[0017] The display device may further include: an organic insulating layer disposed on the power input wiring and the power transmission wiring. The organic insulating layer may include an opening over at least a portion of the connection member.

[0018] The first contact holes may be arranged in two rows in the first direction.

[0019] The second contact holes may be arranged in two rows in the first direction.

[0020] The power input wiring may include a first conductive layer and a second conductive layer stacked one after another.

[0021] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area surrounding the display area; a light-emitting element arranged in the display area and a pixel circuit configured to drive the light-emitting element; a thin film encapsulation layer covering the light-emitting element and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; a fan-out wiring electrically connected to the pixel circuit and arranged in the peripheral area; a connecting member overlapping the fan-out wiring; an interlayer insulating layer covering the connecting member and having a first contact hole and a second contact hole defined in the interlayer insulating layer; and a power input wiring and a power transmission wiring separated from each other in the peripheral area. The power input wiring is connected to the connecting member through the first contact hole, the power transmission wiring is connected to the connecting member through the second contact hole, and the number of the first contact holes is different from the number of the second contact holes.

[0022] The first contact hole may include a 1-1th contact hole above the fan-out wiring. The 1-1th contact hole may be retracted from an edge of the fan-out wiring at a specific interval in a plan view.

[0023] The first contact hole may include a 1-1 contact hole above the fan-out wiring and a 1-2 contact hole not above the fan-out wiring. A center distance between the 1-1 contact hole and the 1-2 contact hole adjacent to each other between which an edge of the fan-out wiring is located may be greater than a center distance between the 1-1 contact holes overlapping the fan-out wiring and adjacent to each other.

[0024] The pixel circuit may include: a first thin film transistor including a first semiconductor layer and a first gate electrode; and a second thin film transistor including a second semiconductor layer and a second gate electrode. The first semiconductor layer may be arranged on a layer different from a layer on which the second semiconductor layer is arranged.

[0025] At least some of the fan-out wirings may be arranged on the same layer as a layer on which the first gate electrode is arranged.

[0026] The connection member may be arranged on the same layer as a layer on which the second gate electrode is arranged.

[0027] The display device may further include: an organic insulating layer disposed on the power input wiring and the power transmission wiring. The organic insulating layer may include an opening over at least a portion of the connection member.

[0028] The first inorganic encapsulating layer may be disposed in the opening of the organic insulating layer and may be in direct contact with the interlayer insulating layer.

[0029] The first contact holes may be arranged in two rows in the first direction.

[0030] The second contact holes may be arranged in two rows in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent from the following description in conjunction with the accompanying drawings.

[0032] Figure 1 is a schematic plan view of a portion of a display device according to an embodiment.

[0033] Figure 2 yes Figure 1 Schematic side view of a display device.

[0034] Figure 3A and Figure 3B Each is an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment.

[0035] Figure 4 is a schematic cross-sectional view of a portion of a display panel according to an embodiment.

[0036] Figure 5 yes Figure 1 An enlarged conceptual diagram of Area A.

[0037] Figure 6 yes Figure 5 An enlarged conceptual diagram of area B.

[0038] Figure 7 is along Figure 6 The line II-II' is intercepted Figure 5 Schematic cross-sectional view of region B.

[0039] Figure 8 is along Figure 6 The line III-III' is intercepted Figure 5 Schematic cross-sectional view of region B.

[0040] Fig. 9 is an enlarged plan conceptual diagram of a portion of a display device according to an embodiment.

[0041] Fig.10 is an enlarged plan conceptual diagram of a portion of a display device according to an embodiment.

[0042] Fig.11 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0043] Fig.12 is an enlarged plan conceptual diagram of a portion of a display device according to an embodiment.

[0044] Fig.13 is along Fig.12 The line IV-IV' is intercepted Fig.12 Schematic cross-sectional view of a portion of a display device. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals refer to the same elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the following only describes embodiments to explain aspects of this specification with reference to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in association. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] Since the specification allows for various variations and numerous embodiments, specific embodiments will be illustrated in the drawings and described in the written description. The effects and features of one or more embodiments and methods for achieving them will become apparent from the detailed description of the one or more embodiments described below in conjunction with the drawings. However, the present embodiments may have different forms and should not be construed as being limited to the description set forth herein.

[0047] One or more embodiments will be described in more detail below with reference to the accompanying drawings. Those elements that are the same or correspond to each other are given the same reference numerals regardless of the figure numbers, and redundant descriptions thereof are omitted.

[0048] It will be understood that when an element such as a layer, film, region, or plate is referred to as being "on" another element, the element may be directly on the other element, or there may be intervening elements between the element and the other element. In addition, the size of the elements in the drawings may be exaggerated or reduced for ease of explanation. For example, since the size and thickness of the elements in the drawings are arbitrarily illustrated for ease of explanation, the following embodiments are not limited thereto.

[0049] Direction x, direction y, and direction z are not limited to directions corresponding to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, direction x, direction y, and direction z can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0050] Although terms such as "first" and "second" may be used to describe various elements, such elements must not be limited to the above terms. The above terms are only used to distinguish one element from another element.

[0051] It will be further understood that the terms “comprising,” “including,” and “having” as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0052] As used herein, the expression "A and / or B" refers to A, B, or A and B. In addition, the expression "at least one of A and B" refers to A, B, or A and B.

[0053] It will be further understood that when layers, regions or elements are referred to as being connected to each other, they may be directly connected to each other, or they may be indirectly connected to each other through intervening layers, regions or elements therebetween. For example, when layers, regions or elements are referred to as being electrically connected to each other, they may be directly electrically connected to each other, or they may be indirectly electrically connected to each other through intervening layers, regions or elements therebetween.

[0054] Figure 1 is a schematic plan view of a portion of a display device according to an embodiment. Figure 2 yes Figure 1 A schematic side view of a display device according to this embodiment. The display device according to this embodiment may have the following Figure 2 However, in Figure 1 , for convenience, the portion is shown as not bent.

[0055] The display device according to this embodiment may include Figure 1 and Figure 2 The display panel 10 shown in FIG. The display device may be any display device including the display panel 10. For example, the display device may be various products such as a smart phone, a tablet computer, a notebook computer, a television, or a billboard.

[0056] The display panel 10 includes a display area DA in which a plurality of pixels are located and a peripheral area PA outside the display area DA. It can be understood that the substrate 100 included in the display device includes the display area DA and the peripheral area PA. The peripheral area PA includes components such as a driver chip 20 or a printed circuit board 30 (in the Figure 2 The first scan driving circuit SDRV1, the second scan driving circuit SDRV2, and the common voltage supply wiring 11 may also be arranged in the peripheral area PA.

[0057] The driving chip 20 may include an integrated circuit configured to drive the display panel 10. The integrated circuit may be a data driving integrated circuit configured to generate a data signal, but one or more embodiments are not limited thereto. The driving chip 20 may be installed in the peripheral area PA to be adjacent to the edge of the substrate 100.

[0058] Figure 1It can be understood as a plan view showing a substrate, etc. during a manufacturing process. In an electronic device such as a final display device or a smart phone including a display device, a portion of the substrate, etc. may be bent to reduce the area of ​​the peripheral area PA recognized by the user. For example, the peripheral area PA may include a bending area BA so that the bending area BA may be between the pad area PADA and the display area DA.

[0059] In this case, if Figure 2 As shown in , the substrate 100 may be bent in the bending area BA, and therefore, the first area A1 on one side of the bending area BA and the second area A2 on the other side of the bending area BA may overlap each other. For example, the substrate 100 may be bent in the bending area BA, and therefore, at least a portion of the pad area PADA may overlap the display area DA. Although the driving chip 20 described above is mounted on the same surface as the display surface of the display area DA, when the display panel 10 is bent in the bending area BA, the driving chip 20 may be placed on the rear surface of the display area DA.

[0060] The display panel 10 may be curved in the curved area BA, and therefore, when the display device is viewed from the front (in the direction -z), the peripheral area PA may not be visible, or even when the peripheral area PA is visible, the visible area of ​​the peripheral area PA may be reduced. One or more embodiments are not limited to curved display devices, and may also be applied to non-curved display devices.

[0061] The substrate 100 may include various materials having flexible or bendable properties, and for example, may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. For example, the substrate 100 may be modified variously to have a multilayer structure including two layers including the above polymer resin and a barrier layer between the two layers and including an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In addition, when the substrate 100 is not bendable, the substrate 100 may include glass.

[0062] The edge of the display area DA may have an overall shape similar to a rectangle or a square. Therefore, the substrate 100 may also have an overall shape similar to a rectangle or a square. In an embodiment, the edge of the display area DA may have a shape such as a circle, an ellipse or other polygons.

[0063] Although an organic light-emitting display device is described below as an example of a display device according to an embodiment, the display device described herein is not limited thereto. In an embodiment, the display device described herein may be a display device such as an inorganic light-emitting display (or an inorganic electroluminescent (EL) display) or a quantum dot light-emitting display. For example, the emission layer of the light-emitting element included in the display device may include an organic material or an inorganic material. In an embodiment, the display device may include an emission layer and quantum dots on the path of light emitted from the emission layer.

[0064] A plurality of pixels are in the display area DA. Each of the pixels refers to a sub-pixel and may include a light-emitting element such as an organic light-emitting diode (OLED) and a pixel circuit electrically connected to the light-emitting element. For example, the pixel may emit red light, green light, blue light, or white light. The pixel may be electrically connected to an external circuit arranged in the peripheral area PA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, and the common voltage supply wiring 11 may be arranged in the peripheral area PA.

[0065] The first scan drive circuit SDRV1 may extend in the direction y at the edge of the substrate 100. The first scan drive circuit SDRV1 may be configured to provide a scan signal to the pixel through a scan line (not shown) extending in the direction x into the display area DA. The second scan drive circuit SDRV2 may be symmetrical with the first scan drive circuit SDRV1, and the display area DA is between the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. Some of the pixels arranged in the display area DA may be electrically connected to the first scan drive circuit SDRV1, and the other pixels may be electrically connected to the second scan drive circuit SDRV2. In some cases, the second scan drive circuit SDRV2 may be omitted, and all of the pixels arranged in the display area DA may be electrically connected to the first scan drive circuit SDRV1.

[0066] In addition, an emission control driving circuit (not shown) may be disposed at one side of the first scan driving circuit SDRV1 or the second scan driving circuit SDRV2, and an emission control signal may be provided to the pixel through an emission control line (not shown) substantially parallel to the scan line.

[0067] A plurality of pads may be in the pad area PADA of the display panel 10. The plurality of pads may not be covered by the insulating layer but may be exposed and electrically connected to the printed circuit board 30. That is, the pads of the printed circuit board 30 may be electrically connected to the plurality of pads of the display panel 10.

[0068] The printed circuit board 30 is configured to transmit a signal or power of a controller (not shown) to the display panel 10. The control signal generated by the controller may be transmitted to the driving chip 20, the first scan driving circuit SDRV1, and the second scan driving circuit SDRV2 through the printed circuit board 30. In addition, the controller may provide a common voltage VSS (at Figure 3A and Figure 3B ), and can provide a driving voltage VDD (in the display area DA) to a driving power wiring (not shown) extending in the direction y and extending into the display area DA. Figure 3A and Figure 3B For reference, the common voltage supply wiring 11 may have a partially open shape, and thus may have a shape that partially surrounds the display area DA.

[0069] The controller may generate a data signal, and the generated data signal may be transmitted to the pixel through the driving chip 20 and the data line DL. For reference, the term "line" may refer to "wiring." This also applies to the following embodiments and modifications thereof.

[0070] Figure 3A and Figure 3B Each is an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment.

[0071] refer to Figure 3A , the light emitting element LED corresponding to the sub-pixel may be electrically connected to the pixel circuit PC, and the pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel circuit PC may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line SL1 and a data line DL, and the voltage line may include a first voltage line VDDL.

[0072] The second transistor T2 may be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 may be configured to provide a first scan signal GW to a gate electrode of the second transistor T2. The second transistor T2 may be configured to transfer a data signal Dm input from the data line DL to the first transistor T1 according to the first scan signal GW input from the first scan line SL1.

[0073] The storage capacitor Cst may be electrically connected to the second transistor T2 and the first voltage line VDDL, and may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a driving voltage VDD supplied by the first voltage line VDDL.

[0074] The first transistor T1 is a driving transistor and can be configured to control a driving current flowing through the light emitting element LED. The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can be configured to control a driving current flowing from the first voltage line VDDL to the light emitting element LED in response to a value of a voltage stored in the storage capacitor Cst. The light emitting element LED can emit light with a specific brightness according to the driving current. A first electrode of the light emitting element LED can be electrically connected to the first transistor T1, and a second electrode of the light emitting element LED can be electrically connected to a second voltage line VSSL configured to supply a common voltage VSS.

[0075] Figure 3A The pixel circuit PC is shown to include two transistors T1, T2 and one storage capacitor Cst. However, in embodiments, the pixel circuit PC may include three or more transistors.

[0076] refer to Figure 3B , the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0077] The pixel circuit PC is electrically connected to the signal line and the voltage line. The signal line may include a gate line such as the first scan line SL1, the second scan line SL2, the third scan line SL3 and the emission control line EML, and the data line DL. The voltage line may include the first initialization voltage line VIL1 and the second initialization voltage line VIL2 and the first voltage line VDDL.

[0078] The first voltage line VDDL may be configured to transmit the driving voltage VDD to the first transistor T1. The first initialization voltage line VIL1 may be configured to transmit the first initialization voltage Vint for initializing the first transistor T1 to the pixel circuit PC. The second initialization voltage line VIL2 may be configured to transmit the second initialization voltage Vaint for initializing the first electrode of the light emitting element LED to the pixel circuit PC.

[0079] The first transistor T1 may be electrically connected to the first voltage line VDDL via the fifth transistor T5 and may be electrically connected to the light emitting element LED via the sixth transistor T6. The first transistor T1 functions as a driving transistor and is configured to receive the data signal Dm and supply a driving current to the light emitting element LED according to a switching operation of the second transistor T2.

[0080] The second transistor T2 is a data writing transistor and is electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 is electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 is turned on according to the first scan signal GW received through the first scan line SL1 to perform a switching operation for transmitting the data signal Dm transmitted through the data line DL to the first node N1.

[0081] The third transistor T3 is electrically connected to the first scan line SL1 and is electrically connected to the light emitting element LED via the sixth transistor T6. The third transistor T3 may be turned on according to the first scan signal GW received through the first scan line SL1 to diode-connect the first transistor T1.

[0082] The fourth transistor T4 is a first initialization transistor and is electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 is turned on according to the third scan signal GI received through the third scan line SL3 to transfer the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1 and initialize the voltage of the gate electrode of the first transistor T1. The third scan signal GI may correspond to a first scan signal of another pixel circuit arranged in a previous row of the corresponding pixel circuit PC.

[0083] The fifth transistor T5 may be an operation control transistor, and the sixth transistor T6 may be an emission control transistor. The fifth transistor T5 and the sixth transistor T6 are electrically connected to the emission control line EML, and are simultaneously turned on according to the emission control signal EM received through the emission control line EML to form a current path allowing a driving current to flow in a direction from the first voltage line VDDL to the light emitting element LED.

[0084] The seventh transistor T7 is a second initialization transistor and may be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 may be turned on according to the second scan signal GB received through the second scan line SL2, and may be configured to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light emitting element LED and initialize the first electrode of the light emitting element LED.

[0085] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the first voltage line VDDL. The storage capacitor Cst can maintain a voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to a voltage difference between both ends connected to the first voltage line VDDL and the gate electrode of the first transistor T1, respectively.

[0086] exist Figure 3B In the embodiment, the plurality of transistors T1 to T7 are all shown as P-type, but one or more embodiments are not limited thereto. Various modifications may be made, for example, at least one of the plurality of transistors T1 to T7 may be N-type.

[0087] In an embodiment, at least one of the plurality of transistors T1 to T7 may include a semiconductor layer including oxide, and the other transistors may include a semiconductor layer including silicon. For example, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor layer, and the other transistors may include a silicon semiconductor layer. However, one or more embodiments are not limited thereto. All of the plurality of transistors T1 to T7 may include a silicon semiconductor layer.

[0088] Figure 4 is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment, and is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment. Figure 1 A schematic cross-sectional view of a portion corresponding to line II'.

[0089] refer to Figure 4 , the pixel circuit PC may be disposed on the substrate 100 of the display panel 10, and the organic light emitting diode OLED may be arranged as a light emitting element connected to the pixel circuit PC. In addition, a bottom conductive layer BML may be further disposed between the substrate 100 and the pixel circuit PC.

[0090] The pixel circuit PC according to the present embodiment may include a first thin film transistor TFT1 including a silicon semiconductor and a second thin film transistor TFT2 including an oxide semiconductor. The pixel circuit PC may further include a storage capacitor Cst.

[0091] The first thin film transistor TFT1 includes a first semiconductor layer AS1 including a silicon semiconductor and a first gate electrode GE1 insulated from the first semiconductor layer AS1. The first thin film transistor TFT1 may include a first source electrode SE1 and / or a first drain electrode DE1 connected to the first semiconductor layer AS1. The first thin film transistor TFT1 may be used as a driving thin film transistor.

[0092] The second thin film transistor TFT2 includes a second semiconductor layer AO2 including an oxide semiconductor and a second gate electrode GE2 insulated from the second semiconductor layer AO2. The second thin film transistor TFT2 may include a second source electrode SE2 and / or a second drain electrode DE2 connected to the second semiconductor layer AO2. The second thin film transistor TFT2 may be used as a switching thin film transistor. In an embodiment, the second thin film transistor TFT2 may be any thin film transistor other than a driving thin film transistor.

[0093] According to an embodiment, the first semiconductor layer AS1 of the first thin film transistor TFT1 serving as a driving thin film transistor may include polysilicon having excellent reliability, and the second semiconductor layer AO2 of the second thin film transistor TFT2 corresponding to the switching thin film transistor may include an oxide semiconductor having low leakage current.

[0094] More specifically, a driving thin film transistor that directly affects the brightness of a light emitting element may include a semiconductor layer formed of polysilicon having high reliability, thereby realizing a high-resolution display device.

[0095] The thin film transistor including the oxide semiconductor has high carrier mobility and low leakage current, and therefore, the voltage drop is not noticeable even when the driving time is long. This means that even during low-frequency driving, the thin film transistor including the oxide semiconductor does not have noticeable color changes in the image due to the voltage drop, which makes low-frequency driving possible. Therefore, compared with the case where all the thin film transistors included in the pixel circuit PC include a semiconductor layer formed of polycrystalline silicon, when the pixel circuit PC includes a thin film transistor including a semiconductor layer formed of an oxide semiconductor, power consumption can be reduced.

[0096] In the present embodiment, at least one of the other thin film transistors except the driving thin film transistor may include a semiconductor layer formed of an oxide semiconductor, thereby reducing power consumption of the display device.

[0097] In addition, according to the present embodiment, the bottom conductive layer BML overlapping the first thin film transistor TFT1 is disposed under the first thin film transistor TFT1. A constant voltage can be applied to the bottom conductive layer BML. Since the bottom conductive layer BML is disposed under the first thin film transistor TFT1, the first thin film transistor TFT1 can be less affected by surrounding interference signals to have improved reliability.

[0098] In this embodiment, it is assumed that an organic light emitting diode is used as a light emitting element. However, in the embodiment, an inorganic light emitting element or a quantum dot light emitting element may be used as a light emitting element.

[0099] Hereinafter, a structure in which configurations included in the display panel 10 are stacked one by one will be described.

[0100] The substrate 100 may include an insulating material such as glass, quartz or a polymer resin. The substrate 100 may be a rigid substrate, or a flexible substrate that is bendable, foldable or rollable. The substrate 100 may have a single-layer structure or a multi-layer structure including the above materials. In the case of a multi-layer structure, the substrate 100 may further include an inorganic layer. In some embodiments, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0101] The buffer layer 111 may be located on the substrate 100 to reduce or prevent penetration of foreign matter, moisture, or external air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic compound, and may have a single-layer structure or a multi-layer structure including an inorganic material and / or an organic material. In some embodiments, the buffer layer 111 may include silicon oxide (SiO 2 ) or silicon nitride (SiN x ).

[0102] The bottom conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The bottom conductive layer BML may include a conductive material. In some embodiments, the bottom conductive layer BML may include a transparent conductive material. For example, the bottom conductive layer BML may include a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The bottom conductive layer BML may overlap with the first thin film transistor TFT1, and a constant voltage may be applied to the bottom conductive layer BML. A barrier layer (not shown) to prevent penetration of external air may be further between the substrate 100 and the bottom conductive layer BML. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic compound, and may have a single-layer structure or a multi-layer structure including an inorganic material and / or an organic material.

[0103] The first semiconductor layer AS1 including a silicon semiconductor may be disposed on the buffer layer 111, and the first semiconductor layer AS1 may include polycrystalline silicon or amorphous silicon. The first semiconductor layer AS1 may include a channel region and source and drain regions doped with impurities.

[0104] The first gate insulating layer 112 may cover the first semiconductor layer AS1. The first gate insulating layer 112 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ) or the like. The first gate insulating layer 112 may have a single layer structure or a multi-layer structure including the above-mentioned inorganic insulating material.

[0105] The first gate electrode GE1 is disposed on the first gate insulating layer 112 to overlap the first semiconductor layer AS1. The first gate electrode GE1 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers. As an example, the first gate electrode GE1 may include a single Mo layer.

[0106] The second gate insulating layer 113 may cover the first gate electrode GE1. The second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ) etc. The second gate insulating layer 113 may have a single layer structure or a multi-layer structure including the above-mentioned inorganic insulating material.

[0107] The storage capacitor Cst may overlap the first gate electrode GE1. The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The second gate insulating layer 113 may be disposed between the first electrode CE1 and the second electrode CE2. In this regard, the first gate electrode GE1 may be used not only as a gate electrode of the first thin film transistor TFT1, but also as a first electrode CE1 of the storage capacitor Cst. That is, the first gate electrode GE1 and the first electrode CE1 may be integrally formed as a single body. The second electrode CE2 is disposed on the second gate insulating layer 113 to at least partially overlap the first electrode CE1.

[0108] The first wiring WL1 and the bottom gate electrode BGE may be disposed on the second gate insulating layer 113. The first wiring WL1 may be configured to transmit a signal to be transmitted to the first thin film transistor TFT1 or the second thin film transistor TFT2. The bottom gate electrode BGE may overlap the second semiconductor layer AO2 of the second thin film transistor TFT2 and apply a gate signal to the second thin film transistor TFT2. In this case, the second thin film transistor TFT2 may have a dual gate electrode structure in which gate electrodes are disposed above and below the second semiconductor layer AO2.

[0109] The bottom gate electrode BGE may be provided as a portion of the first wiring WL1. In this case, the first wiring WL1 may be configured to transmit a gate signal to the second thin film transistor TFT2.

[0110] The second gate insulating layer 113 may include an inorganic material including oxide or nitride. For example, the second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 )wait.

[0111] The first interlayer insulating layer 115 may cover the second electrode CE2, the first wiring WL1, and the bottom gate electrode BGE. The first interlayer insulating layer 115 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ) etc. The first interlayer insulating layer 115 may have a single layer structure or a multilayer structure including the above-mentioned inorganic insulating material.

[0112] The second semiconductor layer AO2 including an oxide semiconductor may be disposed on the first interlayer insulating layer 115. The second semiconductor layer AO2 may include a channel region and a source region and a drain region arranged on both sides of the channel region. The second semiconductor layer AO2 may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti), and zinc (Zn). In some embodiments, the second semiconductor layer AO2 may be an IGZO (In-Ga-Zn-O) semiconductor containing metals such as indium (In) and gallium (Ga) in ZnO.

[0113] The source region and the drain region of the second semiconductor layer AO2 may be formed, for example, by a conductive process that adjusts the carrier concentration of the oxide semiconductor. For example, the source region and the drain region of the second semiconductor layer AO2 may be formed by increasing the carrier concentration of the oxide semiconductor using a plasma treatment using, for example, a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0114] The second gate electrode GE2 may be disposed on the second semiconductor layer AO2 and a second interlayer insulating layer 117 may be disposed between the second semiconductor layer AO2 and the second gate electrode GE2. The second gate electrode GE2 overlaps the second semiconductor layer AO2 and is insulated from the second semiconductor layer AO2 by the second interlayer insulating layer 117.

[0115] The second interlayer insulating layer 117 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ). The second interlayer insulating layer 117 may have a single layer structure or a multilayer structure including the above-mentioned inorganic insulating material.

[0116] A third interlayer insulating layer 119 may be disposed on the second gate electrode GE2, and a first source electrode SE1 and / or a first drain electrode DE1 connected to the first semiconductor layer AS1 and a second source electrode SE2 and / or a second drain electrode DE2 connected to the second semiconductor layer AO2 may be disposed on the third interlayer insulating layer 119. In addition, a data line for transmitting a data signal and a driving voltage line for transmitting a driving voltage may be disposed on the third interlayer insulating layer 119. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, or the second drain electrode DE2 may be connected to the data line or the driving voltage line directly or through another thin film transistor.

[0117] The third interlayer insulating layer 119 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ). The third interlayer insulating layer 119 may have a single layer structure or a multilayer structure including the above-mentioned inorganic insulating material.

[0118] The first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may include a highly conductive material such as a metal, a conductive oxide, etc. For example, the first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may have a single-layer structure or a multi-layer structure including aluminum (Al), copper (Cu), titanium (Ti), etc. In some embodiments, the first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may have a three-layer structure of titanium, aluminum, and titanium (Ti / Al / Ti) sequentially disposed one after another.

[0119] The organic insulating layer 120 is disposed on the first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2. The organic insulating layer 120 may include a single layer or a multilayer. For example, the organic insulating layer 120 may have a first organic insulating layer 121 and a second organic insulating layer 123 stacked one after another. In this case, the second wiring WL2 may be disposed between the first organic insulating layer 121 and the second organic insulating layer 123, and thus, the integration density may be improved.

[0120] The organic insulating layer 120 may include a general commercial polymer such as polyimide, polycarbonate (PC), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as photosensitive polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer or a vinyl alcohol polymer.

[0121] In an embodiment, the organic insulating layer 120 may include a siloxane-based organic material. The siloxane-based organic material may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, and polydimethylsiloxane. The organic insulating layer 120 may be used as a protective layer covering the thin film transistors TFT1 and TFT2.

[0122] An organic light emitting diode OLED including a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 disposed between the pixel electrode 310 and the opposing electrode 330 and including an emission layer may be on the organic insulating layer 120 .

[0123] The pixel electrode 310 may be connected to the first drain electrode DE1 through a contact hole defined in the organic insulating layer 120, and may be connected to the first drain region of the first thin film transistor TFT1 through the first drain electrode DE1. The pixel electrode 310 may be directly connected to the first thin film transistor TFT1, or may be indirectly connected to the first thin film transistor TFT1 via another thin film transistor (not shown) configured to control light emission.

[0124] The pixel electrode 310 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 310 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al) or a compound thereof. For example, the pixel electrode 310 may have a further reflective layer containing ITO, IZO, ZnO or In on / under the reflective layer. 2 O 3 In this case, the pixel electrode 310 may have a stack structure of ITO / Ag / ITO.

[0125] The pixel defining layer 125 may be disposed on the organic insulating layer 120. The pixel defining layer 125 covers the edge of the pixel electrode 310, and has an opening exposing the central portion of the pixel electrode 310 and thus defines a pixel. In addition, the pixel defining layer 125 may prevent arcing, etc., from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining layer 125 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by a method such as spin coating.

[0126] The intermediate layer 320 of the organic light emitting diode OLED may include a low molecular weight material or a polymer material, and may emit red light, green light, blue light, or white light. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single structure or a complex structure, and may include copper phthalocyanine (CuPc), N, N'-bis (naphthalene-1-yl) -N, N'-diphenylbenzidine (NPB) or tris (8-hydroxyquinoline) aluminum (Alq 3 ) These layers can be formed by vacuum deposition.

[0127] When the intermediate layer 320 includes a polymer material, the intermediate layer 320 may have a structure including an HTL and an EML. In this regard, the HTL may include poly (3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a polymer material such as a polyphenylene vinylene (PPV)-based material and a polyfluorene-based material. The intermediate layer 320 may be formed by screen printing, inkjet printing, laser induced thermal imaging (LITI), etc.

[0128] The intermediate layer 320 is not limited thereto, and may have any of various other structures. In addition, the intermediate layer 320 may include a single layer throughout the plurality of pixel electrodes 310 , or may include patterned layers corresponding to the plurality of pixel electrodes 310 , respectively.

[0129] The counter electrode 330 is disposed on the intermediate layer 320. The counter electrode 330 may include a conductive material having a low work function. For example, the counter electrode 330 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lithium (Li), calcium (Ca) or an alloy thereof. In an embodiment, the counter electrode 330 may further include a conductive material such as ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 The counter electrode 330 may be integrally formed as a single body for a plurality of organic light emitting diodes to correspond to the plurality of pixel electrodes 310 .

[0130] The organic light emitting diode OLED may be encapsulated by the thin film encapsulation layer 400. The thin film encapsulation layer 400 may prevent external moisture or foreign matter from penetrating into the organic light emitting diode OLED.

[0131] In some embodiments, the thin film encapsulation layer 400 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, such as Figure 4 In an embodiment, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410 and a second inorganic encapsulation layer 430 and an organic encapsulation layer 420 between the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 .

[0132] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ) and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 420 may include a polymer material. Examples of polymer materials may include silicone resins, acrylic resins, epoxy resins, polyimide, and polyethylene.

[0133] Figure 5 yes Figure 1 An enlarged conceptual diagram of Area A. Figure 6 yes Figure 5 An enlarged conceptual diagram of area B. Figure 7 is along Figure 6 The line II-II' is intercepted Figure 5 Schematic cross-sectional view of region B. Figure 8 is along Figure 6 The line III-III' is intercepted Figure 5 Schematic cross-sectional view of region B of FIG.

[0134] refer to Figure 5 , the first pad PD1 , the second pad PD2 , the third pad PD3 and the fourth pad PD4 are close to the lower edge of the substrate 100 .

[0135] The scan driving circuit line SDL may be located in the peripheral area PA to be adjacent to the left edge of the substrate 100, and may be electrically connected to the first scan driving circuit SDRV1 and the first pad PD1. Figure 2 The control signal input from the printed circuit board 30 can be transmitted to the first scan driving circuit SDRV1 through the scan driving circuit line SDL.

[0136] The second pad PD2 may be connected to the common power input wiring PIW2. The common power input wiring PIW2 may include a first portion extending substantially in the direction x and a second portion protruding from the first portion and extending in the direction -y. The second portion of the common power input wiring PIW2 may be electrically connected to the second pad PD2.

[0137] The common voltage supply wiring 11 may include a first portion extending in the direction x substantially parallel to the first portion of the common power input wiring PIW2. The common power connection member PCM2 may electrically connect the common voltage supply wiring 11 and the common power input wiring PIW2 to each other. The common power connection member PCM2 may overlap with the first portion of the common voltage supply wiring 11 and the first portion of the common power input wiring PIW2, and may be connected to the first portion of the common voltage supply wiring 11 and the first portion of the common power input wiring PIW2, respectively, through contact holes.

[0138] The data signal of the controller input from the printed circuit board through the third pad PD3 can be transmitted to the data line DL in the display area DA through the driving chip 20 and the data transmission line DTL, and finally transmitted to the pixel. To this end, the data transmission line DTL may be in the peripheral area PA. In addition, each of the data transmission lines DTL may extend in the direction y. The data transmission line DTL may be a fan-out wiring FW.

[0139] The driving power input wiring PW1 located in the peripheral area PA to be adjacent to the lower edge of the substrate 100 may include a first portion extending substantially in direction x and a second portion protruding from the first portion and extending in direction y. The second portion of the driving power input wiring PW1 may be electrically connected to the fourth pad PD4.

[0140] A plurality of driving voltage lines (not shown) extending in the direction y and extending into the display area DA may be electrically connected to the driving power transmission wiring PW2 extending in the direction x to be substantially parallel to the first portion of the driving power input wiring PW1. The plurality of driving voltage lines may be substantially parallel to the plurality of data lines DL in the display area DA.

[0141] The driving power input wiring PW1 and the driving power transmission wiring PW2 may be referred to as a power input wiring and a power transmission wiring, respectively. The driving power input wiring PW1 and the driving power transmission wiring PW2 may be arranged in the peripheral area PA to correspond to one side of the display area DA.

[0142] The driving power connection member PCM1 is a connection member that connects the driving power input wiring PW1 and the driving power transmission wiring PW2 to each other, and can electrically connect the driving power input wiring PW1 and the driving power transmission wiring PW2 to each other. The driving power connection member PCM1 may be referred to as a connection member.

[0143] refer to Figure 6 and Figure 7 One end of the driving power connection member PCM1 in the direction -y may overlap the driving power input wiring PW1 from below the driving power input wiring PW1 and may be connected to the driving power input wiring PW1 through a first contact hole CNT1 defined in the third interlayer insulating layer 119 on the driving power connection member PCM1.

[0144] One end of the driving power connection member PCM1 in the direction +y may overlap the driving power transmitting wiring PW2 from below the driving power transmitting wiring PW2 and may be connected to the driving power transmitting wiring PW2 through a second contact hole CNT2 defined in the third interlayer insulating layer 119 on the driving power connection member PCM1.

[0145] The driving power connection member PCM1 may include the same material as that of the second gate electrode GE2, and may be disposed on the second interlayer insulating layer 117, which is a layer on which the second gate electrode GE2 is disposed. The driving power input wiring PW1 and the driving power transmission wiring PW2 may include the same material as that of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2, and may be disposed on the third interlayer insulating layer 119.

[0146] The driving power connection member PCM1 may overlap with a plurality of fan-out wirings FW disposed below the driving power connection member PCM1. The fan-out wirings FW may include a first fan-out wiring FW1 and a second fan-out wiring FW2. The first fan-out wiring FW1 is a wiring disposed on the first gate insulating layer 112 in the peripheral area PA, and may be configured to transmit an electrical signal or a constant voltage to the display area DA. The first fan-out wiring FW1 may include the same material as that of the first gate electrode GE1. The second fan-out wiring FW2 is a wiring disposed on the second gate insulating layer 113 in the peripheral area PA, and may be configured to transmit an electrical signal or a constant voltage to the display area DA. The second fan-out wiring FW2 may include the same material as that of the second electrode CE2 of the storage capacitor Cst. Some of the fan-out wirings FW may be data transmission lines DTL (reference Figure 5 ). Some of the fan-out wirings FW may be initialization voltage lines configured to transmit an initialization voltage to the pixel circuit.

[0147] The second fan-out wiring FW2 may overlap the first fan-out wiring FW1. However, one or more embodiments are not limited thereto. Various modifications may be made, for example, the first fan-out wiring FW1 and the second fan-out wiring FW2 may alternate with each other.

[0148] Because the fan-out wiring FW described above is arranged below the driving power connection component PCM1, the step difference occurring at the edge of the fan-out wiring FW is reflected in the driving power connection component PCM1 and the insulating layer below the driving power connection component PCM1 according to the position of the fan-out wiring FW, and therefore, a step structure can also be formed in the driving power connection component PCM1 and the insulating layer below the driving power connection component PCM1.

[0149] When the first contact hole CNT1 or the second contact hole CNT2 is formed in such a bent region, defects such as cracks may occur in the first contact hole CNT1 or the second contact hole CNT2 due to the step structure.

[0150] According to one or more embodiments, the positions of the first contact hole CNT1 and the second contact hole CNT2 may be selected by considering the position of the fan-out wiring FW disposed below the driving power connection member PCM1. For example, in a plan view, the lower edges of the first contact hole CNT1 and the second contact hole CNT2 may be separated from the edge of the fan-out wiring FW by a specific distance d1 and d2 or greater. The distances d1 and d2 refer to the shortest distance from the edge of the fan-out wiring FW to the edge of the first contact hole CNT1 or the second contact hole CNT2 in a plan view. The specific distances d1 and d2 may be approximately 5 μm. When the distances d1 and d2 are less than 5 μm, the bending area of ​​the insulating layer caused by the end of the fan-out wiring FW may overlap with the contact hole, resulting in defects in the contact hole.

[0151] In a plan view, the first contact hole CNT1 and the second contact hole CNT2 may be arranged inside or outside the fan-out wiring FW so as not to overlap with the edge of the fan-out wiring FW.

[0152] The first contact hole CNT1 may include a 1-1 contact hole CNT1-1 overlapping with the fan-out wiring FW (e.g., above the fan-out wiring FW) and a 1-2 contact hole CNT1-2 not overlapping with the fan-out wiring FW (e.g., not above the fan-out wiring FW). In the same manner, the second contact hole CNT2 may include a 2-1 contact hole CNT2-1 overlapping with the fan-out wiring FW (e.g., above the fan-out wiring FW) and a 2-2 contact hole CNT2-2 not overlapping with the fan-out wiring FW (e.g., not above the fan-out wiring FW).

[0153] The 1-1th contact hole CNT1-1 and the 2-1th contact hole CNT2-1 may overlap the fan-out wiring FW, and may be separated from the edge of the fan-out wiring FW by a specific first distance d1.

[0154] The 1-2 th contact hole CNT1 - 2 and the 2-2 th contact hole CNT2 - 2 may not overlap with the fan-out wiring FW, and may be separated from the edge of the fan-out wiring FW by a specific second distance d2 .

[0155] According to this arrangement, the first contact hole CNT1 and the second contact hole CNT2 may be arranged in the direction x, but the center distance cd between adjacent first contact holes CNT1 and the center distance cd between adjacent second contact holes CNT2 may not be constant. In this article, the center distance between contact holes refers to the distance between the centers of the contact holes.

[0156] For example, the first center distance cd1, which is the center distance between the 1-1 contact hole CNT1-1 and the 1-2 contact hole CNT1-2 adjacent to each other between which the edge of the fan-out wiring FW in the first contact hole CNT1 is located, may be greater than the second center distance cd2, which is the center distance between two 1-1 contact holes CNT1-1 that overlap with the fan-out wiring FW and are adjacent to each other.

[0157] Furthermore, a third center distance cd3, which is a center distance between the 1-1 contact hole CNT1-1 overlapping the first fan-out wiring FW1 and the 1-1 contact hole CNT1-1 overlapping the second fan-out wiring FW2 adjacent to the first fan-out wiring FW1, may be greater than the first center distance cd1.

[0158] The fourth center distance cd4, which is the center distance between two 1-2nd contact holes CNT1-2 that do not overlap the fan-out wiring FW and are adjacent to each other, may be smaller than the first center distance cd1. In some embodiments, the fourth center distance cd4 may be the same as the second center distance cd2.

[0159] Since the fan-out wiring FW overlapping the driving power connection member PCM1 includes a portion extending in the direction y, a portion extending in the direction x, and a portion extending at a specific angle to the direction x, the first contact hole CNT1 and the second contact hole CNT2 may not have a one-to-one correspondence. For example, the number of the first contact holes CNT1 and the number of the second contact holes CNT2 may not be the same, and may be different from each other.

[0160] like Figure 7 As shown in FIG. 1 , in the display panel according to the present embodiment, the organic insulating layer 120 including an organic material may have an opening 120OP in the peripheral area PA, and thus, the third interlayer insulating layer 119, which is an inorganic material layer under the organic insulating layer 120, may be exposed. The opening 120OP in the organic insulating layer 120 may extend in the direction x. The opening 120OP may at least partially overlap with the driving power connection member PCM1.

[0161] The first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 may be in direct contact with the third interlayer insulating layer 119 which is an inorganic material layer. The first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 has a greater adhesion to the layer including the inorganic material than to the layer including the organic material. Therefore, the organic insulating layer 120 including the organic material may have an opening 120OP extending in the direction x, so that the first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 may be in direct contact with the third interlayer insulating layer 119 which is an inorganic material layer, and therefore, the thin film encapsulation layer 400 may be firmly adhered to the layer below the thin film encapsulation layer 400. In an embodiment, since the driving power connection member PCM1 and the common power connection member PCM2 may be stated as inorganic material layers including metal, the first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 may be in direct contact with the inorganic material layer including metal.

[0162] In an embodiment, since the driving power input wiring PW1 and the driving power transmission wiring PW2 may also be stated as an inorganic material layer including a metal, it may be considered that the driving power input wiring PW1 and the driving power transmission wiring PW2 are directly connected to each other without passing through the driving power connection member PCM1, and the first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 is in direct contact with the driving power input wiring PW1 and the driving power transmission wiring PW2. However, when the driving power input wiring PW1 and the driving power transmission wiring PW2 have a three-layer structure of Ti / Al / Ti, during the manufacturing process, the etching rate of Al is higher than the etching rate of Ti, and therefore, a tip of the uppermost Ti layer protruding beyond the Al layer may be formed. In addition, during the manufacturing process, such a tip may be separated from the driving power input wiring PW1 and the driving power transmission wiring PW2 and contact another conductive layer, thereby causing a defect in the display device.

[0163] In the display device according to the present embodiment, during the manufacturing process, the driving power input wiring PW1 and the driving power transmission wiring PW2 are covered by the organic insulating layer 120 immediately after being formed. In addition, the driving power input wiring PW1 and the driving power transmission wiring PW2 are electrically connected to each other through the driving power connection member PCM1 thereunder. Therefore, it is possible to effectively prevent defects from occurring during the manufacturing process, and further, the first inorganic encapsulation layer 410 can be in contact with the driving power connection member PCM1, which is an inorganic material layer, outside the display area DA, or directly in contact with the third interlayer insulating layer 119, which is an inorganic insulating layer covering the driving power connection member PCM1, and therefore, an excellent encapsulation effect can be obtained.

[0164] Fig. 9 and Fig.10 is an enlarged plan view of a portion of a display device according to an embodiment. More specifically, Fig. 9 and Fig.10 FIG. 1 shows a portion of the peripheral area of ​​the display panel. Fig. 9 and Fig.10 In, with Figure 6 The same elements as those in the drawings are denoted by the same reference numerals.

[0165] refer to Fig. 9 and Fig.10 , the fan-out wiring FW, the driving power input wiring PW1 , the driving power transmission wiring PW2 , and the driving power connection member PCM1 may be arranged in a peripheral area of ​​the display panel.

[0166] The fan-out wiring FW is a wiring configured to transmit an electrical signal, a constant voltage, etc. to the display area, and may extend substantially in the direction y, but may include a bent portion. The fan-out wiring FW may include a portion extending in the direction y, a portion extending in the direction x, and a portion extending in a direction between the direction x and the direction y.

[0167] The driving power input wiring PW1 may extend in the direction x and may be connected to the driving power connection member PCM1 through a plurality of first contact holes CNT1. The driving power input wiring PW1 may overlap with the fan-out wiring FW. The driving power transmission wiring PW2 may extend in the direction x and may be connected to the driving power connection member PCM1 through a plurality of second contact holes CNT2. The driving power transmission wiring PW2 may overlap with the fan-out wiring FW. Therefore, the driving power input wiring PW1 and the driving power transmission wiring PW2 may be electrically connected to each other. The driving power connection member PCM1 may overlap with the fan-out wiring FW.

[0168] A plurality of first contact holes CNT1 may be arranged in the direction x. In a plan view, the first contact hole CNT1 may be separated from the edge of the fan-out wiring FW by specific distances d1 and d2. The distances d1 and d2 refer to the shortest distances from the edge of the fan-out wiring FW to the edge of the first contact hole CNT1 in a plan view, and may be about 5 μm or more. The center distance cd between the centers of adjacent first contact holes CNT1 may not be constant.

[0169] In the same manner, a plurality of second contact holes CNT2 may be arranged in the direction x. In a plan view, the second contact hole CNT2 may be separated from the edge of the fan-out wiring FW by specific distances d1 and d2. The distances d1 and d2 refer to the shortest distances from the edge of the fan-out wiring FW to the edge of the second contact hole CNT2 in a plan view, and may be about 5 μm or more. The center distance cd between the centers of adjacent second contact holes CNT2 may not be constant.

[0170] The first contact holes CNT1 and the second contact holes CNT2 may not correspond one to one. For example, the number of the first contact holes CNT1 and the number of the second contact holes CNT2 may be different from each other.

[0171] Since the first contact hole CNT1 and the second contact hole CNT2 are arranged not to overlap the edge of the fan-out wiring FW, additional contact holes may be formed to reduce resistance.

[0172] Various modifications can be made, for example Fig. 9 As shown in FIG. , the first contact holes CNT1 may be arranged in two rows, or as shown in FIG. Fig.10 As shown in , the first contact holes CNT1 and the second contact holes CNT2 may both be arranged in two rows.

[0173] Fig.11 is a schematic cross-sectional view of a portion of a display device according to an embodiment. More specifically, Fig.11 FIG. 1 shows a portion of the peripheral area of ​​the display panel. Fig.11 In, with Figure 4 and Figure 7 The same elements as those in the drawings are denoted by the same reference numerals.

[0174] refer to Fig.11 , the fan-out wiring FW, the driving power input wiring PW1 , the driving power transmission wiring PW2 , and the driving power connection member PCM1 may be arranged in a peripheral area of ​​the display panel.

[0175] The fan-out wiring FW may include a first fan-out wiring FW1 and a second fan-out wiring FW2. The first fan-out wiring FW1 over the substrate 100 may be disposed on the first gate insulating layer 112. The second fan-out wiring FW2 may be disposed on the second gate insulating layer 113. The second fan-out wiring FW2 may overlap the first fan-out wiring FW1.

[0176] The driving power connection member PCM1 may overlap the fan-out wiring FW and may be disposed on the second interlayer insulating layer 117. The driving power connection member PCM1 is a member that connects the driving power input wiring PW1 and the driving power transmission wiring PW2 to each other and may be connected to the driving power input wiring PW1 and the driving power transmission wiring PW2 through the first contact hole CNT1 and the second contact hole CNT2, respectively.

[0177] In the present embodiment, the driving power input wiring PW1 may include a first conductive layer PW1a and a second conductive layer PW1b. The first conductive layer PW1a may include a first source electrode SE1 (reference Figure 4 ) and the first drain electrode DE1 (reference Figure 4The second conductive layer PW1b may include the same material as that of the second wiring WL2.

[0178] In the same manner, the driving power transmission wiring PW2 may include a first conductive layer PW2a and a second conductive layer PW2b. The first conductive layer PW2a may include a conductive layer connected to the first source electrode SE1 (reference Figure 4 ) and the first drain electrode DE1 (reference Figure 4 The second conductive layer PW2b may include the same material as that of the second wiring WL2.

[0179] In this case, the driving power input wiring PW1 and the driving power transmission wiring PW2 may be covered by the second organic insulating layer 123. The second organic insulating layer 123 may have an opening 123OP in the peripheral area PA, and thus may at least partially expose the third interlayer insulating layer 119, which is an inorganic insulating layer. The upper surface of the third interlayer insulating layer 119 exposed by the opening 123OP in the second organic insulating layer 123 may be in direct contact with the first inorganic encapsulation layer 410 of the thin film encapsulation layer 400. Therefore, an excellent encapsulation effect may be obtained.

[0180] Fig.12 is an enlarged plan conceptual diagram of a portion of a display device according to an embodiment. Fig.13 is along Fig.12 The line IV-IV' is intercepted Fig.12 More specifically, Fig.12 and Fig.13 FIG. 1 shows a portion of the peripheral area of ​​the display panel. Fig.12 and Fig.13 In, with Figure 6 and Figure 7 The same elements as those in the drawings are denoted by the same reference numerals.

[0181] refer to Fig.12 and Fig.13 , the power input wiring PW1, the power transmission wiring PW2, and the power connection member PCM may be arranged in the peripheral area of ​​the display panel. The power input wiring PW1 and the power transmission wiring PW2 may be separated from each other and may be electrically connected to each other by the power connection member PCM arranged in the lower layer. The power input wiring PW1 and the power transmission wiring PW2 may be arranged on the third interlayer insulating layer 119. The power connection member PCM may be arranged under the third interlayer insulating layer 119.

[0182] Since there may be a region where no fan-out wiring is arranged in the peripheral area of ​​the display panel, there may be a region where the power input wiring PW1 , the power transmission wiring PW2 , and the power connection member PCM do not overlap with the fan-out wiring.

[0183] In this case, the power connection member PCM may be provided in various layers. For example, the power connection member PCM may be connected to the fan-out wiring FW (refer to Figure 7 ) include the same material. That is, the power connection member PCM may include a first layer PCMa disposed on the first gate insulating layer 112, which is a layer on which the first gate electrode of the first thin film transistor is disposed. The first layer PCMa may be connected to the power input wiring PW1 and the power transmission wiring PW2 through contact holes, respectively.

[0184] The power connection member PCM may include a second layer PCMb disposed on the second gate insulating layer 113, which is a layer on which the second electrode of the storage capacitor is disposed. The second layer PCMb may be connected to the power input wiring PW1 and the power transmission wiring PW2, respectively, through contact holes.

[0185] Furthermore, the power connection member PCM may include a third layer PCMc disposed on the second interlayer insulating layer 117 on which the second gate electrode of the second thin film transistor is disposed. The third layer PCMc may be connected to the power input wiring PW1 and the power transmission wiring PW2 through contact holes, respectively.

[0186] The power connection member PCM may have a structure in which the first layer PCMa, the second layer PCMb, and the third layer PCMc overlap each other. However, one or more embodiments are not limited thereto. The power connection member PCM may include at least one of the first layer PCMa, the second layer PCMb, and the third layer PCMc. That is, the power connection member PCM may have a single-layer structure or a multi-layer structure.

[0187] The power input wiring PW1 and the power transmission wiring PW2 may be configured to transmit a driving voltage VDD (reference voltage VDD). Figure 3A In an embodiment, the power input wiring PW1 and the power transmission wiring PW2 may be configured to transmit a common voltage VSS (refer to Figure 3A ).

[0188] The organic insulating layer 120 may cover the power input wiring PW1 and the power transmission wiring PW2, and may include an opening 120OP exposing the area between the power input wiring PW1 and the power transmission wiring PW2. The first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 may be arranged in the opening 120OP to directly contact the third interlayer insulating layer 119, and therefore, an excellent encapsulation effect may be obtained.

[0189] As described above, according to one or more embodiments, a display device with high reliability in which a high-quality image can be displayed can be provided by appropriately arranging contact holes in the peripheral area. However, such technical features are examples, and the effects of one or more embodiments are not limited thereto.

[0190] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments are described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; a light emitting element arranged in the display area and a pixel circuit configured to drive the light emitting element; a fan-out wiring electrically connected to the pixel circuit and arranged in the peripheral area; a power input wiring and a power transmission wiring separated from each other in the peripheral area; as well as a connecting member connected to the power input wiring through a first contact hole and connected to the power transmission wiring through a second contact hole, The connection member at least partially overlaps the fan-out wiring, and a center distance between the first contact holes is not constant.

2. The display device according to claim 1, wherein: The center distance between the second contact holes is not constant.

3. The display device according to claim 1, wherein: The first contact holes include a 1-1 contact hole above the fan-out wiring and a 1-2 contact hole not above the fan-out wiring, and The center distance between the 1-1 contact hole and the 1-2 contact hole adjacent to each other between the edge of the fan-out wiring is greater than the center distance between the 1-1 contact holes overlapping the fan-out wiring and adjacent to each other.

4. The display device according to claim 1, wherein: The number of the first contact holes and the number of the second contact holes are different from each other.

5. The display device according to claim 1, wherein: The first contact hole includes a 1-1th contact hole above the fan-out wiring, and The 1-1th contact hole is indented from the edge of the fan-out wiring at a specific interval in a plan view.

6. The display device according to claim 5, wherein: The pitch is at least 5 μm.

7. The display device according to any one of claims 1 to 6, wherein: The pixel circuit comprises: A first thin film transistor including a first semiconductor layer and a first gate electrode; and a second thin film transistor including a second semiconductor layer and a second gate electrode, and Wherein, the first semiconductor layer is arranged on a layer different from a layer on which the second semiconductor layer is arranged.

8. The display device according to claim 7, wherein: At least some of the fan-out wirings are arranged on the same layer as the layer on which the first gate electrode is arranged.

9. The display device according to claim 7, wherein: The connection member is arranged on the same layer as a layer on which the second gate electrode is arranged.

10. The display device according to claim 1, further comprising: an organic insulating layer disposed on the power input wiring and the power transmission wiring, Wherein, the organic insulating layer includes an opening above at least a portion of the connecting member.

11. The display device according to claim 1, wherein: The first contact holes are arranged in two rows in a first direction.

12. The display device according to claim 1, wherein: The second contact holes are arranged in two rows in the first direction.

13. The display device according to claim 1, wherein: The power input wiring includes a first conductive layer and a second conductive layer stacked one after another.

14. A display device, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; a light emitting element arranged in the display area and a pixel circuit configured to drive the light emitting element; a thin film encapsulation layer covering the light emitting element and comprising a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; a fan-out wiring electrically connected to the pixel circuit and arranged in the peripheral area; a connecting member overlapping the fan-out wiring; an interlayer insulating layer covering the connection member and having a first contact hole and a second contact hole defined in the interlayer insulating layer; as well as The power input wiring and the power transmission wiring are separated from each other in the peripheral area, The power input wiring is connected to the connection member through the first contact hole, the power transmission wiring is connected to the connection member through the second contact hole, and the number of the first contact holes is different from the number of the second contact holes.

15. The display device according to claim 14, wherein: The first contact hole includes a 1-1th contact hole above the fan-out wiring, and The 1-1th contact hole is indented from the edge of the fan-out wiring at a specific interval in a plan view.

16. The display device according to claim 14, wherein: The first contact holes include a 1-1 contact hole above the fan-out wiring and a 1-2 contact hole not above the fan-out wiring, and The center distance between the 1-1 contact hole and the 1-2 contact hole adjacent to each other between the edge of the fan-out wiring is greater than the center distance between the 1-1 contact holes overlapping the fan-out wiring and adjacent to each other.

17. The display device according to any one of claims 14 to 16, wherein: The pixel circuit comprises: A first thin film transistor including a first semiconductor layer and a first gate electrode; and a second thin film transistor including a second semiconductor layer and a second gate electrode, and Wherein, the first semiconductor layer is arranged on a layer different from a layer on which the second semiconductor layer is arranged.

18. The display device according to claim 17, wherein: At least some of the fan-out wirings are arranged on the same layer as the layer on which the first gate electrode is arranged.

19. The display device according to claim 17, wherein: The connection member is arranged on the same layer as a layer on which the second gate electrode is arranged.

20. The display device according to claim 14, further comprising: an organic insulating layer disposed on the power input wiring and the power transmission wiring, Wherein, the organic insulating layer includes an opening above at least a portion of the connecting member.

21. The display device according to claim 20, wherein: The first inorganic encapsulating layer is disposed in the opening of the organic insulating layer and is in direct contact with the interlayer insulating layer.

22. The display device according to claim 14, wherein: The first contact holes are arranged in two rows in a first direction.

23. The display device according to claim 14, wherein: The second contact holes are arranged in two rows in the first direction.

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