Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel is provided with a display area and a non-display area surrounding the display area, and the non-display area comprises a first straight-edge area located on at least one side of the display area in the first direction, a second straight-edge area located on at least one side of the display area in the second direction and an arc-edge area connected between the first straight-edge area and the second straight-edge area. The first direction intersects with the second direction, and the display panel comprises sub-pixels arranged in the display area; the gate driving circuit is arranged in the first straight-edge area and the arc-edge area, the gate driving circuit comprises a plurality of driving units and output transistors electrically connected with the driving units, the output transistors are electrically connected with the sub-pixels, the output transistors are provided with first channels, the width direction of the first channels is the direction from the non-display area to the display area, and the width direction of the second channels is the direction from the non-display area to the display area. The width of at least one first channel located in the arc edge region in the at least one gate drive circuit is smaller than that of the first channel located in the first straight edge region.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display panel and a display device. Background Art

[0002] Liquid Crystal Display (LCD) panels, Organic Light Emitting Display (OLED) panels, and display panels using Light Emitting Diode (LED) devices have the advantages of high image quality, power saving, thin body, and wide application range. They are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc., becoming the mainstream in display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are intended to reduce the width of a non-display area of ​​the display panel.

[0005] An embodiment of the first aspect of the present application provides a display panel, the display panel having a display area and a non-display area arranged around the display area, the non-display area including a first straight-edge area located on at least one side of the display area in a first direction, a second straight-edge area located on at least one side of the display area in a second direction, and an arc-edge area connected between the first straight-edge area and the second straight-edge area, the first direction intersects with the second direction, the display panel includes: sub-pixels, arranged in the display area; a gate driving circuit, arranged in the first straight-edge area and the arc-edge area, the gate driving circuit including a plurality of driving units and output transistors electrically connected to the driving units, the output transistors being electrically connected to the sub-pixels, the output transistors having a first channel, the width direction of the first channel being in a direction from the non-display area to the display area, wherein the width of at least one first channel located in the arc-edge area in at least one gate driving circuit is smaller than the width of the first channel located in the first straight-edge area.

[0006] According to an implementation of the first aspect of the present application, at least some of the output transistors electrically connected to the same drive unit are arranged in parallel with each other, the output transistor has a first gate, at least one drive unit located in the first straight edge area is electrically connected to the first gate of a first number of output transistors, and at least one drive unit located in the arc edge area is electrically connected to the first gate of a second number of output transistors, and the first number in at least one gate drive circuit is less than the second number.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, in the same gate driving circuit, the width of at least one first channel located in the arc edge region is smaller than the width of the first channel located in the first straight edge region, and the first number is smaller than the second number.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, in the same gate driving circuit, the sum of the widths of a first number of first channels located in the first straight edge region is equal to the sum of the widths of a second number of first channels located in the arc edge region.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the output transistor includes a high-level output tube and a low-level output tube, wherein the high-level output tubes electrically connected to the same driving unit are arranged in parallel with each other, at least one driving unit located in the first straight edge region is electrically connected to the first gate of the high-level output tube of the first sub-number, at least one driving unit located in the arc edge region is electrically connected to the first gate of the high-level output tube of the second sub-number, the first sub-number in at least one gate driving circuit is less than the second sub-number, and / or, the low-level output tubes electrically connected to the same driving unit are arranged in parallel with each other, at least one driving unit located in the first straight edge region is electrically connected to the first gate of the low-level output tube of the third sub-number, at least one driving unit located in the arc edge region is electrically connected to the first gate of the low-level output tube of the fourth sub-number, and the third sub-number in at least one gate driving circuit is less than the fourth sub-number.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the length direction of the first channel is perpendicular to the width direction of the first channel, and the length of at least one first channel located in the arc edge area in at least one gate driving circuit is smaller than the length of the first channel located in the first straight edge area.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, in the same gate drive circuit, the width of at least one first channel located in the arc edge region is smaller than the width of the first channel located in the first straight edge region, and the length of at least one first channel located in the arc edge region is smaller than the length of the first channel located in the first straight edge region.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, in the same gate drive circuit, the ratio of the width to the length of the first channel located in the first straight edge area is a first ratio, the ratio of the width to the length of the first channel located in the arc edge area is a second ratio, and the first ratio is equal to the second ratio.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the output transistor has a first source and drain, and the display panel also includes a first signal line, and the first source and drain of the output transistor are electrically connected to the sub-pixel through the first signal line, wherein the first signal line electrically connected to the output transistor located in the first straight edge area extends along the first direction, and / or the first signal line electrically connected to the output transistor located in the arc edge area includes a first segment and a second segment connected in a bent manner, the first segment is connected to the first source and drain of the output transistor located in the arc edge area, and the second segment is connected to the first segment and extends along the first direction.

[0014] According to any of the aforementioned implementations of the first aspect of the present application, each output transistor electrically connected to the same driving unit is electrically connected to the same first signal line.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the length direction of the first channel is perpendicular to the width direction of the first channel, a plurality of driving units are arranged along the length direction of the first channel, and / or a plurality of output transistors are arranged along the length direction of the first channel.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, the output transistor further has source and drain regions arranged on both sides of the first channel in the length direction, and at least one source and drain region of at least one output transistor can be reused as a source and drain region in an adjacent output transistor.

[0017] According to any of the aforementioned implementations of the first aspect of the present application, there are multiple gate driving circuits, and the multiple gate driving circuits are arranged along the width direction of the first channel.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the gate driving circuit includes a gate scanning driving circuit and a gate light-emitting driving circuit, the width of at least one first channel located in the arc edge region in the gate scanning driving circuit is smaller than the width of the first channel located in the first straight edge region, and /

[0019] Alternatively, the width of at least one first channel located in the arc edge region in the gate light emitting driving circuit is smaller than the width of the first channel located in the first straight edge region.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, the gate scanning drive circuit includes a first type of scanning circuit and a second type of scanning circuit, the width of at least one first channel located in the arc edge area of ​​the first type of scanning circuit is smaller than the width of the first channel located in the first straight edge area, and / or the width of at least one first channel located in the arc edge area of ​​the second type of scanning circuit is smaller than the width of the first channel located in the first straight edge area.

[0021] An embodiment of a second aspect of the present application provides a display device, which includes a display panel according to any of the above embodiments.

[0022] In a display panel provided in an embodiment of the present application, the display panel has a display area and a non-display area arranged around the display area. The display panel includes sub-pixels and a gate drive circuit. The sub-pixels are arranged in the display area, and the display panel in the display area can be used to realize luminous display. The non-display area includes a first straight edge area located on at least one side of the display area in a first direction, a second straight edge area located on at least one side of the display area in a second direction, and an arc edge area connected between the first straight edge area and the second straight edge area. The gate drive circuit is arranged in the first straight edge area and the arc edge area. The gate drive circuit includes a plurality of drive units and an output transistor electrically connected to the drive unit. The output transistor is electrically connected to the sub-pixel, so that the gate drive circuit can be used to transmit a signal to the sub-pixel to realize the luminous display of the sub-pixel in the display area.

[0023] The output transistor has a first channel. Since the width direction of the first channel is from the non-display area to the display area, the width of at least one first channel located in the arc edge area in at least one gate driving circuit can be set to be smaller than the width of the first channel located in the first straight edge area, so as to better reduce the space in the arc edge area occupied by the first channel. In addition, the gate driving circuit in the arc edge area can be moved as a whole toward the display area along the width direction of the first channel without excessively affecting the space between the output transistor and the display area, thereby better reducing the width of the non-display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0026] Figure 2 It is a schematic diagram of partial connection between a gate driving circuit and a sub-pixel provided in an embodiment of the present application;

[0027] Figure 3 is a partial cross-sectional view of a display panel in a display area provided by an embodiment of the present application;

[0028] Figure 4 is a partially enlarged schematic diagram of a first straight edge area provided in an embodiment of the present application;

[0029] Figure 5is a schematic diagram of a partial structure of an output transistor in a first straight edge region provided by an embodiment of the present application;

[0030] Figure 6 This is a schematic diagram of connection between a driving unit and an output transistor in a first straight edge region provided by an embodiment of the present application;

[0031] Figure 7 It is a partial enlarged schematic diagram of an arc edge area provided in an embodiment of the present application;

[0032] Figure 8 It is a schematic diagram of a local structure of an output transistor in an arc edge region provided by an embodiment of the present application;

[0033] Fig. 9 This is a schematic diagram of the connection between a driving unit and an output transistor in an arc edge region provided by an embodiment of the present application;

[0034] Fig.10 is a schematic diagram of a partial structure of an output transistor in an arc edge region provided by another embodiment of the present application;

[0035] Fig.11 is a schematic diagram of connection between a driving unit and an output transistor in an arc edge region provided by another embodiment of the present application;

[0036] Fig.12 is a schematic diagram of connection between a driving unit and an output transistor in a first straight edge region provided by another embodiment of the present application;

[0037] Fig.13 This is a schematic diagram of the connection between a driving unit and an output transistor in an arc edge region provided by another embodiment of the present application.

[0038] Description of reference numerals:

[0039] 10. Display panel;

[0040] 100, substrate; 110, underlay; 120, first insulating layer; 130, second insulating layer; 140, third insulating layer;

[0041] 200, sub-pixel; 210, light-emitting device; 211, first electrode; 212, light-emitting functional layer; 213, second electrode; 220, pixel driving circuit; 221, pixel transistor; 221a, second channel; 221b, second gate; 221c, second source and drain; 222, storage capacitor; 222a, first plate; 222b, second plate;

[0042] 300, gate drive circuit; 301, gate scanning drive circuit; 301a, first type scanning circuit; 301b, second type scanning circuit; 302, gate light emitting drive circuit; 310, drive unit; 320, output transistor; 320a, high level output tube; 320b, low level output tube; 321, first channel; 322, source and drain region; 323, first gate; 324, first source and drain;

[0043] 400, pixel definition layer; 410, pixel opening;

[0044] L1, first signal line; L11, first segment; L12, second segment;

[0045] LC1, first control signal line; LC2, second control signal line;

[0046] AA, display area; NA, non-display area; NA1, first straight edge area; NA2, second straight edge area; NA3, arc edge area

[0047] X, first direction;

[0048] Y, second direction;

[0049] Z, thickness direction;

[0050] WD, width direction;

[0051] LD, length direction. DETAILED DESCRIPTION

[0052] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0053] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0054] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0055] Embodiments of the present application provide a display panel and a display device. Embodiments of the display panel and the display device will be described below in conjunction with the accompanying drawings.

[0056] Figure 1 is a schematic structural diagram of a display panel 10 provided in an embodiment of the present application, Figure 2 is a partial connection diagram of a gate driving circuit 300 and a sub-pixel 200 provided in an embodiment of the present application. Figure 3 is a partial cross-sectional view of a display panel 10 in a display area AA provided in an embodiment of the present application, Figure 4 is a partially enlarged schematic diagram of a first straight edge area NA1 provided in an embodiment of the present application, Figure 5 is a schematic diagram of a partial structure of an output transistor 320 in a first straight edge area NA1 provided in an embodiment of the present application, Figure 6 is a schematic diagram of connection between a driving unit 310 and an output transistor 320 in a first straight edge area NA1 provided by an embodiment of the present application. Figure 7 is a partially enlarged schematic diagram of an arc edge area NA3 provided in an embodiment of the present application, Figure 8 is a schematic diagram of a partial structure of an output transistor 320 in an arc edge area NA3 provided in an embodiment of the present application, Fig. 9 1 is a connection diagram of a driving unit 310 and an output transistor 320 in an arc edge area NA3 provided in an embodiment of the present application.

[0057] For the sake of illustration, the number of output transistors 320 in the figure is not the number of output transistors 320 in an actual product, and this application does not specifically limit the number of output transistors 320.

[0058] The X direction in the figure may indicate the first direction X, the Y direction in the figure may indicate the second direction Y, the Z direction in the figure may indicate the thickness direction Z of the display panel 10, the WD width direction WD in the figure may indicate the width direction WD of the first channel 321, and the LD width direction WD in the figure may indicate the length direction LD of the first channel 321. Among them, the first direction X may intersect with the second direction Y, for example, the first direction X may be perpendicular to the second direction Y. The first direction X, the second direction Y and the thickness direction Z of the display panel 10 intersect in pairs, for example, the first direction X and the second direction Y may be perpendicular to the thickness direction Z of the display panel 10 in pairs. The width direction WD of the first channel 321 may be perpendicular to the length direction LD of the first channel 321. The width direction WD of the first channel 321 and the length direction LD of the first channel 321 may be perpendicular to the thickness direction Z of the display panel 10 in pairs.

[0059] like Figures 1 to 9 As shown, an embodiment of the first aspect of the present application provides a display panel 10, the display panel 10 has a display area AA and a non-display area NA arranged around the display area AA, the non-display area NA includes a first straight edge area NA1 located at least on one side of the display area AA in a first direction X, a second straight edge area NA2 located at least on one side of the display area AA in a second direction Y, and an arc edge area NA3 connected between the first straight edge area NA1 and the second straight edge area NA2, the first direction X intersects with the second direction Y, and the display panel 10 includes: a sub-pixel 200, arranged in the display area AA; a gate driving circuit 30 0, arranged in the first straight edge area NA1 and the arc edge area NA3, the gate driving circuit 300 includes a plurality of driving units 310 and an output transistor 320 electrically connected to the driving unit 310, the output transistor 320 is electrically connected to the sub-pixel 200, the output transistor 320 has a first channel 321, the width direction WD of the first channel 321 is the direction from the non-display area NA to the display area AA, wherein the width of at least one first channel 321 located in the arc edge area NA3 in at least one gate driving circuit 300 is smaller than the width of the first channel 321 located in the first straight edge area NA1.

[0060] In a display panel 10 provided in an embodiment of the present application, the display panel 10 has a display area AA and a non-display area NA arranged around the display area AA. The display panel 10 includes a sub-pixel 200 and a gate driving circuit 300. The sub-pixel 200 is arranged in the display area AA, and the display panel 10 in the display area AA can be used to realize light-emitting display.

[0061] Optionally, a plurality of sub-pixels 200 are arranged in the first direction X to form a pixel row, and a plurality of pixel rows are arranged in the second direction Y.

[0062] Optional, such as Figure 3 As shown, the display panel 10 may further include a substrate 100 , and the sub-pixel 200 may include a light emitting device 210 disposed on one side of the substrate 100 and a pixel driving circuit 220 disposed in the substrate 100 .

[0063] Optionally, the light emitting device 210 may include a first electrode 211 , a light emitting functional layer 212 disposed on a side of the first electrode 211 facing away from the substrate 100 , and a second electrode 213 disposed on a side of the light emitting functional layer 212 facing away from the substrate 100 .

[0064] Optionally, the light-emitting functional layer 212 may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting structure, an electron injection layer (EIL) and an electron transport layer (ETL).

[0065] Optionally, the first electrode 211 and the second electrode 213 can be used as pixel electrodes, one of the first electrode 211 and the second electrode 213 can be used as an anode, and the other can be used as a cathode to drive the light-emitting functional layer 212 to emit light. The embodiment of the present application is described by taking the first electrode 211 as the anode and the second electrode 213 as the cathode.

[0066] Optionally, the display panel 10 may further include a pixel definition layer 400 disposed in the display area AA and located on the side of the first electrode 211 away from the substrate 100. The pixel definition layer 400 may be used to divide sub-pixels. The pixel definition layer 400 may be provided with a pixel opening 410, and a portion of the light-emitting functional layer 212 is located in the pixel opening 410. A portion of the surface of the first electrode 211 on the side away from the substrate 100 is exposed from the pixel opening 410 and connected to the light-emitting functional layer 212, so that the first electrode 211 drives the light-emitting functional layer 212 to emit light.

[0067] Optionally, the pixel driving circuit 220 may be used to provide a driving current to the first electrode 211 to drive the light-emitting functional layer 212 to emit light.

[0068] Exemplarily, the pixel driving circuit 220 may include a pixel transistor 221, a storage capacitor 222, and a driving signal line for connecting various devices. The pixel transistor 221 may include a second channel 221a, a second gate 221b, and a second source and drain 221c. The storage capacitor 222 includes a first plate 222a and a second plate 222b. The second source and drain 221c of some pixel transistors 221 may be electrically connected to the first electrode 211, so that some pixel transistors 221 can be used to provide a driving current to the first electrode 211 to achieve the light emission of the driving function layer 212. For example, the pixel transistor 221 may include a light emission control transistor, a data writing transistor, a pixel driving transistor, a threshold compensation transistor, and a reset transistor, wherein the second source and drain 221c of the light emission control transistor may be electrically connected to the first electrode 211, and the light emission control transistor may be used to control the driving current to flow to the first electrode 211 to achieve the light emission of the driving function layer 212.

[0069] Optionally, the substrate 100 may include a substrate 110 , and a first insulating layer 120 , a second insulating layer 130 , a third insulating layer 140 and a fourth insulating layer 150 which are disposed on one side of the substrate 110 and sequentially stacked in a direction away from the substrate 110 .

[0070] As an example, the second gate 221b and the first electrode 222a can be located between the first insulating layer 120 and the second insulating layer 130, the second electrode 222b can be located between the second insulating layer 130 and the third insulating layer 140, and the second source and drain 221c can be located between the third insulating layer 140 and the fourth insulating layer 150.

[0071] Optionally, the fourth insulating layer 150 may be reused as a planarization layer of the display panel 10 , and the light emitting device 210 may be disposed on a side of the fourth insulating layer 150 facing away from the substrate 110 .

[0072] The non-display area NA includes a first straight-edge area NA1 located on at least one side of the display area AA in the first direction X, a second straight-edge area NA2 located on at least one side of the display area AA in the second direction Y, and an arc-edge area NA3 connected between the first straight-edge area NA1 and the second straight-edge area NA2. The gate driving circuit 300 is arranged in the first straight-edge area NA1 and the arc-edge area NA3. The gate driving circuit 300 includes a plurality of driving units 310 and an output transistor 320 electrically connected to the driving unit 310. The output transistor 320 is electrically connected to the sub-pixel 200, so that the gate driving circuit 300 can be used to transmit a signal to the sub-pixel 200 to realize the luminous display of the sub-pixel 200 in the display area AA.

[0073] Optionally, the gate driving circuit 300 may be a GIP (Gate in Panel) circuit.

[0074] The output transistor 320 has a first channel 321. Optionally, the output transistor 320 may further have a first gate 323, which may be disposed on one side of the first channel 321 in the thickness direction Z of the display panel 10, and a projection of the first gate 323 in the thickness direction Z of the display panel 10 may at least partially overlap with a projection of the first channel 321 in the thickness direction Z of the display panel 10.

[0075] Optionally, the output transistor 320 may further include a first source-drain electrode 324, and the output transistor 320 may further include a source-drain region 322 disposed on both sides of the first channel 321 in the length direction LD, and the first source-drain electrode 324 may be connected to the source-drain region 322. Exemplarily, the first source-drain electrode 324 may include a source and a drain, the source-drain region 322 may include a source region and a drain region, the source may be connected to the source region, the drain may be connected to the drain region, and the source and drain may be turned off and on by controlling the signal of the first gate 323.

[0076] Optionally, the output transistor 320 may be disposed in the substrate 100, and the present application does not limit the position of each structure in the output transistor 320 in the substrate 100. The position of the output transistor 320 may be the same as or different from the position of the pixel driving transistor.

[0077] As an example, the first channel 321 and the source and drain region 322 can be located on the side of the first insulating layer 120 facing the substrate 110, the first gate 323 can be located between the first insulating layer 120 and the second insulating layer 130, and the first source and drain 324 can be located between the third insulating layer 140 and the fourth insulating layer 150.

[0078] Optionally, the width of the first channel 321 may refer to the dimension of the first channel 321 in the width direction WD thereof.

[0079] The width direction WD of the first channel 321 is a direction pointing from the non-display area NA to the display area AA. Exemplarily, the width direction WD of the first channel 321 located in the first straight edge area NA1 may be parallel to the first direction X, and the length direction LD of the first channel 321 located in the first straight edge area NA1 may be parallel to the second direction Y. The width direction WD of the first channel 321 located in the arc edge area NA3 may intersect with the first direction X and the second direction Y, and the length direction LD of the first channel 321 located in the arc edge area NA3 may intersect with the first direction X and the second direction Y. For example, the width direction WD of the first channel 321 located in the arc edge area NA3 may be perpendicular to the edge of the non-display area NA, and the length direction LD of the first channel 321 located in the arc edge area NA3 may be tangent to the edge of the non-display area NA.

[0080] Optionally, the plurality of driving units 310 are arranged along the length direction LD of the first channel 321, and / or the plurality of output transistors 320 are arranged along the length direction LD of the first channel 321. Exemplarily, the plurality of driving units 310 located in the first straight edge area NA1 may be arranged along the second direction Y, and / or the plurality of output transistors 320 located in the first straight edge area NA1 may be arranged along the second direction Y. The plurality of driving units 310 located in the arc edge area NA3 may be arranged along a direction tangent to an edge of the non-display area NA, and / or the plurality of output transistors 320 located in the arc edge area NA3 may be arranged along a direction tangent to an edge of the non-display area NA.

[0081] Optionally, the output transistor 320 is electrically connected to the sub-pixel 200, which may mean that the first source and drain 324 of the output transistor 320 may be electrically connected to the second gate 221b of some pixel transistors 221, so that the output transistor 320 can be used to provide signals to the second gate 221b of some pixel transistors 221 in the sub-pixel 200 to control the turning off and on of some pixel transistors 221.

[0082] Optionally, the output transistor 320 includes a high-level output tube 320a and a low-level output tube 320b. The high-level output tube 320a can be used to provide a high-level signal to the second gate 221b of some pixel transistors 221 in the sub-pixel 200, and the low-level output tube 320b can be used to provide a low-level signal to the second gate 221b of some pixel transistors 221 in the sub-pixel 200 to control the turning on and off of some pixel transistors 221 in the sub-pixel 200.

[0083] Exemplarily, one of the source and the drain in the high-level output tube 320a can be used to receive a high-level signal (VG1 in the figure can indicate a high-level signal), and the other of the source and the drain in the high-level output tube 320a can be electrically connected to the second gate 221b of some pixel transistors 221 in the sub-pixel 200. One of the source and the drain in the low-level output tube 320b can be used to receive a low-level signal (VG2 in the figure can indicate a high-level signal), and the other of the source and the drain in the low-level output tube 320b can be electrically connected to the second gate 221b of some pixel transistors 221 in the sub-pixel 200.

[0084] Optionally, the driving unit 310 is electrically connected to the output transistor 320 , which may mean that the driving unit 310 is electrically connected to the first gate 323 of the output transistor 320 , so that the driving unit 310 can be used to control the turning off and on of the output transistor 320 .

[0085] Optionally, a single driving unit 310 may be electrically connected to a plurality of output transistors 320, that is, a single driving unit 310 may control the switching on and off of the plurality of output transistors 320. For example, a single driving unit 310 may be electrically connected to a high-level output tube 320a and a low-level output tube 320b, so that a single driving unit 310 may control the switching on and off of the high-level output tube 320a and the low-level output tube 320b.

[0086] As an example, the display panel 10 may also include a first control signal line LC1 and a second control signal line LC2. A single driving unit 310 may be electrically connected to a high-level output tube 320a via the first control signal line LC1 and may be electrically connected to a low-level output tube 320b via the second control signal line LC2. The driving unit 310 may provide a control signal to a first gate 323 of the high-level output tube 320a via the first control signal line LC1 to control the turning off and on of the high-level output tube 320a, and the driving unit 310 may provide a control signal to a first gate 323 of the low-level output tube via the second control signal line LC2 to control the turning off and on of the low-level output tube.

[0087] Optionally, a single driving unit 310 may be electrically connected to multiple high-level output tubes 320a and multiple low-level output tubes 320b. For example, a single driving unit 310 may be electrically connected to multiple high-level output tubes 320a via a single first control signal line LC1, and a single driving unit 310 may be electrically connected to multiple low-level output tubes 320b via a single second control signal line LC2.

[0088] Optionally, at least some of the output transistors 320 electrically connected to the same driving unit 310 may be arranged in parallel with each other.

[0089] Exemplarily, high-level output tubes 320a electrically connected to the same driving unit 310 can be arranged in parallel with each other, and low-level output tubes 320b electrically connected to the same driving unit 310 can be arranged in parallel with each other, so that the arrangement of the output transistors 320 is facilitated while also enabling the output transistors 320 in the gate driving circuit 300 to have better working performance.

[0090] Optionally, in each output transistor 320 electrically connected to the same driving unit 310, the high-level output tube 320a can be located on one side of the low-level output tube 320b in the length direction LD of the first channel 321, so as to realize the parallel connection of each high-level output tube 320a and the parallel connection of each low-level output tube 320b.

[0091] Optionally, the display panel 10 further includes a first signal line L1 , and the first source and drain 324 of the output transistor 320 is electrically connected to the sub-pixel 200 through the first signal line L1 .

[0092] Optionally, each output transistor 320 electrically connected to the same driving unit 310 is electrically connected to the same first signal line L1, so that in each output transistor 320 electrically connected to the same driving unit 310, each output transistor 320 can be electrically connected to the sub-pixel 200 through the same first signal line L1. For example, in each output transistor 320 electrically connected to the same driving unit 310, the high-level output tube 320a and the low-level output tube 320b can be electrically connected to the sub-pixel 200 through the same first signal line L1.

[0093] Optionally, a single first signal line L1 may be electrically connected to all sub-pixels 200 in the same pixel row, so that the output transistor 320 may be used to simultaneously provide signals to the second gates 221 b of some pixel transistors 221 in the sub-pixels 200 in the same pixel row.

[0094] Optionally, the output transistor 320 in at least one gate driving circuit 300 may be located on the side of the driving unit 310 facing the display area AA, so that the output transistor 320 is electrically connected to the sub-pixel 200 in the display area AA through the first signal line L1.

[0095] Optionally, the first channels 321 of the output transistors 320 electrically connected to the same driving unit 310 may be arranged adjacent to each other, so as to reduce the space of the non-display area NA occupied by the output transistors 320 .

[0096] Optional, such as Figure 5 and Figure 8 As shown, at least one source-drain region 322 of at least one output transistor 320 can be reused as a source-drain region 322 in an adjacent output transistor 320. Exemplarily, in each output transistor 320 electrically connected to the same driving unit 310, the source-drain region 322 located between two adjacent first channels 321 can be reused as a source-drain region 322 in the output transistors 320 on both sides thereof, so as to better reduce the space of the non-display area NA occupied by the output transistors 320.

[0097] Similarly, optional, such as Figure 6 and Fig. 9 As shown, at least one first source-drain 324 of at least one output transistor 320 can be reused as a first source-drain 324 in an adjacent output transistor 320. Exemplarily, in each output transistor 320 electrically connected to the same driving unit 310, a first source-drain 324 located between two adjacent first channels 321 can be reused as a first source-drain 324 in the output transistors 320 on both sides thereof, so as to better reduce the space of the non-display area NA occupied by the output transistor 320.

[0098] Since the width direction WD of the first channel 321 is the direction pointing from the non-display area NA to the display area AA, the width of at least one first channel 321 located in the arc-edge area NA3 in at least one gate driving circuit 300 can be set to be smaller than the width of the first channel 321 located in the first straight-edge area NA1, so as to better reduce the space of the arc-edge area NA3 occupied by the first channel 321. In addition, the gate driving circuit 300 of the arc-edge area NA3 can be moved as a whole toward the display area AA along the width direction WD of the first channel 321 without excessively affecting the space between the output transistor 320 and the display area AA, thereby better reducing the width of the non-display area NA.

[0099] Exemplarily, by setting the width of at least one first channel 321 located in the arc edge area NA3 in at least one gate driving circuit 300 to be smaller than the width of the first channel 321 located in the first straight edge area NA1, the first channel 321 with a smaller width in the non-display area NA is less likely to affect the arrangement of the first signal line L1, so that there is sufficient space between the output transistor 320 and the display area AA to arrange the first signal line L1, and the gate driving circuit 300 in the arc edge area NA3 can be moved as a whole toward the display area AA along the width direction WD of the first channel 321, so that the width of the non-display area NA can be better reduced.

[0100] Optionally, the width of the first channel 321 located in the arc-edge area NA3 in at least one gate driving circuit 300 may be smaller than the width of the first channel 321 located in the first straight-edge area NA1, or the width of part of the first channel 321 located in the arc-edge area NA3 in at least one gate driving circuit 300 may be smaller than the width of the first channel 321 located in the first straight-edge area NA1, which is not specifically limited in the present application. For ease of illustration, the figure illustrates that "the width of the first channel 321 located in the arc-edge area NA3 in at least one gate driving circuit 300 may be smaller than the width of the first channel 321 located in the first straight-edge area NA1".

[0101] Optionally, the first signal line L1 electrically connected to the output transistor 320 located in the first straight area NA1 may extend along the first direction X, which can facilitate the electrical connection between the first signal line L1 and the sub-pixels 200 in the same pixel row.

[0102] In some optional embodiments, the first signal line L1 electrically connected to the output transistor 320 located in the arc edge area NA3 includes a first segment L11 and a second segment L12 that are bent and connected, the first segment L11 is connected to the first source and drain 324 of the output transistor 320 located in the arc edge area NA3, and the second segment L12 is connected to the first segment L11 and extends along the first direction X.

[0103] Optionally, the first segment L11 is connected to the second segment L12 by a bending, which may mean that the extension direction of at least part of the first segment L11 may intersect with the extension direction of the second segment L12. For example, the first segment L11 may extend along the extension direction of the arc edge of the arc edge area NA3 or in a direction intersecting with the arc edge, and the second segment L12 may extend along the first direction X.

[0104] Optionally, the first segment L11 may be located in the arc edge area NA3.

[0105] Optionally, the first segments L11 of at least two first signal lines L1 located in the arc edge area NA3 may be arranged at intervals in a direction from the non-display area NA to the display area AA.

[0106] In these optional embodiments, by setting the first signal line L1 electrically connected to the output transistor 320 located in the arc edge area NA3 to include a first segment L11 and a second segment L12 that are bent and connected, the arrangement of the first signal line L1 electrically connected to the output transistor 320 located in the arc edge area NA3 can be facilitated, so that the second segment L12 extending into the display area AA can be closer to the sub-pixel 200 electrically connected to it, for example, the second segment L12 can extend from one side of the sub-pixel 200 electrically connected to it in the first direction X to the display area AA, thereby facilitating the electrical connection between the first signal line L1 and the sub-pixel 200.

[0107] Among them, the present application sets the width of at least one first channel 321 located in the arc edge area NA3 in at least one gate driving circuit 300 to be smaller than the width of the first channel 321 located in the first straight edge area NA1, so that the first channel 321 with a smaller width in the non-display area NA is not easy to affect the arrangement of the first segment L11, so that there is a relatively sufficient space between the output transistor 320 and the display area AA to arrange the first segment L11, and the gate driving circuit 300 in the arc edge area NA3 can be moved as a whole toward the display area AA along the width direction WD of the first channel 321, so that the width of the non-display area NA can be better reduced.

[0108] like Figures 4 to 9 As shown, in some optional embodiments, at least one driving unit 310 located in the first straight edge area NA1 is electrically connected to the first gates 323 of the first number of output transistors 320, and at least one driving unit 310 located in the arc edge area NA3 is electrically connected to the first gates 323 of the second number of output transistors 320, and the first number in at least one gate driving circuit 300 is less than the second number.

[0109] Optionally, the first number in at least one gate driving circuit 300 is less than the second number, which may mean that, in the same gate driving circuit 300, the number of output transistors 320 electrically connected to at least one driving unit 310 located in the first straight edge area NA1 is less than the number of output transistors 320 electrically connected to at least one driving unit 310 located in the arc edge area NA3.

[0110] For example, Figure 5 As shown, in the same gate driving circuit 300, the first number may be 4 (for example, the first number in the actual product of the display panel 10 may be greater than 4, for example, the first number in the actual product of the display panel 10 may be 9), that is, the number of output transistors 320 electrically connected to at least one driving unit 310 located in the first straight edge area NA1 may be 4, and as Figure 8 As shown, the second number may be 6 (exemplarily, the second number in the actual product of the display panel 10 may be greater than 6, for example, the second number in the actual product of the display panel 10 may be 10), that is, the number of output transistors 320 electrically connected to at least one driving unit 310 located in the arc edge area NA3 may be 6.

[0111] Optionally, in the same gate driving circuit 300, the width of at least one first channel 321 located in the arc edge area NA3 is smaller than the width of the first channel 321 located in the first straight edge area NA1, and the first number is smaller than the second number, that is, Figure 5 and Figure 8 As shown, in each output transistor 320 of the same gate driving circuit 300, the width of at least one first channel 321 of the output transistor 320 located in the arc edge area NA3 may be smaller than the width of the first channel 321 of the output transistor 320 located in the first straight edge area NA1, and the number of output transistors 320 electrically connected to at least one driving unit 310 located in the first straight edge area NA1 is smaller than the number of output transistors 320 electrically connected to at least one driving unit 310 located in the arc edge area NA3.

[0112] In these optional embodiments, by setting the first number in at least one gate drive circuit 300 to be smaller than the second number, the impact of reducing the width of the first channel 321 of the output transistor 320 in the arc edge area NA3 on the performance of the output transistor 320 in the arc edge area NA3 can be reduced by increasing the number of output transistors 320 electrically connected to a single drive unit 310 in the arc edge area NA3.

[0113] For example, after reducing the width of the first channel 321 of at least one output transistor 320 in the arc edge area NA3, the number of output transistors 320 electrically connected to the same driving unit 310 and connected in parallel with each other in the arc edge area NA3 can be increased to better compensate for the performance loss caused by reducing the width of the first channel 321 of a single output transistor 320 in the arc edge area NA3, so that the performance of the gate driving circuit 300 is not easily affected while the width of the non-display area NA is reduced.

[0114] In some optional embodiments, in the same gate driving circuit 300 , the sum of the widths of the first number of first channels 321 located in the first straight edge area NA1 is equal to the sum of the widths of the second number of first channels 321 located in the arc edge area NA3 .

[0115] Exemplarily, in the same gate driving circuit 300, the width of the first channel 321 of a single output transistor 320 electrically connected to the driving unit 310 located in the first straight edge area NA1 is i, the width of the first channel 321 of a single output transistor 320 electrically connected to the driving unit 310 located in the arc edge area NA3 is j, the first number is a, and the second number is b. For example, the number of output transistors 320 electrically connected to at least one driving unit 310 located in the first straight edge area NA1 is a, and the number of output transistors 320 electrically connected to at least one driving unit 310 located in the arc edge area NA3 is b. Therefore, the sum of the widths of the first channels 321 of the output transistors 320 electrically connected to at least one driving unit 310 located in the first straight edge area NA1 is a*i, and the sum of the widths of the first channels 321 of the output transistors 320 electrically connected to at least one driving unit 310 located in the arc edge area NA3 is b*j.

[0116] The sum of the widths of the first number of first channels 321 located in the first straight edge area NA1 is equal to the sum of the widths of the second number of first channels 321 located in the arc edge area NA3 , which may be referred to as a*i=b*j.

[0117] In this optional embodiment, by setting the sum of the widths of the first number of first channels 321 located in the first straight edge area NA1 to be equal to the sum of the widths of the second number of first channels 321 located in the arc edge area NA3, the width of the first channel 321 of the single output transistor 320 in the first straight edge area NA1 and the number of output transistors 320 electrically connected to the same drive unit 310 and connected in parallel in the first straight edge area NA1 can be appropriately reduced, and the number of output transistors 320 electrically connected to the same drive unit 310 and connected in parallel in the arc edge area NA3 can be appropriately increased. The number of body transistors 320 makes it difficult to increase the number of output transistors 320 electrically connected to the same drive unit 310 and connected in parallel in the arc edge area NA3 too much after reducing the width of the first channel 321 of a single output transistor 320 in the arc edge area NA3, making it difficult to waste the performance of the device structure in the display panel 10. It also makes it difficult to increase the number of output transistors 320 electrically connected to the same drive unit 310 and connected in parallel in a smaller arc edge area NA3 after reducing the width of the first channel 321 of a single output transistor 320 in the arc edge area NA3, making it difficult to reduce the performance of the gate drive circuit 300 in the arc edge area NA3.

[0118] In some optional embodiments, the high-level output tubes 320a electrically connected to the same driving unit 310 are arranged in parallel with each other, at least one driving unit 310 located in the first straight edge area NA1 is electrically connected to the first gate 323 of the first sub-number of high-level output tubes 320a, at least one driving unit 310 located in the arc edge area NA3 is electrically connected to the first gate 323 of the second sub-number of high-level output tubes 320a, the first sub-number in at least one gate driving circuit 300 is less than the second sub-number, and / or, the low-level output tubes 320b electrically connected to the same driving unit 310 are arranged in parallel with each other, at least one driving unit 310 located in the first straight edge area NA1 is electrically connected to the first gate 323 of the third sub-number of low-level output tubes 320b, at least one driving unit 310 located in the arc edge area NA3 is electrically connected to the first gate 323 of the fourth sub-number of low-level output tubes 320b, and the third sub-number in at least one gate driving circuit 300 is less than the fourth sub-number.

[0119] For example, Figure 5As shown, in the same gate driving circuit 300, the first sub-number and the third sub-number can both be 2 (for example, the first sub-number and the third sub-number in the actual product of the display panel 10 can both be greater than 2, for example, the first sub-number and the third sub-number in the actual product of the display panel 10 can be 4), that is, the number of high-level output tubes 320a electrically connected to at least one driving unit 310 located in the first straight edge area NA1 can be 4, and the number of low-level output tubes 320b electrically connected to at least one driving unit 310 located in the first straight edge area NA1 can also be 4. Figure 8 As shown, the second sub-quantity and the fourth sub-quantity may be 3 (exemplarily, the second sub-quantity and the fourth sub-quantity in the actual product of the display panel 10 may be greater than 3, for example, the second sub-quantity and the fourth sub-quantity in the actual product of the display panel 10 may be 5), that is, the number of high-level output tubes 320a electrically connected to at least one driving unit 310 located in the arc edge area NA3 may be 3, and the number of low-level output tubes 320b electrically connected to at least one driving unit 310 located in the arc edge area NA3 may be 3.

[0120] In these optional embodiments, the performance loss caused by reducing the width of the first channel 321 of the single high-level output tube 320a and the single low-level output tube 320b in the arc edge area NA3 can be better compensated by respectively increasing the number of high-level output tubes 320a and low-level output tubes 320b electrically connected to the single driving unit 310 in the arc edge area NA3.

[0121] Fig.10 is a schematic diagram of a partial structure of an output transistor 320 in an arc edge area NA3 provided by another embodiment of the present application. Fig.11 1 is a connection diagram of a driving unit 310 and an output transistor 320 in an arc edge area NA3 provided by another embodiment of the present application.

[0122] like Fig.10 and Fig.11 As shown, in some optional embodiments, the length of at least one first channel 321 located in the arc edge area NA3 in at least one gate driving circuit 300 is smaller than the length of the first channel 321 located in the first straight edge area NA1.

[0123] Optionally, the length of the first channel 321 may refer to a dimension of the first channel 321 in the length direction LD thereof, or the length of the first channel 321 may refer to a distance between two adjacent source and drain regions 322 in the output transistor 320 .

[0124] Optionally, in the same gate driving circuit 300, the width of at least one first channel 321 located in the arc edge area NA3 is smaller than the width of the first channel 321 located in the first straight edge area NA1, and the length of at least one first channel 321 located in the arc edge area NA3 is smaller than the length of the first channel 321 located in the first straight edge area NA1, that is, Fig.10 and Fig.11 As shown, in each output transistor 320 of the same gate driving circuit 300, the width of at least one first channel 321 of the output transistor 320 located in the arc edge area NA3 may be smaller than the width of the first channel 321 of the output transistor 320 located in the first straight edge area NA1, and the length of at least one first channel 321 of the output transistor 320 located in the arc edge area NA3 is smaller than the length of the first channel 321 of the output transistor 320 located in the first straight edge area NA1.

[0125] In these optional embodiments, by setting the length of at least one first channel 321 located in the arc edge area NA3 in at least one gate driving circuit 300 to be smaller than the length of the first channel 321 located in the first straight edge area NA1, the effect of reducing the width of the first channel 321 of the output transistor 320 in the arc edge area NA3 on the performance of the output transistor 320 in the arc edge area NA3 can be reduced by reducing the length of at least one first channel 321 of the output transistor 320 in the arc edge area NA3.

[0126] Exemplarily, after reducing the width of at least one first channel 321 of a single output transistor 320 in the arc-edge area NA3, the length of at least one first channel 321 of the output transistor 320 in the arc-edge area NA3 can be reduced so that the width-to-length ratio of the output transistor 320 in the arc-edge area NA3 and the width-to-length ratio of the output transistor 320 in the first straight-edge area NA1 are not likely to have too large a difference, thereby better compensating for the performance loss caused by reducing the width of the first channel 321 of the single output transistor 320 in the arc-edge area NA3, so that the performance of the gate drive circuit 300 is not easily affected while the width of the non-display area NA is reduced.

[0127] In some optional embodiments, in the same gate driving circuit 300, the ratio of the width to the length of the first channel 321 located in the first straight edge area NA1 is a first ratio, and the ratio of the width to the length of the first channel 321 located in the arc edge area NA3 is a second ratio, and the first ratio is equal to the second ratio.

[0128] Exemplarily, in the same gate driving circuit 300, the width of the first channel 321 of the single output transistor 320 electrically connected to the driving unit 310 located in the first straight edge area NA1 is i, the width of the first channel 321 of the single output transistor 320 electrically connected to the driving unit 310 located in the arc edge area NA3 is j, the length of the first channel 321 of the single output transistor 320 electrically connected to the driving unit 310 located in the first straight edge area NA1 is k, and the length of the first channel 321 of the single output transistor 320 electrically connected to the driving unit 310 located in the arc edge area NA3 is p. Therefore, the first ratio is i / k, and the second ratio is j / p. The first ratio is equal to the second ratio, which can refer to i / k=j / p.

[0129] In this optional embodiment, by setting the first ratio equal to the second ratio, the width and length of the first channel 321 of the single output transistor 320 in the arc edge area NA3 can be appropriately reduced according to the width and length of the first channel 321 of the single output transistor 320 in the first straight edge area NA1, so that it is not easy to reduce the length of the first channel 321 of the single output transistor 320 in the arc edge area NA3 too much or too small after reducing the width of the first channel 321 of the single output transistor 320 in the arc edge area NA3, so that it is not easy to affect the performance of the gate drive circuit 300 in the arc edge area NA3.

[0130] Fig.12 is a connection diagram of a driving unit 310 and an output transistor 320 in a first straight edge area NA1 provided by another embodiment of the present application. Fig.13 1 is a connection diagram of a driving unit 310 and an output transistor 320 in an arc edge area NA3 provided by another embodiment of the present application.

[0131] like Fig.12 and Fig.13 As shown, in some optional embodiments, there are multiple gate driving circuits 300 , and the multiple gate driving circuits 300 are arranged along the width direction WD of the first channel 321 .

[0132] In this optional embodiment, different gate driving circuits 300 may be used to transmit different signals. By arranging multiple gate driving circuits 300 along the width direction WD of the first channel 321 , electrical connection between each gate driving circuit 300 and the sub-pixel 200 can be facilitated.

[0133] Optionally, the gate driving circuit 300 includes a gate scanning driving circuit 301 and a gate light emitting driving circuit 302 .

[0134] Optionally, the gate scanning driving circuit 301 can be used to provide a scanning signal (Scan signal) to a portion of the pixel transistors 221 of the sub-pixel 200, and the gate light emitting driving circuit 302 can be used to provide a light emitting control signal (EM signal) to another portion of the pixel transistors 221 of the sub-pixel 200.

[0135] Exemplarily, the gate scan driving circuit 301 can be used to electrically connect to the second gate 221b of at least one of the data writing transistor, the threshold compensation transistor and the reset transistor to provide a scan signal to the second gate 221b of at least one of the data writing transistor, the threshold compensation transistor and the reset transistor.

[0136] The gate light emitting driving circuit 302 may be used to be electrically connected to the second gate 221 b of the light emitting control transistor to provide a light emitting control signal to the second gate 221 b of the light emitting control transistor.

[0137] In some optional embodiments, the width of at least one first channel 321 located in the arc-edge region NA3 in the gate scan driving circuit 301 is smaller than the width of the first channel 321 located in the first straight-edge region NA1 .

[0138] Optionally, the first number in the gate scanning driving circuit 301 is smaller than the second number, or the length of at least one first channel 321 in the gate scanning driving circuit 301 located in the arc edge area NA3 is smaller than the length of the first channel 321 located in the first straight edge area NA1.

[0139] Optionally, the gate scanning drive circuit 301 includes a first type of scanning circuit 301a and a second type of scanning circuit 301b. The first type of scanning circuit 301a can be used to provide a first type of scanning signal (Scanp signal) to a portion of pixel transistors 221 of the sub-pixel 200, and the second type of scanning circuit 301b can be used to provide a second type of scanning signal (Scann signal) to a portion of pixel transistors 221 of the sub-pixel 200.

[0140] Optionally, the width of at least one first channel 321 in the arc-edge region NA3 of the first type scanning circuit 301a is smaller than the width of the first channel 321 in the first straight-edge region NA1. Exemplarily, the first number in the first type scanning circuit 301a is smaller than the second number, or the length of at least one first channel 321 in the first type scanning circuit 301a in the arc-edge region NA3 is smaller than the length of the first channel 321 in the first straight-edge region NA1.

[0141] Optionally, the width of at least one first channel 321 in the arc edge area NA3 of the second type scanning circuit 301b is smaller than the width of the first channel 321 in the first straight edge area NA1. Exemplarily, the first number in the second type scanning circuit 301b is smaller than the second number, or the length of at least one first channel 321 in the second type scanning circuit 301b in the arc edge area NA3 is smaller than the length of the first channel 321 in the first straight edge area NA1.

[0142] In some optional embodiments, the width of at least one first channel 321 in the gate light emitting driving circuit 302 located in the arc edge area NA3 is smaller than the width of the first channel 321 located in the first straight edge area NA1.

[0143] Optionally, the first number in the gate light-emitting driving circuit 302 is smaller than the second number, or the length of at least one first channel 321 in the gate light-emitting driving circuit 302 located in the arc edge area NA3 is smaller than the length of the first channel 321 located in the first straight edge area NA1.

[0144] The embodiment of the second aspect of the present application provides a display device, and the display device includes the display panel 10 of any of the above-mentioned embodiments. Since the display device provided by the embodiment of the second aspect of the present application includes the display panel 10 of any of the above-mentioned first aspects, the display device provided by the embodiment of the second aspect of the present application has the beneficial effects of the display panel 10 of any of the above-mentioned first aspects, which will not be described in detail here.

[0145] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0146] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area arranged around the display area, the non-display area includes a first straight edge area located at least on one side of the display area in a first direction, a second straight edge area located at least on one side of the display area in a second direction, and an arc edge area connected between the first straight edge area and the second straight edge area, the first direction intersects with the second direction, and the display panel includes: A sub-pixel, arranged in the display area; A gate driving circuit is arranged in the first straight edge area and the arc edge area, the gate driving circuit includes a plurality of driving units and output transistors electrically connected to the driving units, the output transistors are electrically connected to the sub-pixels, the output transistors have a first channel, and the width direction of the first channel is a direction from the non-display area to the display area, Wherein, a width of at least one of the first channels located in the arc-edge region in at least one of the gate driving circuits is smaller than a width of the first channel located in the first straight-edge region.

2. The display panel according to claim 1, characterized in that: At least part of the output transistors electrically connected to the same driving unit are arranged in parallel with each other, the output transistor has a first gate, at least one of the driving units located in the first straight edge region is electrically connected to the first gates of a first number of the output transistors, at least one of the driving units located in the arc edge region is electrically connected to the first gates of a second number of the output transistors, and the first number in at least one of the gate driving circuits is less than the second number; Preferably, in the same gate driving circuit, the width of at least one of the first channels located in the arc edge region is smaller than the width of the first channels located in the first straight edge region, and the first number is smaller than the second number.

3. The display panel according to claim 2, characterized in that: In the same gate driving circuit, the sum of the widths of the first number of the first channels located in the first straight edge region is equal to the sum of the widths of the second number of the first channels located in the arc edge region.

4. The display panel according to claim 2, characterized in that: The output transistors include a high-level output transistor and a low-level output transistor. The high-level output tubes electrically connected to the same driving unit are arranged in parallel with each other, at least one of the driving units located in the first straight edge region is electrically connected to the first gates of a first sub-number of the high-level output tubes, at least one of the driving units located in the arc edge region is electrically connected to the first gates of a second sub-number of the high-level output tubes, and the first sub-number in at least one of the gate driving circuits is less than the second sub-number, And / or, the low-level output tubes electrically connected to the same driving unit are arranged in parallel with each other, at least one of the driving units located in the first straight edge area is electrically connected to the first gates of a third sub-number of the low-level output tubes, at least one of the driving units located in the arc edge area is electrically connected to the first gates of a fourth sub-number of the low-level output tubes, and the third sub-number in at least one of the gate driving circuits is less than the fourth sub-number.

5. The display panel according to claim 1, characterized in that: The length direction of the first channel is perpendicular to the width direction of the first channel, and the length of at least one of the first channels located in the arc edge region in at least one of the gate driving circuits is smaller than the length of the first channel located in the first straight edge region; Preferably, in the same gate driving circuit, the width of at least one of the first channels located in the arc edge region is smaller than the width of the first channel located in the first straight edge region, and the length of at least one of the first channels located in the arc edge region is smaller than the length of the first channel located in the first straight edge region.

6. The display panel according to claim 5, characterized in that: In the same gate driving circuit, the ratio of the width to the length of the first channel located in the first straight edge area is a first ratio, and the ratio of the width to the length of the first channel located in the arc edge area is a second ratio, and the first ratio is equal to the second ratio.

7. The display panel according to claim 1, characterized in that: The output transistor has a first source and drain, and the display panel further includes a first signal line, and the first source and drain of the output transistor is electrically connected to the sub-pixel through the first signal line. The first signal line electrically connected to the output transistor located in the first straight edge region extends along the first direction, and / or the first signal line electrically connected to the output transistor located in the arc edge region includes a first segment and a second segment connected in a bent manner, the first segment is connected to the first source and drain of the output transistor located in the arc edge region, and the second segment is connected to the first segment and extends along the first direction; Preferably, each of the output transistors electrically connected to the same driving unit is electrically connected to the same first signal line.

8. The display panel according to any one of claims 1 to 7, characterized in that: The length direction of the first channel is perpendicular to the width direction of the first channel, the plurality of driving units are arranged along the length direction of the first channel, and / or the plurality of output transistors are arranged along the length direction of the first channel; Preferably, the output transistor further has source and drain regions arranged on both sides of the first channel in the length direction, and at least one of the source and drain regions of at least one of the output transistors can be reused as one of the source and drain regions of an adjacent output transistor.

9. The display panel according to any one of claims 1 to 7, characterized in that: There are multiple gate driving circuits, and the multiple gate driving circuits are arranged along the width direction of the first channel; Preferably, the gate driving circuit includes a gate scanning driving circuit and a gate light-emitting driving circuit, the width of at least one of the first channels located in the arc-edge region in the gate scanning driving circuit is smaller than the width of the first channels located in the first straight-edge region, and / or the width of at least one of the first channels located in the arc-edge region in the gate light-emitting driving circuit is smaller than the width of the first channels located in the first straight-edge region; Preferably, the gate scanning drive circuit includes a first type of scanning circuit and a second type of scanning circuit, the width of at least one of the first channels located in the arc edge area in the first type of scanning circuit is smaller than the width of the first channel located in the first straight edge area, and / or the width of at least one of the first channels located in the arc edge area in the second type of scanning circuit is smaller than the width of the first channel located in the first straight edge area.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

Images