Display device and method for manufacturing display device

Abstract

Embodiments of the present disclosure relate to a display device and a method for manufacturing the same, and may enhance reliability of the display device by reducing an inflow path of harmful gas. The apparatus includes an emissive region and a non-emissive region. The apparatus includes a first planarization layer and a second planarization layer. The second planarization layer includes a first opening in the emission region and a second opening in the non-emission region. The device includes an anode electrode, a light emitting layer, and a cathode electrode on the second planarization layer. The apparatus includes a bank layer disposed in a portion of the emission region and in at least a partial region on the first planarization layer and the second planarization layer in the non-emission region, and the bank layer includes at least one trench in the second opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0152308, filed on November 7, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0004] As technology advances, display devices have been developed to produce higher quality images. In order for a display device to express a higher quality image, the image should be expressed with a greater number of pixels, and for this purpose, the display device requires more internal components such as circuits or elements for emitting light. Therefore, the components within the display device have been reduced in size and integrated.

[0005] However, as internal components are downsized and integrated, the display device may experience reliability degradation as gaps between components decrease, and with a higher chance of interference between components, degrade its optical characteristics. Summary of the invention

[0006] Embodiments of the present disclosure may provide a display device having enhanced reliability and a method of manufacturing the same.

[0007] Embodiments of the present disclosure may provide a display device and a method of manufacturing the same, which may enhance optical characteristics by minimizing interference between components in the display device.

[0008] An embodiment of the present disclosure may provide a display device comprising: a substrate in which a plurality of sub-pixels including an emission region and a non-emission region are arranged; a first planarization layer on the substrate; a second planarization layer arranged on the first planarization layer and including a first opening located in the emission region and a second opening located in the non-emission region; an anode electrode arranged on the second planarization layer; a dam layer, the dam layer being arranged in a portion of the emission region and in at least a portion of the first planarization layer and the second planarization layer in the non-emission region, and the dam layer including at least one groove located in the second opening; a light-emitting layer arranged on the anode electrode; and a cathode electrode arranged on the light-emitting layer.

[0009] An embodiment of the present disclosure may provide a display device comprising: a substrate comprising an emission region and a transmission region; a plurality of insulating layers on the substrate; a first planarization layer disposed on the plurality of insulating layers; a second planarization layer disposed on the first planarization layer and comprising a first opening located in the emission region and a second opening located between the emission region and the transmission region; an anode electrode disposed on the second planarization layer; a dam layer disposed in a portion of the emission region and in at least a portion of the first planarization layer and the second planarization layer between the emission region and the transmission region; a light-emitting layer disposed on the anode electrode; and a cathode electrode disposed on the light-emitting layer.

[0010] An embodiment of the present disclosure may provide a method for manufacturing a display device, the method comprising: forming a first planarization layer on a substrate; forming a second planarization layer so that a first opening is formed in the emission region and a second opening is formed in the non-emission region on the first planarization layer; forming an anode electrode on a portion of the second planarization layer; and forming a dam layer to have an opening in the emission region and a groove in the non-emission region.

[0011] According to an embodiment of the present disclosure, a display device having enhanced reliability and a method of manufacturing the same may be provided.

[0012] According to an embodiment of the present disclosure, a display device and a method of manufacturing the same may be provided, which may enhance optical characteristics by minimizing interference between components in the display device.

[0013] According to an embodiment of the present disclosure, a display device and a method of manufacturing the same may be provided, which may improve the efficiency of the display device by enhancing the reliability and optical characteristics of the display device and thus enable low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a view showing an example of a structure of a display device according to an embodiment of the present disclosure and a circuit structure included in a sub-pixel;

[0016] Figure 2A is a view showing an example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure;

[0017] Figure 2B is shown with Figure 2A A view of an example of a circuit design structure corresponding to a sub-pixel structure;

[0018] Figure 3 It is shown Figure 2B A view of an example of a cross-sectional structure of part II′;

[0019] Figure 4 It is shown Figure 3 an enlarged view of a portion A of;

[0020] Figure 5 is a view showing another example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure;

[0021] Figure 6 It is shown Figure 5 A view showing an example of a cross-sectional structure of a portion II-II′;

[0022] Figure 7 is a view showing another example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure;

[0023] Figure 8 It is shown Figure 7 A view of an example of a cross-sectional structure of a portion III-III′;

[0024] Fig. 9 It is shown Figure 7 A view of another example of the cross-sectional structure of a portion III-III′; and

[0025] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E is a view illustrating an example of a method for manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in the accompanying drawings, the same reference numerals and signs may be used to designate the same or similar parts, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure quite unclear, the detailed description of the well-known functions and parts incorporated herein will be omitted. Terms such as "including", "having", "comprising", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other parts, unless these terms are used together with the term "only". As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0027] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0028] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be interpreted that not only the first element can be “directly connected or coupled to” the second element, or “directly contact or overlaps” the second element, but also a third element can be “interposed” between the first and second elements, or the first and second elements can be “connected or coupled to”, “contacts or overlaps”, etc., with each other via a fourth element. Here, the second element can be included in at least one element of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., with each other.

[0029] When time-related terms such as "after", "subsequently", "next", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless the term "immediately" or "immediately" is used together.

[0030] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. shown in the drawings used to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0031] For ease of description, dimensions including the size and thickness of each component shown in the drawings are shown, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions including the relative size, position and thickness of the components shown in the various drawings submitted herewith are part of the present disclosure.

[0032] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0033] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a view showing an example of a structure of a display device according to an embodiment of the present disclosure and a circuit structure included in a sub-pixel.

[0035] Reference Figure 1 , a plurality of sub-pixels SP may be provided in the display area of ​​the display device 100 .

[0036] Each of the plurality of sub-pixels SP may include a light emitting element ED and a sub-pixel circuit unit configured to drive the light emitting element ED.

[0037] The sub-pixel circuit unit may include a driving transistor T1 for driving the light emitting element ED, a scanning transistor T2 for transmitting a data voltage VDATA to a first node N1 of the driving transistor T1 , and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0038] The driving transistor T1 may include a first node N1 to which a data voltage may be applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL. The first node N1 in the driving transistor T1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. For ease of description, an example in which the first node N1 in the driving transistor T1 is a gate node, the second node N2 is a source node, and the third node N3 is a drain node is described below.

[0039] The light emitting element ED may include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​may be a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor T1 of each sub-pixel SP. The cathode electrode CE may be a common electrode generally disposed in a plurality of sub-pixels SP and may apply a base voltage VSS thereto.

[0040] On the contrary, the anode electrode AE ​​may be a common electrode, and the cathode electrode CE may be a pixel electrode. Hereinafter, for convenience of description, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode.

[0041] The light emitting element ED may have one or more predetermined emission areas.

[0042] The light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode or a quantum dot light emitting element. When the light emitting element ED is an organic light emitting diode, the light emitting layer EL of the light emitting element ED may include an organic light emitting layer EL including an organic material.

[0043] The scan transistor T2 may be turned on / off controlled by a scan signal SCAN as a gate signal applied through the gate line GL, and may be electrically connected between the first node N1 of the driving transistor T1 and the data line DL.

[0044] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor T1 .

[0045] The sub-pixel circuit unit may have a 2T (transistor) 1C (capacitor) structure including two transistors DT and ST and one capacitor Cst, and in some cases, each sub-pixel SP may further include one or more transistors or one or more capacitors.

[0046] The capacitor Cst may be an external capacitor intentionally designed outside the driving transistor T1, rather than a parasitic capacitor (e.g., Cgs or Cgd) which is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor T1. Each of the driving transistor T1 and the scanning transistor T2 may be an n-type transistor or a p-type transistor.

[0047] Since the circuit elements in each sub-pixel SP (particularly the light emitting element ED implemented as an organic light emitting diode (OLED) including an organic material) are easily affected by external moisture or oxygen, an encapsulation layer 180 may be provided on the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit elements (particularly the light emitting element ED). The encapsulation layer 180 may be provided to cover the light emitting element ED.

[0048] The sub-pixel SP may also be referred to as a pixel unit, and each of the plurality of sub-pixels SP may be configured to be connected to a pixel unit according to a circuit structure. Figure 1 Different forms of the above are provided on the display panel 110 .

[0049] Figure 2A is a view illustrating an example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure.

[0050] Reference Figure 1 and Figure 2A , each of the plurality of sub-pixels SP may include a light emitting element ED that emits light of a different color. The plurality of sub-pixels SP may be divided into a first sub-pixel, a second sub-pixel, and a third sub-pixel according to the color of the light emitted by the light emitting element ED. For example, the first sub-pixel may include a light emitting element ED1 (not shown) that emits red light. The first sub-pixel may be referred to as a first pixel unit, the second sub-pixel may be referred to as a second pixel unit, and the third sub-pixel may be referred to as a third pixel unit.

[0051] The first sub-pixel, the second sub-pixel, and the third sub-pixel may be disposed adjacent to each other on the display panel 110 .

[0052] Each sub-pixel SP may include an emission area EA, and a size and a shape of the emission area EA of each sub-pixel SP may be different for each pixel.

[0053] There may be a non-emission region that does not emit light between the sub-pixels SP. The non-emission region may be a region other than the emission region EA in one sub-pixel SP.

[0054] The anode electrode AE ​​may be disposed in a region wider than the emission area EA.

[0055] The reliability of the display device 100 may be enhanced according to the structure and area where the anode electrode AE ​​is disposed. The arrangement structure and area of ​​the anode electrode AE ​​are described below.

[0056] Figure 2B is shown with Figure 2A A view of an example of a circuit design structure corresponding to a sub-pixel structure. Figure 3 It is shown Figure 2B A view of an example of a cross-sectional structure of part II′.

[0057] Reference Figure 2B and Figure 3 The substrate 120 may include a first substrate 121 , an interlayer inorganic film 122 disposed on the first substrate 121 , and a second substrate 123 disposed on the interlayer inorganic film 122 .

[0058] The first substrate 121 and the second substrate 123 may be formed of a plastic material such as polyimide.

[0059] The interlayer inorganic film 122 serves to prevent moisture from penetrating into the substrate, and may be formed of a single layer or multiple layers such as silicon oxide (SiOx). However, embodiments of the present disclosure are not limited thereto.

[0060] A buffer layer 130 may be disposed on the substrate 120 .

[0061] The buffer layer 130 may include a multi-buffer layer 131 and an active buffer layer 132 disposed on the multi-buffer layer 131. The buffer layer 130 may enhance adhesion between a layer formed on the buffer layer 130 and the substrate 120, and delay diffusion of moisture or oxygen penetrating into the substrate 120. The buffer layer 130 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0062] The barrier layer 200 may be positioned between the multi-buffer layer 131 and the active buffer layer 132 .

[0063] The barrier layer 200 may be disposed in a partial region on the multi-buffer layer 131, and a plurality of barrier layers 200 may exist. Figure 3 As shown, the barrier layer 200 may be disposed in a region overlapping with the capacitor electrode.

[0064] The barrier layer 200 may prevent the semiconductor pattern from malfunctioning by irradiating the semiconductor pattern with light incident from the outside of the display device 100 .

[0065] In addition, the blocking layer 200 may be formed of an opaque conductive material to block external light. For example, the blocking layer 200 may be formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au), or an alloy thereof.

[0066] In another sub-pixel SP of the same layer as the barrier layer 200 , a layer having the same function as the barrier layer 200 may be provided using the first material layer M1 .

[0067] A gate insulating layer 140 and an active layer 210 may be disposed on the buffer layer 130 .

[0068] The gate insulating layer 140 is a layer for insulating the active layer 210 and the gate electrode 220 , and may be disposed between the active layer 210 and the gate electrode 220 .

[0069] The active layer 210 may be formed of a polycrystalline semiconductor material. For example, the polycrystalline semiconductor may be formed of low temperature polysilicon (LTPS) having high mobility.

[0070] A source region and a drain region made conductive by a doping process may exist on two opposite sides of the active layer 210. The source / drain region may refer to a portion of the active layer 210 connected to the source / drain electrode 240.

[0071] In another region of the same layer as the active layer 210 , a layer having the same function as the active layer 210 may also be provided using the second material layer M2 .

[0072] A gate electrode 220 and an interlayer insulating layer 150 may be disposed on the gate insulating layer 140 .

[0073] The interlayer insulating layer 150 may include a first interlayer insulating layer 151 and a second interlayer insulating layer 152 disposed on the first interlayer insulating layer 151 .

[0074] The interlayer insulating layer 150 may be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of an insulating organic material.

[0075] The gate electrode 220 may be disposed between the first interlayer insulating layer 151 and the gate insulating layer 140 .

[0076] The first capacitor electrode constituting the storage capacitor may be provided on the same layer as the gate electrode 220 , and the first capacitor electrode may be provided using the third material layer M3 .

[0077] The second capacitor electrode 230 may be disposed between the first interlayer insulating layer 151 and the second interlayer insulating layer 152. A layer having the same function as the second capacitor electrode 230 may be disposed on the same layer as the second capacitor electrode 230 using the fourth material layer M4.

[0078] The source / drain electrode 240 may be disposed on the interlayer insulating layer 150. The source / drain electrode 240 may be formed through the interlayer insulating layer 150 and the gate insulating layer 140, and may be electrically connected to the source / drain region of the active layer 210.

[0079] The fifth material layer M5 may also be used to provide an electrode for wiring on the same layer as the source / drain electrode 240 .

[0080] A planarization layer 160 may be disposed on the interlayer insulating layer 150 and the source / drain electrodes 240 .

[0081] The planarization layer 160 may include a first planarization layer 161 and a second planarization layer 162 disposed on the first planarization layer 161 .

[0082] The planarization layer 160 may protect a thin film transistor disposed therebelow, and may alleviate or planarize steps caused by various patterns.

[0083] The planarization layer 160 may be formed of at least one of organic insulating materials such as, but not limited to, benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The first planarization layer 161 and the second planarization layer 162 may be formed of the same material.

[0084] A hole for electrically connecting the thin film transistor and the light emitting element ED may be formed in the planarization layer 160. The anode electrode AE ​​of the light emitting element ED may be electrically connected to the source / drain electrode 240 of the thin film transistor through the hole.

[0085] The second planarization layer 162 may be disposed on the first planarization layer 161 and may have a plurality of openings. Figure 4 A detailed structure of the opening of the second planarization layer 162 is described.

[0086] A bank layer 170 and an anode electrode AE ​​may be disposed on the second planarization layer 162 .

[0087] The bank layer 170 may be disposed on the second planarization layer 162 and the anode electrode AE. A spacer 171 may be further disposed in a partial region on the bank layer 170.

[0088] The bank layer 170 may have at least one opening region and at least one first trench 300, and the following refers to Figure 4 Describe its detailed structure.

[0089] When the display device 100 has a top emission type, the anode electrode AE ​​is a reflective electrode that reflects light and may be provided using an opaque conductive material.

[0090] A light emitting layer EL may be disposed on the anode electrode AE ​​and the bank layer 170 .

[0091] The light emitting layer EL may include one of a red organic light emitting layer, a green organic light emitting layer, and a blue organic light emitting layer to emit light of a specific color.

[0092] The light emitting layer EL may further include a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer in addition to the organic light emitting layer, but is not limited thereto.

[0093] A cathode electrode CE may be provided on the light emitting layer EL.

[0094] When the display device 100 has a top emission type, the cathode electrode CE may be provided using a transparent conductive material that transmits light.

[0095] An encapsulation layer 180 may be disposed on the cathode electrode CE.

[0096] although Figure 3 Although not shown, the encapsulation layer 180 may include a first encapsulation layer 181 , a second encapsulation layer 182 disposed on the first encapsulation layer 181 , and a third encapsulation layer 183 disposed on the second encapsulation layer 182 .

[0097] The encapsulation layer 180 may be formed of a transparent material to transmit light emitted from the light emitting layer EL.

[0098] The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of at least one inorganic material of silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlyOz), and the second encapsulation layer 182 may be an organic material, for example, a polymer, such as silicon oxycarbide (SiOCz), epoxy, polyimide, polyethylene, acrylate, etc. However, the present disclosure is not necessarily limited thereto.

[0099] A layer for providing a touch function may also be disposed on the encapsulation layer 180. Figure 3Although not shown in the figure, a touch insulating layer, a plurality of touch electrodes, and a touch buffer layer may be disposed on the encapsulation layer 180 to provide a touch function. However, the present disclosure is not necessarily limited thereto.

[0100] In the following, reference is made to Figure 3 and Figure 4 The arrangement structure of the anode electrode AE ​​in the emission area EA and the bank structure in the non-emission area NEA are described in detail.

[0101] Figure 4 It is shown Figure 3 Magnified view of portion A.

[0102] Reference Figure 3 and Figure 4 , a sub-pixel SP or a pixel unit of the display device 100 may include an emission area EA.

[0103] The emission area EA may include an area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap. The overlapping area described above may also be referred to as a first emission area (not shown).

[0104] The emission area EA may include an area other than the area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap. For example, some of the light emitted from the area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap may be reflected from the first electrode inclined portion AEa of the anode electrode AE ​​and travel in a direction perpendicular to the substrate. Therefore, even if the anode electrode AE, the light emitting layer EL, and the cathode electrode CE do not overlap each other in this area, the area where the first electrode inclined portion AEa is provided may be included in the emission area EA. The area where the first electrode inclined portion AEa is provided may also be referred to as a second emission area (not shown).

[0105] However, the emission area EA may partially include an area where no light is emitted. For example, no light may be emitted between an area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap with each other (first emission area) and an area where the first electrode inclined portion AEa is provided (second emission area).

[0106] There may be a non-emission area NEA outside the emission area EA. The non-emission area NEA is an area that does not emit light and may refer to an area other than the emission area EA, and may refer to an area between the emission areas EA of the sub-pixel SP or pixel unit.

[0107] In other words, the non-emission area NEA may refer to an area from one end of the emission area EA of one sub-pixel SP to one end of the emission area of ​​another sub-pixel SP.

[0108] The second planarization layer 162 may be open in the emission area EA and the non-emission area NEA. The second planarization layer 162 may have a first opening FO in the emission area EA, and may have a second opening SO in the non-emission area NEA. The first opening FO is formed in the second planarization layer 162, and the first opening FO extends through the second planarization layer 162. Similarly, the second opening SO is formed in the second planarization layer 162, and the second opening SO extends through the second planarization layer 162. When the first opening FO and the second opening SO are formed, the second planarization layer 162 may have an inclined surface in each of the emission area EA and the non-emission area NEA. The positions of the first opening FO and the second opening SO are different, so that the first opening FO does not overlap with the second opening SO from a plan view.

[0109] The second planarization layer 162 may have inclined surfaces (e.g., a first inclined surface FIS and a second inclined surface SIS) at two opposite ends of the emission area EA, and the inclined surfaces (e.g., the first inclined surface FIS and the second inclined surface SIS) at the two opposite ends of the emission area EA may be inclined at the same angle θ. In detail, the first inclined surface FIS of the second planarization layer 162 has an inclination angle θ relative to the upper surface US of the first planarization layer 161 (or the upper surface USS of the substrate 120), and the second inclined surface SIS of the second planarization layer 162 has the same inclination angle θ relative to the upper surface US of the first planarization layer 161 (or the upper surface USS of the substrate 120).

[0110] In addition, the second planarization layer 162 may have inclined surfaces (e.g., third inclined surface THIS and fourth inclined surface FRIS) at two opposite ends of the non-emission area NEA, and the inclined surfaces (e.g., third inclined surface THIS and fourth inclined surface FRIS) at two opposite ends of the non-emission area NEA may form an inclination of the same angle θ1. In detail, the third inclined surface THIS of the second planarization layer 162 has an inclination angle θ1 relative to the upper surface US of the first planarization layer 161 (or the upper surface USS of the substrate 120), and the fourth inclined surface FRIS of the second planarization layer 162 has the same inclination angle θ1 relative to the upper surface US of the first planarization layer 161 (or the upper surface USS of the substrate 120). In some embodiments, the inclination angle θ may be the same as the inclination angle θ1.

[0111] The anode electrode AE ​​may be disposed on the second planarization layer 162 . Since the anode electrode AE ​​is disposed to cover the upper surface of the second planarization layer 162 , the anode electrode AE ​​may be disposed along the inclined surface of the second planarization layer 162 .

[0112] The anode electrode AE ​​may have a first electrode inclined portion AEa in the first opening of the second planarization layer 162. The first electrode inclined portion AEa may be inclined at the same angle as the inclined surface in the first opening of the second planarization layer 162.

[0113] In addition, the anode electrode AE ​​may have a second electrode inclined portion AEb in the second opening of the second planarization layer 162. The second electrode inclined portion AEb may be inclined at the same angle as the inclined surface in the second opening of the second planarization layer 162.

[0114] The first electrode inclined portion AEa and the second electrode inclined portion AEb may be inclined at the same angle, and the second electrode inclined portion AEb may be inclined at a greater angle than the first electrode inclined portion AEa, but is not limited thereto. Here, the region where the first electrode inclined portion AEa is provided may be the second emission region, but the region where the second electrode inclined portion AEb is provided may not be the second emission region. In other words, the first opening of the second planarization layer 162 has at least one emission region including the second emission region, but the second opening may lack at least one emission region including the second emission region.

[0115] like Figure 3 and Figure 4 As shown, the first planarization layer 161 has an upper surface US. The anode electrode AE ​​located on the second planarization layer 162 contacts the upper surface US of the first planarization layer 161 at the first opening FO.

[0116] The bank layer 170 may be provided to cover upper surfaces of the anode electrode AE ​​and the first planarization layer 161 .

[0117] The bank layer 170 may have an open area in the emission area EA, may have a first groove 300 in the non-emission area NEA, and a first emission area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap may be defined by an open area of ​​the bank layer 170. In other words, the first opening of the second planarization layer 162 includes the first emission area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap.

[0118] For example, Figure 2A As shown, the first trench 300 is disposed between the second electrode inclined portions AEb of the corresponding anode electrodes AE of two adjacent sub-pixels. In addition, the first trench 300 may be disposed between the corresponding second emission regions (ie, the first electrode inclined portions AEa of the anode electrodes AE) of two adjacent sub-pixels.

[0119] The bank layer 170 may be disposed along the first electrode inclined portion AEa of the anode electrode AE ​​in the emission area EA, and may have a first bank inclined portion 170a having the same angle as the first electrode inclined portion AEa. The first bank inclined portion 170a may be equally formed at both opposite ends of the emission area EA. One surface of the first bank inclined portion 170a may be in contact with the light emitting layer EL, and the other surface of the first bank inclined portion 170a may be in contact with the first electrode inclined portion AEa.

[0120] The bank layer 170 may be disposed along the second electrode inclined portion AEb of the anode electrode AE ​​in the non-emission area NEA, and may have a second bank inclined portion 170b having the same angle as the second electrode inclined portion AEb. The second bank inclined portion 170b may be equally formed at two opposite ends of the non-emission area NEA. One surface of the second bank inclined portion 170b may be in contact with the light emitting layer EL, and the other surface of the second bank inclined portion 170b may be in contact with the second electrode inclined portion AEb.

[0121] The bank layer 170 may include a flat region 170c (also referred to as a flat portion 170c) disposed in contact with the upper surface of the first planarization layer 161 in a region where the anode electrode AE ​​is not disposed with the non-emission area NEA. In other words, the second opening of the second planarization layer 162 does not include the first emission region where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap.

[0122] The upper surface of the flat region 170c may be disposed to contact the lower surface of the light emitting layer EL, and the flat region 170c may be connected to the second bank inclined portion 170b. The flat region 170c of the bank layer 170, the light emitting layer EL, and the cathode electrode CE overlap in the second opening of the second planarization layer 162. Here, the flat region 170c of the bank layer 170 may space the planarization layer 160 and the light emitting layer EL from each other. In this case, by minimizing the thickness of the flat region 170c, the influence of the harmful gas HG generated from the planarization layer 160 on the light emitting layer EL may be minimized, thereby enhancing the reliability of the display device 100.

[0123] As described below, since the flat region 170c is formed using a semi-transmissive reflection mask, the flat region 170c may have a height lower than a height of the bank layer 170 on a region where the second planarization layer 162 is disposed. In other words, the height of the bank layer 170 in a region where the first trench 300 is formed may be lower than the height of the bank layer 170 in a region where the second planarization layer 162 is disposed.

[0124] In some embodiments, the planar region 170 c of the bank layer 170 is in direct contact with the upper surface US of the first planarization layer 161 at the second opening SO.

[0125] The thickness of the first bank inclined portion 170a (i.e., the distance from the surface of the first bank inclined portion 170a in contact with the light emitting layer EL to the surface thereof in contact with the first electrode inclined portion AEa) may be greater than the thickness of the second bank inclined portion 170b (i.e., the distance from the surface of the second bank inclined portion 170b in contact with the light emitting layer EL to the surface thereof in contact with the second electrode inclined portion AEb). However, the present disclosure is not necessarily limited thereto.

[0126] The thickness of the flat region 170c (ie, the distance from the surface of the flat region 170c contacting the first planarization layer 161 to the surface thereof contacting the light emitting layer EL) may be greater than the thickness of the second bank inclined portion 170b. However, the present disclosure is not necessarily limited thereto.

[0127] In some embodiments, the bank layer 170 includes a first bank inclined portion 170a and a second bank inclined portion 170b adjacent to the first bank inclined portion 170a. In some embodiments, the first bank inclined portion 170a and the second bank inclined portion 170b are located on the second planarization layer 162. In some embodiments, the first bank inclined portion 170a and the second bank inclined portion 170b are located between the light emitting layer EL and the anode electrode AE.

[0128] A light emitting layer EL may be disposed on the bank layer 170 .

[0129] A cathode electrode CE may be provided on the light emitting layer EL.

[0130] Since the bank layer 170 has the first trench 300 in the non-emission area NEA, the height of the bank layer 170 in the region where the second planarization layer 162 is provided may be greater than that in the region where the second planarization layer 162 is not provided. In other words, the distance from the upper surface of the cathode electrode CE to the upper surface of the first planarization layer 161 in the region where the first trench 300 is formed may be smaller than that in the region where the first trench 300 is not formed.

[0131] In addition, a distance from the upper surface of the cathode electrode CE to the upper surface of the first planarization layer 161 in the first opening of the second planarization layer 162 may be smaller than a distance in a region where the first trench 300 is formed.

[0132] An encapsulation layer 180 may be disposed on the bank layer 170 .

[0133] As described above, since the bank layer 170 has the first groove 300 in the non-emission area NEA, the length of the cathode electrode CE and the light emitting layer EL disposed in the non-emission area NEA may be greater than when the bank layer 170 does not have the first groove 300. When the lengths of the cathode electrode CE and the light emitting layer EL become longer, the path of the current flowing through the cathode electrode CE or the light emitting layer EL becomes longer, and thus the resistance may increase. In other words, the resistance of the cathode electrode CE or the light emitting layer EL may increase in the non-emission area NEA or in the area between the emission areas EA of adjacent sub-pixels SP. Therefore, since the amount of current flowing between adjacent sub-pixels SP may decrease, interference that may occur as the distance between the sub-pixels SP decreases may decrease.

[0134] In addition, since the bank layer 170 has the narrow second bank inclined portion 170b in the non-emission area NEA, the path of the harmful gas HG generated from the planarization layer 160 entering the light emitting element ED can be reduced compared to when the second bank inclined portion 170b does not exist. In addition, the second electrode inclined portion AEb of the anode electrode AE ​​can partially prevent the harmful gas HG from entering the light emitting element ED through the bank layer 170, thereby reducing the path of the harmful gas HG entering the light emitting element ED compared to when the second electrode inclined portion AEb does not exist. Therefore, the reliability of the display device 100 can be enhanced by minimizing the influence of the harmful gas HG on the light emitting element ED.

[0135] Reference Figure 4 , the anode electrode AE ​​exposes at least a portion PPP of the upper surface US of the first planarization layer 161. In the exposed portion PPP of the upper surface US of the first planarization layer 161, the anode electrode AE ​​does not cover the exposed portion PPP. In some embodiments, the first opening FO overlaps with the emission area EA of the display device (for example, the emission area EA corresponding to the area where the light emitting element ED emits light) from a plan view. In some embodiments, the second opening SO overlaps with the non-emission area NEA of the display device from a plan view.

[0136] Hereinafter, an example of another structure to which an embodiment of the present disclosure can be applied is described. Figure 4 Those contents described are not repeated below.

[0137] Figure 5 is a view illustrating another example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure.

[0138] Reference Figure 5 , the display device 100 may include a plurality of sub-pixels SP and a transmission area TMA on a substrate 120 .

[0139] As described above, the plurality of sub-pixels SP may include a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0140] The first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in a straight line on the same plane. The first sub-pixel may be arranged between the second sub-pixel and the third sub-pixel. However, the present disclosure is not necessarily limited thereto.

[0141] although Figure 5 Although not shown in the figure, the display device 100 may include a plurality of wiring units. The plurality of wiring units may include a circuit for providing a voltage for driving a transistor or a light emitting element ED in a sub-pixel SP.

[0142] A plurality of wiring units may be arranged to intersect the sub-pixels SP. Specifically, a plurality of wiring units may be arranged to intersect a line on which the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged. A plurality of wiring units may be arranged to be spaced apart from each other and may be arranged in a straight line below the second sub-pixel and the third sub-pixel. In other words, a line on which a plurality of wiring units are arranged may intersect a line on which the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged.

[0143] The transmissive area TMT may be provided between a plurality of adjacent wiring units. The transmissive area TMA may be defined as an area having a higher transparency than a surrounding area, and may be provided on the front surface of the display panel according to the area in which it is provided, for increasing the transmittance of the display panel, or may be provided on a sensor for identifying an object, for providing a path for light to pass through.

[0144] The transmission area TMA may be disposed in an area different from a line where the first sub-pixel, the second sub-pixel, and the third sub-pixel are disposed. A plurality of adjacent wiring units and the first sub-pixel may be disposed around the transmission area TMA.

[0145] Some layers in the display panel 110 may be omitted from the transmissive area TMA.

[0146] Figure 6 It is shown Figure 5 A view of an example of a cross-sectional structure of part II-II′.

[0147] Reference Figure 6 , the transmission area TMA may be located in an area other than the emission area EA.

[0148] The first planarization layer 161, the second planarization layer 162, and the anode electrode AE ​​may not be disposed in the region overlapping the transmission region TMA.

[0149] A dummy anode electrode DAE may be provided between the emission area EA and the transmission area TMA. The dummy anode electrode DAE may be provided on the same layer as the anode electrode AE ​​(i.e., the second planarization layer 162). The dummy anode electrode DAE may not overlap with the light emitting layer EL and the cathode electrode CE. In other words, the dummy anode electrode DAE may be provided in the non-emission area.

[0150] The bank layer 170 may have a second groove 600 between the emission area EA and the transmission area TMA. The second groove 600 may be formed in an opening of the second planarization layer 162 that exists between the emission area EA and the transmission area TMA. Figure 5 As shown, the second trench 600 is disposed between the second electrode inclined portions AEb of the corresponding anode electrodes AE of two adjacent sub-pixels, or between the transmission area TMA and the second electrode inclined portion AEb of the anode electrode AE ​​of at least one sub-pixel.

[0151] When the second trench 600 or the opening of the second planarization layer 162 is formed, the dummy anode electrode DAE may have a third electrode inclined portion between the emission area EA and the transmission area TMA.

[0152] like Figure 6 As shown, the cathode electrode CE includes a groove shape, or includes a portion having a groove shape (may also be referred to as a groove shape portion). Here, the groove shape portion of the cathode electrode CE protrudes toward the first planarization layer 161.

[0153] Figure 6 The following structure is shown, in which the bank layer 170 has the second groove 600 and the dummy anode electrode DAE between the emission area EA and the transmission area TMA, but the bank layer 170 may also have a groove and a dummy anode electrode between the emission areas EA included in adjacent sub-pixels SP (not shown). For example, the bank layer 170 may have a groove and a dummy anode electrode between the first sub-pixel and the second sub-pixel or between the first sub-pixel and the third sub-pixel.

[0154] Since the lengths of the light emitting layer EL and the cathode electrode CE existing between adjacent sub-pixels SP when the bank layer 170 has the groove and the dummy anode electrode between adjacent sub-pixels SP are greater than when there is no groove, the path of the current flowing through the light emitting layer EL and the cathode electrode CE increases, and the resistance in the light emitting layer EL and the cathode electrode CE increases. Therefore, since the amount of current flowing between adjacent sub-pixels SP may decrease, interference that may occur as the distance between the sub-pixels SP decreases may decrease.

[0155] In addition, when the second trench 600 is formed, the bank layer 170 may have an inclined region between the emission area EA and the transmission area TMA.

[0156] When the embankment layer 170 has an inclined region, a path for harmful gas HG generated in the planarization layer 160 to flow into the light emitting element ED is reduced compared to when the embankment layer 170 does not have an inclined region, and thus the light emitting element ED can be protected from the harmful gas HG, thereby enhancing the reliability of the display device 100.

[0157] Figure 7 is a view illustrating another example of a sub-pixel structure included in a display device according to an embodiment of the present disclosure.

[0158] Reference Figure 7 , the display device 100 may include a plurality of sub-pixels SP and a transmission area TMA on a substrate 120 .

[0159] like Figure 7 As shown, a transmission area TMA may be formed around the plurality of sub-pixels SP.

[0160] Since light can pass through the transmission area TMA, the transmission area TMA can be used as a path for light to enter the sensor for identifying the user. For example, the display device 100 may also include a configuration of a sensor for identifying an object under the display panel 110 in an area overlapping with the transmission area TMA. The sensor may generate light for detecting an object, and the light from the sensor is reflected by the object after passing through the transmission area TMA. The light reflected on the object passes through the transmission area TMA again and enters the sensor. The sensor may sense the position or size of the object by detecting the incident light.

[0161] In addition, refer to Figure 7 , similar to the reference above Figure 5 As described above, the third trench 700 may be provided between the second electrode inclined portions AEb of the corresponding anode electrodes AE of two adjacent sub-pixels.

[0162] Figure 8 It is shown Figure 7 FIG. 2 is a view of an example of a cross-sectional structure of a portion III-III′. Fig. 9 It is shown Figure 7 FIG. 2 is a view of another example of the cross-sectional structure of portion III-III′.

[0163] Referring to Figures 2 to Figure 6 Those contents described are not repeated below.

[0164] Reference Figure 8 , the bank layer 170 may have an opening in the transmission area TMA.

[0165] In the transmission area TMA, the light emitting layer EL may be disposed to cover the first planarization layer 161 .

[0166] The cathode electrode CE may be disposed on the light emitting layer EL in the transmission region TMA. In this case, the cathode electrode CE may have a microstructure 800. The microstructure 800 may have a structure in which a portion of the cathode electrode CE is selectively removed. Light may pass through the microstructure 800 of the cathode electrode CE, and the degree to which the cathode electrode CE is removed may be adjusted to adjust the transmittance of light. In some embodiments, as Figure 8 and Fig. 9 As shown, the transmission area TMA overlaps with the microstructure 800 when viewed from a plan view.

[0167] When the bank layer 170 has the opening in the transmission region TMA, the bank layer 170 may have an inclined portion between the emission region EA and the transmission region TMA.

[0168] When the bank layer 170 has the inclined portion, the moving path of the harmful gas HG introduced through the bank layer 170 may be reduced compared to when the bank layer 170 does not have the inclined portion. Figure 8 and Fig. 9 As shown, the bank layer 170 includes a bank opening BO in which the bank layer 170 is completely open (eg, the bank layer 170 does not exist in the bank opening BO). In addition, since the bank layer 170 is completely open in the transmission area TMA, Figure 3 , Figure 4 and Figure 6 Compared with the case where the bank layer 170 shown has a flat area, the moving path of the harmful gas HG can be further reduced. Therefore, the harmful gas HG can be prevented from flowing into the light emitting element ED, thereby further enhancing the reliability of the display device 100.

[0169] Reference Fig. 9 , the display device 100 may have Figure 8 The structure shown further removes the structure of the first planarization layer 161 .

[0170] The bank layer 170 may have an opening (eg, a bank opening BO) in the transmission region TMA. Fig. 9 It is shown that the bank layer 170 does not exist in the transmission area TMA due to the bank opening BO. The light emitting layer EL may be disposed on the second insulating layer 152 in the transmission area TMA, and the cathode electrode CE may be disposed on the light emitting layer EL in the transmission area TMA.

[0171] although Fig. 9Although not shown in detail, the light emitting layer EL and the cathode electrode CE disposed in the transmission area TMA are connected to the light emitting layer EL and the cathode electrode CE outside the transmission area TMA.

[0172] The cathode electrode CE may have a microstructure 800 in the transmission area TMA. The microstructure 800 may have a structure in which a portion of the cathode electrode CE is selectively removed. Light may pass through the microstructure 800 of the cathode electrode CE, and the degree to which the cathode electrode CE is removed may be adjusted to adjust the transmittance of light.

[0173] In some embodiments, in the transmission area TMA, the light emitting layer EL is disposed on the second interlayer insulating layer 152, and the cathode electrode CE is disposed on the light emitting layer EL to have the microstructure 800. In some embodiments, the first planarization layer 161 has an opening SSO in the transmission area TMA. Fig. 9 It is shown that the first planarization layer 161 does not exist in the transmission area TMA. In the transmission area TMA, the opening SSO in the first planarization layer overlaps the bank opening BO in a plan view.

[0174] When the first planarization layer 161 is partially removed, the amount of harmful gas introduced through the bank layer 170 is reduced, and thus Figure 8 Compared with the structure shown, harmful gases introduced into the light emitting element ED can be more effectively blocked, thereby further enhancing the reliability of the display device 100.

[0175] FIG. 10A to FIG. 10E is a view illustrating an example of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0176] Reference Fig. 10A , a buffer layer 130 , a gate insulating layer 140 , and an interlayer insulating layer 150 may be formed on the substrate 120 , and a transistor for driving the light emitting element and a line for driving the transistor may be formed.

[0177] After forming the transistor and the wiring for driving the transistor, the first planarization layer 161 may be formed. An upper surface of the first planarization layer 161 may have a flat surface through the first planarization layer 161.

[0178] Reference Fig. 10B , a second planarization layer 162 may be formed on the first planarization layer 161 .

[0179] The second planarization layer 162 may be formed of the same material as the first planarization layer 161 and may be formed to have a plurality of openings. For example, the second planarization layer 162 may be formed to have a first opening in the emission area EA and a second opening in the non-emission area.

[0180] When forming the second planarization layer 162 , a mask manufactured so that the non-emission region can be opened may be used.

[0181] Reference Fig. 10C , an anode electrode AE ​​may be formed on the second planarization layer 162 .

[0182] The anode electrode AE ​​may be electrically connected to the source / drain electrodes in some regions, and may be formed on the first planarization layer 161 in some regions.

[0183] Reference Fig. 10D , a bank layer 170 may be formed on the second planarization layer 162 , the anode electrode AE, and the first planarization layer 161 .

[0184] The bank layer 170 may be formed to have at least one opening and may be formed to have at least one trench.

[0185] When forming the grooves in the bank layer 170, a semi-transmissive reflective mask may be used.

[0186] Reference Fig. 10E , a spacer 171 may be formed on a partial region of the bank layer 170 , a light emitting layer EL may be formed on the bank layer 170 and the spacer 171 , and a cathode electrode CE may be formed on the light emitting layer EL.

[0187] An encapsulation layer 180 may be formed on the cathode electrode CE.

[0188] Since the second planarization layer 162 has an opening in the non-emission region and the bank layer 170 has a groove in the non-emission region, the display device 100 manufactured by the method described above can reduce the inflow path of harmful gas generated from the planarization layer 160, thereby enhancing the reliability of the display device 100.

[0189] In addition, since the lengths of the light emitting layer EL and the cathode electrode CE in the region where the grooves are formed are greater than when the grooves are not formed, the path of the current formed through the light emitting layer EL or the cathode electrode CE can be increased, thereby increasing the resistance. Therefore, the current flowing between adjacent sub-pixels SP can be reduced, thereby reducing the interference between the sub-pixels SP.

[0190] The embodiments of the present disclosure described above are briefly described below.

[0191] According to an embodiment of the present disclosure, a display device may be provided, comprising: a substrate in which a plurality of sub-pixels including an emission region and a non-emission region are arranged; a first planarization layer on the substrate; a second planarization layer arranged on the first planarization layer and including a first opening located in the emission region and a second opening located in the non-emission region; an anode electrode arranged on the second planarization layer; a dam layer, the dam layer being arranged in a portion of the emission region and in at least a portion of the first planarization layer and the second planarization layer in the non-emission region, and the dam layer including at least one groove located in the second opening; a light-emitting layer arranged on the anode electrode; and a cathode electrode arranged on the light-emitting layer.

[0192] In the display device according to an embodiment of the present disclosure, the emission region may include a first emission region and a second emission region, and the anode electrode may have a first electrode inclined portion in the second emission region and a second electrode inclined portion in a portion of the non-emission region.

[0193] In the display device according to an embodiment of the present disclosure, the bank layer may include a first bank inclined portion arranged along the first electrode inclined portion and a second bank inclined portion arranged along the second electrode inclined portion. The thickness of the bank layer in the second bank inclined portion may be different from the thickness of the bank layer in the first bank inclined portion.

[0194] In the display device according to an embodiment of the present disclosure, the thickness of the bank layer in the second bank inclined portion may be smaller than the thickness of the bank layer in the first bank inclined portion.

[0195] In the display device according to an embodiment of the present disclosure, the bank layer may further include a flat region disposed in contact with the first planarization layer in the region where the groove is formed. The thickness of the bank layer in the flat region may be greater than the thickness of the bank layer in the second bank inclined portion.

[0196] In the display device according to an embodiment of the present disclosure, a vertical distance between the cathode electrode in the groove-formed region and the upper surface of the first planarization layer may be greater than a vertical distance between the cathode electrode and the upper surface of the first planarization layer in the groove-unformed region.

[0197] In the display device according to an embodiment of the present disclosure, the first planarization layer and the second planarization layer may be formed of the same material.

[0198] In the display device according to the embodiment of the present disclosure, the first electrode inclined portion and the second electrode inclined portion may have an inclination at the same angle.

[0199] According to an embodiment of the present disclosure, a display device can be provided, which includes: a substrate including an emission region and a transmission region; a plurality of insulating layers on the substrate; a first planarization layer arranged on the plurality of insulating layers; a second planarization layer arranged on the first planarization layer and including a first opening located in the emission region and a second opening located between the emission region and the transmission region; an anode electrode arranged on the second planarization layer; a dam layer, which is arranged in a portion of the emission region and in at least a portion of the first planarization layer and the second planarization layer between the emission region and the transmission region; a light-emitting layer arranged on the anode electrode; and a cathode electrode arranged on the light-emitting layer.

[0200] In a display device according to an embodiment of the present disclosure, the display device may further include: a plurality of pixel units emitting light of different colors; and a plurality of wiring units arranged to intersect with the plurality of pixel units, wherein the plurality of pixel units include a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit, the second pixel unit, and the third pixel unit may be arranged in a straight line on the same plane. The first pixel unit may be arranged between the second pixel unit and the third pixel unit.

[0201] In the display device according to an embodiment of the present disclosure, a plurality of wiring units may be provided on the second pixel unit and the third pixel unit, and a transmission area may be formed between the plurality of adjacent wiring units.

[0202] In the display device according to the embodiment of the present disclosure, the bank layer may have a groove between the first pixel unit and the second pixel unit, or between the first pixel unit and the third pixel unit, or between the first pixel unit and the transmission area.

[0203] In the display device according to the embodiment of the present disclosure, the emission region may include a first emission region and a second emission region. The anode electrode may have a first electrode inclined portion in the second emission region and a second electrode inclined portion between the emission region and the transmission region.

[0204] The display device according to an embodiment of the present disclosure may further include a dummy anode electrode disposed on the same layer as the anode electrode and having a third electrode inclined portion disposed on the second planarization layer.

[0205] In the display device according to the embodiment of the present disclosure, the bank layer may have a bank opening in the transmission region. In the transmission region, the light emitting layer may be disposed on the first planarization layer, and the cathode electrode may be disposed to have a microstructure on the light emitting layer.

[0206] In a display device according to an embodiment of the present disclosure, the bank layer may have a bank opening in the transmission region. The first planarization layer may have a structure opened in the transmission region. In the transmission region, the light emitting layer may be disposed on a plurality of insulating layers, and the cathode electrode may be disposed to have a microstructure on the light emitting layer.

[0207] According to an embodiment of the present disclosure, a method for manufacturing a display device can be provided, the method comprising: forming a first planarization layer on a substrate; forming a second planarization layer so that a first opening is formed in the emission region and a second opening is formed in the non-emission region on the first planarization layer; forming an anode electrode on a portion of the second planarization layer; and forming a dam layer to have an opening in the emission region and a groove in the non-emission region.

[0208] In the method for manufacturing a display device according to an embodiment of the present disclosure, the bank layer may be formed to have the groove using a semi-transmissive reflection mask.

[0209] The above description has been presented to enable any technician in the field to implement and use the technical ideas of the present disclosure, and the above description has been provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be very obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure.

[0210] The various embodiments described above can be combined to provide additional embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. Various aspects of the embodiments can be modified as necessary to provide additional embodiments using the concepts of various patents, applications, and disclosures.

[0211] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A display device, comprising: A substrate in which a plurality of sub-pixels including an emission region and a non-emission region are disposed; a first planarization layer on the substrate; a second planarization layer on the first planarization layer and including a first opening in the emission region and a second opening in the non-emission region; an anode electrode on the second planarization layer; a bank layer, the bank layer being disposed in a portion of the emission region and in at least a portion of the region on the first planarization layer and the second planarization layer in the non-emission region, the bank layer comprising at least one groove; a light-emitting layer on the anode electrode; as well as a cathode electrode on the light emitting layer, Wherein, the at least one groove overlaps with the second opening in a plan view.

2. The display device according to claim 1, wherein: The emission area includes a first emission area and a second emission area, and The anode electrode has a first electrode inclined portion in the second emission region and a second electrode inclined portion in a portion of the non-emission region.

3. The display device according to claim 2, wherein: The bank layer includes a first bank inclined portion disposed along the first electrode inclined portion and a second bank inclined portion disposed along the second electrode inclined portion, and The thickness of the bank layer in the second bank inclined portion is different from the thickness of the bank layer in the first bank inclined portion.

4. The display device according to claim 3, wherein: A thickness of the bank layer in the second bank inclined portion is smaller than a thickness of the bank layer in the first bank inclined portion.

5. The display device according to claim 4, wherein: The bank layer further includes a flat region disposed in contact with the first planarization layer in a region where the at least one trench is formed, and Wherein, a thickness of the bank layer in the flat region is greater than a thickness of the bank layer in the second bank inclined portion.

6. The display device according to claim 1, wherein: A vertical distance between the cathode electrode and an upper surface of the first planarization layer in a region where the at least one groove is formed is greater than a vertical distance between the cathode electrode and an upper surface of the first planarization layer in a region where the at least one groove is not formed.

7. The display device according to claim 1, wherein: The first planarization layer and the second planarization layer include the same material.

8. The display device according to claim 1, wherein: The first electrode inclined portion and the second electrode inclined portion have the same inclination angle.

9. A display device, comprising: A substrate, the substrate comprising an emitting region and a transmitting region; a plurality of insulating layers on the substrate; a first planarization layer on the plurality of insulating layers; a second planarization layer on the first planarization layer and including a first opening located in the emission region and a second opening located between the emission region and the transmission region as viewed from a plan view; an anode electrode on the second planarization layer; a bank layer in a portion of the emission region and in at least a portion of the first planarization layer and the second planarization layer between the emission region and the transmission region; a light-emitting layer on the anode electrode; as well as A cathode electrode is on the light emitting layer.

10. The display device according to claim 9, further comprising: A plurality of pixel units, wherein the plurality of pixel units emit light of different colors; as well as a plurality of wiring units, the plurality of wiring units being arranged to cross the plurality of pixel units, The plurality of pixel units include a first pixel unit, a second pixel unit and a third pixel unit. The first pixel unit, the second pixel unit and the third pixel unit are arranged in a straight line on the same plane, and Wherein, the first pixel unit is arranged between the second pixel unit and the third pixel unit.

11. The display device according to claim 10, wherein: The plurality of wiring units are disposed on the second pixel unit and the third pixel unit, and Wherein, the transmission area is formed between a plurality of adjacent wiring units.

12. The display device according to claim 10, further comprising a groove, the groove being included in the bank layer, the groove being: between the first pixel unit and the second pixel unit, or between the first pixel unit and the third pixel unit, or Between the first pixel unit and the transmission area.

13. The display device according to claim 9, wherein: The emission area includes a first emission area and a second emission area, and The anode electrode has a first electrode inclined portion in the second emission region and a second electrode inclined portion between the emission region and the transmission region. 14 . The display device according to claim 9 , further comprising a dummy anode electrode on the same layer as the anode electrode and having a third electrode inclined portion disposed on the second planarization layer.

15. The display device according to claim 9, wherein: The bank layer has a bank opening in the transmission region, and Wherein, in the transmission region, the light emitting layer is disposed on the first planarization layer, and the cathode electrode is disposed to have a microstructure on the light emitting layer.

16. The display device according to claim 9, wherein: The bank layer has a bank opening in the transmission region, wherein the first planarization layer has a structure that is open in the transmission region, and Wherein, in the transmission region, the light emitting layer is disposed on the plurality of insulating layers, and the cathode electrode is disposed to have a microstructure on the light emitting layer.

17. A method for manufacturing a display device, the method comprising: forming a first planarization layer on the substrate; forming a second planarization layer on the first planarization layer; forming a first opening in the second planarization layer in the emission region; forming a second opening in the second planarization layer in a non-emitting region; forming an anode electrode on a portion of the second planarization layer; as well as The bank layer is formed to have an opening in the emission region and a groove in the non-emission region.

18. The method according to claim 17, wherein: The bank layer is formed to have the groove using a semi-transmissive reflection mask.

19. A display device comprising: a first planarization layer on the substrate, the first planarization layer having a first surface; a second planarizing layer on the first surface of the first planarizing layer; a first opening in the second planarization layer, the first opening extending through the second planarization layer; a second opening in the second planarization layer, the second opening extending through the second planarization layer; an anode electrode on the second planarization layer, the anode electrode contacting the first surface of the first planarization layer at the first opening; a light emitting layer on the second planarization layer; a cathode electrode on the second planarization layer; as well as a light emitting element, the light emitting element including the anode electrode, the cathode electrode, and the light emitting layer between the anode electrode and the cathode electrode, the light emitting element overlapping the first opening in a plan view, and the light emitting element being configured to emit light, The first opening does not overlap with the second opening when viewed from a plan view.

20. The display device according to claim 19, wherein: The anode electrode exposes at least a portion of the first surface of the first planarization layer and does not cover the exposed portion of the first surface of the first planarization layer. wherein the first opening overlaps with the emission area of ​​the display device, wherein the second opening overlaps with a non-emitting area of ​​the display device, and The emission area of ​​the display device corresponds to the area where the light-emitting element emits light.

21. The display device according to claim 19, wherein: The anode electrode exposes at least a portion of the first surface of the first planarization layer and does not cover the exposed portion of the first surface of the first planarization layer. wherein the first opening overlaps with the emission area of ​​the display device, wherein the second opening overlaps with the transmissive area of ​​the display device, and The emission area of ​​the display device corresponds to the area where the light-emitting element emits light.

22. The display device according to claim 21, wherein: The cathode electrode comprises a microstructure, The microstructure is formed by selectively removing a portion of the cathode electrode to allow light to pass through the microstructure, and Wherein, the transmission area overlaps with the microstructure when viewed from a plan view.

23. The display device according to claim 19, wherein: The cathode electrode is on the first opening and the second opening, wherein the cathode electrode includes a portion having a groove shape at the second opening, The groove shape of the cathode electrode protrudes toward the first planarization layer.

24. The display device according to claim 19, further comprising: a bank layer including a first bank inclined portion and a second bank inclined portion adjacent to the first bank inclined portion, wherein the first bank inclined portion and the second bank inclined portion are on the second planarization layer, The first bank inclined portion and the second bank inclined portion are between the light emitting layer and the anode electrode.

25. The display device according to claim 24, wherein: The bank layer also includes a flat portion, The flat portion of the bank layer is in direct contact with the first surface of the first planarization layer at the second opening.

Images